Update repo
This commit is contained in:
@@ -1,3 +1,9 @@
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# STM32F7_Cortex_M7
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## STM32F767ZI NUCLEO
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The bare-metal demo code for NUCLEO-F767ZI
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STM32F767ZI (LQFP144)
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- CPU: 216MHz
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- Flash: 2MB
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- SRAM: 512KB
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<a href="url"><img src="./images/stm32f767zi_nucleo.png" width="600"></a>
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Binary file not shown.
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After Width: | Height: | Size: 2.1 MiB |
@@ -0,0 +1,99 @@
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||||
@@ -1,6 +1,6 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>09_uart_rx</name>
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||||
<name>09_UART_RX</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
|
||||
@@ -0,0 +1,99 @@
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||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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||||
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<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/09_UART_RX.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="09_UART_RX"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.2074128981"/>
|
||||
<booleanAttribute key="org.eclipse.debug.core.ATTR_FORCE_SYSTEM_CONSOLE_ENCODING" value="false"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/09_UART_RX"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><memoryBlockExpressionList context="reserved-for-future-use"/>"/>
|
||||
<stringAttribute key="process_factory_id" value="com.st.stm32cube.ide.mcu.debug.launch.HardwareDebugProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
@@ -6588,7 +6588,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -7491,7 +7491,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -11413,7 +11413,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -12750,7 +12750,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -12824,7 +12824,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -13007,7 +13007,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
|
||||
#define USART_TCBGT_SUPPORT
|
||||
|
||||
@@ -6604,7 +6604,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -7507,7 +7507,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -11435,7 +11435,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -12772,7 +12772,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -12846,7 +12846,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -13029,7 +13029,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
|
||||
#define USART_TCBGT_SUPPORT
|
||||
|
||||
@@ -6818,7 +6818,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -7721,7 +7721,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -11658,7 +11658,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -12995,7 +12995,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -13069,7 +13069,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -13252,7 +13252,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
|
||||
#define USART_TCBGT_SUPPORT
|
||||
|
||||
@@ -6802,7 +6802,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -7705,7 +7705,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -11636,7 +11636,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -12973,7 +12973,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -13047,7 +13047,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -13230,7 +13230,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
|
||||
#define USART_TCBGT_SUPPORT
|
||||
|
||||
@@ -6818,7 +6818,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -7721,7 +7721,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -11658,7 +11658,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -12995,7 +12995,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -13069,7 +13069,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -13252,7 +13252,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
|
||||
#define USART_TCBGT_SUPPORT
|
||||
|
||||
@@ -7379,7 +7379,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -8282,7 +8282,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -12509,7 +12509,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -13852,7 +13852,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -13926,7 +13926,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -14632,6 +14632,9 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/* Bit definition for Ethernet MAC Control Register register */
|
||||
#define ETH_MACCR_CSTF_Pos (25U)
|
||||
#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos) /*!< 0x02000000 */
|
||||
#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
|
||||
#define ETH_MACCR_WD_Pos (23U)
|
||||
#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
|
||||
@@ -15054,7 +15057,7 @@ typedef struct
|
||||
/* Ethernet MMC Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet MMC Contol Register */
|
||||
/* Bit definition for Ethernet MMC Control Register */
|
||||
#define ETH_MMCCR_MCFHP_Pos (5U)
|
||||
#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
|
||||
#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
|
||||
@@ -15138,7 +15141,7 @@ typedef struct
|
||||
#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
|
||||
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
|
||||
#define ETH_MMCRFAECR_RFAEC_Pos (0U)
|
||||
#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
|
||||
@@ -15152,34 +15155,37 @@ typedef struct
|
||||
/* Ethernet PTP Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
||||
/* Bit definition for Ethernet PTP Time Stamp Control Register */
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
|
||||
#define ETH_PTPTSCR_TSCNT_Pos (16U)
|
||||
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
|
||||
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
|
||||
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSSR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSSR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSCR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSCR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
|
||||
#define ETH_PTPTSCR_TSARU_Pos (5U)
|
||||
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
|
||||
@@ -15264,6 +15270,9 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet DMA Bus Mode Register */
|
||||
#define ETH_DMABMR_MB_Pos (26U)
|
||||
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
|
||||
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
|
||||
#define ETH_DMABMR_AAB_Pos (25U)
|
||||
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
|
||||
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
|
||||
@@ -15406,7 +15415,7 @@ typedef struct
|
||||
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
|
||||
#define ETH_DMASR_RPS_Queuing_Pos (17U)
|
||||
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
|
||||
#define ETH_DMASR_NIS_Pos (16U)
|
||||
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
|
||||
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
|
||||
|
||||
@@ -7434,7 +7434,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -8337,7 +8337,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -9541,7 +9541,7 @@ typedef struct
|
||||
|
||||
#define LTDC_AWCR_AAH_Pos (0U)
|
||||
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
|
||||
#define LTDC_AWCR_AAW_Pos (16U)
|
||||
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
|
||||
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
|
||||
@@ -12857,7 +12857,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -14200,7 +14200,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -14274,7 +14274,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -14980,6 +14980,9 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/* Bit definition for Ethernet MAC Control Register register */
|
||||
#define ETH_MACCR_CSTF_Pos (25U)
|
||||
#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos) /*!< 0x02000000 */
|
||||
#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
|
||||
#define ETH_MACCR_WD_Pos (23U)
|
||||
#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
|
||||
@@ -15402,7 +15405,7 @@ typedef struct
|
||||
/* Ethernet MMC Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet MMC Contol Register */
|
||||
/* Bit definition for Ethernet MMC Control Register */
|
||||
#define ETH_MMCCR_MCFHP_Pos (5U)
|
||||
#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
|
||||
#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
|
||||
@@ -15486,7 +15489,7 @@ typedef struct
|
||||
#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
|
||||
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
|
||||
#define ETH_MMCRFAECR_RFAEC_Pos (0U)
|
||||
#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
|
||||
@@ -15500,34 +15503,37 @@ typedef struct
|
||||
/* Ethernet PTP Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
||||
/* Bit definition for Ethernet PTP Time Stamp Control Register */
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
|
||||
#define ETH_PTPTSCR_TSCNT_Pos (16U)
|
||||
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
|
||||
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
|
||||
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSSR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSSR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSCR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSCR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
|
||||
#define ETH_PTPTSCR_TSARU_Pos (5U)
|
||||
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
|
||||
@@ -15612,6 +15618,9 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet DMA Bus Mode Register */
|
||||
#define ETH_DMABMR_MB_Pos (26U)
|
||||
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
|
||||
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
|
||||
#define ETH_DMABMR_AAB_Pos (25U)
|
||||
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
|
||||
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
|
||||
@@ -15754,7 +15763,7 @@ typedef struct
|
||||
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
|
||||
#define ETH_DMASR_RPS_Queuing_Pos (17U)
|
||||
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
|
||||
#define ETH_DMASR_NIS_Pos (16U)
|
||||
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
|
||||
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
|
||||
|
||||
@@ -7622,7 +7622,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -8525,7 +8525,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -9816,7 +9816,7 @@ typedef struct
|
||||
|
||||
#define LTDC_AWCR_AAH_Pos (0U)
|
||||
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
|
||||
#define LTDC_AWCR_AAW_Pos (16U)
|
||||
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
|
||||
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
|
||||
@@ -13150,7 +13150,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -14493,7 +14493,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -14567,7 +14567,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -15273,6 +15273,9 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/* Bit definition for Ethernet MAC Control Register register */
|
||||
#define ETH_MACCR_CSTF_Pos (25U)
|
||||
#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos) /*!< 0x02000000 */
|
||||
#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
|
||||
#define ETH_MACCR_WD_Pos (23U)
|
||||
#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
|
||||
@@ -15695,7 +15698,7 @@ typedef struct
|
||||
/* Ethernet MMC Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet MMC Contol Register */
|
||||
/* Bit definition for Ethernet MMC Control Register */
|
||||
#define ETH_MMCCR_MCFHP_Pos (5U)
|
||||
#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
|
||||
#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
|
||||
@@ -15779,7 +15782,7 @@ typedef struct
|
||||
#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
|
||||
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
|
||||
#define ETH_MMCRFAECR_RFAEC_Pos (0U)
|
||||
#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
|
||||
@@ -15793,34 +15796,37 @@ typedef struct
|
||||
/* Ethernet PTP Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
||||
/* Bit definition for Ethernet PTP Time Stamp Control Register */
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
|
||||
#define ETH_PTPTSCR_TSCNT_Pos (16U)
|
||||
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
|
||||
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
|
||||
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSSR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSSR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSCR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSCR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
|
||||
#define ETH_PTPTSCR_TSARU_Pos (5U)
|
||||
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
|
||||
@@ -15905,6 +15911,9 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet DMA Bus Mode Register */
|
||||
#define ETH_DMABMR_MB_Pos (26U)
|
||||
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
|
||||
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
|
||||
#define ETH_DMABMR_AAB_Pos (25U)
|
||||
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
|
||||
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
|
||||
@@ -16047,7 +16056,7 @@ typedef struct
|
||||
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
|
||||
#define ETH_DMASR_RPS_Queuing_Pos (17U)
|
||||
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
|
||||
#define ETH_DMASR_NIS_Pos (16U)
|
||||
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
|
||||
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
|
||||
|
||||
@@ -7622,7 +7622,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -8525,7 +8525,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -9816,7 +9816,7 @@ typedef struct
|
||||
|
||||
#define LTDC_AWCR_AAH_Pos (0U)
|
||||
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
|
||||
#define LTDC_AWCR_AAW_Pos (16U)
|
||||
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
|
||||
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
|
||||
@@ -13150,7 +13150,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -14493,7 +14493,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -14567,7 +14567,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -15273,6 +15273,9 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/* Bit definition for Ethernet MAC Control Register register */
|
||||
#define ETH_MACCR_CSTF_Pos (25U)
|
||||
#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos) /*!< 0x02000000 */
|
||||
#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
|
||||
#define ETH_MACCR_WD_Pos (23U)
|
||||
#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
|
||||
@@ -15695,7 +15698,7 @@ typedef struct
|
||||
/* Ethernet MMC Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet MMC Contol Register */
|
||||
/* Bit definition for Ethernet MMC Control Register */
|
||||
#define ETH_MMCCR_MCFHP_Pos (5U)
|
||||
#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
|
||||
#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
|
||||
@@ -15779,7 +15782,7 @@ typedef struct
|
||||
#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
|
||||
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
|
||||
#define ETH_MMCRFAECR_RFAEC_Pos (0U)
|
||||
#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
|
||||
@@ -15793,34 +15796,37 @@ typedef struct
|
||||
/* Ethernet PTP Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
||||
/* Bit definition for Ethernet PTP Time Stamp Control Register */
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
|
||||
#define ETH_PTPTSCR_TSCNT_Pos (16U)
|
||||
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
|
||||
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
|
||||
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSSR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSSR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSCR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSCR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
|
||||
#define ETH_PTPTSCR_TSARU_Pos (5U)
|
||||
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
|
||||
@@ -15905,6 +15911,9 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet DMA Bus Mode Register */
|
||||
#define ETH_DMABMR_MB_Pos (26U)
|
||||
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
|
||||
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
|
||||
#define ETH_DMABMR_AAB_Pos (25U)
|
||||
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
|
||||
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
|
||||
@@ -16047,7 +16056,7 @@ typedef struct
|
||||
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
|
||||
#define ETH_DMASR_RPS_Queuing_Pos (17U)
|
||||
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
|
||||
#define ETH_DMASR_NIS_Pos (16U)
|
||||
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
|
||||
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
|
||||
|
||||
@@ -6835,7 +6835,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
|
||||
/******************** Bit definition for DMA2D_CR register ******************/
|
||||
@@ -7892,7 +7892,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -8795,7 +8795,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -11582,7 +11582,7 @@ typedef struct
|
||||
#define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define RCC_SAI1SEL_PLLSRC_SUPPORT
|
||||
#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
|
||||
@@ -11592,7 +11592,7 @@ typedef struct
|
||||
#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define RCC_SAI2SEL_PLLSRC_SUPPORT
|
||||
#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
|
||||
@@ -13077,7 +13077,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -13829,7 +13829,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature available on specific devices */
|
||||
/******************* Bit definition for TIM_CR1 register ********************/
|
||||
@@ -14434,7 +14434,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -14508,7 +14508,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -15266,6 +15266,9 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/* Bit definition for Ethernet MAC Control Register register */
|
||||
#define ETH_MACCR_CSTF_Pos (25U)
|
||||
#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos) /*!< 0x02000000 */
|
||||
#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
|
||||
#define ETH_MACCR_WD_Pos (23U)
|
||||
#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
|
||||
@@ -15688,7 +15691,7 @@ typedef struct
|
||||
/* Ethernet MMC Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet MMC Contol Register */
|
||||
/* Bit definition for Ethernet MMC Control Register */
|
||||
#define ETH_MMCCR_MCFHP_Pos (5U)
|
||||
#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
|
||||
#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
|
||||
@@ -15772,7 +15775,7 @@ typedef struct
|
||||
#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
|
||||
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
|
||||
#define ETH_MMCRFAECR_RFAEC_Pos (0U)
|
||||
#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
|
||||
@@ -15786,34 +15789,37 @@ typedef struct
|
||||
/* Ethernet PTP Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
||||
/* Bit definition for Ethernet PTP Time Stamp Control Register */
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
|
||||
#define ETH_PTPTSCR_TSCNT_Pos (16U)
|
||||
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
|
||||
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
|
||||
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSSR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSSR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSCR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSCR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
|
||||
#define ETH_PTPTSCR_TSARU_Pos (5U)
|
||||
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
|
||||
@@ -15898,6 +15904,9 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet DMA Bus Mode Register */
|
||||
#define ETH_DMABMR_MB_Pos (26U)
|
||||
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
|
||||
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
|
||||
#define ETH_DMABMR_AAB_Pos (25U)
|
||||
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
|
||||
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
|
||||
@@ -16040,7 +16049,7 @@ typedef struct
|
||||
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
|
||||
#define ETH_DMASR_RPS_Queuing_Pos (17U)
|
||||
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
|
||||
#define ETH_DMASR_NIS_Pos (16U)
|
||||
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
|
||||
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
|
||||
|
||||
@@ -6929,7 +6929,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
|
||||
/******************** Bit definition for DMA2D_CR register ******************/
|
||||
@@ -7986,7 +7986,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -8889,7 +8889,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -10091,7 +10091,7 @@ typedef struct
|
||||
|
||||
#define LTDC_AWCR_AAH_Pos (0U)
|
||||
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
|
||||
#define LTDC_AWCR_AAW_Pos (16U)
|
||||
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
|
||||
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
|
||||
@@ -11976,7 +11976,7 @@ typedef struct
|
||||
#define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define RCC_SAI1SEL_PLLSRC_SUPPORT
|
||||
#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
|
||||
@@ -11986,7 +11986,7 @@ typedef struct
|
||||
#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define RCC_SAI2SEL_PLLSRC_SUPPORT
|
||||
#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
|
||||
@@ -13471,7 +13471,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -14223,7 +14223,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature available on specific devices */
|
||||
/******************* Bit definition for TIM_CR1 register ********************/
|
||||
@@ -14828,7 +14828,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -14902,7 +14902,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -15660,6 +15660,9 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/* Bit definition for Ethernet MAC Control Register register */
|
||||
#define ETH_MACCR_CSTF_Pos (25U)
|
||||
#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos) /*!< 0x02000000 */
|
||||
#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
|
||||
#define ETH_MACCR_WD_Pos (23U)
|
||||
#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
|
||||
@@ -16082,7 +16085,7 @@ typedef struct
|
||||
/* Ethernet MMC Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet MMC Contol Register */
|
||||
/* Bit definition for Ethernet MMC Control Register */
|
||||
#define ETH_MMCCR_MCFHP_Pos (5U)
|
||||
#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
|
||||
#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
|
||||
@@ -16166,7 +16169,7 @@ typedef struct
|
||||
#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
|
||||
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
|
||||
#define ETH_MMCRFAECR_RFAEC_Pos (0U)
|
||||
#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
|
||||
@@ -16180,34 +16183,37 @@ typedef struct
|
||||
/* Ethernet PTP Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
||||
/* Bit definition for Ethernet PTP Time Stamp Control Register */
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
|
||||
#define ETH_PTPTSCR_TSCNT_Pos (16U)
|
||||
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
|
||||
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
|
||||
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSSR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSSR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSCR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSCR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
|
||||
#define ETH_PTPTSCR_TSARU_Pos (5U)
|
||||
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
|
||||
@@ -16292,6 +16298,9 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet DMA Bus Mode Register */
|
||||
#define ETH_DMABMR_MB_Pos (26U)
|
||||
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
|
||||
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
|
||||
#define ETH_DMABMR_AAB_Pos (25U)
|
||||
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
|
||||
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
|
||||
@@ -16434,7 +16443,7 @@ typedef struct
|
||||
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
|
||||
#define ETH_DMASR_RPS_Queuing_Pos (17U)
|
||||
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
|
||||
#define ETH_DMASR_NIS_Pos (16U)
|
||||
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
|
||||
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
|
||||
@@ -18205,7 +18214,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register *******************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
|
||||
@@ -1343,7 +1343,7 @@ typedef struct
|
||||
uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
|
||||
__IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
|
||||
__IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
|
||||
__IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
|
||||
__IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */
|
||||
__IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
|
||||
__IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
|
||||
__IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
|
||||
@@ -7012,7 +7012,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
|
||||
/******************** Bit definition for DMA2D_CR register ******************/
|
||||
@@ -8069,7 +8069,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -8972,7 +8972,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -10174,7 +10174,7 @@ typedef struct
|
||||
|
||||
#define LTDC_AWCR_AAH_Pos (0U)
|
||||
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
|
||||
#define LTDC_AWCR_AAW_Pos (16U)
|
||||
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
|
||||
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
|
||||
@@ -12068,7 +12068,7 @@ typedef struct
|
||||
#define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define RCC_SAI1SEL_PLLSRC_SUPPORT
|
||||
#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
|
||||
@@ -12078,7 +12078,7 @@ typedef struct
|
||||
#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define RCC_SAI2SEL_PLLSRC_SUPPORT
|
||||
#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
|
||||
@@ -13566,7 +13566,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -14318,7 +14318,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature available on specific devices */
|
||||
/******************* Bit definition for TIM_CR1 register ********************/
|
||||
@@ -14923,7 +14923,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -14997,7 +14997,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -15755,6 +15755,9 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/* Bit definition for Ethernet MAC Control Register register */
|
||||
#define ETH_MACCR_CSTF_Pos (25U)
|
||||
#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos) /*!< 0x02000000 */
|
||||
#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
|
||||
#define ETH_MACCR_WD_Pos (23U)
|
||||
#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
|
||||
@@ -16177,7 +16180,7 @@ typedef struct
|
||||
/* Ethernet MMC Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet MMC Contol Register */
|
||||
/* Bit definition for Ethernet MMC Control Register */
|
||||
#define ETH_MMCCR_MCFHP_Pos (5U)
|
||||
#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
|
||||
#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
|
||||
@@ -16261,7 +16264,7 @@ typedef struct
|
||||
#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
|
||||
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
|
||||
#define ETH_MMCRFAECR_RFAEC_Pos (0U)
|
||||
#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
|
||||
@@ -16275,34 +16278,37 @@ typedef struct
|
||||
/* Ethernet PTP Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
||||
/* Bit definition for Ethernet PTP Time Stamp Control Register */
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
|
||||
#define ETH_PTPTSCR_TSCNT_Pos (16U)
|
||||
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
|
||||
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
|
||||
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSSR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSSR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSCR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSCR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
|
||||
#define ETH_PTPTSCR_TSARU_Pos (5U)
|
||||
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
|
||||
@@ -16387,6 +16393,9 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet DMA Bus Mode Register */
|
||||
#define ETH_DMABMR_MB_Pos (26U)
|
||||
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
|
||||
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
|
||||
#define ETH_DMABMR_AAB_Pos (25U)
|
||||
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
|
||||
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
|
||||
@@ -16529,7 +16538,7 @@ typedef struct
|
||||
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
|
||||
#define ETH_DMASR_RPS_Queuing_Pos (17U)
|
||||
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
|
||||
#define ETH_DMASR_NIS_Pos (16U)
|
||||
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
|
||||
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
|
||||
@@ -18300,7 +18309,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register *******************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@@ -18512,7 +18521,7 @@ typedef struct
|
||||
|
||||
#define DSI_LCOLCR_LPE_Pos (8U)
|
||||
#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
|
||||
#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
|
||||
#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */
|
||||
|
||||
/******************* Bit definition for DSI_LPCR register ***************/
|
||||
#define DSI_LPCR_DEP_Pos (0U)
|
||||
|
||||
@@ -7117,7 +7117,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
|
||||
/******************** Bit definition for DMA2D_CR register ******************/
|
||||
@@ -8174,7 +8174,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -9077,7 +9077,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -10366,7 +10366,7 @@ typedef struct
|
||||
|
||||
#define LTDC_AWCR_AAH_Pos (0U)
|
||||
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
|
||||
#define LTDC_AWCR_AAW_Pos (16U)
|
||||
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
|
||||
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
|
||||
@@ -12269,7 +12269,7 @@ typedef struct
|
||||
#define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define RCC_SAI1SEL_PLLSRC_SUPPORT
|
||||
#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
|
||||
@@ -12279,7 +12279,7 @@ typedef struct
|
||||
#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define RCC_SAI2SEL_PLLSRC_SUPPORT
|
||||
#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
|
||||
@@ -13764,7 +13764,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -14516,7 +14516,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature available on specific devices */
|
||||
/******************* Bit definition for TIM_CR1 register ********************/
|
||||
@@ -15121,7 +15121,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -15195,7 +15195,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -15953,6 +15953,9 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/* Bit definition for Ethernet MAC Control Register register */
|
||||
#define ETH_MACCR_CSTF_Pos (25U)
|
||||
#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos) /*!< 0x02000000 */
|
||||
#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
|
||||
#define ETH_MACCR_WD_Pos (23U)
|
||||
#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
|
||||
@@ -16375,7 +16378,7 @@ typedef struct
|
||||
/* Ethernet MMC Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet MMC Contol Register */
|
||||
/* Bit definition for Ethernet MMC Control Register */
|
||||
#define ETH_MMCCR_MCFHP_Pos (5U)
|
||||
#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
|
||||
#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
|
||||
@@ -16459,7 +16462,7 @@ typedef struct
|
||||
#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
|
||||
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
|
||||
#define ETH_MMCRFAECR_RFAEC_Pos (0U)
|
||||
#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
|
||||
@@ -16473,34 +16476,37 @@ typedef struct
|
||||
/* Ethernet PTP Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
||||
/* Bit definition for Ethernet PTP Time Stamp Control Register */
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
|
||||
#define ETH_PTPTSCR_TSCNT_Pos (16U)
|
||||
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
|
||||
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
|
||||
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSSR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSSR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSCR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSCR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
|
||||
#define ETH_PTPTSCR_TSARU_Pos (5U)
|
||||
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
|
||||
@@ -16585,6 +16591,9 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet DMA Bus Mode Register */
|
||||
#define ETH_DMABMR_MB_Pos (26U)
|
||||
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
|
||||
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
|
||||
#define ETH_DMABMR_AAB_Pos (25U)
|
||||
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
|
||||
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
|
||||
@@ -16727,7 +16736,7 @@ typedef struct
|
||||
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
|
||||
#define ETH_DMASR_RPS_Queuing_Pos (17U)
|
||||
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
|
||||
#define ETH_DMASR_NIS_Pos (16U)
|
||||
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
|
||||
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
|
||||
@@ -18498,7 +18507,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register *******************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
|
||||
@@ -1412,7 +1412,7 @@ typedef struct
|
||||
uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
|
||||
__IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
|
||||
__IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
|
||||
__IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
|
||||
__IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */
|
||||
__IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
|
||||
__IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
|
||||
__IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
|
||||
@@ -7200,7 +7200,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
|
||||
/******************** Bit definition for DMA2D_CR register ******************/
|
||||
@@ -8257,7 +8257,7 @@ typedef struct
|
||||
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
|
||||
#define FMC_BCR1_CCLKEN_Pos (20U)
|
||||
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
|
||||
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
|
||||
#define FMC_BCR1_WFDIS_Pos (21U)
|
||||
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
|
||||
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
|
||||
@@ -9160,7 +9160,7 @@ typedef struct
|
||||
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
|
||||
#define FMC_SDRTR_REIE_Pos (14U)
|
||||
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
|
||||
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
|
||||
|
||||
/****************** Bit definition for FMC_SDSR register ******************/
|
||||
#define FMC_SDSR_RE_Pos (0U)
|
||||
@@ -10449,7 +10449,7 @@ typedef struct
|
||||
|
||||
#define LTDC_AWCR_AAH_Pos (0U)
|
||||
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
|
||||
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
|
||||
#define LTDC_AWCR_AAW_Pos (16U)
|
||||
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
|
||||
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
|
||||
@@ -12361,7 +12361,7 @@ typedef struct
|
||||
#define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define RCC_SAI1SEL_PLLSRC_SUPPORT
|
||||
#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
|
||||
@@ -12371,7 +12371,7 @@ typedef struct
|
||||
#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */
|
||||
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define RCC_SAI2SEL_PLLSRC_SUPPORT
|
||||
#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
|
||||
@@ -13859,7 +13859,7 @@ typedef struct
|
||||
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
|
||||
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
|
||||
|
||||
/****************** Bit definition for SDMMC_STA registe ********************/
|
||||
/****************** Bit definition for SDMMC_STA register ********************/
|
||||
#define SDMMC_STA_CCRCFAIL_Pos (0U)
|
||||
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
|
||||
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
|
||||
@@ -14611,7 +14611,7 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
|
||||
*/
|
||||
#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature available on specific devices */
|
||||
/******************* Bit definition for TIM_CR1 register ********************/
|
||||
@@ -15216,7 +15216,7 @@ typedef struct
|
||||
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
|
||||
|
||||
/******************* Bit definition for TIM_OR regiter *********************/
|
||||
/******************* Bit definition for TIM_OR register *********************/
|
||||
#define TIM_OR_TI4_RMP_Pos (6U)
|
||||
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
|
||||
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
||||
@@ -15290,7 +15290,7 @@ typedef struct
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
@@ -16048,6 +16048,9 @@ typedef struct
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
/* Bit definition for Ethernet MAC Control Register register */
|
||||
#define ETH_MACCR_CSTF_Pos (25U)
|
||||
#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos) /*!< 0x02000000 */
|
||||
#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
|
||||
#define ETH_MACCR_WD_Pos (23U)
|
||||
#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
|
||||
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
|
||||
@@ -16470,7 +16473,7 @@ typedef struct
|
||||
/* Ethernet MMC Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet MMC Contol Register */
|
||||
/* Bit definition for Ethernet MMC Control Register */
|
||||
#define ETH_MMCCR_MCFHP_Pos (5U)
|
||||
#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
|
||||
#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
|
||||
@@ -16554,7 +16557,7 @@ typedef struct
|
||||
#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
|
||||
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
||||
/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
|
||||
#define ETH_MMCRFAECR_RFAEC_Pos (0U)
|
||||
#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
|
||||
#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
|
||||
@@ -16568,34 +16571,37 @@ typedef struct
|
||||
/* Ethernet PTP Registers bits definition */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
||||
/* Bit definition for Ethernet PTP Time Stamp Control Register */
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
|
||||
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
|
||||
#define ETH_PTPTSCR_TSCNT_Pos (16U)
|
||||
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
|
||||
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
|
||||
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSSR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSSR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
|
||||
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
|
||||
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
|
||||
#define ETH_PTPTSCR_TSSEME_Pos (14U)
|
||||
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
|
||||
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
|
||||
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
|
||||
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
|
||||
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
|
||||
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
|
||||
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
|
||||
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
|
||||
#define ETH_PTPTSCR_TSSSR_Pos (9U)
|
||||
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
|
||||
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
|
||||
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
|
||||
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
|
||||
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
|
||||
|
||||
#define ETH_PTPTSCR_TSARU_Pos (5U)
|
||||
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
|
||||
@@ -16680,6 +16686,9 @@ typedef struct
|
||||
/******************************************************************************/
|
||||
|
||||
/* Bit definition for Ethernet DMA Bus Mode Register */
|
||||
#define ETH_DMABMR_MB_Pos (26U)
|
||||
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
|
||||
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
|
||||
#define ETH_DMABMR_AAB_Pos (25U)
|
||||
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
|
||||
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
|
||||
@@ -16822,7 +16831,7 @@ typedef struct
|
||||
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
|
||||
#define ETH_DMASR_RPS_Queuing_Pos (17U)
|
||||
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
|
||||
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
|
||||
#define ETH_DMASR_NIS_Pos (16U)
|
||||
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
|
||||
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
|
||||
@@ -18593,7 +18602,7 @@ typedef struct
|
||||
/******************** Bit definition for SR register *******************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
@@ -18805,7 +18814,7 @@ typedef struct
|
||||
|
||||
#define DSI_LCOLCR_LPE_Pos (8U)
|
||||
#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
|
||||
#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
|
||||
#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */
|
||||
|
||||
/******************* Bit definition for DSI_LPCR register ***************/
|
||||
#define DSI_LPCR_DEP_Pos (0U)
|
||||
|
||||
@@ -96,11 +96,11 @@
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.2.7
|
||||
* @brief CMSIS Device version number V1.2.10
|
||||
*/
|
||||
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32F7_CMSIS_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */
|
||||
#define __STM32F7_CMSIS_VERSION_SUB2 (0x0A) /*!< [15:8] sub2 version */
|
||||
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
||||
@@ -11,43 +11,73 @@
|
||||
span.underline{text-decoration: underline;}
|
||||
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
||||
</style>
|
||||
<link rel="stylesheet" href="_htmresc/mini-st.css" />
|
||||
<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
|
||||
<!--[if lt IE 9]>
|
||||
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
|
||||
<![endif]-->
|
||||
<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
|
||||
</head>
|
||||
<body>
|
||||
<div class="row">
|
||||
<div class="col-sm-12 col-lg-4">
|
||||
<div class="card fluid">
|
||||
<div class="sectione dark">
|
||||
<center>
|
||||
<h1 id="release-notes-for-stm32f7xx-cmsis"><strong>Release Notes for STM32F7xx CMSIS</strong></h1>
|
||||
<p>Copyright © 2019 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
|
||||
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
|
||||
</center>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history"><strong>Update History</strong></h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_7" checked aria-hidden="true"> <label for="collapse-section1_2_7" aria-hidden="true"><strong>V1.2.7 / 22-November-2021</strong></label>
|
||||
<input type="checkbox" id="collapse-section1_2_10" checked aria-hidden="true"> <label for="collapse-section1_2_10" aria-hidden="true"><strong>V1.2.10 / 25-April-2025</strong></label>
|
||||
<div>
|
||||
<ul>
|
||||
<li>Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.</li>
|
||||
<li>Fix Capture Compare register TIMx_CCR5 defintion.</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_9" aria-hidden="true"> <label for="collapse-section1_2_9" aria-hidden="true"><strong>V1.2.9 / 10-May-2024</strong></label>
|
||||
<div>
|
||||
<ul>
|
||||
<li>Update GCC start-up files to call SystemInit() API <span class="citation" data-cites="Reset_Handler">@Reset_Handler</span> step: alignment with EWARM and MDK-ARM start-up files.</li>
|
||||
<li>Update ETH bit definitions : Add CRC stripping for Type frames bit definition (CSFT).</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_8" aria-hidden="true"> <label for="collapse-section1_2_8" aria-hidden="true"><strong>V1.2.8 / 29-April-2022</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
|
||||
<li>All source files: update disclaimer to add reference to the new license agreement.</li>
|
||||
<li>General updates to fix known defects and enhancements implementation.</li>
|
||||
<li>Update gcc start-up files to remove duplication for DMA2_Stream4_IRQHandler.</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_7" aria-hidden="true"> <label for="collapse-section1_2_7" aria-hidden="true"><strong>V1.2.7 / 22-November-2021</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<ul>
|
||||
<li>General updates to fix known defects and enhancements implementation.</li>
|
||||
<li><p>All source files: update disclaimer to add reference to the new license agreement.</p></li>
|
||||
<li><strong>Headline</strong>
|
||||
<ul>
|
||||
<li>Add new atomic register access macros in stm32f7xx.h file.</li>
|
||||
<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li>
|
||||
<li>__FPU_PRESENT defined with 1U instead of 1 to avoid compilation warning.</li>
|
||||
<li>Add “PTPPPSCR” register definition for Ethernet Peripheral.</li>
|
||||
</ul></li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_6" aria-hidden="true"> <label for="collapse-section1_2_6" aria-hidden="true"><strong>V1.2.6 / 12-February-2021</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<h2 id="main-changes-2">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Improved GCC startup files robustness.</li>
|
||||
<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.</li>
|
||||
@@ -58,7 +88,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_5" aria-hidden="true"> <label for="collapse-section1_2_5" aria-hidden="true"><strong>V1.2.5 / 13-February-2020</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-2">Main Changes</h2>
|
||||
<h2 id="main-changes-3">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Add ADC missing calibration address for Vref and Temperature sensor.</li>
|
||||
<li>Align GPIO Bits Definitions to use _POS and _MSK.</li>
|
||||
@@ -73,7 +103,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_4" aria-hidden="true"> <label for="collapse-section1_2_4" aria-hidden="true"><strong>V1.2.4 / 08-February-2019</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-3">Main Changes</h2>
|
||||
<h2 id="main-changes-4">Main Changes</h2>
|
||||
<ul>
|
||||
<li>CRYP
|
||||
<ul>
|
||||
@@ -126,7 +156,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_3" aria-hidden="true"> <label for="collapse-section1_2_3" aria-hidden="true"><strong>V1.2.3 / 29-June-2018</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-4">Main Changes</h2>
|
||||
<h2 id="main-changes-5">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Add the support of <strong>STM32F730xx and STM32F750xx</strong> devices
|
||||
<ul>
|
||||
@@ -141,7 +171,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_2" aria-hidden="true"> <label for="collapse-section1_2_2" aria-hidden="true"><strong>V1.2.2 / 26-December-2017</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-5">Main Changes</h2>
|
||||
<h2 id="main-changes-6">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Update bits definition for USBPHYC_PLL1 and USBPHYC_LDO registers to be inline with products documentation.</li>
|
||||
</ul>
|
||||
@@ -150,7 +180,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_1" aria-hidden="true"> <label for="collapse-section1_2_1" aria-hidden="true"><strong>V1.2.1 / 25-August-2017</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-6">Main Changes</h2>
|
||||
<h2 id="main-changes-7">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Update FLASHSIZE_BASE and UID_BASE defined values for STM32F72x and STM32F73x devices.</li>
|
||||
<li>Update stm32f7xx.h to include stm32f7xx_hal.h file instead of stm32f7xx_hal_conf.h file</li>
|
||||
@@ -161,7 +191,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_2_0" aria-hidden="true"> <label for="collapse-section1_2_0" aria-hidden="true"><strong>V1.2.0 / 30-December-2016</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-7">Main Changes</h2>
|
||||
<h2 id="main-changes-8">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Add the support of <strong>STM32F722xx, STM32F723xx, STM32F732xx and STM32F733xx</strong> devices
|
||||
<ul>
|
||||
@@ -200,7 +230,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_1_1" aria-hidden="true"> <label for="collapse-section1_1_1" aria-hidden="true"><strong>V1.1.1 / 01-July-2016</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-8">Main Changes</h2>
|
||||
<h2 id="main-changes-9">Main Changes</h2>
|
||||
<ul>
|
||||
<li>stm32f7xx.h
|
||||
<ul>
|
||||
@@ -212,7 +242,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_1_0" aria-hidden="true"> <label for="collapse-section1_1_0" aria-hidden="true"><strong>V1.1.0 / 22-April-2016</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-9">Main Changes</h2>
|
||||
<h2 id="main-changes-10">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Add the support of <strong>STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx and STM32F779xx</strong> devices
|
||||
<ul>
|
||||
@@ -276,7 +306,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_0_3" aria-hidden="true"> <label for="collapse-section1_0_3" aria-hidden="true"><strong>V1.0.3 / 13-November-2015</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-10">Main Changes</h2>
|
||||
<h2 id="main-changes-11">Main Changes</h2>
|
||||
<ul>
|
||||
<li>stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
|
||||
<ul>
|
||||
@@ -296,7 +326,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_0_2" aria-hidden="true"> <label for="collapse-section1_0_2" aria-hidden="true"><strong>V1.0.2 / 21-September-2015</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-11">Main Changes</h2>
|
||||
<h2 id="main-changes-12">Main Changes</h2>
|
||||
<ul>
|
||||
<li>stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
|
||||
<ul>
|
||||
@@ -309,7 +339,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_0_1" aria-hidden="true"> <label for="collapse-section1_0_1" aria-hidden="true"><strong>V1.0.1 / 25-June-2015</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-12">Main Changes</h2>
|
||||
<h2 id="main-changes-13">Main Changes</h2>
|
||||
<ul>
|
||||
<li>stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
|
||||
<ul>
|
||||
@@ -329,7 +359,7 @@
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1_0_0" aria-hidden="true"> <label for="collapse-section1_0_0" aria-hidden="true"><strong>V1.0.0 / 12-April-2019</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-13">Main Changes</h2>
|
||||
<h2 id="main-changes-14">Main Changes</h2>
|
||||
<h3 id="first-release">First release</h3>
|
||||
<p>First official release for <strong>STM32F756xx/746xx/745xx</strong> devices</p>
|
||||
</div>
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -466,9 +467,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -466,9 +467,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -466,9 +467,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -466,9 +467,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -466,9 +467,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -460,9 +461,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -460,9 +461,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -460,9 +461,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+4
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,7 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -460,9 +462,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-6
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -90,9 +93,6 @@ FillZerobss:
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -472,9 +472,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -472,9 +473,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -472,9 +473,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -472,9 +473,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+3
-5
@@ -60,6 +60,9 @@ defined in linker script */
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -91,8 +94,6 @@ LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
@@ -472,9 +473,6 @@ g_pfnVectors:
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
+5
-5
@@ -86,14 +86,14 @@
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#if !defined(VECT_TAB_OFFSET)
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#endif /* VECT_TAB_OFFSET */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
/******************************************************************************/
|
||||
|
||||
@@ -199,7 +199,7 @@ void SystemInit(void)
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
uint32_t tmp, pllvco, pllp, pllsource, pllm;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
@@ -37,14 +37,12 @@ extern "C" {
|
||||
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
|
||||
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
|
||||
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
|
||||
#if defined(STM32U5)
|
||||
#if defined(STM32H7) || defined(STM32MP1)
|
||||
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
|
||||
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
|
||||
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
|
||||
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
|
||||
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
|
||||
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
|
||||
#endif /* STM32U5 */
|
||||
#endif /* STM32H7 || STM32MP1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -104,6 +102,16 @@ extern "C" {
|
||||
#if defined(STM32H7)
|
||||
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
|
||||
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
|
||||
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
|
||||
#endif /* STM32H5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -131,7 +139,8 @@ extern "C" {
|
||||
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
|
||||
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
|
||||
#if defined(STM32L0)
|
||||
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
|
||||
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
|
||||
input 1 for COMP1, LPTIM input 2 for COMP2 */
|
||||
#endif
|
||||
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
@@ -205,6 +214,11 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -225,8 +239,13 @@ extern "C" {
|
||||
/** @defgroup CRC_Aliases CRC API aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
|
||||
#if defined(STM32H5) || defined(STM32C0)
|
||||
#else
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
|
||||
inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
|
||||
inter STM32 series compatibility */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -268,7 +287,13 @@ extern "C" {
|
||||
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
|
||||
#if defined(STM32H5)
|
||||
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
|
||||
#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
|
||||
defined(STM32F4) || defined(STM32G4)
|
||||
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
|
||||
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
|
||||
#endif
|
||||
@@ -333,7 +358,8 @@ extern "C" {
|
||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||
|
||||
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
|
||||
defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
|
||||
#endif
|
||||
|
||||
@@ -410,6 +436,10 @@ extern "C" {
|
||||
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
|
||||
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
|
||||
#endif /* STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -442,7 +472,9 @@ extern "C" {
|
||||
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
|
||||
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
|
||||
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
|
||||
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
|
||||
#define PAGESIZE FLASH_PAGE_SIZE
|
||||
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
|
||||
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
|
||||
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
|
||||
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
|
||||
@@ -489,7 +521,7 @@ extern "C" {
|
||||
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
|
||||
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
|
||||
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
|
||||
#if defined(STM32G0)
|
||||
#if defined(STM32G0) || defined(STM32C0)
|
||||
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
|
||||
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
|
||||
#else
|
||||
@@ -506,6 +538,10 @@ extern "C" {
|
||||
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
|
||||
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
|
||||
#endif /* STM32H7 */
|
||||
#if defined(STM32H7RS)
|
||||
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
|
||||
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
|
||||
#endif /* STM32H7RS */
|
||||
#if defined(STM32U5)
|
||||
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
|
||||
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
|
||||
@@ -514,7 +550,20 @@ extern "C" {
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
|
||||
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
|
||||
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
|
||||
#endif /* STM32U5 */
|
||||
#if defined(STM32U0)
|
||||
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
|
||||
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
|
||||
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
|
||||
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_USER_nBOOT1 OB_USER_NBOOT1
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#endif /* STM32U0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -558,6 +607,115 @@ extern "C" {
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
|
||||
#endif /* STM32G4 */
|
||||
|
||||
#if defined(STM32U5)
|
||||
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
|
||||
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
|
||||
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
|
||||
#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
|
||||
#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
|
||||
#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
|
||||
#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
|
||||
|
||||
#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
|
||||
#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
|
||||
#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
|
||||
#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
|
||||
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
|
||||
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
|
||||
|
||||
#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
|
||||
#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
|
||||
#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
|
||||
#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
|
||||
|
||||
#define SYSCFG_ETH_MII SBS_ETH_MII
|
||||
#define SYSCFG_ETH_RMII SBS_ETH_RMII
|
||||
#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
|
||||
|
||||
#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
|
||||
#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
|
||||
#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
|
||||
|
||||
#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
|
||||
|
||||
#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
|
||||
#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SYSCFG_SAU SBS_SAU
|
||||
#define SYSCFG_MPU_SEC SBS_MPU_SEC
|
||||
#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
|
||||
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
|
||||
#else
|
||||
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define SYSCFG_CLK SBS_CLK
|
||||
#define SYSCFG_CLASSB SBS_CLASSB
|
||||
#define SYSCFG_FPU SBS_FPU
|
||||
#define SYSCFG_ALL SBS_ALL
|
||||
|
||||
#define SYSCFG_SEC SBS_SEC
|
||||
#define SYSCFG_NSEC SBS_NSEC
|
||||
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
|
||||
|
||||
#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
|
||||
|
||||
#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
|
||||
#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
|
||||
|
||||
#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
|
||||
#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
|
||||
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
|
||||
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
|
||||
#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
|
||||
#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
|
||||
#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
|
||||
#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
|
||||
#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
|
||||
|
||||
#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
|
||||
#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
|
||||
#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
|
||||
#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
|
||||
#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
|
||||
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
|
||||
#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
|
||||
|
||||
#define HAL_SYSCFG_Lock HAL_SBS_Lock
|
||||
#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
|
||||
#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#endif /* STM32H5 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -625,14 +783,16 @@ extern "C" {
|
||||
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
|
||||
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
|
||||
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
|
||||
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
|
||||
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
|
||||
STM32H757xx */
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
|
||||
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
||||
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
|
||||
defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
||||
@@ -654,9 +814,28 @@ extern "C" {
|
||||
|
||||
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
|
||||
|
||||
#if defined(STM32U5)
|
||||
#if defined(STM32U5) || defined(STM32H5)
|
||||
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
|
||||
#endif /* STM32U5 || STM32H5 */
|
||||
#if defined(STM32U5)
|
||||
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
|
||||
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32WBA)
|
||||
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
|
||||
#endif /* STM32WBA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -666,7 +845,25 @@ extern "C" {
|
||||
*/
|
||||
#if defined(STM32U5)
|
||||
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
|
||||
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
|
||||
#endif /* STM32U5 */
|
||||
#if defined(STM32H5)
|
||||
#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
|
||||
#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
|
||||
#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
|
||||
#endif /* STM32H5 */
|
||||
#if defined(STM32H5) || defined(STM32U5)
|
||||
#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
|
||||
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
|
||||
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
|
||||
#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
|
||||
#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
|
||||
#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
|
||||
#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
|
||||
#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
|
||||
#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
|
||||
#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
|
||||
#endif /* STM32H5 || STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -693,6 +890,10 @@ extern "C" {
|
||||
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
|
||||
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
|
||||
|
||||
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
|
||||
#define HRTIMInterruptResquests HRTIMInterruptRequests
|
||||
#endif /* STM32F3 || STM32G4 || STM32H7 */
|
||||
|
||||
#if defined(STM32G4)
|
||||
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
|
||||
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
|
||||
@@ -830,8 +1031,8 @@ extern "C" {
|
||||
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
|
||||
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
|
||||
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
|
||||
|
||||
#endif /* STM32F3 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -847,7 +1048,8 @@ extern "C" {
|
||||
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
|
||||
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
|
||||
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
|
||||
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
|
||||
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
|
||||
defined(STM32L1) || defined(STM32F7)
|
||||
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
|
||||
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
@@ -985,7 +1187,7 @@ extern "C" {
|
||||
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
|
||||
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
|
||||
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
|
||||
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
|
||||
#endif
|
||||
@@ -1081,15 +1283,42 @@ extern "C" {
|
||||
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
|
||||
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
|
||||
|
||||
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
|
||||
#endif /* STM32H5 || STM32H7RS || STM32N6 */
|
||||
|
||||
#if defined(STM32WBA)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
|
||||
#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
|
||||
#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
|
||||
#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
|
||||
#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
|
||||
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
|
||||
#endif /* STM32WBA */
|
||||
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
|
||||
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
|
||||
|
||||
#if defined(STM32F7) || defined(STM32WB)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
|
||||
#endif /* STM32F7 || STM32WB */
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
|
||||
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
|
||||
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
|
||||
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
|
||||
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
|
||||
#endif /* STM32H7 */
|
||||
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
|
||||
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -1373,26 +1602,36 @@ extern "C" {
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
|
||||
the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
|
||||
MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
|
||||
or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
|
||||
of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
|
||||
transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
|
||||
frame for transmission */
|
||||
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
|
||||
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
|
||||
de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
|
||||
activate threshold */
|
||||
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
|
||||
#if defined(STM32F1)
|
||||
#else
|
||||
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
|
||||
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
|
||||
(or time-stamp) */
|
||||
#endif
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
|
||||
status */
|
||||
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
|
||||
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
|
||||
@@ -1400,6 +1639,8 @@ extern "C" {
|
||||
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
|
||||
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
|
||||
|
||||
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1563,7 +1804,8 @@ extern "C" {
|
||||
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
|
||||
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
|
||||
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
|
||||
HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
|
||||
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
|
||||
#if defined(STM32L0)
|
||||
@@ -1572,8 +1814,10 @@ extern "C" {
|
||||
#endif
|
||||
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
|
||||
HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
|
||||
defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
|
||||
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
|
||||
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
|
||||
@@ -1607,16 +1851,21 @@ extern "C" {
|
||||
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
|
||||
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
||||
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
|
||||
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
|
||||
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
|
||||
defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
|
||||
defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
|
||||
STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
|
||||
defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||
@@ -1690,6 +1939,107 @@ extern "C" {
|
||||
|
||||
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
|
||||
|
||||
#if defined (STM32U5)
|
||||
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
|
||||
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
|
||||
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
|
||||
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
|
||||
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
|
||||
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
|
||||
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
|
||||
#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
|
||||
#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
|
||||
#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
|
||||
#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
|
||||
#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
|
||||
#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
|
||||
|
||||
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
|
||||
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
|
||||
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
|
||||
|
||||
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
|
||||
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
|
||||
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
|
||||
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
|
||||
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
|
||||
#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
|
||||
#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
|
||||
#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
|
||||
#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
|
||||
#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
|
||||
#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
|
||||
#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
|
||||
#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
|
||||
#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
|
||||
|
||||
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
|
||||
|
||||
#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
|
||||
#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
|
||||
#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
|
||||
#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
|
||||
#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
|
||||
#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
|
||||
#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
|
||||
#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
|
||||
#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
|
||||
#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
|
||||
#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
|
||||
#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
|
||||
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
|
||||
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
|
||||
|
||||
#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
|
||||
#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
|
||||
#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
|
||||
#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
|
||||
#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
|
||||
#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
|
||||
#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
|
||||
#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
|
||||
#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
|
||||
|
||||
|
||||
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
|
||||
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
|
||||
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
|
||||
#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
|
||||
#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
|
||||
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
|
||||
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
|
||||
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
|
||||
#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
|
||||
|
||||
|
||||
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
|
||||
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
|
||||
#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
|
||||
|
||||
#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
|
||||
#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
|
||||
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
|
||||
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
|
||||
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
|
||||
#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
|
||||
|
||||
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
|
||||
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
|
||||
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
|
||||
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
|
||||
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1719,7 +2069,8 @@ extern "C" {
|
||||
#define HAL_TIM_DMAError TIM_DMAError
|
||||
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
||||
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
|
||||
defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
|
||||
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
|
||||
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
|
||||
@@ -1976,7 +2327,8 @@ extern "C" {
|
||||
#define COMP_STOP __HAL_COMP_DISABLE
|
||||
#define COMP_LOCK __HAL_COMP_LOCK
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
|
||||
defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
|
||||
@@ -2148,8 +2500,10 @@ extern "C" {
|
||||
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
|
||||
done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
|
||||
done into HAL_COMP_Init() */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -2308,7 +2662,9 @@ extern "C" {
|
||||
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
|
||||
@@ -2317,8 +2673,12 @@ extern "C" {
|
||||
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
|
||||
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
|
||||
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
|
||||
HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
|
||||
HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
|
||||
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
|
||||
@@ -2354,8 +2714,8 @@ extern "C" {
|
||||
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
|
||||
|
||||
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
|
||||
HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
@@ -2405,6 +2765,12 @@ extern "C" {
|
||||
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
|
||||
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
|
||||
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
|
||||
#if defined(STM32C0)
|
||||
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
|
||||
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
|
||||
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
|
||||
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
|
||||
#endif /* STM32C0 */
|
||||
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
|
||||
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
|
||||
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
|
||||
@@ -2859,6 +3225,11 @@ extern "C" {
|
||||
|
||||
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
|
||||
#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
|
||||
#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
|
||||
#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
|
||||
#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
|
||||
#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
|
||||
#endif
|
||||
|
||||
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
|
||||
@@ -3323,7 +3694,13 @@ extern "C" {
|
||||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
|
||||
#if defined(STM32U0)
|
||||
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
|
||||
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
|
||||
defined(STM32U0)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
@@ -3425,8 +3802,10 @@ extern "C" {
|
||||
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
|
||||
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
|
||||
#if !defined(STM32U0)
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
|
||||
#endif
|
||||
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
|
||||
@@ -3459,7 +3838,100 @@ extern "C" {
|
||||
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
|
||||
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
|
||||
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
|
||||
#endif
|
||||
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
|
||||
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
|
||||
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
|
||||
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
|
||||
|
||||
#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
|
||||
#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
|
||||
#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
|
||||
#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
|
||||
#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
|
||||
#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
|
||||
#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
|
||||
#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
|
||||
#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
|
||||
#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
|
||||
|
||||
#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
|
||||
#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
|
||||
#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
|
||||
#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
|
||||
#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
|
||||
#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
|
||||
#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
|
||||
#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
|
||||
#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
|
||||
#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
|
||||
|
||||
#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
|
||||
#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
|
||||
#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
|
||||
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
|
||||
#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
|
||||
#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
|
||||
#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
|
||||
#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
|
||||
#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
|
||||
#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
|
||||
|
||||
#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
|
||||
#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
|
||||
|
||||
#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
|
||||
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
|
||||
|
||||
#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
|
||||
#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
|
||||
#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
|
||||
#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
|
||||
|
||||
#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
|
||||
#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
|
||||
|
||||
#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
|
||||
#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
|
||||
#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
|
||||
#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
|
||||
|
||||
#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
|
||||
#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
|
||||
#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
|
||||
#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
|
||||
|
||||
#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
|
||||
#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
|
||||
|
||||
#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
|
||||
#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
|
||||
#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
|
||||
#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
|
||||
|
||||
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -3477,7 +3949,10 @@ extern "C" {
|
||||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
|
||||
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
|
||||
defined (STM32WBA) || defined (STM32H5) || \
|
||||
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
@@ -3512,6 +3987,13 @@ extern "C" {
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
#endif /* STM32F1 */
|
||||
|
||||
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
|
||||
defined (STM32H7) || \
|
||||
defined (STM32L0) || defined (STM32L1) || \
|
||||
defined (STM32WB)
|
||||
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
|
||||
#endif
|
||||
|
||||
#define IS_ALARM IS_RTC_ALARM
|
||||
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
|
||||
#define IS_TAMPER IS_RTC_TAMPER
|
||||
@@ -3530,6 +4012,11 @@ extern "C" {
|
||||
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
|
||||
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
|
||||
|
||||
#if defined (STM32H5)
|
||||
#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
|
||||
#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -3759,6 +4246,33 @@ extern "C" {
|
||||
|
||||
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
|
||||
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
|
||||
#if defined(STM32U5)
|
||||
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
|
||||
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
|
||||
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
|
||||
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
|
||||
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
|
||||
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
|
||||
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
|
||||
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
|
||||
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
|
||||
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
|
||||
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
|
||||
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
|
||||
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
|
||||
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
|
||||
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
|
||||
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
|
||||
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
|
||||
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
|
||||
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
|
||||
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
|
||||
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
|
||||
#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
|
||||
#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
|
||||
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
|
||||
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -3788,6 +4302,9 @@ extern "C" {
|
||||
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
|
||||
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
|
||||
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -3878,6 +4395,16 @@ extern "C" {
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F7)
|
||||
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
|
||||
#endif /* STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
+2212
File diff suppressed because it is too large
Load Diff
@@ -859,7 +859,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
||||
* @param _CHANNELNB_ Channel number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
|
||||
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << ((3UL * ((uint32_t)((uint16_t)(_CHANNELNB_)))) & 0x1FUL))
|
||||
|
||||
/**
|
||||
* @brief Set the selected regular channel rank for rank between 1 and 6.
|
||||
|
||||
@@ -102,21 +102,25 @@ typedef struct
|
||||
{
|
||||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
@@ -205,7 +209,11 @@ typedef struct
|
||||
/**
|
||||
* @brief CAN handle Structure definition
|
||||
*/
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
typedef struct __CAN_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
{
|
||||
CAN_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
@@ -329,7 +337,8 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to
|
||||
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
|
||||
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
|
||||
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
|
||||
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
|
||||
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with
|
||||
silent mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -644,7 +653,8 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
|
||||
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID,
|
||||
void (* pCallback)(CAN_HandleTypeDef *_hcan));
|
||||
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
|
||||
|
||||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||
@@ -658,7 +668,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca
|
||||
*/
|
||||
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -674,14 +684,16 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
|
||||
uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
|
||||
const uint8_t aData[], uint32_t *pTxMailbox);
|
||||
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
|
||||
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
|
||||
uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
|
||||
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
|
||||
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
|
||||
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
|
||||
uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
|
||||
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
|
||||
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
|
||||
uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -729,8 +741,8 @@ void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
@@ -808,7 +820,8 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
|
||||
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
|
||||
((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
|
||||
((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
|
||||
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
|
||||
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \
|
||||
CAN_TX_MAILBOX2))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
|
||||
|
||||
@@ -48,70 +48,80 @@ extern "C" {
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
|
||||
It can be one of @ref CEC_Signal_Free_Time
|
||||
It can be one of CEC_Signal_Free_Time
|
||||
and belongs to the set {0,...,7} where
|
||||
0x0 is the default configuration
|
||||
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
|
||||
|
||||
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
|
||||
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
|
||||
or CEC_EXTENDED_TOLERANCE */
|
||||
it can be a value of CEC_Tolerance :
|
||||
it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */
|
||||
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising
|
||||
Error stops the reception.
|
||||
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
|
||||
CEC_RX_STOP_ON_BRE: reception is stopped. */
|
||||
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an
|
||||
Error-Bit is generated on the
|
||||
CEC line upon Bit Rising Error detection.
|
||||
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
|
||||
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an
|
||||
Error-Bit is generated on the
|
||||
CEC line upon Long Bit Period Error detection.
|
||||
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
|
||||
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an
|
||||
Error-Bit generation on the CEC line
|
||||
upon an error detected on a broadcast message.
|
||||
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error
|
||||
handling. It can take two values:
|
||||
|
||||
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
|
||||
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if
|
||||
BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
b) LBPE detection: error-bit generation on the CEC line
|
||||
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
|
||||
|
||||
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
|
||||
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
|
||||
there is no error-bit generation in case of Short Bit Period Error detection in
|
||||
a broadcast message while LSTN bit is set. */
|
||||
no error-bit generation in case neither a) nor b) are satisfied.
|
||||
Additionally, there is no error-bit generation in case of Short Bit
|
||||
Period Error detection in a broadcast message while LSTN bit is set. */
|
||||
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts.
|
||||
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end
|
||||
of message transmission/reception. */
|
||||
|
||||
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
|
||||
uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode.
|
||||
It can take two values:
|
||||
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
|
||||
own address (OAR). Messages addressed to different destination are ignored.
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed
|
||||
to its own address (OAR). Messages addressed to different destination
|
||||
are ignored.
|
||||
Broadcast messages are always received.
|
||||
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
|
||||
address (OAR) with positive acknowledge. Messages addressed to different destination
|
||||
are received, but without interfering with the CEC bus: no acknowledge sent. */
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its
|
||||
own address (OAR) with positive acknowledge. Messages addressed to
|
||||
different destination are received, but without interfering with the
|
||||
CEC bus: no acknowledge sent. */
|
||||
|
||||
uint16_t OwnAddress; /*!< Own addresses configuration
|
||||
This parameter can be a value of @ref CEC_OWN_ADDRESS */
|
||||
This parameter can be a value of CEC_OWN_ADDRESS */
|
||||
|
||||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
|
||||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
|
||||
|
||||
|
||||
} CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC State definition
|
||||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
|
||||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState
|
||||
(see CEC_State_Definition).
|
||||
* - gState contains CEC state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
@@ -163,7 +173,7 @@ typedef struct
|
||||
|
||||
CEC_InitTypeDef Init; /*!< CEC communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
|
||||
|
||||
@@ -173,10 +183,10 @@ typedef struct
|
||||
|
||||
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||
This parameter can be a value of HAL_CEC_StateTypeDef */
|
||||
|
||||
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||
This parameter can be a value of HAL_CEC_StateTypeDef */
|
||||
|
||||
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
|
||||
in case error is reported */
|
||||
@@ -212,7 +222,8 @@ typedef enum
|
||||
*/
|
||||
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
|
||||
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
|
||||
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed
|
||||
callback function */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
@@ -622,7 +633,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
||||
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \
|
||||
(__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -660,8 +672,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
|
||||
uint8_t *pData, uint32_t Size);
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
|
||||
const uint8_t *pData, uint32_t Size);
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
@@ -675,8 +687,8 @@ void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -731,7 +743,8 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
||||
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
|
||||
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
|
||||
@@ -789,4 +802,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
||||
#endif
|
||||
|
||||
#endif /* STM32F7xxHAL_CEC_H */
|
||||
|
||||
|
||||
@@ -45,6 +45,7 @@
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_DMA2D_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
@@ -146,7 +147,7 @@
|
||||
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 1U /* To enable prefetch */
|
||||
#define ART_ACCLERATOR_ENABLE 1U /* To enable ART Accelerator */
|
||||
#define ART_ACCELERATOR_ENABLE 1U /* To enable ART Accelerator */
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
|
||||
@@ -207,8 +208,8 @@
|
||||
#define MAC_ADDR5 0U
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RX_BUF_SIZE 1528U /* ETH Max buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE 1528U /* ETH Max buffer size for transmit */
|
||||
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
@@ -330,6 +331,10 @@
|
||||
#include "stm32f7xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_eth_legacy.h"
|
||||
#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
@@ -274,6 +274,8 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
#if (__MPU_PRESENT == 1)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
|
||||
@@ -318,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -51,7 +51,8 @@ typedef struct
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
|
||||
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
|
||||
128 or 256 bit key length in TinyAES This parameter can be a value
|
||||
of @ref CRYP_Key_Size */
|
||||
uint32_t *pKey; /*!< The key used for encryption/decryption */
|
||||
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
|
||||
counter in CTR mode */
|
||||
@@ -402,8 +403,11 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
|
||||
*/
|
||||
#define CRYP_FLAG_MASK 0x0000001FU
|
||||
#if defined(CRYP)
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
|
||||
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)? \
|
||||
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) \
|
||||
& CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
|
||||
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK))\
|
||||
== ((__FLAG__) & CRYP_FLAG_MASK)))
|
||||
#else /* AES*/
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
@@ -398,7 +398,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
|
||||
@@ -424,8 +424,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
|
||||
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -434,8 +435,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -471,4 +472,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
|
||||
|
||||
#endif /* STM32F7xx_HAL_DAC_H */
|
||||
|
||||
|
||||
@@ -81,6 +81,7 @@ extern "C" {
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -149,7 +150,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
@@ -198,4 +199,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
#endif
|
||||
|
||||
#endif /* STM32F7xx_HAL_DAC_EX_H */
|
||||
|
||||
|
||||
@@ -56,7 +56,7 @@ typedef enum
|
||||
} HAL_DCMI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMIEx Embedded Synchronisation CODE Init structure definition
|
||||
* @brief DCMI Embedded Synchronisation CODE Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
@@ -67,7 +67,7 @@ typedef struct
|
||||
} DCMI_CodesInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI Embedded Synchronisation CODE Init structure definition
|
||||
* @brief DCMI Embedded Synchronisation UNMASK Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
@@ -116,6 +116,7 @@ typedef struct
|
||||
This parameter can be a value of @ref DCMI_Line_Select_Mode */
|
||||
|
||||
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
|
||||
by the interface is even or odd
|
||||
This parameter can be a value of @ref DCMI_Line_Select_Start */
|
||||
#endif
|
||||
} DCMI_InitTypeDef;
|
||||
@@ -123,7 +124,11 @@ typedef struct
|
||||
/**
|
||||
* @brief DCMI handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __DCMI_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
{
|
||||
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
|
||||
|
||||
@@ -144,6 +149,7 @@ typedef struct __DCMI_HandleTypeDef
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DCMI Error code */
|
||||
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
|
||||
void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
|
||||
@@ -155,6 +161,9 @@ typedef struct __DCMI_HandleTypeDef
|
||||
} DCMI_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DCMI Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */
|
||||
@@ -166,7 +175,10 @@ typedef enum
|
||||
|
||||
} HAL_DCMI_CallbackIDTypeDef;
|
||||
|
||||
typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @brief HAL DCMI Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); /*!< pointer to a DCMI callback function */
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
@@ -182,14 +194,14 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Error_Code DCMI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */
|
||||
#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */
|
||||
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
|
||||
#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */
|
||||
#define HAL_DCMI_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_DCMI_ERROR_OVR (0x00000001U) /*!< Overrun error */
|
||||
#define HAL_DCMI_ERROR_SYNC (0x00000002U) /*!< Synchronization error */
|
||||
#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_DCMI_ERROR_DMA (0x00000040U) /*!< DMA error */
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid callback error */
|
||||
#endif
|
||||
#define HAL_DCMI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -197,10 +209,11 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously
|
||||
#define DCMI_MODE_CONTINUOUS (0x00000000U) /*!< The received data are transferred continuously
|
||||
into the destination memory through the DMA */
|
||||
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
|
||||
frame and then transfers a single frame through the DMA */
|
||||
frame and then transfers a single frame
|
||||
through the DMA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -208,10 +221,10 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
|
||||
#define DCMI_SYNCHRO_HARDWARE (0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
|
||||
is synchronized with the HSYNC/VSYNC signals */
|
||||
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
|
||||
synchronization codes embedded in the data flow */
|
||||
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized
|
||||
with synchronization codes embedded in the data flow */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -220,7 +233,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */
|
||||
#define DCMI_PCKPOLARITY_FALLING (0x00000000U) /*!< Pixel clock active on Falling edge */
|
||||
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
|
||||
|
||||
/**
|
||||
@@ -230,7 +243,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */
|
||||
#define DCMI_VSPOLARITY_LOW (0x00000000U) /*!< Vertical synchronization active Low */
|
||||
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
|
||||
|
||||
/**
|
||||
@@ -240,7 +253,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */
|
||||
#define DCMI_HSPOLARITY_LOW (0x00000000U) /*!< Horizontal synchronization active Low */
|
||||
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
|
||||
|
||||
/**
|
||||
@@ -250,7 +263,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< Mode JPEG Disabled */
|
||||
#define DCMI_JPEG_DISABLE (0x00000000U) /*!< Mode JPEG Disabled */
|
||||
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
|
||||
|
||||
/**
|
||||
@@ -260,7 +273,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */
|
||||
#define DCMI_CR_ALL_FRAME (0x00000000U) /*!< All frames are captured */
|
||||
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
|
||||
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
|
||||
|
||||
@@ -271,10 +284,11 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_8B (0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 |\
|
||||
DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -283,7 +297,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */
|
||||
#define DCMI_WINDOW_COORDINATE (0x3FFFU) /*!< Window coordinate */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -292,7 +306,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Window_Height DCMI Window Height
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */
|
||||
#define DCMI_WINDOW_HEIGHT (0x1FFFU) /*!< Window Height */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -317,8 +331,10 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @brief DCMI SR register
|
||||
*/
|
||||
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
|
||||
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
|
||||
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization
|
||||
between lines) */
|
||||
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization
|
||||
between frames) */
|
||||
#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
|
||||
/**
|
||||
* @brief DCMI RIS register
|
||||
@@ -331,7 +347,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @brief DCMI MIS register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
|
||||
#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked
|
||||
interrupt status */
|
||||
#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
|
||||
#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
|
||||
#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
|
||||
@@ -343,10 +360,12 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_BSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received data */
|
||||
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
|
||||
#define DCMI_BSM_ALL (0x00000000U) /*!< Interface captures all received data */
|
||||
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte
|
||||
from the received data */
|
||||
#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
|
||||
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
|
||||
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 |\
|
||||
DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -355,8 +374,10 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_OEBS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
|
||||
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
|
||||
#define DCMI_OEBS_ODD (0x00000000U) /*!< Interface captures first data from the frame/line start,
|
||||
second one being dropped */
|
||||
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from
|
||||
the frame/line start, first one being dropped */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -365,7 +386,7 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_LSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received lines */
|
||||
#define DCMI_LSM_ALL (0x00000000U) /*!< Interface captures all received lines */
|
||||
#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
|
||||
|
||||
/**
|
||||
@@ -375,8 +396,10 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_OELS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
|
||||
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
|
||||
#define DCMI_OELS_ODD (0x00000000U) /*!< Interface captures first line from the frame start,
|
||||
second one being dropped */
|
||||
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start,
|
||||
first one being dropped */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -395,11 +418,15 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
* @param __HANDLE__ specifies the DCMI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the DCMI.
|
||||
@@ -438,7 +465,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
*/
|
||||
#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
|
||||
(((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
|
||||
(((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) :\
|
||||
((__HANDLE__)->Instance->SR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the DCMI pending flags.
|
||||
@@ -516,7 +544,8 @@ void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID,
|
||||
pDCMI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
@@ -544,10 +573,11 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize,
|
||||
uint32_t YSize);
|
||||
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -557,8 +587,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
|
||||
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi);
|
||||
uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -573,8 +603,24 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
|
||||
/** @defgroup DCMI_Private_Constants DCMI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DCMI_MIS_INDEX DCMI Mis Index
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_SR_INDEX DCMI SR Index
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -653,4 +699,3 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
|
||||
#endif
|
||||
|
||||
#endif /* STM32F7xx_HAL_DCMI_H */
|
||||
|
||||
|
||||
@@ -54,7 +54,9 @@ typedef enum
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
#if !defined(UNUSED)
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||
#endif /* UNUSED */
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
|
||||
@@ -581,11 +581,11 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
|
||||
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
|
||||
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
|
||||
|
||||
void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
@@ -597,7 +597,7 @@ void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
* @{
|
||||
*/
|
||||
/* Channel state function *****************************************************/
|
||||
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -658,16 +658,16 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
DFSDM_Filter_AwdParamTypeDef* awdParam);
|
||||
const DFSDM_Filter_AwdParamTypeDef* awdParam);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
|
||||
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
|
||||
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
|
||||
@@ -688,8 +688,8 @@ void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
* @{
|
||||
*/
|
||||
/* Filter state functions *****************************************************/
|
||||
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -484,9 +484,9 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
@@ -523,8 +523,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ***************************************************/
|
||||
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
|
||||
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d);
|
||||
uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -976,7 +976,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
||||
#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
/* Delay after an DSI warpper enabling */ \
|
||||
/* Delay after an DSI wrapper enabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
@@ -989,7 +989,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
||||
#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
/* Delay after an DSI warpper disabling*/ \
|
||||
/* Delay after an DSI wrapper disabling*/ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
@@ -1184,7 +1184,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
|
||||
uint32_t Mode,
|
||||
uint32_t NbParams,
|
||||
uint32_t Param1,
|
||||
uint8_t *ParametersTable);
|
||||
const uint8_t *ParametersTable);
|
||||
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
|
||||
uint32_t ChannelNbr,
|
||||
uint8_t *Array,
|
||||
@@ -1222,8 +1222,8 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
|
||||
* @brief Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
|
||||
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
|
||||
uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi);
|
||||
HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -1271,10 +1271,10 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
|
||||
|| ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
|
||||
#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
|
||||
|| ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
|
||||
#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\
|
||||
|| ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\
|
||||
|| ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\
|
||||
|| ((Vsync) == DSI_VSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\
|
||||
|| ((Hsync) == DSI_HSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
|
||||
((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
|
||||
((VideoModeType) == DSI_VID_MODE_BURST))
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -459,7 +459,7 @@
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
@@ -490,7 +490,7 @@
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
@@ -520,7 +520,7 @@
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
@@ -553,7 +553,7 @@
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
@@ -615,7 +615,7 @@
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM14) || \
|
||||
((AF) == GPIO_AF9_TIM13) || ((AF) == GPIO_AF9_TIM14) || \
|
||||
((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_HS) || \
|
||||
((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || \
|
||||
((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
|
||||
|
||||
@@ -117,13 +117,13 @@ typedef struct
|
||||
{
|
||||
HASH_InitTypeDef Init; /*!< HASH required parameters */
|
||||
|
||||
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
|
||||
uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */
|
||||
|
||||
uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
|
||||
|
||||
uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
|
||||
|
||||
uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
|
||||
uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
|
||||
|
||||
uint32_t HashBuffSize; /*!< Size of buffer to be processed */
|
||||
|
||||
@@ -476,15 +476,17 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
|
||||
|
||||
|
||||
/* HASH processing using polling *********************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
|
||||
@@ -497,15 +499,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
|
||||
*/
|
||||
|
||||
/* HASH processing using IT **************************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
@@ -517,9 +519,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
*/
|
||||
|
||||
/* HASH processing using DMA *************************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
@@ -531,9 +533,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu
|
||||
*/
|
||||
|
||||
/* HASH-MAC processing using polling *****************************************/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
|
||||
/**
|
||||
@@ -544,9 +548,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
@@ -558,8 +562,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
|
||||
*/
|
||||
|
||||
/* HASH-HMAC processing using DMA ********************************************/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -571,13 +575,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
|
||||
|
||||
|
||||
/* Peripheral State methods **************************************************/
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer);
|
||||
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer);
|
||||
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
|
||||
uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -594,19 +598,27 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
|
||||
*/
|
||||
|
||||
/* Private functions */
|
||||
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
|
||||
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -50,15 +50,15 @@ extern "C" {
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
@@ -69,15 +69,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
@@ -87,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
||||
/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
@@ -99,9 +101,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p
|
||||
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
@@ -111,9 +113,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
@@ -124,8 +126,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -135,20 +137,24 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -159,6 +159,10 @@ typedef struct
|
||||
|
||||
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \
|
||||
((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
|
||||
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
@@ -167,6 +171,9 @@ typedef struct
|
||||
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
|
||||
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
|
||||
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
|
||||
#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT)
|
||||
#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT)
|
||||
#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -248,6 +255,11 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n
|
||||
uint8_t token, uint8_t *pbuff,
|
||||
uint16_t length, uint8_t do_ping);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t addr, uint8_t PortNbr);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
@@ -277,16 +289,13 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
||||
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
|
||||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
|
||||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
|
||||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -307,6 +316,9 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -118,8 +118,6 @@ typedef enum
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
@@ -207,6 +205,7 @@ typedef struct __I2C_HandleTypeDef
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
@@ -217,6 +216,10 @@ typedef struct __I2C_HandleTypeDef
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
__IO uint32_t Devaddress; /*!< I2C Target device address */
|
||||
|
||||
__IO uint32_t Memaddress; /*!< I2C Target memory address */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Tx Transfer completed callback */
|
||||
@@ -705,9 +708,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -800,8 +803,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
|
||||
(~I2C_CR2_RD_WRN)))
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
|
||||
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
@@ -462,8 +462,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
|
||||
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s);
|
||||
uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -361,6 +361,9 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_ISR_REACK)
|
||||
#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
|
||||
#endif /* USART_ISR_REACK */
|
||||
#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
|
||||
#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
|
||||
#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
|
||||
@@ -520,6 +523,9 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
#if defined(USART_ISR_REACK)
|
||||
* @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
|
||||
#endif
|
||||
* @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_BUSY Busy flag
|
||||
* @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
|
||||
@@ -824,8 +830,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -388,6 +388,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
|
||||
* @brief Write the passed parameter in the Autoreload register.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __VALUE__ Autoreload value
|
||||
* This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF.
|
||||
* @retval None
|
||||
* @note The ARR register can only be modified when the LPTIM instance is enabled.
|
||||
*/
|
||||
@@ -664,9 +665,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
* @{
|
||||
*/
|
||||
/* Reading operation functions ************************************************/
|
||||
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -702,7 +703,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -793,11 +794,10 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
|
||||
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
|
||||
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
|
||||
#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\
|
||||
((__PERIOD__) <= 0x0000FFFFUL))
|
||||
|
||||
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
|
||||
|
||||
|
||||
@@ -79,28 +79,36 @@ typedef struct
|
||||
This parameter can be one of value of @ref LTDC_PC_POLARITY */
|
||||
|
||||
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x000 and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x000 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
|
||||
This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
|
||||
This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
|
||||
This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
|
||||
This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t TotalWidth; /*!< configures the total width.
|
||||
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t TotalHeigh; /*!< configures the total height.
|
||||
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
|
||||
|
||||
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
|
||||
} LTDC_InitTypeDef;
|
||||
@@ -111,25 +119,31 @@ typedef struct
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x000 and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x000 and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x000 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t PixelFormat; /*!< Specifies the pixel format.
|
||||
This parameter can be one of value of @ref LTDC_Pixelformat */
|
||||
|
||||
uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
|
||||
uint32_t Alpha0; /*!< Configures the default alpha value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
|
||||
uint32_t BlendingFactor1; /*!< Select the blending factor 1.
|
||||
This parameter can be one of value of @ref LTDC_BlendingFactor1 */
|
||||
@@ -140,10 +154,12 @@ typedef struct
|
||||
uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
|
||||
|
||||
uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0x1FFF. */
|
||||
|
||||
uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x000 and Max_Data = 0x7FF. */
|
||||
|
||||
LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
|
||||
} LTDC_LayerCfgTypeDef;
|
||||
@@ -429,7 +445,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer
|
||||
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
|
||||
#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
|
||||
|= (uint32_t)LTDC_LxCR_LEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the LTDC Layer.
|
||||
@@ -438,7 +455,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer
|
||||
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
|
||||
#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
|
||||
&= ~(uint32_t)LTDC_LxCR_LEN)
|
||||
|
||||
/**
|
||||
* @brief Reload immediately all LTDC Layers.
|
||||
@@ -544,7 +562,8 @@ void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
|
||||
pLTDC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
||||
|
||||
@@ -573,7 +592,8 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u
|
||||
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
@@ -582,9 +602,12 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t
|
||||
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
|
||||
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
|
||||
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
|
||||
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
|
||||
@@ -603,8 +626,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
|
||||
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
|
||||
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc);
|
||||
uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -620,12 +643,18 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
|
||||
/** @defgroup LTDC_Private_Macros LTDC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
|
||||
#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\
|
||||
((uint32_t)((__HANDLE__)->Instance))\
|
||||
+ 0x84U + (0x80U*(__LAYER__)))))
|
||||
#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
|
||||
#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
|
||||
#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
|
||||
#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
|
||||
#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
|
||||
#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\
|
||||
|| ((__HSPOL__) == LTDC_HSPOLARITY_AH))
|
||||
#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\
|
||||
|| ((__VSPOL__) == LTDC_VSPOLARITY_AH))
|
||||
#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\
|
||||
|| ((__DEPOL__) == LTDC_DEPOLARITY_AH))
|
||||
#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\
|
||||
|| ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
|
||||
#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
|
||||
#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
|
||||
#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
|
||||
@@ -641,10 +670,14 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
|
||||
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
|
||||
#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
|
||||
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
|
||||
#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
|
||||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
|
||||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
|
||||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
|
||||
#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \
|
||||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
|
||||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \
|
||||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
|
||||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \
|
||||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
|
||||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \
|
||||
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
|
||||
#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
|
||||
#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
|
||||
#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
|
||||
@@ -654,7 +687,8 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
|
||||
#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
|
||||
#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
|
||||
#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
|
||||
#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
|
||||
#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \
|
||||
((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -683,3 +717,4 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
|
||||
#endif
|
||||
|
||||
#endif /* STM32F7xx_HAL_LTDC_H */
|
||||
|
||||
|
||||
@@ -104,9 +104,8 @@ typedef struct
|
||||
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
|
||||
parameter is mandatory for some NAND parts after the read
|
||||
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
|
||||
Example: Toshiba THTH58BYG3S0HBAI6.
|
||||
This parameter could be ENABLE or DISABLE
|
||||
Please check the Read Mode sequnece in the NAND device datasheet */
|
||||
Please check the Read Mode sequence in the NAND device datasheet */
|
||||
} NAND_DeviceConfigTypeDef;
|
||||
|
||||
/**
|
||||
@@ -126,7 +125,7 @@ typedef struct
|
||||
|
||||
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
|
||||
|
||||
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
|
||||
NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
|
||||
@@ -194,7 +193,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
|
||||
FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
|
||||
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
|
||||
|
||||
@@ -214,27 +213,27 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
|
||||
/* IO operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
|
||||
uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
|
||||
uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint8_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
|
||||
uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
|
||||
uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint16_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
|
||||
|
||||
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
/* NAND callback registering/unregistering */
|
||||
@@ -264,8 +263,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
|
||||
* @{
|
||||
*/
|
||||
/* NAND State functions *******************************************************/
|
||||
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
|
||||
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
||||
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
|
||||
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
|
||||
*/
|
||||
|
||||
/* NOR State functions ********************************************************/
|
||||
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
|
||||
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
|
||||
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -106,6 +106,7 @@ typedef struct
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
||||
uint32_t BESL;
|
||||
uint32_t FrameNumber; /*!< Store Current Frame number */
|
||||
|
||||
|
||||
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
|
||||
@@ -185,13 +186,13 @@ typedef struct
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
|
||||
((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
|
||||
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
@@ -284,12 +285,10 @@ typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgType
|
||||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
|
||||
HAL_PCD_CallbackIDTypeDef CallbackID,
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
|
||||
pPCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
|
||||
HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataOutStageCallbackTypeDef pCallback);
|
||||
@@ -311,9 +310,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_LpmCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
@@ -353,24 +350,21 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint16_t ep_mps, uint8_t ep_type);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint8_t *pBuf, uint32_t len);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint8_t *pBuf, uint32_t len);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode);
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode);
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -379,7 +373,7 @@ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr
|
||||
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -45,7 +45,6 @@ extern "C" {
|
||||
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
||||
|
||||
@@ -456,7 +456,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset QSPI handle state.
|
||||
* @param __HANDLE__ : QSPI handle.
|
||||
* @param __HANDLE__ QSPI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
@@ -470,20 +470,20 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
|
||||
#endif
|
||||
|
||||
/** @brief Enable the QSPI peripheral.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
|
||||
|
||||
/** @brief Disable the QSPI peripheral.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
|
||||
|
||||
/** @brief Enable the specified QSPI interrupt.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
@@ -496,8 +496,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
|
||||
/** @brief Disable the specified QSPI interrupt.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
@@ -509,8 +509,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
|
||||
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ specifies the QSPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
@@ -523,8 +523,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/**
|
||||
* @brief Check whether the selected QSPI flag is set or not.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __FLAG__ : specifies the QSPI flag to check.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __FLAG__ specifies the QSPI flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
|
||||
* @arg QSPI_FLAG_TO: QSPI Timeout flag
|
||||
@@ -537,8 +537,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
|
||||
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clears the specified QSPI's flag status.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __FLAG__ specifies the QSPI clear register flag that needs to be set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_FLAG_TO: QSPI Timeout flag
|
||||
* @arg QSPI_FLAG_SM: QSPI Status match flag
|
||||
@@ -623,13 +623,13 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi,
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
|
||||
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi);
|
||||
uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
|
||||
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
|
||||
uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -1133,8 +1133,8 @@ typedef struct
|
||||
*/
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_RCC_DeInit(void);
|
||||
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
||||
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
|
||||
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct);
|
||||
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -1326,6 +1326,9 @@ typedef struct
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
|
||||
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
|
||||
defined (STM32F750xx)
|
||||
#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
|
||||
@@ -1333,6 +1336,7 @@ typedef struct
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
||||
|
||||
#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
@@ -1415,7 +1419,13 @@ typedef struct
|
||||
#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
|
||||
#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
|
||||
#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
|
||||
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
|
||||
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
|
||||
defined (STM32F750xx)
|
||||
#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
||||
|
||||
#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
|
||||
#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
|
||||
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
|
||||
@@ -1664,7 +1674,13 @@ typedef struct
|
||||
#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
|
||||
#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
|
||||
#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
|
||||
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
|
||||
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
|
||||
defined (STM32F750xx)
|
||||
#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
||||
|
||||
#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
|
||||
#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
|
||||
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
|
||||
@@ -1699,7 +1715,13 @@ typedef struct
|
||||
#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
|
||||
#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
|
||||
#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
|
||||
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
|
||||
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
|
||||
defined (STM32F750xx)
|
||||
#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
||||
|
||||
#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
|
||||
#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
|
||||
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
|
||||
@@ -1897,7 +1919,13 @@ typedef struct
|
||||
#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
|
||||
#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
|
||||
#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
|
||||
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
|
||||
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
|
||||
defined (STM32F750xx)
|
||||
#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
||||
|
||||
#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
|
||||
#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
|
||||
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
|
||||
@@ -1919,7 +1947,13 @@ typedef struct
|
||||
#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
|
||||
#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
|
||||
#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
|
||||
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
|
||||
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
|
||||
defined (STM32F750xx)
|
||||
#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
||||
|
||||
#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
|
||||
#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
|
||||
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
|
||||
|
||||
@@ -304,7 +304,7 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef
|
||||
*hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng);
|
||||
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
|
||||
@@ -317,8 +317,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
|
||||
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -17,14 +17,15 @@
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_RTC_H
|
||||
#define __STM32F7xx_HAL_RTC_H
|
||||
#ifndef STM32F7xx_HAL_RTC_H
|
||||
#define STM32F7xx_HAL_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
@@ -36,6 +37,7 @@
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Types RTC Exported Types
|
||||
* @{
|
||||
*/
|
||||
@@ -50,7 +52,6 @@ typedef enum
|
||||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
|
||||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
|
||||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
|
||||
|
||||
} HAL_RTCStateTypeDef;
|
||||
|
||||
/**
|
||||
@@ -65,10 +66,10 @@ typedef struct
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FFF */
|
||||
|
||||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
|
||||
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
|
||||
This parameter can be a value of @ref RTC_Output_selection_Definitions */
|
||||
|
||||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
|
||||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
|
||||
@@ -83,7 +84,7 @@ typedef struct
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
|
||||
|
||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
@@ -92,24 +93,24 @@ typedef struct
|
||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
|
||||
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
|
||||
This parameter corresponds to a time unit range between [0-1] Second
|
||||
with [1 Sec / SecondFraction +1] granularity */
|
||||
|
||||
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
|
||||
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
|
||||
corresponding to Synchronous prescaler factor value (PREDIV_S)
|
||||
This parameter corresponds to a time unit range between [0-1] Second
|
||||
with [1 Sec / SecondFraction +1] granularity.
|
||||
This field will be used only by HAL_RTC_GetTime function */
|
||||
|
||||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight
|
||||
Saving Time, please use HAL_RTC_DST_xxx functions */
|
||||
|
||||
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time,
|
||||
please use HAL_RTC_DST_xxx functions */
|
||||
|
||||
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time,
|
||||
please use HAL_RTC_DST_xxx functions */
|
||||
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight
|
||||
Saving Time, please use HAL_RTC_DST_xxx functions */
|
||||
} RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
@@ -162,7 +163,7 @@ typedef struct
|
||||
typedef struct __RTC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
{
|
||||
RTC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
@@ -177,7 +178,7 @@ typedef struct
|
||||
|
||||
void (* AlarmBEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */
|
||||
|
||||
void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */
|
||||
void (* TimeStampEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Timestamp Event callback */
|
||||
|
||||
void (* WakeUpTimerEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
|
||||
|
||||
@@ -191,7 +192,7 @@ typedef struct
|
||||
|
||||
void (* MspDeInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
|
||||
} RTC_HandleTypeDef;
|
||||
|
||||
@@ -201,15 +202,15 @@ typedef struct
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
|
||||
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */
|
||||
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */
|
||||
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */
|
||||
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
|
||||
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */
|
||||
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06u, /*!< RTC Tamper 3 Callback ID */
|
||||
HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
|
||||
HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
|
||||
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */
|
||||
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */
|
||||
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC Timestamp Event Callback ID */
|
||||
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC Wakeup Timer Event Callback ID */
|
||||
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
|
||||
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
|
||||
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
|
||||
HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
|
||||
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
|
||||
} HAL_RTC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
@@ -223,6 +224,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
@@ -231,17 +233,27 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT_24 0x00000000U
|
||||
#define RTC_HOURFORMAT_12 0x00000040U
|
||||
#define RTC_HOURFORMAT_12 RTC_CR_FMT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_DISABLE 0x00000000U
|
||||
#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
|
||||
#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
|
||||
#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
|
||||
#define RTC_OUTPUT_POLARITY_LOW 0x00100000U
|
||||
#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -250,7 +262,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
|
||||
#define RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMTYPE /* 0x00000008 */
|
||||
#define RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMOUTTYPE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -258,8 +270,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
|
||||
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U)
|
||||
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
|
||||
#define RTC_HOURFORMAT12_PM ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -267,8 +279,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U
|
||||
#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U
|
||||
#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
|
||||
#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
|
||||
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
@@ -278,7 +290,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @{
|
||||
*/
|
||||
#define RTC_STOREOPERATION_RESET 0x00000000U
|
||||
#define RTC_STOREOPERATION_SET 0x00040000U
|
||||
#define RTC_STOREOPERATION_SET RTC_CR_BKP
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -292,22 +304,21 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
|
||||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format)
|
||||
* @{
|
||||
*/
|
||||
/* Coded in BCD format */
|
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
|
||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
|
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03U)
|
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04U)
|
||||
#define RTC_MONTH_MAY ((uint8_t)0x05U)
|
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06U)
|
||||
#define RTC_MONTH_JULY ((uint8_t)0x07U)
|
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
|
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
|
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
|
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
|
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
|
||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
|
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03)
|
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04)
|
||||
#define RTC_MONTH_MAY ((uint8_t)0x05)
|
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06)
|
||||
#define RTC_MONTH_JULY ((uint8_t)0x07)
|
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
|
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
|
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
|
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -315,13 +326,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
|
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
|
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
|
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
|
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
|
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
|
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
|
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
|
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
|
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
|
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
|
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
|
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
|
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -330,7 +341,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -343,7 +354,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
|
||||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
|
||||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
|
||||
#define RTC_ALARMMASK_ALL 0x80808080U
|
||||
#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | \
|
||||
RTC_ALARMMASK_HOURS | \
|
||||
RTC_ALARMMASK_MINUTES | \
|
||||
RTC_ALARMMASK_SECONDS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -360,39 +374,38 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
/*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
|
||||
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U
|
||||
/*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
|
||||
/*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
|
||||
/*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
|
||||
/*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
|
||||
/*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
|
||||
/*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
|
||||
/*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
|
||||
/*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
|
||||
/*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
|
||||
/*!< SS[14:0] are compared and must match to activate alarm. */
|
||||
#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -400,14 +413,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS RTC_CR_TSIE
|
||||
#define RTC_IT_WUT RTC_CR_WUTIE
|
||||
#define RTC_IT_ALRA RTC_CR_ALRAIE
|
||||
#define RTC_IT_ALRB RTC_CR_ALRBIE
|
||||
#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE
|
||||
#define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE
|
||||
#define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE
|
||||
#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */
|
||||
#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */
|
||||
#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */
|
||||
#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -415,23 +424,23 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
|
||||
#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
|
||||
#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
|
||||
#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
|
||||
#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
|
||||
#define RTC_FLAG_TSF RTC_ISR_TSF
|
||||
#define RTC_FLAG_ITSF RTC_ISR_ITSF
|
||||
#define RTC_FLAG_WUTF RTC_ISR_WUTF
|
||||
#define RTC_FLAG_ALRBF RTC_ISR_ALRBF
|
||||
#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
|
||||
#define RTC_FLAG_INITF RTC_ISR_INITF
|
||||
#define RTC_FLAG_RSF RTC_ISR_RSF
|
||||
#define RTC_FLAG_INITS RTC_ISR_INITS
|
||||
#define RTC_FLAG_SHPF RTC_ISR_SHPF
|
||||
#define RTC_FLAG_WUTWF RTC_ISR_WUTWF
|
||||
#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF
|
||||
#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
|
||||
#define RTC_FLAG_RECALPF RTC_ISR_RECALPF /*!< Recalibration pending flag */
|
||||
#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F /*!< Tamper 3 event flag */
|
||||
#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F /*!< Tamper 2 event flag */
|
||||
#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F /*!< Tamper 1 event flag */
|
||||
#define RTC_FLAG_TSOVF RTC_ISR_TSOVF /*!< Timestamp overflow flag */
|
||||
#define RTC_FLAG_TSF RTC_ISR_TSF /*!< Timestamp event flag */
|
||||
#define RTC_FLAG_ITSF RTC_ISR_ITSF /*!< Internal Timestamp event flag */
|
||||
#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Wakeup timer event flag */
|
||||
#define RTC_FLAG_ALRBF RTC_ISR_ALRBF /*!< Alarm B event flag */
|
||||
#define RTC_FLAG_ALRAF RTC_ISR_ALRAF /*!< Alarm A event flag */
|
||||
#define RTC_FLAG_INITF RTC_ISR_INITF /*!< RTC in initialization mode flag */
|
||||
#define RTC_FLAG_RSF RTC_ISR_RSF /*!< Register synchronization flag */
|
||||
#define RTC_FLAG_INITS RTC_ISR_INITS /*!< RTC initialization status flag */
|
||||
#define RTC_FLAG_SHPF RTC_ISR_SHPF /*!< Shift operation pending flag */
|
||||
#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< WUTR register write allowance flag */
|
||||
#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF /*!< ALRMBR register write allowance flag */
|
||||
#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /*!< ALRMAR register write allowance flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -440,7 +449,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Macros RTC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
@@ -454,7 +464,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
(__HANDLE__)->State = HAL_RTC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
}while(0u)
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
@@ -464,8 +474,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do { \
|
||||
(__HANDLE__)->Instance->WPR = 0xCAU; \
|
||||
(__HANDLE__)->Instance->WPR = 0x53U; \
|
||||
} while(0U)
|
||||
@@ -475,11 +484,17 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do { \
|
||||
(__HANDLE__)->Instance->WPR = 0xFFU; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Calendar is initialized.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
@@ -539,31 +554,31 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) & 0x0000FFFFU) != RESET)? SET : RESET)
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarm's flag status.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Alarm Flag to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @arg RTC_FLAG_ALRBF
|
||||
* @arg RTC_FLAG_ALRAWF
|
||||
* @arg RTC_FLAG_ALRBWF
|
||||
* @arg RTC_FLAG_ALRAF: Alarm A interrupt flag
|
||||
* @arg RTC_FLAG_ALRAWF: Alarm A 'write allowed' flag
|
||||
* @arg RTC_FLAG_ALRBF: Alarm B interrupt flag
|
||||
* @arg RTC_FLAG_ALRBWF: Alarm B 'write allowed' flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm's pending flags.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||
* @param __FLAG__ specifies the RTC Alarm flag to be cleared.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @arg RTC_FLAG_ALRBF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFFU)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
||||
@@ -574,82 +589,88 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
|
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Alarm associated Exti line.
|
||||
* @brief Enable interrupt on the RTC Alarm associated EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Alarm associated Exti line.
|
||||
* @brief Disable interrupt on the RTC Alarm associated EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Alarm associated Exti line.
|
||||
* @brief Enable event on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Alarm associated Exti line.
|
||||
* @brief Disable event on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @brief Enable falling edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @brief Disable falling edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @brief Enable rising edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @brief Disable rising edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @brief Enable rising & falling edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @brief Disable rising & falling edge trigger on the RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
|
||||
* @brief Check whether the RTC Alarm associated EXTI line interrupt flag is set or not.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm associated Exti line flag.
|
||||
* @brief Clear the RTC Alarm associated EXTI line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on RTC Alarm associated Exti line.
|
||||
* @brief Generate a Software interrupt on RTC Alarm associated EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
@@ -657,10 +678,11 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include RTC HAL Extension module */
|
||||
/* Include RTC HAL Extended module */
|
||||
#include "stm32f7xx_hal_rtc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
@@ -691,11 +713,6 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
|
||||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -720,6 +737,13 @@ void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* RTC Daylight Saving Time functions *****************************************/
|
||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -740,23 +764,39 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Private_Constants RTC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Masks Definition */
|
||||
#define RTC_TR_RESERVED_MASK 0x007F7F7FU
|
||||
#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
|
||||
#define RTC_TR_RESERVED_MASK ((uint32_t)(RTC_TR_HT | RTC_TR_HU | \
|
||||
RTC_TR_MNT | RTC_TR_MNU | \
|
||||
RTC_TR_ST | RTC_TR_SU | \
|
||||
RTC_TR_PM))
|
||||
#define RTC_DR_RESERVED_MASK ((uint32_t)(RTC_DR_YT | RTC_DR_YU | \
|
||||
RTC_DR_MT | RTC_DR_MU | \
|
||||
RTC_DR_DT | RTC_DR_DU | \
|
||||
RTC_DR_WDU))
|
||||
#define RTC_ISR_RESERVED_MASK ((uint32_t)(RTC_FLAGS_MASK | RTC_ISR_INIT))
|
||||
#define RTC_INIT_MASK 0xFFFFFFFFU
|
||||
#define RTC_RSF_MASK 0xFFFFFF5FU
|
||||
#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
|
||||
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \
|
||||
RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \
|
||||
RTC_FLAG_ALRBF | RTC_FLAG_ALRBWF | \
|
||||
RTC_FLAG_WUTF | RTC_FLAG_WUTWF | \
|
||||
RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \
|
||||
RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
|
||||
RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK))
|
||||
|
||||
#define RTC_TIMEOUT_VALUE 1000U
|
||||
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_IM17 /*!< External interrupt line 17 connected to the RTC Alarm event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Private_Macros RTC Private Macros
|
||||
* @{
|
||||
*/
|
||||
@@ -764,66 +804,87 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || \
|
||||
((__FORMAT__) == RTC_HOURFORMAT_24))
|
||||
#define IS_RTC_OUTPUT_POL(__POL__) (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \
|
||||
((__POL__) == RTC_OUTPUT_POLARITY_LOW))
|
||||
#define IS_RTC_OUTPUT_TYPE(__TYPE__) (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
|
||||
((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL))
|
||||
#define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= 0x7FU)
|
||||
#define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= 0x7FFFU)
|
||||
#define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
|
||||
#define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
|
||||
#define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
|
||||
#define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
|
||||
#define IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))
|
||||
#define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \
|
||||
((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
||||
((__SAVE__) == RTC_DAYLIGHTSAVING_NONE))
|
||||
#define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \
|
||||
((__OPERATION__) == RTC_STOREOPERATION_SET))
|
||||
#define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))
|
||||
#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
|
||||
#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
|
||||
#define IS_RTC_DATE(__DATE__) (((__DATE__) >= 1U) && ((__DATE__) <= 31U))
|
||||
#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
|
||||
((FORMAT) == RTC_HOURFORMAT_24))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >0U) && ((__DATE__) <= 31U))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
|
||||
((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
|
||||
#define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7FU) == (uint32_t)RESET)
|
||||
#define IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= 0x00007FFFU)
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__) (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE))
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
|
||||
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
|
||||
((OUTPUT) == RTC_OUTPUT_ALARMB) || \
|
||||
((OUTPUT) == RTC_OUTPUT_WAKEUP))
|
||||
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
|
||||
((POL) == RTC_OUTPUT_POLARITY_LOW))
|
||||
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
|
||||
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
|
||||
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
|
||||
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
|
||||
|
||||
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
|
||||
((PM) == RTC_HOURFORMAT12_PM))
|
||||
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
|
||||
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
|
||||
((OPERATION) == RTC_STOREOPERATION_SET))
|
||||
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
|
||||
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
|
||||
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
|
||||
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
|
||||
|
||||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ((uint32_t)~RTC_ALARMMASK_ALL)) == 0U)
|
||||
|
||||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -833,12 +894,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Private_Functions RTC Private Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
|
||||
uint8_t RTC_ByteToBcd2(uint8_t Value);
|
||||
uint8_t RTC_Bcd2ToByte(uint8_t Value);
|
||||
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
|
||||
uint8_t RTC_ByteToBcd2(uint8_t number);
|
||||
uint8_t RTC_Bcd2ToByte(uint8_t number);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -855,5 +918,4 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_RTC_H */
|
||||
|
||||
#endif /* STM32F7xx_HAL_RTC_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -734,8 +734,8 @@ void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
|
||||
uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
|
||||
HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai);
|
||||
uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -211,7 +211,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
|
||||
* @{
|
||||
*/
|
||||
/* SDRAM State functions ********************************************************/
|
||||
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
|
||||
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -606,6 +606,7 @@ typedef enum
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
|
||||
* @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
|
||||
* @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
|
||||
* @arg @ref SMARTCARD_FLAG_BUSY Busy flag
|
||||
* @arg @ref SMARTCARD_FLAG_EOBF End of block flag
|
||||
@@ -1121,8 +1122,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -79,6 +79,9 @@ extern "C" {
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
#if defined(USART_ISR_REACK)
|
||||
#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
|
||||
#endif /* USART_ISR_REACK */
|
||||
#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
|
||||
#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
|
||||
#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
|
||||
|
||||
@@ -100,8 +100,6 @@ typedef struct
|
||||
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
|
||||
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
|
||||
/**
|
||||
* @}
|
||||
@@ -749,8 +747,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
*/
|
||||
|
||||
/* Peripheral State and Errors functions **************************************************/
|
||||
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
|
||||
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
|
||||
uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
|
||||
uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -56,7 +56,8 @@ typedef struct
|
||||
uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
|
||||
This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
|
||||
|
||||
uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
|
||||
uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status
|
||||
from channel A or B.
|
||||
This parameter can be a value of @ref SPDIFRX_Channel_Selection */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
|
||||
@@ -65,16 +66,19 @@ typedef struct
|
||||
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
|
||||
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
|
||||
|
||||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
|
||||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PT_Mask */
|
||||
|
||||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
|
||||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
|
||||
|
||||
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_V_Mask */
|
||||
|
||||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
|
||||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PE_Mask */
|
||||
} SPDIFRX_InitTypeDef;
|
||||
|
||||
@@ -89,16 +93,19 @@ typedef struct
|
||||
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
|
||||
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
|
||||
|
||||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
|
||||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PT_Mask */
|
||||
|
||||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
|
||||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
|
||||
|
||||
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_V_Mask */
|
||||
|
||||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
|
||||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not
|
||||
into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PE_Mask */
|
||||
|
||||
} SPDIFRX_SetDataFormatTypeDef;
|
||||
@@ -123,7 +130,7 @@ typedef enum
|
||||
typedef struct __SPDIFRX_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
|
||||
{
|
||||
SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
|
||||
|
||||
@@ -151,7 +158,8 @@ typedef struct
|
||||
decremented when a sample is received.
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
|
||||
DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
|
||||
DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information
|
||||
DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
|
||||
|
||||
@@ -162,9 +170,11 @@ typedef struct
|
||||
__IO uint32_t ErrorCode; /* SPDIFRX Error code */
|
||||
|
||||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
|
||||
void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed callback */
|
||||
void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed
|
||||
callback */
|
||||
void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */
|
||||
void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */
|
||||
void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed
|
||||
callback */
|
||||
void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */
|
||||
void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */
|
||||
void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */
|
||||
@@ -172,9 +182,6 @@ typedef struct
|
||||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
|
||||
|
||||
} SPDIFRX_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
@@ -194,9 +201,12 @@ typedef enum
|
||||
/**
|
||||
* @brief HAL SPDIFRX Callback pointer definition
|
||||
*/
|
||||
typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< pointer to an SPDIFRX callback function */
|
||||
typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback
|
||||
function */
|
||||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
|
||||
* @{
|
||||
@@ -260,8 +270,10 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
|
||||
/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
|
||||
#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
|
||||
#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied
|
||||
into the SPDIF_DR */
|
||||
#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied
|
||||
into the SPDIF_DR, zeros are written instead*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -410,7 +422,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
|
||||
#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
|
||||
#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\
|
||||
&= (uint16_t)(~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the SPDIFRX Handle.
|
||||
@@ -425,7 +438,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
|
||||
* @arg SPDIFRX_IT_IFEIE
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified SPDIFRX flag is set or not.
|
||||
* @param __HANDLE__ specifies the SPDIFRX Handle.
|
||||
@@ -442,7 +456,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
|
||||
* @arg SPDIFRX_FLAG_TERR
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\
|
||||
& (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
@@ -478,8 +493,10 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID,
|
||||
pSPDIFRX_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
|
||||
HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
@@ -490,8 +507,10 @@ HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
|
||||
@@ -594,4 +613,4 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SPDIFRX_H */
|
||||
#endif /* STM32F7xx_HAL_SPDIFRX_H */
|
||||
|
||||
@@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef
|
||||
|
||||
SPI_InitTypeDef Init; /*!< SPI communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
|
||||
|
||||
@@ -426,7 +426,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
@@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
|
||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
|
||||
#define SPI_RESET_CRC(__HANDLE__) \
|
||||
do{ \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
|
||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of SPI SR register.
|
||||
@@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
|
||||
@@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
|
||||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
|
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
|
||||
uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -48,7 +48,7 @@ extern "C" {
|
||||
/** @addtogroup SPIEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -204,7 +204,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
|
||||
*/
|
||||
|
||||
/* SRAM State functions ******************************************************/
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -416,7 +416,6 @@ typedef enum
|
||||
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
|
||||
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
@@ -737,6 +736,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */
|
||||
#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Flag_definition TIM Flag Definition
|
||||
* @{
|
||||
*/
|
||||
@@ -777,16 +785,16 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
/** @defgroup TIM_Clock_Source TIM Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
|
||||
#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
|
||||
#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
|
||||
#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
|
||||
#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
|
||||
#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
|
||||
#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
|
||||
#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
|
||||
#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
|
||||
#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
|
||||
#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
|
||||
#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
|
||||
#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
|
||||
#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
|
||||
#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -993,8 +1001,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
|
||||
#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
|
||||
#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
|
||||
#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
|
||||
#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1699,6 +1707,17 @@ mode.
|
||||
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
|
||||
}while(0)
|
||||
|
||||
/** @brief Select the Capture/compare DMA request source.
|
||||
* @param __HANDLE__ specifies the TIM Handle.
|
||||
* @param __CCDMA__ specifies Capture/compare DMA request source
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
|
||||
* @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \
|
||||
MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1710,7 +1729,8 @@ mode.
|
||||
*/
|
||||
/* The counter of a timer instance is disabled only if all the CCx and CCxN
|
||||
channels have been disabled */
|
||||
#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
|
||||
#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \
|
||||
TIM_CCER_CC5E | TIM_CCER_CC6E))
|
||||
#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
|
||||
/**
|
||||
* @}
|
||||
@@ -1783,7 +1803,7 @@ mode.
|
||||
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
|
||||
|
||||
#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
|
||||
((__MODE__) == TIM_UIFREMAP_ENALE))
|
||||
((__MODE__) == TIM_UIFREMAP_ENABLE))
|
||||
|
||||
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
|
||||
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
|
||||
@@ -1823,6 +1843,10 @@ mode.
|
||||
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
|
||||
((__PRESCALER__) == TIM_ICPSC_DIV8))
|
||||
|
||||
#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
|
||||
((__CHANNEL__) != (TIM_CHANNEL_5)) && \
|
||||
((__CHANNEL__) != (TIM_CHANNEL_6)))
|
||||
|
||||
#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
|
||||
((__MODE__) == TIM_OPMODE_REPETITIVE))
|
||||
|
||||
@@ -1843,20 +1867,24 @@ mode.
|
||||
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
|
||||
(((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
|
||||
((__PERIOD__) > 0U))
|
||||
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_3))
|
||||
|
||||
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
|
||||
|
||||
#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
|
||||
((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
|
||||
@@ -1894,7 +1922,6 @@ mode.
|
||||
|
||||
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
|
||||
|
||||
|
||||
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
|
||||
((__STATE__) == TIM_BREAK_DISABLE))
|
||||
|
||||
@@ -1953,8 +1980,8 @@ mode.
|
||||
((__MODE__) == TIM_OCMODE_PWM2) || \
|
||||
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
|
||||
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
|
||||
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
|
||||
|
||||
#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
|
||||
((__MODE__) == TIM_OCMODE_ACTIVE) || \
|
||||
@@ -2069,7 +2096,8 @@ mode.
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\
|
||||
do {\
|
||||
(__HANDLE__)->ChannelState[0] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelState[1] = \
|
||||
@@ -2096,7 +2124,8 @@ mode.
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
|
||||
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
|
||||
|
||||
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
|
||||
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\
|
||||
do {\
|
||||
(__HANDLE__)->ChannelNState[0] = \
|
||||
(__CHANNEL_STATE__); \
|
||||
(__HANDLE__)->ChannelNState[1] = \
|
||||
@@ -2136,7 +2165,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
@@ -2158,7 +2187,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
|
||||
uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
@@ -2180,7 +2210,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
|
||||
uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
@@ -2232,7 +2263,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
|
||||
* @{
|
||||
*/
|
||||
/* Timer Encoder functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
@@ -2265,21 +2296,26 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
|
||||
* @{
|
||||
*/
|
||||
/* Control functions *********************************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
|
||||
uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
|
||||
uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
|
||||
uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
|
||||
uint32_t OutputChannel, uint32_t InputChannel);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
|
||||
const TIM_ClearInputConfigTypeDef *sClearInputConfig,
|
||||
uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
@@ -2289,7 +2325,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
|
||||
uint32_t BurstLength, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
|
||||
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
|
||||
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -2326,17 +2362,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Peripheral Channel state functions ************************************************/
|
||||
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -2350,9 +2386,9 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
|
||||
/** @defgroup TIM_Private_Functions TIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
|
||||
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
|
||||
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
|
||||
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
|
||||
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
|
||||
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
||||
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
|
||||
|
||||
|
||||
@@ -203,7 +203,7 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
/* Timer Hall Sensor functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||||
@@ -236,7 +236,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
|
||||
uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
@@ -255,7 +256,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
|
||||
uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
@@ -289,12 +291,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
||||
TIM_MasterConfigTypeDef *sMasterConfig);
|
||||
const TIM_MasterConfigTypeDef *sMasterConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||
#if defined(TIM_BREAK_INPUT_SUPPORT)
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
|
||||
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
|
||||
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||||
@@ -320,8 +322,8 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
|
||||
* @{
|
||||
*/
|
||||
/* Extended Peripheral State functions ***************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -186,7 +186,7 @@ typedef enum
|
||||
/**
|
||||
* @brief HAL UART Reception type definition
|
||||
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
|
||||
* It is expected to admit following values :
|
||||
* This parameter can be a value of @ref UART_Reception_Type_Values :
|
||||
* HAL_UART_RECEPTION_STANDARD = 0x00U,
|
||||
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
|
||||
* HAL_UART_RECEPTION_TORTO = 0x02U,
|
||||
@@ -194,6 +194,17 @@ typedef enum
|
||||
*/
|
||||
typedef uint32_t HAL_UART_RxTypeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL UART Rx Event type definition
|
||||
* @note HAL UART Rx Event type value aims to identify which type of Event has occurred
|
||||
* leading to call of the RxEvent callback.
|
||||
* This parameter can be a value of @ref UART_RxEvent_Type_Values :
|
||||
* HAL_UART_RXEVENT_TC = 0x00U,
|
||||
* HAL_UART_RXEVENT_HT = 0x01U,
|
||||
* HAL_UART_RXEVENT_IDLE = 0x02U,
|
||||
*/
|
||||
typedef uint32_t HAL_UART_RxEventTypeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UART handle Structure definition
|
||||
*/
|
||||
@@ -221,6 +232,8 @@ typedef struct __UART_HandleTypeDef
|
||||
|
||||
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
|
||||
|
||||
__IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */
|
||||
|
||||
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
|
||||
|
||||
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
|
||||
@@ -276,7 +289,11 @@ typedef enum
|
||||
HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
|
||||
HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
|
||||
HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
|
||||
HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
|
||||
HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
|
||||
@@ -782,7 +799,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
|
||||
/** @defgroup UART_Reception_Type_Values UART Reception type values
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
|
||||
@@ -793,6 +810,16 @@ typedef void (*pUART_RxEventCallbackTypeDef)
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */
|
||||
#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */
|
||||
#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1585,8 +1612,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
|
||||
*/
|
||||
|
||||
/* Peripheral State and Errors functions **************************************************/
|
||||
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
|
||||
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
|
||||
HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
|
||||
uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -113,8 +113,10 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
|
||||
*/
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
|
||||
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
@@ -144,6 +146,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -454,7 +454,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
|
||||
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
|
||||
|
||||
|
||||
|
||||
/** @brief Enable the specified USART interrupt.
|
||||
* @param __HANDLE__ specifies the USART Handle.
|
||||
* @param __INTERRUPT__ specifies the USART interrupt source to enable.
|
||||
@@ -806,7 +805,8 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
@@ -843,8 +843,8 @@ void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
|
||||
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
|
||||
HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
|
||||
uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -296,3 +296,4 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
|
||||
#endif
|
||||
|
||||
#endif /* STM32F7xx_HAL_WWDG_H */
|
||||
|
||||
|
||||
@@ -3970,7 +3970,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
|
||||
{
|
||||
return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
|
||||
return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3985,7 +3985,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
|
||||
{
|
||||
return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
|
||||
return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -4188,7 +4188,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
|
||||
return (uint8_t)(READ_BIT(*preg,
|
||||
ADC_JDR1_JDATA)
|
||||
ADC_JDR1_JDATA) & 0x000000FFUL
|
||||
);
|
||||
}
|
||||
|
||||
@@ -4215,7 +4215,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32
|
||||
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
|
||||
|
||||
return (uint8_t)(READ_BIT(*preg,
|
||||
ADC_JDR1_JDATA)
|
||||
ADC_JDR1_JDATA) & 0x000000FFUL
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
@@ -164,6 +164,8 @@ extern "C" {
|
||||
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
|
||||
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
|
||||
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
|
||||
|
||||
/* Legacy Define */
|
||||
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
|
||||
/**
|
||||
* @}
|
||||
@@ -572,7 +574,7 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
|
||||
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
|
||||
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
|
||||
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
|
||||
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
|
||||
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
|
||||
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
|
||||
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
|
||||
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
|
||||
@@ -586,7 +588,7 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisa
|
||||
/* Set base address */
|
||||
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
|
||||
/* Configure MPU */
|
||||
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
|
||||
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -184,7 +184,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySi
|
||||
* @arg @ref LL_CRC_POLYLENGTH_8B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_7B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
|
||||
}
|
||||
@@ -215,7 +215,7 @@ __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
|
||||
}
|
||||
@@ -242,7 +242,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
|
||||
}
|
||||
@@ -270,7 +270,7 @@ __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable initial CRC value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->INIT));
|
||||
}
|
||||
@@ -301,7 +301,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t Polyno
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable Polynomial value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->POL));
|
||||
}
|
||||
@@ -359,7 +359,7 @@ __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->DR));
|
||||
}
|
||||
@@ -371,7 +371,7 @@ __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint16_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
@@ -383,7 +383,7 @@ __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
@@ -395,7 +395,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
|
||||
}
|
||||
@@ -433,7 +433,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
|
||||
ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -471,9 +471,7 @@ typedef struct
|
||||
* @arg @ref LL_DAC_RESOLUTION_8B
|
||||
* @retval DAC conversion data (unit: digital value)
|
||||
*/
|
||||
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
|
||||
__DAC_VOLTAGE__,\
|
||||
__DAC_RESOLUTION__) \
|
||||
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
|
||||
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
|
||||
/ (__VREFANALOG_VOLTAGE__) \
|
||||
)
|
||||
@@ -491,6 +489,7 @@ typedef struct
|
||||
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the conversion trigger source for the selected DAC channel.
|
||||
* @note For conversion trigger source to be effective, DAC trigger
|
||||
@@ -545,7 +544,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
||||
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
|
||||
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@@ -588,7 +587,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA
|
||||
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
|
||||
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@@ -654,7 +653,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
|
||||
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
|
||||
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@@ -721,7 +720,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
|
||||
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
|
||||
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@@ -760,7 +759,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan
|
||||
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
|
||||
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||
@@ -822,7 +821,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
@@ -861,7 +860,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
|
||||
* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
|
||||
* @retval DAC register address
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
|
||||
__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
|
||||
{
|
||||
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
|
||||
/* DAC channel selected. */
|
||||
@@ -922,7 +921,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
@@ -980,7 +979,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
return ((READ_BIT(DACx->CR,
|
||||
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
|
||||
@@ -1153,7 +1152,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
|
||||
* @arg @ref LL_DAC_CHANNEL_2
|
||||
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
|
||||
& DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
|
||||
@@ -1175,7 +1174,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1187,7 +1186,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1279,7 +1278,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1291,7 +1290,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
|
||||
* @param DACx DAC instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
|
||||
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
|
||||
{
|
||||
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1306,8 +1305,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
|
||||
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
|
||||
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
|
||||
/**
|
||||
@@ -1334,4 +1333,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
|
||||
#endif
|
||||
|
||||
#endif /* STM32F7xx_LL_DAC_H */
|
||||
|
||||
|
||||
@@ -1632,7 +1632,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Str
|
||||
*/
|
||||
__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
|
||||
{
|
||||
MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
|
||||
WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, Address);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -544,7 +544,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -581,7 +581,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -606,7 +606,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -637,7 +637,7 @@ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
|
||||
* @arg @ref LL_DMA2D_MODE_M2M_BLEND
|
||||
* @arg @ref LL_DMA2D_MODE_R2M
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
|
||||
}
|
||||
@@ -670,7 +670,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
|
||||
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
|
||||
}
|
||||
@@ -752,7 +752,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t Line
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
|
||||
}
|
||||
@@ -775,7 +775,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
|
||||
}
|
||||
@@ -798,7 +798,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrO
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
|
||||
}
|
||||
@@ -821,7 +821,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t O
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
|
||||
}
|
||||
@@ -842,8 +842,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
|
||||
{
|
||||
MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
|
||||
OutputColor);
|
||||
WRITE_REG(DMA2Dx->OCOLR, OutputColor);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -858,7 +857,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t Out
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
|
||||
(DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
|
||||
@@ -882,7 +881,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t L
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
|
||||
}
|
||||
@@ -905,7 +904,7 @@ __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTi
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Dead time value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
|
||||
}
|
||||
@@ -938,7 +937,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -965,7 +964,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
|
||||
}
|
||||
@@ -987,7 +986,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1032,7 +1031,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @arg @ref LL_DMA2D_INPUT_MODE_A8
|
||||
* @arg @ref LL_DMA2D_INPUT_MODE_A4
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
|
||||
}
|
||||
@@ -1061,7 +1060,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
|
||||
* @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
|
||||
}
|
||||
@@ -1084,7 +1083,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Alpha value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
|
||||
}
|
||||
@@ -1164,7 +1163,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
|
||||
}
|
||||
@@ -1204,7 +1203,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Red color value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
|
||||
}
|
||||
@@ -1227,7 +1226,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Green color value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
|
||||
}
|
||||
@@ -1250,7 +1249,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Blue color value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
|
||||
}
|
||||
@@ -1273,7 +1272,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
|
||||
}
|
||||
@@ -1296,7 +1295,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
|
||||
}
|
||||
@@ -1323,7 +1322,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3
|
||||
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
|
||||
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
|
||||
}
|
||||
@@ -1354,7 +1353,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
|
||||
}
|
||||
@@ -1376,7 +1375,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1421,7 +1420,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @arg @ref LL_DMA2D_INPUT_MODE_A8
|
||||
* @arg @ref LL_DMA2D_INPUT_MODE_A4
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
|
||||
}
|
||||
@@ -1450,7 +1449,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
|
||||
* @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
|
||||
}
|
||||
@@ -1473,7 +1472,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Alpha value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
|
||||
}
|
||||
@@ -1553,7 +1552,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
|
||||
}
|
||||
@@ -1593,7 +1592,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Red color value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
|
||||
}
|
||||
@@ -1616,7 +1615,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Green color value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
|
||||
}
|
||||
@@ -1639,7 +1638,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Blue color value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
|
||||
}
|
||||
@@ -1662,7 +1661,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
|
||||
}
|
||||
@@ -1685,7 +1684,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
|
||||
}
|
||||
@@ -1712,7 +1711,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3
|
||||
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
|
||||
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
|
||||
}
|
||||
@@ -1736,7 +1735,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1747,7 +1746,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1758,7 +1757,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1769,7 +1768,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1780,7 +1779,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1791,7 +1790,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -2008,7 +2007,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -2019,7 +2018,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -2030,7 +2029,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -2041,7 +2040,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -2052,7 +2051,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -2063,7 +2062,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
|
||||
* @param DMA2Dx DMA2D Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
|
||||
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx)
|
||||
{
|
||||
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -2079,16 +2078,16 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
|
||||
ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx);
|
||||
ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
|
||||
void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
|
||||
void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
|
||||
void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
|
||||
void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
|
||||
uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
|
||||
uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
|
||||
uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
|
||||
uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
|
||||
uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
|
||||
uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
|
||||
uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
|
||||
uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
|
||||
void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
|
||||
|
||||
/**
|
||||
|
||||
@@ -216,7 +216,8 @@ typedef struct
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FMC_Wait_Timing */
|
||||
|
||||
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
|
||||
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device
|
||||
by the FMC.
|
||||
This parameter can be a value of @ref FMC_Write_Operation */
|
||||
|
||||
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
|
||||
@@ -597,11 +598,13 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(FMC_BCR1_WFDIS)
|
||||
/** @defgroup FMC_Write_FIFO FMC Write FIFO
|
||||
* @{
|
||||
*/
|
||||
#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
|
||||
#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
|
||||
#endif /* FMC_BCR1_WFDIS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -1043,11 +1046,11 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
|
||||
FMC_NORSRAM_InitTypeDef *Init);
|
||||
const FMC_NORSRAM_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
|
||||
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
|
||||
const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
|
||||
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
|
||||
const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
|
||||
uint32_t ExtendedMode);
|
||||
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
|
||||
FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
|
||||
@@ -1073,11 +1076,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic
|
||||
/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
|
||||
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
|
||||
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
@@ -1088,7 +1091,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
*/
|
||||
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
|
||||
HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
|
||||
uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
@@ -1104,9 +1107,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u
|
||||
/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
|
||||
FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
|
||||
const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
|
||||
HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
@@ -1118,11 +1121,11 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
||||
HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
|
||||
FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
|
||||
const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
|
||||
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
|
||||
HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
|
||||
uint32_t AutoRefreshNumber);
|
||||
uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
||||
uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -451,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -500,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
|
||||
}
|
||||
@@ -535,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -568,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -601,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -616,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
|
||||
* @retval Address of data register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
|
||||
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
|
||||
{
|
||||
uint32_t data_reg_addr;
|
||||
|
||||
@@ -664,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -697,7 +697,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -732,7 +732,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -760,7 +760,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t
|
||||
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
|
||||
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
|
||||
}
|
||||
@@ -809,7 +809,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -865,7 +865,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -890,7 +890,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
|
||||
}
|
||||
@@ -901,7 +901,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
|
||||
}
|
||||
@@ -912,7 +912,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
|
||||
}
|
||||
@@ -923,7 +923,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
|
||||
}
|
||||
@@ -934,7 +934,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
|
||||
}
|
||||
@@ -971,7 +971,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
|
||||
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
|
||||
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
|
||||
}
|
||||
@@ -1020,7 +1020,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1059,7 +1059,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1110,7 +1110,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
|
||||
}
|
||||
@@ -1142,7 +1142,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim
|
||||
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
|
||||
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
|
||||
}
|
||||
@@ -1170,7 +1170,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
|
||||
}
|
||||
@@ -1224,7 +1224,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
|
||||
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
|
||||
(ClockTimeout)) ? 1UL : 0UL);
|
||||
@@ -1266,7 +1266,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1299,7 +1299,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1332,7 +1332,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1365,7 +1365,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1398,7 +1398,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1437,7 +1437,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1488,7 +1488,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1509,7 +1509,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1522,7 +1522,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1535,7 +1535,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1548,7 +1548,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1561,7 +1561,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1574,7 +1574,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1587,7 +1587,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1600,7 +1600,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1613,7 +1613,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1626,7 +1626,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1639,7 +1639,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1654,7 +1654,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1669,7 +1669,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1685,7 +1685,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1698,7 +1698,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1859,7 +1859,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1894,7 +1894,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -1918,7 +1918,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
|
||||
}
|
||||
@@ -1995,7 +1995,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -2023,7 +2023,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans
|
||||
* @arg @ref LL_I2C_REQUEST_WRITE
|
||||
* @arg @ref LL_I2C_REQUEST_READ
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
|
||||
}
|
||||
@@ -2047,7 +2047,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0x3F
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
|
||||
}
|
||||
@@ -2093,11 +2093,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
|
||||
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
|
||||
{
|
||||
/* Declaration of tmp to prevent undefined behavior of volatile usage */
|
||||
uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
|
||||
((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
|
||||
(((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
||||
(uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
|
||||
|
||||
/* update CR2 register */
|
||||
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
|
||||
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
|
||||
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
|
||||
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
|
||||
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
|
||||
tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -2110,7 +2117,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr
|
||||
* @arg @ref LL_I2C_DIRECTION_WRITE
|
||||
* @arg @ref LL_I2C_DIRECTION_READ
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
|
||||
}
|
||||
@@ -2121,7 +2128,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
|
||||
}
|
||||
@@ -2151,7 +2158,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -2164,7 +2171,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
|
||||
}
|
||||
@@ -2175,7 +2182,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
|
||||
}
|
||||
@@ -2201,8 +2208,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
|
||||
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
|
||||
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
|
||||
|
||||
|
||||
@@ -208,7 +208,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale
|
||||
* @arg @ref LL_IWDG_PRESCALER_128
|
||||
* @arg @ref LL_IWDG_PRESCALER_256
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->PR));
|
||||
}
|
||||
@@ -231,7 +231,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->RLR));
|
||||
}
|
||||
@@ -254,7 +254,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_REG(IWDGx->WINR));
|
||||
}
|
||||
@@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -284,7 +284,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -308,7 +308,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bits (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
@@ -306,14 +306,27 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Legacy definitions for compatibility purpose
|
||||
@cond 0
|
||||
*/
|
||||
#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
|
||||
#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
|
||||
#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
|
||||
#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
|
||||
#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
|
||||
#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
|
||||
/**
|
||||
@endcond
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
|
||||
ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
|
||||
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
|
||||
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
|
||||
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
|
||||
void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
|
||||
/**
|
||||
* @}
|
||||
@@ -343,7 +356,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -389,7 +402,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda
|
||||
* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
|
||||
* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
|
||||
}
|
||||
@@ -404,7 +417,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
|
||||
* @note autoreload value be strictly greater than the compare value.
|
||||
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
|
||||
* @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
|
||||
@@ -416,9 +429,9 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto
|
||||
* @brief Get actual auto reload value
|
||||
* @rmtoll ARR ARR LL_LPTIM_GetAutoReload
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
|
||||
* @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
|
||||
}
|
||||
@@ -445,7 +458,7 @@ __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t Compare
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
|
||||
}
|
||||
@@ -460,7 +473,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
|
||||
}
|
||||
@@ -488,7 +501,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou
|
||||
* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
|
||||
* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
|
||||
}
|
||||
@@ -537,7 +550,7 @@ __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Wavefo
|
||||
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
|
||||
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
|
||||
}
|
||||
@@ -564,7 +577,7 @@ __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polari
|
||||
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
|
||||
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
|
||||
}
|
||||
@@ -608,7 +621,7 @@ __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Presc
|
||||
* @arg @ref LL_LPTIM_PRESCALER_DIV64
|
||||
* @arg @ref LL_LPTIM_PRESCALER_DIV128
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
|
||||
}
|
||||
@@ -658,7 +671,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -723,7 +736,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Sour
|
||||
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
|
||||
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
|
||||
}
|
||||
@@ -738,7 +751,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
|
||||
* @arg @ref LL_LPTIM_TRIG_FILTER_4
|
||||
* @arg @ref LL_LPTIM_TRIG_FILTER_8
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
|
||||
}
|
||||
@@ -752,7 +765,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
|
||||
* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
|
||||
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
|
||||
}
|
||||
@@ -788,7 +801,7 @@ __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t Clo
|
||||
* @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
|
||||
* @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
|
||||
}
|
||||
@@ -830,7 +843,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockF
|
||||
* @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
|
||||
* @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
|
||||
}
|
||||
@@ -845,7 +858,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
|
||||
* @arg @ref LL_LPTIM_CLK_FILTER_4
|
||||
* @arg @ref LL_LPTIM_CLK_FILTER_8
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
|
||||
}
|
||||
@@ -883,7 +896,7 @@ __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t Enc
|
||||
* @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
|
||||
* @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
|
||||
}
|
||||
@@ -922,7 +935,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -935,13 +948,14 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear the compare match flag (CMPMCF)
|
||||
* @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
|
||||
* @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
|
||||
}
|
||||
@@ -952,18 +966,18 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the autoreload match flag (ARRMCF)
|
||||
* @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
|
||||
* @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
|
||||
}
|
||||
@@ -974,7 +988,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -996,7 +1010,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1019,7 +1033,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1042,7 +1056,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1065,7 +1079,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1088,7 +1102,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1129,7 +1143,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1162,7 +1176,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1195,7 +1209,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1228,7 +1242,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1261,7 +1275,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit(1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1294,7 +1308,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit(1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
|
||||
}
|
||||
@@ -1327,7 +1341,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
|
||||
* @param LPTIMx Low-Power Timer instance
|
||||
* @retval State of bit(1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
|
||||
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
|
||||
{
|
||||
return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
@@ -42,9 +42,9 @@ extern "C" {
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(RCC_DCKCFGR1_PLLSAIDIVR)
|
||||
#if defined(LTDC)
|
||||
static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
|
||||
#endif /* RCC_DCKCFGR1_PLLSAIDIVR */
|
||||
#endif /* LTDC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -38,6 +38,7 @@ extern "C" {
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
@@ -145,7 +146,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -164,7 +165,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -175,7 +176,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -186,7 +187,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -197,7 +198,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -208,7 +209,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -274,7 +275,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
|
||||
}
|
||||
@@ -293,7 +294,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
|
||||
* @param RNGx RNG Instance
|
||||
* @retval Generated 32-bit random value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
|
||||
__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(RNGx->DR));
|
||||
}
|
||||
@@ -306,7 +307,7 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
|
||||
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
|
||||
ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@@ -17,8 +17,8 @@
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_RTC_H
|
||||
#define __STM32F7xx_LL_RTC_H
|
||||
#ifndef STM32F7xx_LL_RTC_H
|
||||
#define STM32F7xx_LL_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@@ -45,7 +45,7 @@ extern "C" {
|
||||
*/
|
||||
/* Masks Definition */
|
||||
#define RTC_INIT_MASK 0xFFFFFFFFU
|
||||
#define RTC_RSF_MASK 0xFFFFFF5FU
|
||||
#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
|
||||
|
||||
/* Write protection defines */
|
||||
#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
|
||||
@@ -167,7 +167,7 @@ typedef struct
|
||||
This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
|
||||
or @ref LL_RTC_ALMB_SetMask() for ALARM B
|
||||
or @ref LL_RTC_ALMB_SetMask() for ALARM B.
|
||||
*/
|
||||
|
||||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
|
||||
@@ -204,8 +204,8 @@ typedef struct
|
||||
/** @defgroup RTC_LL_EC_FORMAT FORMAT
|
||||
* @{
|
||||
*/
|
||||
#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */
|
||||
#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */
|
||||
#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */
|
||||
#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -408,7 +408,7 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
|
||||
#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
|
||||
#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -452,7 +452,6 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(RTC_TAMPCR_TAMPPRCH)
|
||||
/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
|
||||
* @{
|
||||
*/
|
||||
@@ -463,9 +462,7 @@ typedef struct
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* RTC_TAMPCR_TAMPPRCH */
|
||||
|
||||
#if defined(RTC_TAMPCR_TAMPFLT)
|
||||
/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
|
||||
* @{
|
||||
*/
|
||||
@@ -476,9 +473,7 @@ typedef struct
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* RTC_TAMPCR_TAMPFLT */
|
||||
|
||||
#if defined(RTC_TAMPCR_TAMPFREQ)
|
||||
/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
|
||||
* @{
|
||||
*/
|
||||
@@ -493,7 +488,6 @@ typedef struct
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* RTC_TAMPCR_TAMPFREQ */
|
||||
|
||||
/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
|
||||
* @{
|
||||
@@ -526,7 +520,6 @@ typedef struct
|
||||
#define LL_RTC_BKP_DR2 0x00000002U
|
||||
#define LL_RTC_BKP_DR3 0x00000003U
|
||||
#define LL_RTC_BKP_DR4 0x00000004U
|
||||
#if RTC_BKP_NUMBER > 5
|
||||
#define LL_RTC_BKP_DR5 0x00000005U
|
||||
#define LL_RTC_BKP_DR6 0x00000006U
|
||||
#define LL_RTC_BKP_DR7 0x00000007U
|
||||
@@ -538,16 +531,10 @@ typedef struct
|
||||
#define LL_RTC_BKP_DR13 0x0000000DU
|
||||
#define LL_RTC_BKP_DR14 0x0000000EU
|
||||
#define LL_RTC_BKP_DR15 0x0000000FU
|
||||
#endif /* RTC_BKP_NUMBER > 5 */
|
||||
|
||||
#if RTC_BKP_NUMBER > 16
|
||||
#define LL_RTC_BKP_DR16 0x00000010U
|
||||
#define LL_RTC_BKP_DR17 0x00000011U
|
||||
#define LL_RTC_BKP_DR18 0x00000012U
|
||||
#define LL_RTC_BKP_DR19 0x00000013U
|
||||
#endif /* RTC_BKP_NUMBER > 16 */
|
||||
|
||||
#if RTC_BKP_NUMBER > 20
|
||||
#define LL_RTC_BKP_DR20 0x00000014U
|
||||
#define LL_RTC_BKP_DR21 0x00000015U
|
||||
#define LL_RTC_BKP_DR22 0x00000016U
|
||||
@@ -560,7 +547,6 @@ typedef struct
|
||||
#define LL_RTC_BKP_DR29 0x0000001DU
|
||||
#define LL_RTC_BKP_DR30 0x0000001EU
|
||||
#define LL_RTC_BKP_DR31 0x0000001FU
|
||||
#endif /* RTC_BKP_NUMBER > 20 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -594,6 +580,15 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_LL_EC_TSINSEL TIMESTAMP mapping
|
||||
* @{
|
||||
*/
|
||||
#define LL_RTC_TimeStampPin_Default 0x00000000U /*!< Use RTC_AF1 as TIMESTAMP */
|
||||
#define LL_RTC_TimeStampPin_Pos1 RTC_OR_TSINSEL /*!< Use RTC_AF2 as TIMESTAMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -922,7 +917,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
|
||||
return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1046,7 +1041,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma
|
||||
|
||||
/**
|
||||
* @brief Get time format (AM or PM notation)
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
|
||||
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
|
||||
@@ -1080,7 +1075,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
|
||||
|
||||
/**
|
||||
* @brief Get Hours in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
|
||||
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
|
||||
@@ -1115,7 +1110,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
|
||||
|
||||
/**
|
||||
* @brief Get Minutes in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
|
||||
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
|
||||
@@ -1150,7 +1145,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
|
||||
|
||||
/**
|
||||
* @brief Get Seconds in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
|
||||
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
|
||||
@@ -1189,7 +1184,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
|
||||
{
|
||||
uint32_t temp = 0U;
|
||||
uint32_t temp;
|
||||
|
||||
temp = Format12_24 | \
|
||||
(((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
|
||||
@@ -1200,7 +1195,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24,
|
||||
|
||||
/**
|
||||
* @brief Get time (hour, minute and second) in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
|
||||
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
|
||||
@@ -1217,12 +1212,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24,
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
|
||||
{
|
||||
uint32_t temp = 0U;
|
||||
|
||||
temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
|
||||
return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
|
||||
(((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
|
||||
((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
|
||||
return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1257,7 +1247,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
|
||||
return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1285,17 +1275,18 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Sub second value in the synchronous prescaler counter.
|
||||
* @brief Get subseconds value in the synchronous prescaler counter.
|
||||
* @note You can use both SubSeconds value and SecondFraction (PREDIV_S through
|
||||
* LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
|
||||
* SubSeconds value in second fraction ratio with time unit following
|
||||
* generic formula:
|
||||
* ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
|
||||
* ==> Seconds fraction ratio * time_unit =
|
||||
* [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
|
||||
* This conversion can be performed only if no shift operation is pending
|
||||
* (ie. SHFP=0) when PREDIV_S >= SS.
|
||||
* @rmtoll SSR SS LL_RTC_TIME_GetSubSecond
|
||||
* @param RTCx RTC Instance
|
||||
* @retval Sub second value (number between 0 and 65535)
|
||||
* @retval Subseconds value (number between 0 and 65535)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
|
||||
{
|
||||
@@ -1346,7 +1337,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
|
||||
|
||||
/**
|
||||
* @brief Get Year in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
|
||||
* @rmtoll DR YT LL_RTC_DATE_GetYear\n
|
||||
@@ -1380,7 +1371,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
|
||||
|
||||
/**
|
||||
* @brief Get Week day
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @rmtoll DR WDU LL_RTC_DATE_GetWeekDay
|
||||
* @param RTCx RTC Instance
|
||||
@@ -1427,7 +1418,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
|
||||
|
||||
/**
|
||||
* @brief Get Month in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
|
||||
* @rmtoll DR MT LL_RTC_DATE_GetMonth\n
|
||||
@@ -1469,7 +1460,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
|
||||
|
||||
/**
|
||||
* @brief Get Day in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
|
||||
* @rmtoll DR DT LL_RTC_DATE_GetDay\n
|
||||
@@ -1519,7 +1510,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
|
||||
{
|
||||
uint32_t temp = 0U;
|
||||
uint32_t temp;
|
||||
|
||||
temp = ( WeekDay << RTC_DR_WDU_Pos) | \
|
||||
(((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
|
||||
@@ -1531,7 +1522,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin
|
||||
|
||||
/**
|
||||
* @brief Get date (WeekDay, Day, Month and Year) in BCD format
|
||||
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
|
||||
* @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
|
||||
* before reading this bit
|
||||
* @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
|
||||
* and __LL_RTC_GET_DAY are available to get independently each parameter.
|
||||
@@ -1547,13 +1538,14 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
|
||||
{
|
||||
uint32_t temp = 0U;
|
||||
uint32_t temp;
|
||||
|
||||
temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
|
||||
|
||||
return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
|
||||
(((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
|
||||
(((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
|
||||
((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
|
||||
(((temp & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos) << RTC_OFFSET_DAY) | \
|
||||
(((temp & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos) << RTC_OFFSET_MONTH) | \
|
||||
((temp & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1847,9 +1839,10 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
|
||||
{
|
||||
uint32_t temp = 0U;
|
||||
uint32_t temp;
|
||||
|
||||
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
|
||||
temp = Format12_24 | \
|
||||
(((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
|
||||
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
|
||||
(((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
|
||||
|
||||
@@ -1875,7 +1868,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Alarm A Mask the most-significant bits starting at this bit
|
||||
* @brief Mask the most-significant bits of the subseconds field starting from
|
||||
* the bit specified in parameter Mask
|
||||
* @note This register can be written only when ALRAE is reset in RTC_CR register,
|
||||
* or in initialization mode.
|
||||
* @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
|
||||
@@ -1889,7 +1883,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Alarm A Mask the most-significant bits starting at this bit
|
||||
* @brief Get Alarm A subseconds mask
|
||||
* @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
|
||||
* @param RTCx RTC Instance
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xF
|
||||
@@ -1900,7 +1894,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Alarm A Sub seconds value
|
||||
* @brief Set Alarm A subseconds value
|
||||
* @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond
|
||||
* @param RTCx RTC Instance
|
||||
* @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
|
||||
@@ -1912,7 +1906,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Alarm A Sub seconds value
|
||||
* @brief Get Alarm A subseconds value
|
||||
* @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond
|
||||
* @param RTCx RTC Instance
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
|
||||
@@ -2028,7 +2022,7 @@ __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
|
||||
{
|
||||
MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
|
||||
MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
|
||||
(((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
|
||||
}
|
||||
|
||||
@@ -2213,9 +2207,10 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
|
||||
{
|
||||
uint32_t temp = 0U;
|
||||
uint32_t temp;
|
||||
|
||||
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
|
||||
temp = Format12_24 | \
|
||||
(((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
|
||||
(((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
|
||||
(((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
|
||||
|
||||
@@ -2241,7 +2236,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Alarm B Mask the most-significant bits starting at this bit
|
||||
* @brief Mask the most-significant bits of the subseconds field starting from
|
||||
* the bit specified in parameter Mask
|
||||
* @note This register can be written only when ALRBE is reset in RTC_CR register,
|
||||
* or in initialization mode.
|
||||
* @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
|
||||
@@ -2255,7 +2251,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Alarm B Mask the most-significant bits starting at this bit
|
||||
* @brief Get Alarm B subseconds mask
|
||||
* @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
|
||||
* @param RTCx RTC Instance
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xF
|
||||
@@ -2266,7 +2262,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Alarm B Sub seconds value
|
||||
* @brief Set Alarm B subseconds value
|
||||
* @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
|
||||
* @param RTCx RTC Instance
|
||||
* @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
|
||||
@@ -2278,7 +2274,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Alarm B Sub seconds value
|
||||
* @brief Get Alarm B subseconds value
|
||||
* @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
|
||||
* @param RTCx RTC Instance
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
|
||||
@@ -2519,7 +2515,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get time-stamp sub second value
|
||||
* @brief Get time-stamp subseconds value
|
||||
* @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond
|
||||
* @param RTCx RTC Instance
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
|
||||
@@ -2553,6 +2549,35 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
|
||||
}
|
||||
#endif /* RTC_TAMPCR_TAMPTS */
|
||||
|
||||
/**
|
||||
* @brief Set timestamp Pin
|
||||
* @rmtoll TAMPCR TSINSEL LL_RTC_TS_SetPin
|
||||
* @param RTCx RTC Instance
|
||||
* @param TSPin specifies the RTC Timestamp Pin.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC Timestamp Pin.
|
||||
* @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is used as RTC Timestamp Pin.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RTC_TS_SetPin(RTC_TypeDef *RTCx, uint32_t TSPin)
|
||||
{
|
||||
MODIFY_REG(RTCx->OR, RTC_OR_TSINSEL, TSPin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get timestamp Pin
|
||||
* @rmtoll TAMPCR TSINSEL LL_RTC_TS_GetPin
|
||||
* @param RTCx RTC Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC Timestamp Pin.
|
||||
* @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is used as RTC Timestamp Pin.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_TS_GetPin(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_TSINSEL));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -2670,7 +2695,6 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t T
|
||||
SET_BIT(RTCx->TAMPCR, Tamper);
|
||||
}
|
||||
|
||||
#if defined(RTC_TAMPCR_TAMPPUDIS)
|
||||
/**
|
||||
* @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
|
||||
* @rmtoll TAMPCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
|
||||
@@ -2692,9 +2716,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
|
||||
{
|
||||
CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
|
||||
}
|
||||
#endif /* RTC_TAMPCR_TAMPPUDIS */
|
||||
|
||||
#if defined(RTC_TAMPCR_TAMPPRCH)
|
||||
/**
|
||||
* @brief Set RTC_TAMPx precharge duration
|
||||
* @rmtoll TAMPCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
|
||||
@@ -2725,9 +2747,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH));
|
||||
}
|
||||
#endif /* RTC_TAMPCR_TAMPPRCH */
|
||||
|
||||
#if defined(RTC_TAMPCR_TAMPFLT)
|
||||
/**
|
||||
* @brief Set RTC_TAMPx filter count
|
||||
* @rmtoll TAMPCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
|
||||
@@ -2758,9 +2778,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT));
|
||||
}
|
||||
#endif /* RTC_TAMPCR_TAMPFLT */
|
||||
|
||||
#if defined(RTC_TAMPCR_TAMPFREQ)
|
||||
/**
|
||||
* @brief Set Tamper sampling frequency
|
||||
* @rmtoll TAMPCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
|
||||
@@ -2799,7 +2817,6 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ));
|
||||
}
|
||||
#endif /* RTC_TAMPCR_TAMPFREQ */
|
||||
|
||||
/**
|
||||
* @brief Enable Active level for Tamper input
|
||||
@@ -2877,7 +2894,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
|
||||
return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -2991,13 +3008,13 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
uint32_t temp;
|
||||
|
||||
tmp = (uint32_t)(&(RTCx->BKP0R));
|
||||
tmp += (BackupRegister * 4U);
|
||||
temp = (uint32_t)(&(RTCx->BKP0R));
|
||||
temp += (BackupRegister * 4U);
|
||||
|
||||
/* Write the specified register */
|
||||
*(__IO uint32_t *)tmp = (uint32_t)Data;
|
||||
*(__IO uint32_t *)temp = (uint32_t)Data;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3041,13 +3058,13 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
uint32_t temp;
|
||||
|
||||
tmp = (uint32_t)(&(RTCx->BKP0R));
|
||||
tmp += (BackupRegister * 4U);
|
||||
temp = (uint32_t)(&(RTCx->BKP0R));
|
||||
temp += (BackupRegister * 4U);
|
||||
|
||||
/* Read the specified register */
|
||||
return (*(__IO uint32_t *)tmp);
|
||||
return (*(__IO uint32_t *)temp);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3068,6 +3085,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back
|
||||
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
|
||||
* @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
|
||||
* @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
|
||||
@@ -3084,6 +3102,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque
|
||||
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
|
||||
* @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
|
||||
* @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
|
||||
{
|
||||
@@ -3114,11 +3133,11 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
|
||||
return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the calibration cycle period
|
||||
* @brief Set smooth calibration cycle period
|
||||
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
|
||||
* @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
|
||||
* @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n
|
||||
@@ -3136,7 +3155,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the calibration cycle period
|
||||
* @brief Get smooth calibration cycle period
|
||||
* @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n
|
||||
* CALR CALW16 LL_RTC_CAL_GetPeriod
|
||||
* @param RTCx RTC Instance
|
||||
@@ -3151,7 +3170,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Calibration minus
|
||||
* @brief Set smooth Calibration minus
|
||||
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
|
||||
* @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
|
||||
* @rmtoll CALR CALM LL_RTC_CAL_SetMinus
|
||||
@@ -3165,7 +3184,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Calibration minus
|
||||
* @brief Get smooth Calibration minus
|
||||
* @rmtoll CALR CALM LL_RTC_CAL_GetMinus
|
||||
* @param RTCx RTC Instance
|
||||
* @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
|
||||
@@ -3191,7 +3210,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3202,7 +3221,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3213,7 +3232,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3224,7 +3243,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3235,7 +3254,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3246,7 +3265,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3257,7 +3276,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3268,7 +3287,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3279,7 +3298,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3290,7 +3309,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3400,7 +3419,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3411,7 +3430,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3433,7 +3452,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3444,7 +3463,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3455,7 +3474,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3466,7 +3485,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3477,7 +3496,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
|
||||
return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3680,7 +3699,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
|
||||
return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3691,7 +3710,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
|
||||
return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3702,7 +3721,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
|
||||
return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3713,7 +3732,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
|
||||
return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3724,8 +3743,8 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->TAMPCR,
|
||||
RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE));
|
||||
return ((READ_BIT(RTCx->TAMPCR,
|
||||
RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3736,8 +3755,8 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->TAMPCR,
|
||||
RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE));
|
||||
return ((READ_BIT(RTCx->TAMPCR,
|
||||
RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL);
|
||||
|
||||
}
|
||||
|
||||
@@ -3749,8 +3768,8 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->TAMPCR,
|
||||
RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE));
|
||||
return ((READ_BIT(RTCx->TAMPCR,
|
||||
RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3761,8 +3780,8 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
|
||||
{
|
||||
return (READ_BIT(RTCx->TAMPCR,
|
||||
RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE));
|
||||
return ((READ_BIT(RTCx->TAMPCR,
|
||||
RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -3812,5 +3831,4 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_RTC_H */
|
||||
|
||||
#endif /* STM32F7xx_LL_RTC_H */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user