Missing clock detectionΒΆ

group sdl_ex_mcd_test

sdl_ex_mcd_test

This example demonstrates how to check the missing clock detection functionality.

Once the MCD is simulated by disconnecting the clock to the MCD module an NMI is generated. This NMI determines that an MCD error was generated due to a clock failure which is handled in the ISR.

Before the MCD the clock frequency will be as per device initialization. Post MCD error, the clock will be running at the speed of INTOSC1 with the PLL disabled (10 MHz).

The example also shows how to lock the PLL after missing clock detection, by first explicitly switching the clock source to INTOSC1, resetting the missing clock detect circuit and then re-locking the PLL. After that the clock frequency will be restored to the original configuration.

External Connections

  • None.

Watch Variables

  • fail - Indicates that a missing clock was either not detected or was not handled correctly.

  • nmiISRFlag - Indicates that the missing clock failure caused an NMI to be triggered and called the ISR to handle it.

  • mcdDetect - Indicates that a missing clock was detected.

  • result - Status of a successful handling of missing clock detection.