Update repo
This commit is contained in:
@@ -0,0 +1,247 @@
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MEMORY
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{
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PAGE 0: /* Program Memory */
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PAGE 1: /* Data Memory */
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ACCESSPROTECTION : origin = 0x0005F4C0, length = 0x00000040
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ADCA : origin = 0x00007400, length = 0x00000080
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ADCB : origin = 0x00007480, length = 0x00000080
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ADCC : origin = 0x00007500, length = 0x00000080
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ADCD : origin = 0x00007580, length = 0x00000080
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ADCARESULT : origin = 0x00000B00, length = 0x00000018
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ADCBRESULT : origin = 0x00000B20, length = 0x00000018
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ADCCRESULT : origin = 0x00000B40, length = 0x00000018
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ADCDRESULT : origin = 0x00000B60, length = 0x00000018
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ANALOGSUBSYS : origin = 0x0005D180, length = 0x00000048
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CANA : origin = 0x00048000, length = 0x00000200
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CANB : origin = 0x0004A000, length = 0x00000200
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CLA1 : origin = 0x00001400, length = 0x00000080
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CLB1DATAEXCH : origin = 0x00003200, length = 0x00000200
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CLB2DATAEXCH : origin = 0x00003600, length = 0x00000200
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CLB3DATAEXCH : origin = 0x00003A00, length = 0x00000200
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CLB4DATAEXCH : origin = 0x00003E00, length = 0x00000200
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CLB1LOGICCFG : origin = 0x00003000, length = 0x00000052
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CLB2LOGICCFG : origin = 0x00003400, length = 0x00000052
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CLB3LOGICCFG : origin = 0x00003800, length = 0x00000052
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CLB4LOGICCFG : origin = 0x00003C00, length = 0x00000052
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CLB1LOGICCTRL : origin = 0x00003100, length = 0x00000040
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CLB2LOGICCTRL : origin = 0x00003500, length = 0x00000040
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CLB3LOGICCTRL : origin = 0x00003900, length = 0x00000040
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CLB4LOGICCTRL : origin = 0x00003D00, length = 0x00000040
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CLBXBAR : origin = 0x00007A40, length = 0x00000040
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CLKCFG : origin = 0x0005D200, length = 0x00000032
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CMPSS1 : origin = 0x00005C80, length = 0x00000020
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CMPSS2 : origin = 0x00005CA0, length = 0x00000020
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CMPSS3 : origin = 0x00005CC0, length = 0x00000020
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CMPSS4 : origin = 0x00005CE0, length = 0x00000020
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CMPSS5 : origin = 0x00005D00, length = 0x00000020
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CMPSS6 : origin = 0x00005D20, length = 0x00000020
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CMPSS7 : origin = 0x00005D40, length = 0x00000020
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CMPSS8 : origin = 0x00005D60, length = 0x00000020
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CPUTIMER0 : origin = 0x00000C00, length = 0x00000008
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CPUTIMER1 : origin = 0x00000C08, length = 0x00000008
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CPUTIMER2 : origin = 0x00000C10, length = 0x00000008
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CPUSYS : origin = 0x0005D300, length = 0x00000082
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DACA : origin = 0x00005C00, length = 0x00000008
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DACB : origin = 0x00005C10, length = 0x00000008
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DACC : origin = 0x00005C20, length = 0x00000008
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DCSMCOMMON : origin = 0x0005F070, length = 0x00000008
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DCSMZ1 : origin = 0x0005F000, length = 0x00000024
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DCSMZ2 : origin = 0x0005F040, length = 0x00000024
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DEVCFG : origin = 0x0005D000, length = 0x0000012E
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DMACLASRCSEL : origin = 0x00007980, length = 0x0000001A
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DMA : origin = 0x00001000, length = 0x00000200
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ECAP1 : origin = 0x00005000, length = 0x00000020
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ECAP2 : origin = 0x00005020, length = 0x00000020
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ECAP3 : origin = 0x00005040, length = 0x00000020
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ECAP4 : origin = 0x00005060, length = 0x00000020
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ECAP5 : origin = 0x00005080, length = 0x00000020
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ECAP6 : origin = 0x000050A0, length = 0x00000020
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EMIF1CONFIG : origin = 0x0005F480, length = 0x00000020
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EMIF2CONFIG : origin = 0x0005F4A0, length = 0x00000020
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EMIF1 : origin = 0x00047000, length = 0x00000070
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EMIF2 : origin = 0x00047800, length = 0x00000070
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EPWM1 : origin = 0x00004000, length = 0x00000100
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EPWM2 : origin = 0x00004100, length = 0x00000100
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EPWM3 : origin = 0x00004200, length = 0x00000100
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EPWM4 : origin = 0x00004300, length = 0x00000100
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EPWM5 : origin = 0x00004400, length = 0x00000100
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EPWM6 : origin = 0x00004500, length = 0x00000100
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EPWM7 : origin = 0x00004600, length = 0x00000100
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EPWM8 : origin = 0x00004700, length = 0x00000100
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EPWM9 : origin = 0x00004800, length = 0x00000100
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EPWM10 : origin = 0x00004900, length = 0x00000100
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EPWM11 : origin = 0x00004A00, length = 0x00000100
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EPWM12 : origin = 0x00004B00, length = 0x00000100
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EPWMXBAR : origin = 0x00007A00, length = 0x00000040
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EQEP1 : origin = 0x00005100, length = 0x00000022
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EQEP2 : origin = 0x00005140, length = 0x00000022
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EQEP3 : origin = 0x00005180, length = 0x00000022
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FLASH0CTRL : origin = 0x0005F800, length = 0x00000182
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FLASH0ECC : origin = 0x0005FB00, length = 0x00000028
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FLASHPUMPSEMAPHORE : origin = 0x00050024, length = 0x00000002
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GPIOCTRL : origin = 0x00007C00, length = 0x00000180
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GPIODATA : origin = 0x00007F00, length = 0x00000030
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I2CA : origin = 0x00007300, length = 0x00000022
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I2CB : origin = 0x00007340, length = 0x00000022
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INPUTXBAR : origin = 0x00007900, length = 0x00000020
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IPC : origin = 0x00050000, length = 0x00000024
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MEMORYERROR : origin = 0x0005F500, length = 0x00000040
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MEMCFG : origin = 0x0005F400, length = 0x00000080
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MCBSPA : origin = 0x00006000, length = 0x00000024
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MCBSPB : origin = 0x00006040, length = 0x00000024
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NMIINTRUPT : origin = 0x00007060, length = 0x00000007
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OUTPUTXBAR : origin = 0x00007A80, length = 0x00000040
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PIECTRL : origin = 0x00000CE0, length = 0x0000001A
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PIEVECTTABLE : origin = 0x00000D00, length = 0x00000200
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ROMPREFETCH : origin = 0x0005E608, length = 0x00000002
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ROMWAITSTATE : origin = 0x0005F540, length = 0x00000002
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SCIA : origin = 0x00007200, length = 0x00000010
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SCIB : origin = 0x00007210, length = 0x00000010
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SCIC : origin = 0x00007220, length = 0x00000010
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SCID : origin = 0x00007230, length = 0x00000010
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SDFM1 : origin = 0x00005E00, length = 0x00000080
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SDFM2 : origin = 0x00005E80, length = 0x00000080
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SPIA : origin = 0x00006100, length = 0x00000010
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SPIB : origin = 0x00006110, length = 0x00000010
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SPIC : origin = 0x00006120, length = 0x00000010
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SYNCSOC : origin = 0x00007940, length = 0x00000006
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UID : origin = 0x000703C0, length = 0x00000010
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UPP : origin = 0x00006200, length = 0x00000048
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WD : origin = 0x00007000, length = 0x0000002B
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XBAR : origin = 0x00007920, length = 0x00000020
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XINT : origin = 0x00007070, length = 0x0000000B
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}
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SECTIONS
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{
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/*** PIE Vect Table and Boot ROM Variables Structures ***/
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UNION run = PIEVECTTABLE
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{
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PieVectTableFile : TYPE=DSECT
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GROUP
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{
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EmuKeyVar : TYPE=DSECT
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EmuBModeVar : TYPE=DSECT
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EmuBootPinsVar : TYPE=DSECT
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FlashCallbackVar : TYPE=DSECT
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FlashScalingVar : TYPE=DSECT
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}
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}
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AccessProtectionRegsFile : > ACCESSPROTECTION, type=NOINIT
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AdcaRegsFile : > ADCA, type=NOINIT
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AdcbRegsFile : > ADCB, type=NOINIT
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AdccRegsFile : > ADCC, type=NOINIT
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AdcdRegsFile : > ADCD, type=NOINIT
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AdcaResultRegsFile : > ADCARESULT, type=NOINIT
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AdcbResultRegsFile : > ADCBRESULT, type=NOINIT
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AdccResultRegsFile : > ADCCRESULT, type=NOINIT
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AdcdResultRegsFile : > ADCDRESULT, type=NOINIT
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AnalogSubsysRegsFile : > ANALOGSUBSYS, type=NOINIT
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CanaRegsFile : > CANA, type=NOINIT
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CanbRegsFile : > CANB, type=NOINIT
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Cla1RegsFile : > CLA1, type=NOINIT
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Clb1DataExchRegsFile : > CLB1DATAEXCH, type=NOINIT
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Clb2DataExchRegsFile : > CLB2DATAEXCH, type=NOINIT
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Clb3DataExchRegsFile : > CLB3DATAEXCH, type=NOINIT
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Clb4DataExchRegsFile : > CLB4DATAEXCH, type=NOINIT
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Clb1LogicCfgRegsFile : > CLB1LOGICCFG, type=NOINIT
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Clb2LogicCfgRegsFile : > CLB2LOGICCFG, type=NOINIT
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Clb3LogicCfgRegsFile : > CLB3LOGICCFG, type=NOINIT
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Clb4LogicCfgRegsFile : > CLB4LOGICCFG, type=NOINIT
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Clb1LogicCtrlRegsFile : > CLB1LOGICCTRL, type=NOINIT
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Clb2LogicCtrlRegsFile : > CLB2LOGICCTRL, type=NOINIT
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Clb3LogicCtrlRegsFile : > CLB3LOGICCTRL, type=NOINIT
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Clb4LogicCtrlRegsFile : > CLB4LOGICCTRL, type=NOINIT
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ClbXbarRegsFile : > CLBXBAR, type=NOINIT
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ClkCfgRegsFile : > CLKCFG, type=NOINIT
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Cmpss1RegsFile : > CMPSS1, type=NOINIT
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Cmpss2RegsFile : > CMPSS2, type=NOINIT
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Cmpss3RegsFile : > CMPSS3, type=NOINIT
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Cmpss4RegsFile : > CMPSS4, type=NOINIT
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Cmpss5RegsFile : > CMPSS5, type=NOINIT
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Cmpss6RegsFile : > CMPSS6, type=NOINIT
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Cmpss7RegsFile : > CMPSS7, type=NOINIT
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Cmpss8RegsFile : > CMPSS8, type=NOINIT
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CpuTimer0RegsFile : > CPUTIMER0, type=NOINIT
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CpuTimer1RegsFile : > CPUTIMER1, type=NOINIT
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CpuTimer2RegsFile : > CPUTIMER2, type=NOINIT
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CpuSysRegsFile : > CPUSYS, type=NOINIT
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DacaRegsFile : > DACA, type=NOINIT
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DacbRegsFile : > DACB, type=NOINIT
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DaccRegsFile : > DACC, type=NOINIT
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DcsmCommonRegsFile : > DCSMCOMMON, type=NOINIT
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DcsmZ1RegsFile : > DCSMZ1, type=NOINIT
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DcsmZ2RegsFile : > DCSMZ2, type=NOINIT
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DevCfgRegsFile : > DEVCFG, type=NOINIT
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DmaClaSrcSelRegsFile : > DMACLASRCSEL, type=NOINIT
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DmaRegsFile : > DMA, type=NOINIT
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ECap1RegsFile : > ECAP1, type=NOINIT
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ECap2RegsFile : > ECAP2, type=NOINIT
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ECap3RegsFile : > ECAP3, type=NOINIT
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ECap4RegsFile : > ECAP4, type=NOINIT
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ECap5RegsFile : > ECAP5, type=NOINIT
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ECap6RegsFile : > ECAP6, type=NOINIT
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Emif1ConfigRegsFile : > EMIF1CONFIG, type=NOINIT
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Emif2ConfigRegsFile : > EMIF2CONFIG, type=NOINIT
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Emif1RegsFile : > EMIF1, type=NOINIT
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Emif2RegsFile : > EMIF2, type=NOINIT
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EPwm1RegsFile : > EPWM1, type=NOINIT
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EPwm2RegsFile : > EPWM2, type=NOINIT
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EPwm3RegsFile : > EPWM3, type=NOINIT
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EPwm4RegsFile : > EPWM4, type=NOINIT
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EPwm5RegsFile : > EPWM5, type=NOINIT
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EPwm6RegsFile : > EPWM6, type=NOINIT
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EPwm7RegsFile : > EPWM7, type=NOINIT
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EPwm8RegsFile : > EPWM8, type=NOINIT
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EPwm9RegsFile : > EPWM9, type=NOINIT
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EPwm10RegsFile : > EPWM10, type=NOINIT
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EPwm11RegsFile : > EPWM11, type=NOINIT
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EPwm12RegsFile : > EPWM12, type=NOINIT
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EPwmXbarRegsFile : > EPWMXBAR, type=NOINIT
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EQep1RegsFile : > EQEP1, type=NOINIT
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EQep2RegsFile : > EQEP2, type=NOINIT
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EQep3RegsFile : > EQEP3, type=NOINIT
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Flash0CtrlRegsFile : > FLASH0CTRL, type=NOINIT
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Flash0EccRegsFile : > FLASH0ECC, type=NOINIT
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FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, type=NOINIT
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GpioCtrlRegsFile : > GPIOCTRL, type=NOINIT
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GpioDataRegsFile : > GPIODATA, type=NOINIT
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I2caRegsFile : > I2CA, type=NOINIT
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I2cbRegsFile : > I2CB, type=NOINIT
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InputXbarRegsFile : > INPUTXBAR, type=NOINIT
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IpcRegsFile : > IPC, type=NOINIT
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MemoryErrorRegsFile : > MEMORYERROR, type=NOINIT
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MemCfgRegsFile : > MEMCFG, type=NOINIT
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McbspaRegsFile : > MCBSPA, type=NOINIT
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McbspbRegsFile : > MCBSPB, type=NOINIT
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NmiIntruptRegsFile : > NMIINTRUPT, type=NOINIT
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OutputXbarRegsFile : > OUTPUTXBAR, type=NOINIT
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PieCtrlRegsFile : > PIECTRL, type=NOINIT
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RomPrefetchRegsFile : > ROMPREFETCH, type=NOINIT
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RomWaitStateRegsFile : > ROMWAITSTATE, type=NOINIT
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SciaRegsFile : > SCIA, type=NOINIT
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ScibRegsFile : > SCIB, type=NOINIT
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ScicRegsFile : > SCIC, type=NOINIT
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ScidRegsFile : > SCID, type=NOINIT
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Sdfm1RegsFile : > SDFM1, type=NOINIT
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Sdfm2RegsFile : > SDFM2, type=NOINIT
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SpiaRegsFile : > SPIA, type=NOINIT
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SpibRegsFile : > SPIB, type=NOINIT
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SpicRegsFile : > SPIC, type=NOINIT
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SyncSocRegsFile : > SYNCSOC, type=NOINIT
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UidRegsFile : > UID, type=NOINIT
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UppRegsFile : > UPP, type=NOINIT
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WdRegsFile : > WD, type=NOINIT
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XbarRegsFile : > XBAR, type=NOINIT
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XintRegsFile : > XINT, type=NOINIT
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}
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/*
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//===========================================================================
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// End of file.
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//===========================================================================
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*/
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@@ -0,0 +1,221 @@
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MEMORY
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{
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PAGE 0: /* Program Memory */
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PAGE 1: /* Data Memory */
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ACCESSPROTECTION : origin = 0x0005F4C0, length = 0x00000040
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ADCA : origin = 0x00007400, length = 0x00000080
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ADCB : origin = 0x00007480, length = 0x00000080
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ADCC : origin = 0x00007500, length = 0x00000080
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ADCD : origin = 0x00007580, length = 0x00000080
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ADCARESULT : origin = 0x00000B00, length = 0x00000018
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ADCBRESULT : origin = 0x00000B20, length = 0x00000018
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ADCCRESULT : origin = 0x00000B40, length = 0x00000018
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ADCDRESULT : origin = 0x00000B60, length = 0x00000018
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CANA : origin = 0x00048000, length = 0x00000200
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CANB : origin = 0x0004A000, length = 0x00000200
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CLA1 : origin = 0x00001400, length = 0x00000080
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CLB1DATAEXCH : origin = 0x00003200, length = 0x00000200
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CLB2DATAEXCH : origin = 0x00003600, length = 0x00000200
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CLB3DATAEXCH : origin = 0x00003A00, length = 0x00000200
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CLB4DATAEXCH : origin = 0x00003E00, length = 0x00000200
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CLB1LOGICCFG : origin = 0x00003000, length = 0x00000052
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CLB2LOGICCFG : origin = 0x00003400, length = 0x00000052
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CLB3LOGICCFG : origin = 0x00003800, length = 0x00000052
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CLB4LOGICCFG : origin = 0x00003C00, length = 0x00000052
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CLB1LOGICCTRL : origin = 0x00003100, length = 0x00000040
|
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CLB2LOGICCTRL : origin = 0x00003500, length = 0x00000040
|
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CLB3LOGICCTRL : origin = 0x00003900, length = 0x00000040
|
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CLB4LOGICCTRL : origin = 0x00003D00, length = 0x00000040
|
||||
CLKCFG : origin = 0x0005D200, length = 0x00000032
|
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CMPSS1 : origin = 0x00005C80, length = 0x00000020
|
||||
CMPSS2 : origin = 0x00005CA0, length = 0x00000020
|
||||
CMPSS3 : origin = 0x00005CC0, length = 0x00000020
|
||||
CMPSS4 : origin = 0x00005CE0, length = 0x00000020
|
||||
CMPSS5 : origin = 0x00005D00, length = 0x00000020
|
||||
CMPSS6 : origin = 0x00005D20, length = 0x00000020
|
||||
CMPSS7 : origin = 0x00005D40, length = 0x00000020
|
||||
CMPSS8 : origin = 0x00005D60, length = 0x00000020
|
||||
CPUTIMER0 : origin = 0x00000C00, length = 0x00000008
|
||||
CPUTIMER1 : origin = 0x00000C08, length = 0x00000008
|
||||
CPUTIMER2 : origin = 0x00000C10, length = 0x00000008
|
||||
CPUSYS : origin = 0x0005D300, length = 0x00000082
|
||||
DACA : origin = 0x00005C00, length = 0x00000008
|
||||
DACB : origin = 0x00005C10, length = 0x00000008
|
||||
DACC : origin = 0x00005C20, length = 0x00000008
|
||||
DCSMCOMMON : origin = 0x0005F070, length = 0x00000008
|
||||
DCSMZ1 : origin = 0x0005F000, length = 0x00000024
|
||||
DCSMZ2 : origin = 0x0005F040, length = 0x00000024
|
||||
DMACLASRCSEL : origin = 0x00007980, length = 0x0000001A
|
||||
DMA : origin = 0x00001000, length = 0x00000200
|
||||
ECAP1 : origin = 0x00005000, length = 0x00000020
|
||||
ECAP2 : origin = 0x00005020, length = 0x00000020
|
||||
ECAP3 : origin = 0x00005040, length = 0x00000020
|
||||
ECAP4 : origin = 0x00005060, length = 0x00000020
|
||||
ECAP5 : origin = 0x00005080, length = 0x00000020
|
||||
ECAP6 : origin = 0x000050A0, length = 0x00000020
|
||||
EMIF1CONFIG : origin = 0x0005F480, length = 0x00000020
|
||||
EMIF1 : origin = 0x00047000, length = 0x00000070
|
||||
EPWM1 : origin = 0x00004000, length = 0x00000100
|
||||
EPWM2 : origin = 0x00004100, length = 0x00000100
|
||||
EPWM3 : origin = 0x00004200, length = 0x00000100
|
||||
EPWM4 : origin = 0x00004300, length = 0x00000100
|
||||
EPWM5 : origin = 0x00004400, length = 0x00000100
|
||||
EPWM6 : origin = 0x00004500, length = 0x00000100
|
||||
EPWM7 : origin = 0x00004600, length = 0x00000100
|
||||
EPWM8 : origin = 0x00004700, length = 0x00000100
|
||||
EPWM9 : origin = 0x00004800, length = 0x00000100
|
||||
EPWM10 : origin = 0x00004900, length = 0x00000100
|
||||
EPWM11 : origin = 0x00004A00, length = 0x00000100
|
||||
EPWM12 : origin = 0x00004B00, length = 0x00000100
|
||||
EQEP1 : origin = 0x00005100, length = 0x00000022
|
||||
EQEP2 : origin = 0x00005140, length = 0x00000022
|
||||
EQEP3 : origin = 0x00005180, length = 0x00000022
|
||||
FLASH0CTRL : origin = 0x0005F800, length = 0x00000182
|
||||
FLASH0ECC : origin = 0x0005FB00, length = 0x00000028
|
||||
FLASHPUMPSEMAPHORE : origin = 0x00050024, length = 0x00000002
|
||||
GPIODATA : origin = 0x00007F00, length = 0x00000030
|
||||
I2CA : origin = 0x00007300, length = 0x00000022
|
||||
I2CB : origin = 0x00007340, length = 0x00000022
|
||||
IPC : origin = 0x00050000, length = 0x00000024
|
||||
MEMORYERROR : origin = 0x0005F500, length = 0x00000040
|
||||
MEMCFG : origin = 0x0005F400, length = 0x00000080
|
||||
MCBSPA : origin = 0x00006000, length = 0x00000024
|
||||
MCBSPB : origin = 0x00006040, length = 0x00000024
|
||||
NMIINTRUPT : origin = 0x00007060, length = 0x00000007
|
||||
PIECTRL : origin = 0x00000CE0, length = 0x0000001A
|
||||
PIEVECTTABLE : origin = 0x00000D00, length = 0x00000200
|
||||
ROMPREFETCH : origin = 0x0005E608, length = 0x00000002
|
||||
SCIA : origin = 0x00007200, length = 0x00000010
|
||||
SCIB : origin = 0x00007210, length = 0x00000010
|
||||
SCIC : origin = 0x00007220, length = 0x00000010
|
||||
SCID : origin = 0x00007230, length = 0x00000010
|
||||
SDFM1 : origin = 0x00005E00, length = 0x00000080
|
||||
SDFM2 : origin = 0x00005E80, length = 0x00000080
|
||||
SPIA : origin = 0x00006100, length = 0x00000010
|
||||
SPIB : origin = 0x00006110, length = 0x00000010
|
||||
SPIC : origin = 0x00006120, length = 0x00000010
|
||||
UID : origin = 0x000703C0, length = 0x00000010
|
||||
WD : origin = 0x00007000, length = 0x0000002B
|
||||
XINT : origin = 0x00007070, length = 0x0000000B
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*** PIE Vect Table and Boot ROM Variables Structures ***/
|
||||
UNION run = PIEVECTTABLE
|
||||
{
|
||||
PieVectTableFile : TYPE=DSECT
|
||||
GROUP
|
||||
{
|
||||
EmuKeyVar : TYPE=DSECT
|
||||
EmuBModeVar : TYPE=DSECT
|
||||
EmuBootPinsVar : TYPE=DSECT
|
||||
FlashCallbackVar : TYPE=DSECT
|
||||
FlashScalingVar : TYPE=DSECT
|
||||
}
|
||||
}
|
||||
|
||||
AccessProtectionRegsFile : > ACCESSPROTECTION, type=NOINIT
|
||||
AdcaRegsFile : > ADCA, type=NOINIT
|
||||
AdcbRegsFile : > ADCB, type=NOINIT
|
||||
AdccRegsFile : > ADCC, type=NOINIT
|
||||
AdcdRegsFile : > ADCD, type=NOINIT
|
||||
AdcaResultRegsFile : > ADCARESULT, type=NOINIT
|
||||
AdcbResultRegsFile : > ADCBRESULT, type=NOINIT
|
||||
AdccResultRegsFile : > ADCCRESULT, type=NOINIT
|
||||
AdcdResultRegsFile : > ADCDRESULT, type=NOINIT
|
||||
CanaRegsFile : > CANA, type=NOINIT
|
||||
CanbRegsFile : > CANB, type=NOINIT
|
||||
Cla1RegsFile : > CLA1, type=NOINIT
|
||||
Clb1DataExchRegsFile : > CLB1DATAEXCH, type=NOINIT
|
||||
Clb2DataExchRegsFile : > CLB2DATAEXCH, type=NOINIT
|
||||
Clb3DataExchRegsFile : > CLB3DATAEXCH, type=NOINIT
|
||||
Clb4DataExchRegsFile : > CLB4DATAEXCH, type=NOINIT
|
||||
Clb1LogicCfgRegsFile : > CLB1LOGICCFG, type=NOINIT
|
||||
Clb2LogicCfgRegsFile : > CLB2LOGICCFG, type=NOINIT
|
||||
Clb3LogicCfgRegsFile : > CLB3LOGICCFG, type=NOINIT
|
||||
Clb4LogicCfgRegsFile : > CLB4LOGICCFG, type=NOINIT
|
||||
Clb1LogicCtrlRegsFile : > CLB1LOGICCTRL, type=NOINIT
|
||||
Clb2LogicCtrlRegsFile : > CLB2LOGICCTRL, type=NOINIT
|
||||
Clb3LogicCtrlRegsFile : > CLB3LOGICCTRL, type=NOINIT
|
||||
Clb4LogicCtrlRegsFile : > CLB4LOGICCTRL, type=NOINIT
|
||||
ClkCfgRegsFile : > CLKCFG, type=NOINIT
|
||||
Cmpss1RegsFile : > CMPSS1, type=NOINIT
|
||||
Cmpss2RegsFile : > CMPSS2, type=NOINIT
|
||||
Cmpss3RegsFile : > CMPSS3, type=NOINIT
|
||||
Cmpss4RegsFile : > CMPSS4, type=NOINIT
|
||||
Cmpss5RegsFile : > CMPSS5, type=NOINIT
|
||||
Cmpss6RegsFile : > CMPSS6, type=NOINIT
|
||||
Cmpss7RegsFile : > CMPSS7, type=NOINIT
|
||||
Cmpss8RegsFile : > CMPSS8, type=NOINIT
|
||||
CpuTimer0RegsFile : > CPUTIMER0, type=NOINIT
|
||||
CpuTimer1RegsFile : > CPUTIMER1, type=NOINIT
|
||||
CpuTimer2RegsFile : > CPUTIMER2, type=NOINIT
|
||||
CpuSysRegsFile : > CPUSYS, type=NOINIT
|
||||
DacaRegsFile : > DACA, type=NOINIT
|
||||
DacbRegsFile : > DACB, type=NOINIT
|
||||
DaccRegsFile : > DACC, type=NOINIT
|
||||
DcsmCommonRegsFile : > DCSMCOMMON, type=NOINIT
|
||||
DcsmZ1RegsFile : > DCSMZ1, type=NOINIT
|
||||
DcsmZ2RegsFile : > DCSMZ2, type=NOINIT
|
||||
DmaClaSrcSelRegsFile : > DMACLASRCSEL, type=NOINIT
|
||||
DmaRegsFile : > DMA, type=NOINIT
|
||||
ECap1RegsFile : > ECAP1, type=NOINIT
|
||||
ECap2RegsFile : > ECAP2, type=NOINIT
|
||||
ECap3RegsFile : > ECAP3, type=NOINIT
|
||||
ECap4RegsFile : > ECAP4, type=NOINIT
|
||||
ECap5RegsFile : > ECAP5, type=NOINIT
|
||||
ECap6RegsFile : > ECAP6, type=NOINIT
|
||||
Emif1ConfigRegsFile : > EMIF1CONFIG, type=NOINIT
|
||||
Emif1RegsFile : > EMIF1, type=NOINIT
|
||||
EPwm1RegsFile : > EPWM1, type=NOINIT
|
||||
EPwm2RegsFile : > EPWM2, type=NOINIT
|
||||
EPwm3RegsFile : > EPWM3, type=NOINIT
|
||||
EPwm4RegsFile : > EPWM4, type=NOINIT
|
||||
EPwm5RegsFile : > EPWM5, type=NOINIT
|
||||
EPwm6RegsFile : > EPWM6, type=NOINIT
|
||||
EPwm7RegsFile : > EPWM7, type=NOINIT
|
||||
EPwm8RegsFile : > EPWM8, type=NOINIT
|
||||
EPwm9RegsFile : > EPWM9, type=NOINIT
|
||||
EPwm10RegsFile : > EPWM10, type=NOINIT
|
||||
EPwm11RegsFile : > EPWM11, type=NOINIT
|
||||
EPwm12RegsFile : > EPWM12, type=NOINIT
|
||||
EQep1RegsFile : > EQEP1, type=NOINIT
|
||||
EQep2RegsFile : > EQEP2, type=NOINIT
|
||||
EQep3RegsFile : > EQEP3, type=NOINIT
|
||||
Flash0CtrlRegsFile : > FLASH0CTRL, type=NOINIT
|
||||
Flash0EccRegsFile : > FLASH0ECC, type=NOINIT
|
||||
FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, type=NOINIT
|
||||
GpioDataRegsFile : > GPIODATA, type=NOINIT
|
||||
I2caRegsFile : > I2CA, type=NOINIT
|
||||
I2cbRegsFile : > I2CB, type=NOINIT
|
||||
IpcRegsFile : > IPC, type=NOINIT
|
||||
MemoryErrorRegsFile : > MEMORYERROR, type=NOINIT
|
||||
MemCfgRegsFile : > MEMCFG, type=NOINIT
|
||||
McbspaRegsFile : > MCBSPA, type=NOINIT
|
||||
McbspbRegsFile : > MCBSPB, type=NOINIT
|
||||
NmiIntruptRegsFile : > NMIINTRUPT, type=NOINIT
|
||||
PieCtrlRegsFile : > PIECTRL, type=NOINIT
|
||||
RomPrefetchRegsFile : > ROMPREFETCH, type=NOINIT
|
||||
SciaRegsFile : > SCIA, type=NOINIT
|
||||
ScibRegsFile : > SCIB, type=NOINIT
|
||||
ScicRegsFile : > SCIC, type=NOINIT
|
||||
ScidRegsFile : > SCID, type=NOINIT
|
||||
Sdfm1RegsFile : > SDFM1, type=NOINIT
|
||||
Sdfm2RegsFile : > SDFM2, type=NOINIT
|
||||
SpiaRegsFile : > SPIA, type=NOINIT
|
||||
SpibRegsFile : > SPIB, type=NOINIT
|
||||
SpicRegsFile : > SPIC, type=NOINIT
|
||||
UidRegsFile : > UID, type=NOINIT
|
||||
WdRegsFile : > WD, type=NOINIT
|
||||
XintRegsFile : > XINT, type=NOINIT
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
|
||||
@@ -0,0 +1,247 @@
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0: /* Program Memory */
|
||||
PAGE 1: /* Data Memory */
|
||||
ACCESSPROTECTION : origin = 0x0005F4C0, length = 0x00000040
|
||||
ADCA : origin = 0x00007400, length = 0x00000080
|
||||
ADCB : origin = 0x00007480, length = 0x00000080
|
||||
ADCC : origin = 0x00007500, length = 0x00000080
|
||||
ADCD : origin = 0x00007580, length = 0x00000080
|
||||
ADCARESULT : origin = 0x00000B00, length = 0x00000018
|
||||
ADCBRESULT : origin = 0x00000B20, length = 0x00000018
|
||||
ADCCRESULT : origin = 0x00000B40, length = 0x00000018
|
||||
ADCDRESULT : origin = 0x00000B60, length = 0x00000018
|
||||
ANALOGSUBSYS : origin = 0x0005D180, length = 0x00000048
|
||||
CANA : origin = 0x00048000, length = 0x00000200
|
||||
CANB : origin = 0x0004A000, length = 0x00000200
|
||||
CLA1 : origin = 0x00001400, length = 0x00000080
|
||||
CLB1DATAEXCH : origin = 0x00003200, length = 0x00000200
|
||||
CLB2DATAEXCH : origin = 0x00003600, length = 0x00000200
|
||||
CLB3DATAEXCH : origin = 0x00003A00, length = 0x00000200
|
||||
CLB4DATAEXCH : origin = 0x00003E00, length = 0x00000200
|
||||
CLB1LOGICCFG : origin = 0x00003000, length = 0x00000052
|
||||
CLB2LOGICCFG : origin = 0x00003400, length = 0x00000052
|
||||
CLB3LOGICCFG : origin = 0x00003800, length = 0x00000052
|
||||
CLB4LOGICCFG : origin = 0x00003C00, length = 0x00000052
|
||||
CLB1LOGICCTRL : origin = 0x00003100, length = 0x00000040
|
||||
CLB2LOGICCTRL : origin = 0x00003500, length = 0x00000040
|
||||
CLB3LOGICCTRL : origin = 0x00003900, length = 0x00000040
|
||||
CLB4LOGICCTRL : origin = 0x00003D00, length = 0x00000040
|
||||
CLBXBAR : origin = 0x00007A40, length = 0x00000040
|
||||
CLKCFG : origin = 0x0005D200, length = 0x00000032
|
||||
CMPSS1 : origin = 0x00005C80, length = 0x00000020
|
||||
CMPSS2 : origin = 0x00005CA0, length = 0x00000020
|
||||
CMPSS3 : origin = 0x00005CC0, length = 0x00000020
|
||||
CMPSS4 : origin = 0x00005CE0, length = 0x00000020
|
||||
CMPSS5 : origin = 0x00005D00, length = 0x00000020
|
||||
CMPSS6 : origin = 0x00005D20, length = 0x00000020
|
||||
CMPSS7 : origin = 0x00005D40, length = 0x00000020
|
||||
CMPSS8 : origin = 0x00005D60, length = 0x00000020
|
||||
CPUTIMER0 : origin = 0x00000C00, length = 0x00000008
|
||||
CPUTIMER1 : origin = 0x00000C08, length = 0x00000008
|
||||
CPUTIMER2 : origin = 0x00000C10, length = 0x00000008
|
||||
CPUSYS : origin = 0x0005D300, length = 0x00000082
|
||||
DACA : origin = 0x00005C00, length = 0x00000008
|
||||
DACB : origin = 0x00005C10, length = 0x00000008
|
||||
DACC : origin = 0x00005C20, length = 0x00000008
|
||||
DCSMCOMMON : origin = 0x0005F070, length = 0x00000008
|
||||
DCSMZ1 : origin = 0x0005F000, length = 0x00000024
|
||||
DCSMZ2 : origin = 0x0005F040, length = 0x00000024
|
||||
DEVCFG : origin = 0x0005D000, length = 0x0000012E
|
||||
DMACLASRCSEL : origin = 0x00007980, length = 0x0000001A
|
||||
DMA : origin = 0x00001000, length = 0x00000200
|
||||
ECAP1 : origin = 0x00005000, length = 0x00000020
|
||||
ECAP2 : origin = 0x00005020, length = 0x00000020
|
||||
ECAP3 : origin = 0x00005040, length = 0x00000020
|
||||
ECAP4 : origin = 0x00005060, length = 0x00000020
|
||||
ECAP5 : origin = 0x00005080, length = 0x00000020
|
||||
ECAP6 : origin = 0x000050A0, length = 0x00000020
|
||||
EMIF1CONFIG : origin = 0x0005F480, length = 0x00000020
|
||||
EMIF2CONFIG : origin = 0x0005F4A0, length = 0x00000020
|
||||
EMIF1 : origin = 0x00047000, length = 0x00000070
|
||||
EMIF2 : origin = 0x00047800, length = 0x00000070
|
||||
EPWM1 : origin = 0x00004000, length = 0x00000100
|
||||
EPWM2 : origin = 0x00004100, length = 0x00000100
|
||||
EPWM3 : origin = 0x00004200, length = 0x00000100
|
||||
EPWM4 : origin = 0x00004300, length = 0x00000100
|
||||
EPWM5 : origin = 0x00004400, length = 0x00000100
|
||||
EPWM6 : origin = 0x00004500, length = 0x00000100
|
||||
EPWM7 : origin = 0x00004600, length = 0x00000100
|
||||
EPWM8 : origin = 0x00004700, length = 0x00000100
|
||||
EPWM9 : origin = 0x00004800, length = 0x00000100
|
||||
EPWM10 : origin = 0x00004900, length = 0x00000100
|
||||
EPWM11 : origin = 0x00004A00, length = 0x00000100
|
||||
EPWM12 : origin = 0x00004B00, length = 0x00000100
|
||||
EPWMXBAR : origin = 0x00007A00, length = 0x00000040
|
||||
EQEP1 : origin = 0x00005100, length = 0x00000022
|
||||
EQEP2 : origin = 0x00005140, length = 0x00000022
|
||||
EQEP3 : origin = 0x00005180, length = 0x00000022
|
||||
FLASH0CTRL : origin = 0x0005F800, length = 0x00000182
|
||||
FLASH0ECC : origin = 0x0005FB00, length = 0x00000028
|
||||
FLASHPUMPSEMAPHORE : origin = 0x00050024, length = 0x00000002
|
||||
GPIOCTRL : origin = 0x00007C00, length = 0x00000180
|
||||
GPIODATA : origin = 0x00007F00, length = 0x00000030
|
||||
I2CA : origin = 0x00007300, length = 0x00000022
|
||||
I2CB : origin = 0x00007340, length = 0x00000022
|
||||
INPUTXBAR : origin = 0x00007900, length = 0x00000020
|
||||
IPC : origin = 0x00050000, length = 0x00000024
|
||||
MEMORYERROR : origin = 0x0005F500, length = 0x00000040
|
||||
MEMCFG : origin = 0x0005F400, length = 0x00000080
|
||||
MCBSPA : origin = 0x00006000, length = 0x00000024
|
||||
MCBSPB : origin = 0x00006040, length = 0x00000024
|
||||
NMIINTRUPT : origin = 0x00007060, length = 0x00000007
|
||||
OUTPUTXBAR : origin = 0x00007A80, length = 0x00000040
|
||||
PIECTRL : origin = 0x00000CE0, length = 0x0000001A
|
||||
PIEVECTTABLE : origin = 0x00000D00, length = 0x00000200
|
||||
ROMPREFETCH : origin = 0x0005E608, length = 0x00000002
|
||||
ROMWAITSTATE : origin = 0x0005F540, length = 0x00000002
|
||||
SCIA : origin = 0x00007200, length = 0x00000010
|
||||
SCIB : origin = 0x00007210, length = 0x00000010
|
||||
SCIC : origin = 0x00007220, length = 0x00000010
|
||||
SCID : origin = 0x00007230, length = 0x00000010
|
||||
SDFM1 : origin = 0x00005E00, length = 0x00000080
|
||||
SDFM2 : origin = 0x00005E80, length = 0x00000080
|
||||
SPIA : origin = 0x00006100, length = 0x00000010
|
||||
SPIB : origin = 0x00006110, length = 0x00000010
|
||||
SPIC : origin = 0x00006120, length = 0x00000010
|
||||
SYNCSOC : origin = 0x00007940, length = 0x00000006
|
||||
UID : origin = 0x000703C0, length = 0x00000010
|
||||
UPP : origin = 0x00006200, length = 0x00000048
|
||||
WD : origin = 0x00007000, length = 0x0000002B
|
||||
XBAR : origin = 0x00007920, length = 0x00000020
|
||||
XINT : origin = 0x00007070, length = 0x0000000B
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*** PIE Vect Table and Boot ROM Variables Structures ***/
|
||||
UNION run = PIEVECTTABLE
|
||||
{
|
||||
PieVectTableFile
|
||||
GROUP
|
||||
{
|
||||
EmuKeyVar
|
||||
EmuBModeVar
|
||||
EmuBootPinsVar
|
||||
FlashCallbackVar
|
||||
FlashScalingVar
|
||||
}
|
||||
}
|
||||
|
||||
AccessProtectionRegsFile : > ACCESSPROTECTION, type=NOINIT
|
||||
AdcaRegsFile : > ADCA, type=NOINIT
|
||||
AdcbRegsFile : > ADCB, type=NOINIT
|
||||
AdccRegsFile : > ADCC, type=NOINIT
|
||||
AdcdRegsFile : > ADCD, type=NOINIT
|
||||
AdcaResultRegsFile : > ADCARESULT, type=NOINIT
|
||||
AdcbResultRegsFile : > ADCBRESULT, type=NOINIT
|
||||
AdccResultRegsFile : > ADCCRESULT, type=NOINIT
|
||||
AdcdResultRegsFile : > ADCDRESULT, type=NOINIT
|
||||
AnalogSubsysRegsFile : > ANALOGSUBSYS, type=NOINIT
|
||||
CanaRegsFile : > CANA, type=NOINIT
|
||||
CanbRegsFile : > CANB, type=NOINIT
|
||||
Cla1RegsFile : > CLA1, type=NOINIT
|
||||
Clb1DataExchRegsFile : > CLB1DATAEXCH, type=NOINIT
|
||||
Clb2DataExchRegsFile : > CLB2DATAEXCH, type=NOINIT
|
||||
Clb3DataExchRegsFile : > CLB3DATAEXCH, type=NOINIT
|
||||
Clb4DataExchRegsFile : > CLB4DATAEXCH, type=NOINIT
|
||||
Clb1LogicCfgRegsFile : > CLB1LOGICCFG, type=NOINIT
|
||||
Clb2LogicCfgRegsFile : > CLB2LOGICCFG, type=NOINIT
|
||||
Clb3LogicCfgRegsFile : > CLB3LOGICCFG, type=NOINIT
|
||||
Clb4LogicCfgRegsFile : > CLB4LOGICCFG, type=NOINIT
|
||||
Clb1LogicCtrlRegsFile : > CLB1LOGICCTRL, type=NOINIT
|
||||
Clb2LogicCtrlRegsFile : > CLB2LOGICCTRL, type=NOINIT
|
||||
Clb3LogicCtrlRegsFile : > CLB3LOGICCTRL, type=NOINIT
|
||||
Clb4LogicCtrlRegsFile : > CLB4LOGICCTRL, type=NOINIT
|
||||
ClbXbarRegsFile : > CLBXBAR, type=NOINIT
|
||||
ClkCfgRegsFile : > CLKCFG, type=NOINIT
|
||||
Cmpss1RegsFile : > CMPSS1, type=NOINIT
|
||||
Cmpss2RegsFile : > CMPSS2, type=NOINIT
|
||||
Cmpss3RegsFile : > CMPSS3, type=NOINIT
|
||||
Cmpss4RegsFile : > CMPSS4, type=NOINIT
|
||||
Cmpss5RegsFile : > CMPSS5, type=NOINIT
|
||||
Cmpss6RegsFile : > CMPSS6, type=NOINIT
|
||||
Cmpss7RegsFile : > CMPSS7, type=NOINIT
|
||||
Cmpss8RegsFile : > CMPSS8, type=NOINIT
|
||||
CpuTimer0RegsFile : > CPUTIMER0, type=NOINIT
|
||||
CpuTimer1RegsFile : > CPUTIMER1, type=NOINIT
|
||||
CpuTimer2RegsFile : > CPUTIMER2, type=NOINIT
|
||||
CpuSysRegsFile : > CPUSYS, type=NOINIT
|
||||
DacaRegsFile : > DACA, type=NOINIT
|
||||
DacbRegsFile : > DACB, type=NOINIT
|
||||
DaccRegsFile : > DACC, type=NOINIT
|
||||
DcsmCommonRegsFile : > DCSMCOMMON, type=NOINIT
|
||||
DcsmZ1RegsFile : > DCSMZ1, type=NOINIT
|
||||
DcsmZ2RegsFile : > DCSMZ2, type=NOINIT
|
||||
DevCfgRegsFile : > DEVCFG, type=NOINIT
|
||||
DmaClaSrcSelRegsFile : > DMACLASRCSEL, type=NOINIT
|
||||
DmaRegsFile : > DMA, type=NOINIT
|
||||
ECap1RegsFile : > ECAP1, type=NOINIT
|
||||
ECap2RegsFile : > ECAP2, type=NOINIT
|
||||
ECap3RegsFile : > ECAP3, type=NOINIT
|
||||
ECap4RegsFile : > ECAP4, type=NOINIT
|
||||
ECap5RegsFile : > ECAP5, type=NOINIT
|
||||
ECap6RegsFile : > ECAP6, type=NOINIT
|
||||
Emif1ConfigRegsFile : > EMIF1CONFIG, type=NOINIT
|
||||
Emif2ConfigRegsFile : > EMIF2CONFIG, type=NOINIT
|
||||
Emif1RegsFile : > EMIF1, type=NOINIT
|
||||
Emif2RegsFile : > EMIF2, type=NOINIT
|
||||
EPwm1RegsFile : > EPWM1, type=NOINIT
|
||||
EPwm2RegsFile : > EPWM2, type=NOINIT
|
||||
EPwm3RegsFile : > EPWM3, type=NOINIT
|
||||
EPwm4RegsFile : > EPWM4, type=NOINIT
|
||||
EPwm5RegsFile : > EPWM5, type=NOINIT
|
||||
EPwm6RegsFile : > EPWM6, type=NOINIT
|
||||
EPwm7RegsFile : > EPWM7, type=NOINIT
|
||||
EPwm8RegsFile : > EPWM8, type=NOINIT
|
||||
EPwm9RegsFile : > EPWM9, type=NOINIT
|
||||
EPwm10RegsFile : > EPWM10, type=NOINIT
|
||||
EPwm11RegsFile : > EPWM11, type=NOINIT
|
||||
EPwm12RegsFile : > EPWM12, type=NOINIT
|
||||
EPwmXbarRegsFile : > EPWMXBAR, type=NOINIT
|
||||
EQep1RegsFile : > EQEP1, type=NOINIT
|
||||
EQep2RegsFile : > EQEP2, type=NOINIT
|
||||
EQep3RegsFile : > EQEP3, type=NOINIT
|
||||
Flash0CtrlRegsFile : > FLASH0CTRL, type=NOINIT
|
||||
Flash0EccRegsFile : > FLASH0ECC, type=NOINIT
|
||||
FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, type=NOINIT
|
||||
GpioCtrlRegsFile : > GPIOCTRL, type=NOINIT
|
||||
GpioDataRegsFile : > GPIODATA, type=NOINIT
|
||||
I2caRegsFile : > I2CA, type=NOINIT
|
||||
I2cbRegsFile : > I2CB, type=NOINIT
|
||||
InputXbarRegsFile : > INPUTXBAR, type=NOINIT
|
||||
IpcRegsFile : > IPC, type=NOINIT
|
||||
MemoryErrorRegsFile : > MEMORYERROR, type=NOINIT
|
||||
MemCfgRegsFile : > MEMCFG, type=NOINIT
|
||||
McbspaRegsFile : > MCBSPA, type=NOINIT
|
||||
McbspbRegsFile : > MCBSPB, type=NOINIT
|
||||
NmiIntruptRegsFile : > NMIINTRUPT, type=NOINIT
|
||||
OutputXbarRegsFile : > OUTPUTXBAR, type=NOINIT
|
||||
PieCtrlRegsFile : > PIECTRL, type=NOINIT
|
||||
RomPrefetchRegsFile : > ROMPREFETCH, type=NOINIT
|
||||
RomWaitStateRegsFile : > ROMWAITSTATE, type=NOINIT
|
||||
SciaRegsFile : > SCIA, type=NOINIT
|
||||
ScibRegsFile : > SCIB, type=NOINIT
|
||||
ScicRegsFile : > SCIC, type=NOINIT
|
||||
ScidRegsFile : > SCID, type=NOINIT
|
||||
Sdfm1RegsFile : > SDFM1, type=NOINIT
|
||||
Sdfm2RegsFile : > SDFM2, type=NOINIT
|
||||
SpiaRegsFile : > SPIA, type=NOINIT
|
||||
SpibRegsFile : > SPIB, type=NOINIT
|
||||
SpicRegsFile : > SPIC, type=NOINIT
|
||||
SyncSocRegsFile : > SYNCSOC, type=NOINIT
|
||||
UppRegsFile : > UPP, type=NOINIT
|
||||
WdRegsFile : > WD, type=NOINIT
|
||||
UidRegsFile : > UID, type=NOINIT
|
||||
XbarRegsFile : > XBAR, type=NOINIT
|
||||
XintRegsFile : > XINT, type=NOINIT
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
|
||||
@@ -0,0 +1,221 @@
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0: /* Program Memory */
|
||||
PAGE 1: /* Data Memory */
|
||||
ACCESSPROTECTION : origin = 0x0005F4C0, length = 0x00000040
|
||||
ADCA : origin = 0x00007400, length = 0x00000080
|
||||
ADCB : origin = 0x00007480, length = 0x00000080
|
||||
ADCC : origin = 0x00007500, length = 0x00000080
|
||||
ADCD : origin = 0x00007580, length = 0x00000080
|
||||
ADCARESULT : origin = 0x00000B00, length = 0x00000018
|
||||
ADCBRESULT : origin = 0x00000B20, length = 0x00000018
|
||||
ADCCRESULT : origin = 0x00000B40, length = 0x00000018
|
||||
ADCDRESULT : origin = 0x00000B60, length = 0x00000018
|
||||
CANA : origin = 0x00048000, length = 0x00000200
|
||||
CANB : origin = 0x0004A000, length = 0x00000200
|
||||
CLA1 : origin = 0x00001400, length = 0x00000080
|
||||
CLB1DATAEXCH : origin = 0x00003200, length = 0x00000200
|
||||
CLB2DATAEXCH : origin = 0x00003600, length = 0x00000200
|
||||
CLB3DATAEXCH : origin = 0x00003A00, length = 0x00000200
|
||||
CLB4DATAEXCH : origin = 0x00003E00, length = 0x00000200
|
||||
CLB1LOGICCFG : origin = 0x00003000, length = 0x00000052
|
||||
CLB2LOGICCFG : origin = 0x00003400, length = 0x00000052
|
||||
CLB3LOGICCFG : origin = 0x00003800, length = 0x00000052
|
||||
CLB4LOGICCFG : origin = 0x00003C00, length = 0x00000052
|
||||
CLB1LOGICCTRL : origin = 0x00003100, length = 0x00000040
|
||||
CLB2LOGICCTRL : origin = 0x00003500, length = 0x00000040
|
||||
CLB3LOGICCTRL : origin = 0x00003900, length = 0x00000040
|
||||
CLB4LOGICCTRL : origin = 0x00003D00, length = 0x00000040
|
||||
CLKCFG : origin = 0x0005D200, length = 0x00000032
|
||||
CMPSS1 : origin = 0x00005C80, length = 0x00000020
|
||||
CMPSS2 : origin = 0x00005CA0, length = 0x00000020
|
||||
CMPSS3 : origin = 0x00005CC0, length = 0x00000020
|
||||
CMPSS4 : origin = 0x00005CE0, length = 0x00000020
|
||||
CMPSS5 : origin = 0x00005D00, length = 0x00000020
|
||||
CMPSS6 : origin = 0x00005D20, length = 0x00000020
|
||||
CMPSS7 : origin = 0x00005D40, length = 0x00000020
|
||||
CMPSS8 : origin = 0x00005D60, length = 0x00000020
|
||||
CPUTIMER0 : origin = 0x00000C00, length = 0x00000008
|
||||
CPUTIMER1 : origin = 0x00000C08, length = 0x00000008
|
||||
CPUTIMER2 : origin = 0x00000C10, length = 0x00000008
|
||||
CPUSYS : origin = 0x0005D300, length = 0x00000082
|
||||
DACA : origin = 0x00005C00, length = 0x00000008
|
||||
DACB : origin = 0x00005C10, length = 0x00000008
|
||||
DACC : origin = 0x00005C20, length = 0x00000008
|
||||
DCSMCOMMON : origin = 0x0005F070, length = 0x00000008
|
||||
DCSMZ1 : origin = 0x0005F000, length = 0x00000024
|
||||
DCSMZ2 : origin = 0x0005F040, length = 0x00000024
|
||||
DMACLASRCSEL : origin = 0x00007980, length = 0x0000001A
|
||||
DMA : origin = 0x00001000, length = 0x00000200
|
||||
ECAP1 : origin = 0x00005000, length = 0x00000020
|
||||
ECAP2 : origin = 0x00005020, length = 0x00000020
|
||||
ECAP3 : origin = 0x00005040, length = 0x00000020
|
||||
ECAP4 : origin = 0x00005060, length = 0x00000020
|
||||
ECAP5 : origin = 0x00005080, length = 0x00000020
|
||||
ECAP6 : origin = 0x000050A0, length = 0x00000020
|
||||
EMIF1CONFIG : origin = 0x0005F480, length = 0x00000020
|
||||
EMIF1 : origin = 0x00047000, length = 0x00000070
|
||||
EPWM1 : origin = 0x00004000, length = 0x00000100
|
||||
EPWM2 : origin = 0x00004100, length = 0x00000100
|
||||
EPWM3 : origin = 0x00004200, length = 0x00000100
|
||||
EPWM4 : origin = 0x00004300, length = 0x00000100
|
||||
EPWM5 : origin = 0x00004400, length = 0x00000100
|
||||
EPWM6 : origin = 0x00004500, length = 0x00000100
|
||||
EPWM7 : origin = 0x00004600, length = 0x00000100
|
||||
EPWM8 : origin = 0x00004700, length = 0x00000100
|
||||
EPWM9 : origin = 0x00004800, length = 0x00000100
|
||||
EPWM10 : origin = 0x00004900, length = 0x00000100
|
||||
EPWM11 : origin = 0x00004A00, length = 0x00000100
|
||||
EPWM12 : origin = 0x00004B00, length = 0x00000100
|
||||
EQEP1 : origin = 0x00005100, length = 0x00000022
|
||||
EQEP2 : origin = 0x00005140, length = 0x00000022
|
||||
EQEP3 : origin = 0x00005180, length = 0x00000022
|
||||
FLASH0CTRL : origin = 0x0005F800, length = 0x00000182
|
||||
FLASH0ECC : origin = 0x0005FB00, length = 0x00000028
|
||||
FLASHPUMPSEMAPHORE : origin = 0x00050024, length = 0x00000002
|
||||
GPIODATA : origin = 0x00007F00, length = 0x00000030
|
||||
I2CA : origin = 0x00007300, length = 0x00000022
|
||||
I2CB : origin = 0x00007340, length = 0x00000022
|
||||
IPC : origin = 0x00050000, length = 0x00000024
|
||||
MEMORYERROR : origin = 0x0005F500, length = 0x00000040
|
||||
MEMCFG : origin = 0x0005F400, length = 0x00000080
|
||||
MCBSPA : origin = 0x00006000, length = 0x00000024
|
||||
MCBSPB : origin = 0x00006040, length = 0x00000024
|
||||
NMIINTRUPT : origin = 0x00007060, length = 0x00000007
|
||||
PIECTRL : origin = 0x00000CE0, length = 0x0000001A
|
||||
PIEVECTTABLE : origin = 0x00000D00, length = 0x00000200
|
||||
ROMPREFETCH : origin = 0x0005E608, length = 0x00000002
|
||||
SCIA : origin = 0x00007200, length = 0x00000010
|
||||
SCIB : origin = 0x00007210, length = 0x00000010
|
||||
SCIC : origin = 0x00007220, length = 0x00000010
|
||||
SCID : origin = 0x00007230, length = 0x00000010
|
||||
SDFM1 : origin = 0x00005E00, length = 0x00000080
|
||||
SDFM2 : origin = 0x00005E80, length = 0x00000080
|
||||
SPIA : origin = 0x00006100, length = 0x00000010
|
||||
SPIB : origin = 0x00006110, length = 0x00000010
|
||||
SPIC : origin = 0x00006120, length = 0x00000010
|
||||
UID : origin = 0x000703C0, length = 0x00000010
|
||||
WD : origin = 0x00007000, length = 0x0000002B
|
||||
XINT : origin = 0x00007070, length = 0x0000000B
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*** PIE Vect Table and Boot ROM Variables Structures ***/
|
||||
UNION run = PIEVECTTABLE
|
||||
{
|
||||
PieVectTableFile
|
||||
GROUP
|
||||
{
|
||||
EmuKeyVar
|
||||
EmuBModeVar
|
||||
EmuBootPinsVar
|
||||
FlashCallbackVar
|
||||
FlashScalingVar
|
||||
}
|
||||
}
|
||||
|
||||
AccessProtectionRegsFile : > ACCESSPROTECTION, type=NOINIT
|
||||
AdcaRegsFile : > ADCA, type=NOINIT
|
||||
AdcbRegsFile : > ADCB, type=NOINIT
|
||||
AdccRegsFile : > ADCC, type=NOINIT
|
||||
AdcdRegsFile : > ADCD, type=NOINIT
|
||||
AdcaResultRegsFile : > ADCARESULT, type=NOINIT
|
||||
AdcbResultRegsFile : > ADCBRESULT, type=NOINIT
|
||||
AdccResultRegsFile : > ADCCRESULT, type=NOINIT
|
||||
AdcdResultRegsFile : > ADCDRESULT, type=NOINIT
|
||||
CanaRegsFile : > CANA, type=NOINIT
|
||||
CanbRegsFile : > CANB, type=NOINIT
|
||||
Cla1RegsFile : > CLA1, type=NOINIT
|
||||
Clb1DataExchRegsFile : > CLB1DATAEXCH, type=NOINIT
|
||||
Clb2DataExchRegsFile : > CLB2DATAEXCH, type=NOINIT
|
||||
Clb3DataExchRegsFile : > CLB3DATAEXCH, type=NOINIT
|
||||
Clb4DataExchRegsFile : > CLB4DATAEXCH, type=NOINIT
|
||||
Clb1LogicCfgRegsFile : > CLB1LOGICCFG, type=NOINIT
|
||||
Clb2LogicCfgRegsFile : > CLB2LOGICCFG, type=NOINIT
|
||||
Clb3LogicCfgRegsFile : > CLB3LOGICCFG, type=NOINIT
|
||||
Clb4LogicCfgRegsFile : > CLB4LOGICCFG, type=NOINIT
|
||||
Clb1LogicCtrlRegsFile : > CLB1LOGICCTRL, type=NOINIT
|
||||
Clb2LogicCtrlRegsFile : > CLB2LOGICCTRL, type=NOINIT
|
||||
Clb3LogicCtrlRegsFile : > CLB3LOGICCTRL, type=NOINIT
|
||||
Clb4LogicCtrlRegsFile : > CLB4LOGICCTRL, type=NOINIT
|
||||
ClkCfgRegsFile : > CLKCFG, type=NOINIT
|
||||
Cmpss1RegsFile : > CMPSS1, type=NOINIT
|
||||
Cmpss2RegsFile : > CMPSS2, type=NOINIT
|
||||
Cmpss3RegsFile : > CMPSS3, type=NOINIT
|
||||
Cmpss4RegsFile : > CMPSS4, type=NOINIT
|
||||
Cmpss5RegsFile : > CMPSS5, type=NOINIT
|
||||
Cmpss6RegsFile : > CMPSS6, type=NOINIT
|
||||
Cmpss7RegsFile : > CMPSS7, type=NOINIT
|
||||
Cmpss8RegsFile : > CMPSS8, type=NOINIT
|
||||
CpuTimer0RegsFile : > CPUTIMER0, type=NOINIT
|
||||
CpuTimer1RegsFile : > CPUTIMER1, type=NOINIT
|
||||
CpuTimer2RegsFile : > CPUTIMER2, type=NOINIT
|
||||
CpuSysRegsFile : > CPUSYS, type=NOINIT
|
||||
DacaRegsFile : > DACA, type=NOINIT
|
||||
DacbRegsFile : > DACB, type=NOINIT
|
||||
DaccRegsFile : > DACC, type=NOINIT
|
||||
DcsmCommonRegsFile : > DCSMCOMMON, type=NOINIT
|
||||
DcsmZ1RegsFile : > DCSMZ1, type=NOINIT
|
||||
DcsmZ2RegsFile : > DCSMZ2, type=NOINIT
|
||||
DmaClaSrcSelRegsFile : > DMACLASRCSEL, type=NOINIT
|
||||
DmaRegsFile : > DMA, type=NOINIT
|
||||
ECap1RegsFile : > ECAP1, type=NOINIT
|
||||
ECap2RegsFile : > ECAP2, type=NOINIT
|
||||
ECap3RegsFile : > ECAP3, type=NOINIT
|
||||
ECap4RegsFile : > ECAP4, type=NOINIT
|
||||
ECap5RegsFile : > ECAP5, type=NOINIT
|
||||
ECap6RegsFile : > ECAP6, type=NOINIT
|
||||
Emif1ConfigRegsFile : > EMIF1CONFIG, type=NOINIT
|
||||
Emif1RegsFile : > EMIF1, type=NOINIT
|
||||
EPwm1RegsFile : > EPWM1, type=NOINIT
|
||||
EPwm2RegsFile : > EPWM2, type=NOINIT
|
||||
EPwm3RegsFile : > EPWM3, type=NOINIT
|
||||
EPwm4RegsFile : > EPWM4, type=NOINIT
|
||||
EPwm5RegsFile : > EPWM5, type=NOINIT
|
||||
EPwm6RegsFile : > EPWM6, type=NOINIT
|
||||
EPwm7RegsFile : > EPWM7, type=NOINIT
|
||||
EPwm8RegsFile : > EPWM8, type=NOINIT
|
||||
EPwm9RegsFile : > EPWM9, type=NOINIT
|
||||
EPwm10RegsFile : > EPWM10, type=NOINIT
|
||||
EPwm11RegsFile : > EPWM11, type=NOINIT
|
||||
EPwm12RegsFile : > EPWM12, type=NOINIT
|
||||
EQep1RegsFile : > EQEP1, type=NOINIT
|
||||
EQep2RegsFile : > EQEP2, type=NOINIT
|
||||
EQep3RegsFile : > EQEP3, type=NOINIT
|
||||
Flash0CtrlRegsFile : > FLASH0CTRL, type=NOINIT
|
||||
Flash0EccRegsFile : > FLASH0ECC, type=NOINIT
|
||||
FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, type=NOINIT
|
||||
GpioDataRegsFile : > GPIODATA, type=NOINIT
|
||||
I2caRegsFile : > I2CA, type=NOINIT
|
||||
I2cbRegsFile : > I2CB, type=NOINIT
|
||||
IpcRegsFile : > IPC, type=NOINIT
|
||||
MemoryErrorRegsFile : > MEMORYERROR, type=NOINIT
|
||||
MemCfgRegsFile : > MEMCFG, type=NOINIT
|
||||
McbspaRegsFile : > MCBSPA, type=NOINIT
|
||||
McbspbRegsFile : > MCBSPB, type=NOINIT
|
||||
NmiIntruptRegsFile : > NMIINTRUPT, type=NOINIT
|
||||
PieCtrlRegsFile : > PIECTRL, type=NOINIT
|
||||
RomPrefetchRegsFile : > ROMPREFETCH, type=NOINIT
|
||||
SciaRegsFile : > SCIA, type=NOINIT
|
||||
ScibRegsFile : > SCIB, type=NOINIT
|
||||
ScicRegsFile : > SCIC, type=NOINIT
|
||||
ScidRegsFile : > SCID, type=NOINIT
|
||||
Sdfm1RegsFile : > SDFM1, type=NOINIT
|
||||
Sdfm2RegsFile : > SDFM2, type=NOINIT
|
||||
SpiaRegsFile : > SPIA, type=NOINIT
|
||||
SpibRegsFile : > SPIB, type=NOINIT
|
||||
SpicRegsFile : > SPIC, type=NOINIT
|
||||
UidRegsFile : > UID, type=NOINIT
|
||||
WdRegsFile : > WD, type=NOINIT
|
||||
XintRegsFile : > XINT, type=NOINIT
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,199 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_analogsubsys.h
|
||||
//
|
||||
// TITLE: Definitions for the ANALOGSUBSYS registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_ANALOGSUBSYS_H
|
||||
#define F2837xD_ANALOGSUBSYS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// ANALOGSUBSYS Individual Register Bit Definitions:
|
||||
|
||||
struct INTOSC1TRIM_BITS { // bits description
|
||||
Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
Uint16 rsvd2:8; // 23:16 Reserved
|
||||
Uint16 rsvd3:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union INTOSC1TRIM_REG {
|
||||
Uint32 all;
|
||||
struct INTOSC1TRIM_BITS bit;
|
||||
};
|
||||
|
||||
struct INTOSC2TRIM_BITS { // bits description
|
||||
Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
Uint16 rsvd2:8; // 23:16 Reserved
|
||||
Uint16 rsvd3:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union INTOSC2TRIM_REG {
|
||||
Uint32 all;
|
||||
struct INTOSC2TRIM_BITS bit;
|
||||
};
|
||||
|
||||
struct TSNSCTL_BITS { // bits description
|
||||
Uint16 ENABLE:1; // 0 Temperature Sensor Enable
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
};
|
||||
|
||||
union TSNSCTL_REG {
|
||||
Uint16 all;
|
||||
struct TSNSCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct LOCK_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 rsvd2:1; // 1 Reserved
|
||||
Uint16 rsvd3:1; // 2 Reserved
|
||||
Uint16 TSNSCTL:1; // 3 Temperature Sensor Control Register Lock
|
||||
Uint16 rsvd4:1; // 4 Reserved
|
||||
Uint16 rsvd5:1; // 5 Reserved
|
||||
Uint16 rsvd6:1; // 6 Reserved
|
||||
Uint16 rsvd7:9; // 15:7 Reserved
|
||||
Uint16 rsvd8:3; // 18:16 Reserved
|
||||
Uint16 rsvd9:1; // 19 Reserved
|
||||
Uint16 rsvd10:1; // 20 Reserved
|
||||
Uint16 rsvd11:1; // 21 Reserved
|
||||
Uint16 rsvd12:1; // 22 Reserved
|
||||
Uint16 ANAREFTRIMA:1; // 23 Analog Reference A Trim Register Lock
|
||||
Uint16 ANAREFTRIMB:1; // 24 Analog Reference B Trim Register Lock
|
||||
Uint16 ANAREFTRIMC:1; // 25 Analog Reference C Trim Register Lock
|
||||
Uint16 ANAREFTRIMD:1; // 26 Analog Reference D Trim Register Lock
|
||||
Uint16 rsvd13:1; // 27 Reserved
|
||||
Uint16 rsvd14:1; // 28 Reserved
|
||||
Uint16 rsvd15:1; // 29 Reserved
|
||||
Uint16 rsvd16:1; // 30 Reserved
|
||||
Uint16 rsvd17:1; // 31 Reserved
|
||||
};
|
||||
|
||||
union LOCK_REG {
|
||||
Uint32 all;
|
||||
struct LOCK_BITS bit;
|
||||
};
|
||||
|
||||
struct ANAREFTRIMA_BITS { // bits description
|
||||
Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim
|
||||
Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim
|
||||
Uint16 IREFTRIM:5; // 15:11 Reference Current Trim
|
||||
Uint16 rsvd1:8; // 23:16 Reserved
|
||||
Uint16 rsvd2:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union ANAREFTRIMA_REG {
|
||||
Uint32 all;
|
||||
struct ANAREFTRIMA_BITS bit;
|
||||
};
|
||||
|
||||
struct ANAREFTRIMB_BITS { // bits description
|
||||
Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim
|
||||
Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim
|
||||
Uint16 IREFTRIM:5; // 15:11 Reference Current Trim
|
||||
Uint16 rsvd1:8; // 23:16 Reserved
|
||||
Uint16 rsvd2:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union ANAREFTRIMB_REG {
|
||||
Uint32 all;
|
||||
struct ANAREFTRIMB_BITS bit;
|
||||
};
|
||||
|
||||
struct ANAREFTRIMC_BITS { // bits description
|
||||
Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim
|
||||
Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim
|
||||
Uint16 IREFTRIM:5; // 15:11 Reference Current Trim
|
||||
Uint16 rsvd1:8; // 23:16 Reserved
|
||||
Uint16 rsvd2:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union ANAREFTRIMC_REG {
|
||||
Uint32 all;
|
||||
struct ANAREFTRIMC_BITS bit;
|
||||
};
|
||||
|
||||
struct ANAREFTRIMD_BITS { // bits description
|
||||
Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim
|
||||
Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim
|
||||
Uint16 IREFTRIM:5; // 15:11 Reference Current Trim
|
||||
Uint16 rsvd1:8; // 23:16 Reserved
|
||||
Uint16 rsvd2:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union ANAREFTRIMD_REG {
|
||||
Uint32 all;
|
||||
struct ANAREFTRIMD_BITS bit;
|
||||
};
|
||||
|
||||
struct ANALOG_SUBSYS_REGS {
|
||||
Uint16 rsvd1[32]; // Reserved
|
||||
union INTOSC1TRIM_REG INTOSC1TRIM; // Internal Oscillator 1 Trim Register
|
||||
union INTOSC2TRIM_REG INTOSC2TRIM; // Internal Oscillator 2 Trim Register
|
||||
Uint16 rsvd2[2]; // Reserved
|
||||
union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register
|
||||
Uint16 rsvd3[7]; // Reserved
|
||||
union LOCK_REG LOCK; // Lock Register
|
||||
Uint16 rsvd4[6]; // Reserved
|
||||
union ANAREFTRIMA_REG ANAREFTRIMA; // Analog Reference Trim A Register
|
||||
union ANAREFTRIMB_REG ANAREFTRIMB; // Analog Reference Trim B Register
|
||||
union ANAREFTRIMC_REG ANAREFTRIMC; // Analog Reference Trim C Register
|
||||
union ANAREFTRIMD_REG ANAREFTRIMD; // Analog Reference Trim D Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// ANALOGSUBSYS External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,612 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_can.h
|
||||
//
|
||||
// TITLE: Definitions for the CAN registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_CAN_H
|
||||
#define F2837xD_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CAN Individual Register Bit Definitions:
|
||||
|
||||
struct CAN_CTL_BITS { // bits description
|
||||
bp_16 Init:1; // 0 Initialization
|
||||
bp_16 IE0:1; // 1 Interrupt line 0 Enable
|
||||
bp_16 SIE:1; // 2 Status Change Interrupt Enable
|
||||
bp_16 EIE:1; // 3 Error Interrupt Enable
|
||||
bp_16 rsvd1:1; // 4 Reserved
|
||||
bp_16 DAR:1; // 5 Disable Automatic Retransmission
|
||||
bp_16 CCE:1; // 6 Configuration Change Enable
|
||||
bp_16 Test:1; // 7 Test Mode Enable
|
||||
bp_16 IDS:1; // 8 Interruption Debug Support Enable
|
||||
bp_16 ABO:1; // 9 Auto-Bus-On Enable
|
||||
bp_16 PMD:4; // 13:10 Parity on/off
|
||||
bp_16 rsvd2:1; // 14 Reserved
|
||||
bp_16 SWR:1; // 15 SW Reset Enable
|
||||
bp_32 INITDBG:1; // 16 Debug Mode Status
|
||||
bp_32 IE1:1; // 17 Interrupt line 1 Enable Disabled
|
||||
bp_32 rsvd3:1; // 18 Reserved
|
||||
bp_32 rsvd4:1; // 19 Reserved
|
||||
bp_32 rsvd5:1; // 20 Reserved
|
||||
bp_32 rsvd6:3; // 23:21 Reserved
|
||||
bp_32 rsvd7:1; // 24 Reserved
|
||||
bp_32 rsvd8:1; // 25 Reserved
|
||||
bp_32 rsvd9:6; // 31:26 Reserved
|
||||
};
|
||||
|
||||
union CAN_CTL_REG {
|
||||
bp_32 all;
|
||||
struct CAN_CTL_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_ES_BITS { // bits description
|
||||
bp_16 LEC:3; // 2:0 Last Error Code
|
||||
bp_16 TxOk:1; // 3 Transmission status
|
||||
bp_16 RxOk:1; // 4 Reception status
|
||||
bp_16 EPass:1; // 5 Error Passive State
|
||||
bp_16 EWarn:1; // 6 Warning State
|
||||
bp_16 BOff:1; // 7 Bus-Off State
|
||||
bp_16 PER:1; // 8 Parity Error Detected
|
||||
bp_16 rsvd1:1; // 9 Reserved
|
||||
bp_16 rsvd2:1; // 10 Reserved
|
||||
bp_16 rsvd3:5; // 15:11 Reserved
|
||||
bp_32 rsvd4:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_ES_REG {
|
||||
bp_32 all;
|
||||
struct CAN_ES_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_ERRC_BITS { // bits description
|
||||
bp_16 TEC:8; // 7:0 Transmit Error Counter
|
||||
bp_16 REC:7; // 14:8 Receive Error Counter
|
||||
bp_16 RP:1; // 15 Receive Error Passive
|
||||
bp_32 rsvd1:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_ERRC_REG {
|
||||
bp_32 all;
|
||||
struct CAN_ERRC_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_BTR_BITS { // bits description
|
||||
bp_16 BRP:6; // 5:0 Baud Rate Prescaler
|
||||
bp_16 SJW:2; // 7:6 Synchronization Jump Width
|
||||
bp_16 TSEG1:4; // 11:8 Time segment
|
||||
bp_16 TSEG2:3; // 14:12 Time segment
|
||||
bp_16 rsvd1:1; // 15 Reserved
|
||||
bp_32 BRPE:4; // 19:16 Baud Rate Prescaler Extension
|
||||
bp_32 rsvd2:12; // 31:20 Reserved
|
||||
};
|
||||
|
||||
union CAN_BTR_REG {
|
||||
bp_32 all;
|
||||
struct CAN_BTR_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_INT_BITS { // bits description
|
||||
bp_16 INT0ID:16; // 15:0 Interrupt Identifier
|
||||
bp_32 INT1ID:8; // 23:16 Interrupt 1 Identifier
|
||||
bp_32 rsvd1:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union CAN_INT_REG {
|
||||
bp_32 all;
|
||||
struct CAN_INT_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_TEST_BITS { // bits description
|
||||
bp_16 rsvd1:3; // 2:0 Reserved
|
||||
bp_16 SILENT:1; // 3 Silent Mode
|
||||
bp_16 LBACK:1; // 4 Loopback Mode
|
||||
bp_16 TX:2; // 6:5 CANTX Pin Control
|
||||
bp_16 RX:1; // 7 CANRX Pin Status
|
||||
bp_16 EXL:1; // 8 External Loopback Mode
|
||||
bp_16 RDA:1; // 9 RAM Direct Access Enable:
|
||||
bp_16 rsvd2:6; // 15:10 Reserved
|
||||
bp_32 rsvd3:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_TEST_REG {
|
||||
bp_32 all;
|
||||
struct CAN_TEST_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_PERR_BITS { // bits description
|
||||
bp_16 MSG_NUM:8; // 7:0 Message Number
|
||||
bp_16 WORD_NUM:3; // 10:8 Word Number
|
||||
bp_16 rsvd1:5; // 15:11 Reserved
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_PERR_REG {
|
||||
bp_32 all;
|
||||
struct CAN_PERR_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_RAM_INIT_BITS { // bits description
|
||||
bp_16 KEY0:1; // 0 KEY0
|
||||
bp_16 KEY1:1; // 1 KEY1
|
||||
bp_16 KEY2:1; // 2 KEY2
|
||||
bp_16 KEY3:1; // 3 KEY3
|
||||
bp_16 CAN_RAM_INIT:1; // 4 Initialize CAN Mailbox RAM
|
||||
bp_16 RAM_INIT_DONE:1; // 5 CAN RAM initialization complete
|
||||
bp_16 rsvd1:10; // 15:6 Reserved
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_RAM_INIT_REG {
|
||||
bp_32 all;
|
||||
struct CAN_RAM_INIT_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_GLB_INT_EN_BITS { // bits description
|
||||
bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for CANINT0
|
||||
bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for CANINT1
|
||||
bp_16 rsvd1:14; // 15:2 Reserved
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_GLB_INT_EN_REG {
|
||||
bp_32 all;
|
||||
struct CAN_GLB_INT_EN_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_GLB_INT_FLG_BITS { // bits description
|
||||
bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for CANINT0
|
||||
bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for CANINT1
|
||||
bp_16 rsvd1:14; // 15:2 Reserved
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_GLB_INT_FLG_REG {
|
||||
bp_32 all;
|
||||
struct CAN_GLB_INT_FLG_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_GLB_INT_CLR_BITS { // bits description
|
||||
bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for CANINT0
|
||||
bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for CANINT1
|
||||
bp_16 rsvd1:14; // 15:2 Reserved
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_GLB_INT_CLR_REG {
|
||||
bp_32 all;
|
||||
struct CAN_GLB_INT_CLR_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_TXRQ_X_BITS { // bits description
|
||||
bp_16 TxRqstReg1:2; // 1:0 Transmit Request Register 1
|
||||
bp_16 TxRqstReg2:2; // 3:2 Transmit Request Register 2
|
||||
bp_16 rsvd1:12; // 15:4 Reserved
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_TXRQ_X_REG {
|
||||
bp_32 all;
|
||||
struct CAN_TXRQ_X_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_NDAT_X_BITS { // bits description
|
||||
bp_16 NewDatReg1:2; // 1:0 New Data Register 1
|
||||
bp_16 NewDatReg2:2; // 3:2 New Data Register 2
|
||||
bp_16 rsvd1:12; // 15:4 Reserved
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_NDAT_X_REG {
|
||||
bp_32 all;
|
||||
struct CAN_NDAT_X_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IPEN_X_BITS { // bits description
|
||||
bp_16 IntPndReg1:2; // 1:0 Interrupt Pending Register 1
|
||||
bp_16 IntPndReg2:2; // 3:2 Interrupt Pending Register 2
|
||||
bp_16 rsvd1:12; // 15:4 Reserved
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_IPEN_X_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IPEN_X_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_MVAL_X_BITS { // bits description
|
||||
bp_16 MsgValReg1:2; // 1:0 Message Valid Register 1
|
||||
bp_16 MsgValReg2:2; // 3:2 Message Valid Register 2
|
||||
bp_16 rsvd1:12; // 15:4 Reserved
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_MVAL_X_REG {
|
||||
bp_32 all;
|
||||
struct CAN_MVAL_X_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF1CMD_BITS { // bits description
|
||||
bp_16 MSG_NUM:8; // 7:0 Message Number
|
||||
bp_16 rsvd1:6; // 13:8 Reserved
|
||||
bp_16 rsvd2:1; // 14 Reserved
|
||||
bp_16 Busy:1; // 15 Busy Flag
|
||||
bp_32 DATA_B:1; // 16 Access Data Bytes 4-7
|
||||
bp_32 DATA_A:1; // 17 Access Data Bytes 0-3
|
||||
bp_32 TXRQST:1; // 18 Access Transmission Request Bit
|
||||
bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit
|
||||
bp_32 Control:1; // 20 Access Control Bits
|
||||
bp_32 Arb:1; // 21 Access Arbitration Bits
|
||||
bp_32 Mask:1; // 22 Access Mask Bits
|
||||
bp_32 DIR:1; // 23 Write/Read Direction
|
||||
bp_32 rsvd3:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union CAN_IF1CMD_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF1CMD_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF1MSK_BITS { // bits description
|
||||
bp_32 Msk:29; // 28:0 Identifier Mask
|
||||
bp_32 rsvd1:1; // 29 Reserved
|
||||
bp_32 MDir:1; // 30 Mask Message Direction
|
||||
bp_32 MXtd:1; // 31 Mask Extended Identifier
|
||||
};
|
||||
|
||||
union CAN_IF1MSK_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF1MSK_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF1ARB_BITS { // bits description
|
||||
bp_32 ID:29; // 28:0 `
|
||||
bp_32 Dir:1; // 29 Message Direction
|
||||
bp_32 Xtd:1; // 30 Extended Identifier
|
||||
bp_32 MsgVal:1; // 31 Message Valid
|
||||
};
|
||||
|
||||
union CAN_IF1ARB_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF1ARB_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF1MCTL_BITS { // bits description
|
||||
bp_16 DLC:4; // 3:0 Data length code
|
||||
bp_16 rsvd1:3; // 6:4 Reserved
|
||||
bp_16 EoB:1; // 7 End of Block
|
||||
bp_16 TxRqst:1; // 8 Transmit Request
|
||||
bp_16 RmtEn:1; // 9 Remote Enable
|
||||
bp_16 RxIE:1; // 10 Receive Interrupt Enable
|
||||
bp_16 TxIE:1; // 11 Transmit Interrupt Enable
|
||||
bp_16 UMask:1; // 12 Use Acceptance Mask
|
||||
bp_16 IntPnd:1; // 13 Interrupt Pending
|
||||
bp_16 MsgLst:1; // 14 Message Lost
|
||||
bp_16 NewDat:1; // 15 New Data
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_IF1MCTL_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF1MCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF1DATA_BITS { // bits description
|
||||
bp_16 Data_0:8; // 7:0 Data Byte 0
|
||||
bp_16 Data_1:8; // 15:8 Data Byte 1
|
||||
bp_32 Data_2:8; // 23:16 Data Byte 2
|
||||
bp_32 Data_3:8; // 31:24 Data Byte 3
|
||||
};
|
||||
|
||||
union CAN_IF1DATA_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF1DATA_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF1DATB_BITS { // bits description
|
||||
bp_16 Data_4:8; // 7:0 Data Byte 4
|
||||
bp_16 Data_5:8; // 15:8 Data Byte 5
|
||||
bp_32 Data_6:8; // 23:16 Data Byte 6
|
||||
bp_32 Data_7:8; // 31:24 Data Byte 7
|
||||
};
|
||||
|
||||
union CAN_IF1DATB_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF1DATB_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF2CMD_BITS { // bits description
|
||||
bp_16 MSG_NUM:8; // 7:0 Message Number
|
||||
bp_16 rsvd1:6; // 13:8 Reserved
|
||||
bp_16 rsvd2:1; // 14 Reserved
|
||||
bp_16 Busy:1; // 15 Busy Flag
|
||||
bp_32 DATA_B:1; // 16 Access Data Bytes 4-7
|
||||
bp_32 DATA_A:1; // 17 Access Data Bytes 0-3
|
||||
bp_32 TxRqst:1; // 18 Access Transmission Request Bit
|
||||
bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit
|
||||
bp_32 Control:1; // 20 Access Control Bits
|
||||
bp_32 Arb:1; // 21 Access Arbitration Bits
|
||||
bp_32 Mask:1; // 22 Access Mask Bits
|
||||
bp_32 DIR:1; // 23 Write/Read Direction
|
||||
bp_32 rsvd3:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union CAN_IF2CMD_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF2CMD_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF2MSK_BITS { // bits description
|
||||
bp_32 Msk:29; // 28:0 Identifier Mask
|
||||
bp_32 rsvd1:1; // 29 Reserved
|
||||
bp_32 MDir:1; // 30 Mask Message Direction
|
||||
bp_32 MXtd:1; // 31 Mask Extended Identifier
|
||||
};
|
||||
|
||||
union CAN_IF2MSK_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF2MSK_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF2ARB_BITS { // bits description
|
||||
bp_32 ID:29; // 28:0 Message Identifier
|
||||
bp_32 Dir:1; // 29 Message Direction
|
||||
bp_32 Xtd:1; // 30 Extended Identifier
|
||||
bp_32 MsgVal:1; // 31 Message Valid
|
||||
};
|
||||
|
||||
union CAN_IF2ARB_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF2ARB_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF2MCTL_BITS { // bits description
|
||||
bp_16 DLC:4; // 3:0 Data length code
|
||||
bp_16 rsvd1:3; // 6:4 Reserved
|
||||
bp_16 EoB:1; // 7 End of Block
|
||||
bp_16 TxRqst:1; // 8 Transmit Request
|
||||
bp_16 RmtEn:1; // 9 Remote Enable
|
||||
bp_16 RxIE:1; // 10 Receive Interrupt Enable
|
||||
bp_16 TxIE:1; // 11 Transmit Interrupt Enable
|
||||
bp_16 UMask:1; // 12 Use Acceptance Mask
|
||||
bp_16 IntPnd:1; // 13 Interrupt Pending
|
||||
bp_16 MsgLst:1; // 14 Message Lost
|
||||
bp_16 NewDat:1; // 15 New Data
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_IF2MCTL_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF2MCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF2DATA_BITS { // bits description
|
||||
bp_16 Data_0:8; // 7:0 Data Byte 0
|
||||
bp_16 Data_1:8; // 15:8 Data Byte 1
|
||||
bp_32 Data_2:8; // 23:16 Data Byte 2
|
||||
bp_32 Data_3:8; // 31:24 Data Byte 3
|
||||
};
|
||||
|
||||
union CAN_IF2DATA_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF2DATA_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF2DATB_BITS { // bits description
|
||||
bp_16 Data_4:8; // 7:0 Data Byte 4
|
||||
bp_16 Data_5:8; // 15:8 Data Byte 5
|
||||
bp_32 Data_6:8; // 23:16 Data Byte 6
|
||||
bp_32 Data_7:8; // 31:24 Data Byte 7
|
||||
};
|
||||
|
||||
union CAN_IF2DATB_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF2DATB_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF3OBS_BITS { // bits description
|
||||
bp_16 Mask:1; // 0 Mask data read observation
|
||||
bp_16 Arb:1; // 1 Arbitration data read observation
|
||||
bp_16 Ctrl:1; // 2 Ctrl read observation
|
||||
bp_16 Data_A:1; // 3 Data A read observation
|
||||
bp_16 Data_B:1; // 4 Data B read observation
|
||||
bp_16 rsvd1:3; // 7:5 Reserved
|
||||
bp_16 IF3SM:1; // 8 IF3 Status of Mask data read access
|
||||
bp_16 IF3SA:1; // 9 IF3 Status of Arbitration data read access
|
||||
bp_16 IF3SC:1; // 10 IF3 Status of Control bits read access
|
||||
bp_16 IF3SDA:1; // 11 IF3 Status of Data A read access
|
||||
bp_16 IF3SDB:1; // 12 IF3 Status of Data B read access
|
||||
bp_16 rsvd2:2; // 14:13 Reserved
|
||||
bp_16 IF3Upd:1; // 15 IF3 Update Data
|
||||
bp_32 rsvd3:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_IF3OBS_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF3OBS_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF3MSK_BITS { // bits description
|
||||
bp_32 Msk:29; // 28:0 Mask
|
||||
bp_32 rsvd1:1; // 29 Reserved
|
||||
bp_32 MDir:1; // 30 Mask Message Direction
|
||||
bp_32 MXtd:1; // 31 Mask Extended Identifier
|
||||
};
|
||||
|
||||
union CAN_IF3MSK_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF3MSK_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF3ARB_BITS { // bits description
|
||||
bp_32 ID:29; // 28:0 Message Identifier
|
||||
bp_32 Dir:1; // 29 Message Direction
|
||||
bp_32 Xtd:1; // 30 Extended Identifier
|
||||
bp_32 MsgVal:1; // 31 Message Valid
|
||||
};
|
||||
|
||||
union CAN_IF3ARB_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF3ARB_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF3MCTL_BITS { // bits description
|
||||
bp_16 DLC:4; // 3:0 Data length code
|
||||
bp_16 rsvd1:3; // 6:4 Reserved
|
||||
bp_16 EoB:1; // 7 End of Block
|
||||
bp_16 TxRqst:1; // 8 Transmit Request
|
||||
bp_16 RmtEn:1; // 9 Remote Enable
|
||||
bp_16 RxIE:1; // 10 Receive Interrupt Enable
|
||||
bp_16 TxIE:1; // 11 Transmit Interrupt Enable
|
||||
bp_16 UMask:1; // 12 Use Acceptance Mask
|
||||
bp_16 IntPnd:1; // 13 Interrupt Pending
|
||||
bp_16 MsgLst:1; // 14 Message Lost
|
||||
bp_16 NewDat:1; // 15 New Data
|
||||
bp_32 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CAN_IF3MCTL_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF3MCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF3DATA_BITS { // bits description
|
||||
bp_16 Data_0:8; // 7:0 Data Byte 0
|
||||
bp_16 Data_1:8; // 15:8 Data Byte 1
|
||||
bp_32 Data_2:8; // 23:16 Data Byte 2
|
||||
bp_32 Data_3:8; // 31:24 Data Byte 3
|
||||
};
|
||||
|
||||
union CAN_IF3DATA_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF3DATA_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_IF3DATB_BITS { // bits description
|
||||
bp_16 Data_4:8; // 7:0 Data Byte 4
|
||||
bp_16 Data_5:8; // 15:8 Data Byte 5
|
||||
bp_32 Data_6:8; // 23:16 Data Byte 6
|
||||
bp_32 Data_7:8; // 31:24 Data Byte 7
|
||||
};
|
||||
|
||||
union CAN_IF3DATB_REG {
|
||||
bp_32 all;
|
||||
struct CAN_IF3DATB_BITS bit;
|
||||
};
|
||||
|
||||
struct CAN_REGS {
|
||||
union CAN_CTL_REG CAN_CTL; // CAN Control Register
|
||||
union CAN_ES_REG CAN_ES; // Error and Status Register
|
||||
union CAN_ERRC_REG CAN_ERRC; // Error Counter Register
|
||||
union CAN_BTR_REG CAN_BTR; // Bit Timing Register
|
||||
union CAN_INT_REG CAN_INT; // Interrupt Register
|
||||
union CAN_TEST_REG CAN_TEST; // Test Register
|
||||
uint32_t rsvd1[2]; // Reserved
|
||||
union CAN_PERR_REG CAN_PERR; // CAN Parity Error Code Register
|
||||
uint32_t rsvd2[16]; // Reserved
|
||||
union CAN_RAM_INIT_REG CAN_RAM_INIT; // CAN RAM Initialization Register
|
||||
uint32_t rsvd3[6]; // Reserved
|
||||
union CAN_GLB_INT_EN_REG CAN_GLB_INT_EN; // CAN Global Interrupt Enable Register
|
||||
union CAN_GLB_INT_FLG_REG CAN_GLB_INT_FLG; // CAN Global Interrupt Flag Register
|
||||
union CAN_GLB_INT_CLR_REG CAN_GLB_INT_CLR; // CAN Global Interrupt Clear Register
|
||||
uint32_t rsvd4[18]; // Reserved
|
||||
bp_32 CAN_ABOTR; // Auto-Bus-On Time Register
|
||||
union CAN_TXRQ_X_REG CAN_TXRQ_X; // CAN Transmission Request Register
|
||||
bp_32 CAN_TXRQ_21; // CAN Transmission Request 2_1 Register
|
||||
uint32_t rsvd5[6]; // Reserved
|
||||
union CAN_NDAT_X_REG CAN_NDAT_X; // CAN New Data Register
|
||||
bp_32 CAN_NDAT_21; // CAN New Data 2_1 Register
|
||||
uint32_t rsvd6[6]; // Reserved
|
||||
union CAN_IPEN_X_REG CAN_IPEN_X; // CAN Interrupt Pending Register
|
||||
bp_32 CAN_IPEN_21; // CAN Interrupt Pending 2_1 Register
|
||||
uint32_t rsvd7[6]; // Reserved
|
||||
union CAN_MVAL_X_REG CAN_MVAL_X; // CAN Message Valid Register
|
||||
bp_32 CAN_MVAL_21; // CAN Message Valid 2_1 Register
|
||||
uint32_t rsvd8[8]; // Reserved
|
||||
bp_32 CAN_IP_MUX21; // CAN Interrupt Multiplexer 2_1 Register
|
||||
uint32_t rsvd9[18]; // Reserved
|
||||
union CAN_IF1CMD_REG CAN_IF1CMD; // IF1 Command Register
|
||||
union CAN_IF1MSK_REG CAN_IF1MSK; // IF1 Mask Register
|
||||
union CAN_IF1ARB_REG CAN_IF1ARB; // IF1 Arbitration Register
|
||||
union CAN_IF1MCTL_REG CAN_IF1MCTL; // IF1 Message Control Register
|
||||
union CAN_IF1DATA_REG CAN_IF1DATA; // IF1 Data A Register
|
||||
union CAN_IF1DATB_REG CAN_IF1DATB; // IF1 Data B Register
|
||||
uint32_t rsvd10[4]; // Reserved
|
||||
union CAN_IF2CMD_REG CAN_IF2CMD; // IF2 Command Register
|
||||
union CAN_IF2MSK_REG CAN_IF2MSK; // IF2 Mask Register
|
||||
union CAN_IF2ARB_REG CAN_IF2ARB; // IF2 Arbitration Register
|
||||
union CAN_IF2MCTL_REG CAN_IF2MCTL; // IF2 Message Control Register
|
||||
union CAN_IF2DATA_REG CAN_IF2DATA; // IF2 Data A Register
|
||||
union CAN_IF2DATB_REG CAN_IF2DATB; // IF2 Data B Register
|
||||
uint32_t rsvd11[4]; // Reserved
|
||||
union CAN_IF3OBS_REG CAN_IF3OBS; // IF3 Observation Register
|
||||
union CAN_IF3MSK_REG CAN_IF3MSK; // IF3 Mask Register
|
||||
union CAN_IF3ARB_REG CAN_IF3ARB; // IF3 Arbitration Register
|
||||
union CAN_IF3MCTL_REG CAN_IF3MCTL; // IF3 Message Control Register
|
||||
union CAN_IF3DATA_REG CAN_IF3DATA; // IF3 Data A Register
|
||||
union CAN_IF3DATB_REG CAN_IF3DATB; // IF3 Data B Register
|
||||
uint32_t rsvd12[4]; // Reserved
|
||||
bp_32 CAN_IF3UPD; // IF3 Update Enable Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CAN External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct CAN_REGS CanaRegs;
|
||||
extern volatile struct CAN_REGS CanbRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct CAN_REGS CanaRegs;
|
||||
extern volatile struct CAN_REGS CanbRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,302 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_cla.h
|
||||
//
|
||||
// TITLE: Definitions for the CLA registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_CLA_H
|
||||
#define F2837xD_CLA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CLA Individual Register Bit Definitions:
|
||||
|
||||
struct MCTL_BITS { // bits description
|
||||
Uint16 HARDRESET:1; // 0 Hard Reset
|
||||
Uint16 SOFTRESET:1; // 1 Soft Reset
|
||||
Uint16 IACKE:1; // 2 IACK enable
|
||||
Uint16 rsvd1:13; // 15:3 Reserved
|
||||
};
|
||||
|
||||
union MCTL_REG {
|
||||
Uint16 all;
|
||||
struct MCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct MIFR_BITS { // bits description
|
||||
Uint16 INT1:1; // 0 Task 1 Interrupt Flag
|
||||
Uint16 INT2:1; // 1 Task 2 Interrupt Flag
|
||||
Uint16 INT3:1; // 2 Task 3 Interrupt Flag
|
||||
Uint16 INT4:1; // 3 Task 4 Interrupt Flag
|
||||
Uint16 INT5:1; // 4 Task 5 Interrupt Flag
|
||||
Uint16 INT6:1; // 5 Task 6 Interrupt Flag
|
||||
Uint16 INT7:1; // 6 Task 7 Interrupt Flag
|
||||
Uint16 INT8:1; // 7 Task 8 Interrupt Flag
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union MIFR_REG {
|
||||
Uint16 all;
|
||||
struct MIFR_BITS bit;
|
||||
};
|
||||
|
||||
struct MIOVF_BITS { // bits description
|
||||
Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag
|
||||
Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag
|
||||
Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag
|
||||
Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag
|
||||
Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag
|
||||
Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag
|
||||
Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag
|
||||
Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union MIOVF_REG {
|
||||
Uint16 all;
|
||||
struct MIOVF_BITS bit;
|
||||
};
|
||||
|
||||
struct MIFRC_BITS { // bits description
|
||||
Uint16 INT1:1; // 0 Task 1 Interrupt Force
|
||||
Uint16 INT2:1; // 1 Task 2 Interrupt Force
|
||||
Uint16 INT3:1; // 2 Task 3 Interrupt Force
|
||||
Uint16 INT4:1; // 3 Task 4 Interrupt Force
|
||||
Uint16 INT5:1; // 4 Task 5 Interrupt Force
|
||||
Uint16 INT6:1; // 5 Task 6 Interrupt Force
|
||||
Uint16 INT7:1; // 6 Task 7 Interrupt Force
|
||||
Uint16 INT8:1; // 7 Task 8 Interrupt Force
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union MIFRC_REG {
|
||||
Uint16 all;
|
||||
struct MIFRC_BITS bit;
|
||||
};
|
||||
|
||||
struct MICLR_BITS { // bits description
|
||||
Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear
|
||||
Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear
|
||||
Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear
|
||||
Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear
|
||||
Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear
|
||||
Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear
|
||||
Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear
|
||||
Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union MICLR_REG {
|
||||
Uint16 all;
|
||||
struct MICLR_BITS bit;
|
||||
};
|
||||
|
||||
struct MICLROVF_BITS { // bits description
|
||||
Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear
|
||||
Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear
|
||||
Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear
|
||||
Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear
|
||||
Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear
|
||||
Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear
|
||||
Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear
|
||||
Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union MICLROVF_REG {
|
||||
Uint16 all;
|
||||
struct MICLROVF_BITS bit;
|
||||
};
|
||||
|
||||
struct MIER_BITS { // bits description
|
||||
Uint16 INT1:1; // 0 Task 1 Interrupt Enable
|
||||
Uint16 INT2:1; // 1 Task 2 Interrupt Enable
|
||||
Uint16 INT3:1; // 2 Task 3 Interrupt Enable
|
||||
Uint16 INT4:1; // 3 Task 4 Interrupt Enable
|
||||
Uint16 INT5:1; // 4 Task 5 Interrupt Enable
|
||||
Uint16 INT6:1; // 5 Task 6 Interrupt Enable
|
||||
Uint16 INT7:1; // 6 Task 7 Interrupt Enable
|
||||
Uint16 INT8:1; // 7 Task 8 Interrupt Enable
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union MIER_REG {
|
||||
Uint16 all;
|
||||
struct MIER_BITS bit;
|
||||
};
|
||||
|
||||
struct MIRUN_BITS { // bits description
|
||||
Uint16 INT1:1; // 0 Task 1 Run Status
|
||||
Uint16 INT2:1; // 1 Task 2 Run Status
|
||||
Uint16 INT3:1; // 2 Task 3 Run Status
|
||||
Uint16 INT4:1; // 3 Task 4 Run Status
|
||||
Uint16 INT5:1; // 4 Task 5 Run Status
|
||||
Uint16 INT6:1; // 5 Task 6 Run Status
|
||||
Uint16 INT7:1; // 6 Task 7 Run Status
|
||||
Uint16 INT8:1; // 7 Task 8 Run Status
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union MIRUN_REG {
|
||||
Uint16 all;
|
||||
struct MIRUN_BITS bit;
|
||||
};
|
||||
|
||||
struct _MSTF_BITS { // bits description
|
||||
Uint16 LVF:1; // 0 Latched Overflow Flag
|
||||
Uint16 LUF:1; // 1 Latched Underflow Flag
|
||||
Uint16 NF:1; // 2 Negative Float Flag
|
||||
Uint16 ZF:1; // 3 Zero Float Flag
|
||||
Uint16 rsvd1:2; // 5:4 Reserved
|
||||
Uint16 TF:1; // 6 Test Flag
|
||||
Uint16 rsvd2:2; // 8:7 Reserved
|
||||
Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode
|
||||
Uint16 rsvd3:1; // 10 Reserved
|
||||
Uint16 MEALLOW:1; // 11 MEALLOW Status
|
||||
Uint32 _RPC:16; // 27:12 Return PC
|
||||
Uint16 rsvd4:4; // 31:28 Reserved
|
||||
};
|
||||
|
||||
union _MSTF_REG {
|
||||
Uint32 all;
|
||||
struct _MSTF_BITS bit;
|
||||
};
|
||||
|
||||
union MR_REG {
|
||||
Uint32 i32;
|
||||
float f32;
|
||||
};
|
||||
|
||||
struct CLA_REGS {
|
||||
Uint16 MVECT1; // Task Interrupt Vector
|
||||
Uint16 MVECT2; // Task Interrupt Vector
|
||||
Uint16 MVECT3; // Task Interrupt Vector
|
||||
Uint16 MVECT4; // Task Interrupt Vector
|
||||
Uint16 MVECT5; // Task Interrupt Vector
|
||||
Uint16 MVECT6; // Task Interrupt Vector
|
||||
Uint16 MVECT7; // Task Interrupt Vector
|
||||
Uint16 MVECT8; // Task Interrupt Vector
|
||||
Uint16 rsvd1[8]; // Reserved
|
||||
union MCTL_REG MCTL; // Control Register
|
||||
Uint16 rsvd2[15]; // Reserved
|
||||
union MIFR_REG MIFR; // Interrupt Flag Register
|
||||
union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register
|
||||
union MIFRC_REG MIFRC; // Interrupt Force Register
|
||||
union MICLR_REG MICLR; // Interrupt Flag Clear Register
|
||||
union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register
|
||||
union MIER_REG MIER; // Interrupt Enable Register
|
||||
union MIRUN_REG MIRUN; // Interrupt Run Status Register
|
||||
Uint16 rsvd3; // Reserved
|
||||
Uint16 _MPC; // CLA Program Counter
|
||||
Uint16 rsvd4; // Reserved
|
||||
Uint16 _MAR0; // CLA Auxiliary Register 0
|
||||
Uint16 _MAR1; // CLA Auxiliary Register 1
|
||||
Uint16 rsvd5[2]; // Reserved
|
||||
union _MSTF_REG _MSTF; // CLA Floating-Point Status Register
|
||||
union MR_REG _MR0; // CLA Floating-Point Result Register 0
|
||||
Uint16 rsvd6[2]; // Reserved
|
||||
union MR_REG _MR1; // CLA Floating-Point Result Register 1
|
||||
Uint16 rsvd7[2]; // Reserved
|
||||
union MR_REG _MR2; // CLA Floating-Point Result Register 2
|
||||
Uint16 rsvd8[2]; // Reserved
|
||||
union MR_REG _MR3; // CLA Floating-Point Result Register 3
|
||||
};
|
||||
|
||||
struct SOFTINTEN_BITS { // bits description
|
||||
Uint16 TASK1:1; // 0 Configure Software Interrupt or End of Task interrupt.
|
||||
Uint16 TASK2:1; // 1 Configure Software Interrupt or End of Task interrupt.
|
||||
Uint16 TASK3:1; // 2 Configure Software Interrupt or End of Task interrupt.
|
||||
Uint16 TASK4:1; // 3 Configure Software Interrupt or End of Task interrupt.
|
||||
Uint16 TASK5:1; // 4 Configure Software Interrupt or End of Task interrupt.
|
||||
Uint16 TASK6:1; // 5 Configure Software Interrupt or End of Task interrupt.
|
||||
Uint16 TASK7:1; // 6 Configure Software Interrupt or End of Task interrupt.
|
||||
Uint16 TASK8:1; // 7 Configure Software Interrupt or End of Task interrupt.
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SOFTINTEN_REG {
|
||||
Uint16 all;
|
||||
struct SOFTINTEN_BITS bit;
|
||||
};
|
||||
|
||||
struct SOFTINTFRC_BITS { // bits description
|
||||
Uint16 TASK1:1; // 0 Force CLA software interrupt for the corresponding task.
|
||||
Uint16 TASK2:1; // 1 Force CLA software interrupt for the corresponding task.
|
||||
Uint16 TASK3:1; // 2 Force CLA software interrupt for the corresponding task.
|
||||
Uint16 TASK4:1; // 3 Force CLA software interrupt for the corresponding task.
|
||||
Uint16 TASK5:1; // 4 Force CLA software interrupt for the corresponding task.
|
||||
Uint16 TASK6:1; // 5 Force CLA software interrupt for the corresponding task.
|
||||
Uint16 TASK7:1; // 6 Force CLA software interrupt for the corresponding task.
|
||||
Uint16 TASK8:1; // 7 Force CLA software interrupt for the corresponding task.
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SOFTINTFRC_REG {
|
||||
Uint16 all;
|
||||
struct SOFTINTFRC_BITS bit;
|
||||
};
|
||||
|
||||
struct CLA_SOFTINT_REGS {
|
||||
union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register
|
||||
Uint16 rsvd1; // Reserved
|
||||
union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CLA External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct CLA_REGS Cla1Regs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct CLA_REGS Cla1Regs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,734 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_clb.h
|
||||
//
|
||||
// TITLE: Definitions for the CLB registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_CLB_H
|
||||
#define F2837xD_CLB_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CLB Individual Register Bit Definitions:
|
||||
|
||||
struct CLB_COUNT_RESET_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 Count Reset Select 0
|
||||
Uint16 SEL_1:5; // 9:5 Count Reset Select 1
|
||||
Uint16 SEL_2:5; // 14:10 Count Reset Select 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_COUNT_RESET_REG {
|
||||
Uint32 all;
|
||||
struct CLB_COUNT_RESET_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_COUNT_MODE_1_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 Counter mode 1 select 0
|
||||
Uint16 SEL_1:5; // 9:5 Counter mode 1 select 1
|
||||
Uint16 SEL_2:5; // 14:10 Counter mode 1 select 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_COUNT_MODE_1_REG {
|
||||
Uint32 all;
|
||||
struct CLB_COUNT_MODE_1_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_COUNT_MODE_0_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 Counter mode 0 select 0
|
||||
Uint16 SEL_1:5; // 9:5 Counter mode 0 select 1
|
||||
Uint16 SEL_2:5; // 14:10 Counter mode 0 select 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_COUNT_MODE_0_REG {
|
||||
Uint32 all;
|
||||
struct CLB_COUNT_MODE_0_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_COUNT_EVENT_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 Counter event select 0
|
||||
Uint16 SEL_1:5; // 9:5 Counter event select 1
|
||||
Uint16 SEL_2:5; // 14:10 Counter event select 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_COUNT_EVENT_REG {
|
||||
Uint32 all;
|
||||
struct CLB_COUNT_EVENT_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_FSM_EXTRA_IN0_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 FSM extra ext input select 0
|
||||
Uint16 SEL_1:5; // 9:5 FSM extra ext input select 1
|
||||
Uint16 SEL_2:5; // 14:10 FSM extra ext input select 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_FSM_EXTRA_IN0_REG {
|
||||
Uint32 all;
|
||||
struct CLB_FSM_EXTRA_IN0_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_FSM_EXTERNAL_IN0_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 FSM EXT_IN0 select input for unit 0
|
||||
Uint16 SEL_1:5; // 9:5 FSM EXT_IN0 select input for unit 1
|
||||
Uint16 SEL_2:5; // 14:10 FSM EXT_IN0 select input for unit 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_FSM_EXTERNAL_IN0_REG {
|
||||
Uint32 all;
|
||||
struct CLB_FSM_EXTERNAL_IN0_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_FSM_EXTERNAL_IN1_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 FSM EXT_IN1 select input for unit 0
|
||||
Uint16 SEL_1:5; // 9:5 FSM EXT_IN1 select input for unit 1
|
||||
Uint16 SEL_2:5; // 14:10 FSM EXT_IN1 select input for unit 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_FSM_EXTERNAL_IN1_REG {
|
||||
Uint32 all;
|
||||
struct CLB_FSM_EXTERNAL_IN1_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_FSM_EXTRA_IN1_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 FSM extra ext input select 0
|
||||
Uint16 SEL_1:5; // 9:5 FSM extra ext input select 1
|
||||
Uint16 SEL_2:5; // 14:10 FSM extra ext input select 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_FSM_EXTRA_IN1_REG {
|
||||
Uint32 all;
|
||||
struct CLB_FSM_EXTRA_IN1_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LUT4_IN0_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 Select inputs for unit 0
|
||||
Uint16 SEL_1:5; // 9:5 Select inputs for unit 1
|
||||
Uint16 SEL_2:5; // 14:10 Select inputs for unit 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_LUT4_IN0_REG {
|
||||
Uint32 all;
|
||||
struct CLB_LUT4_IN0_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LUT4_IN1_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 Select inputs for unit 0
|
||||
Uint16 SEL_1:5; // 9:5 Select inputs for unit 1
|
||||
Uint16 SEL_2:5; // 14:10 Select inputs for unit 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_LUT4_IN1_REG {
|
||||
Uint32 all;
|
||||
struct CLB_LUT4_IN1_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LUT4_IN2_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 Select inputs for unit 0
|
||||
Uint16 SEL_1:5; // 9:5 Select inputs for unit 1
|
||||
Uint16 SEL_2:5; // 14:10 Select inputs for unit 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_LUT4_IN2_REG {
|
||||
Uint32 all;
|
||||
struct CLB_LUT4_IN2_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LUT4_IN3_BITS { // bits description
|
||||
Uint16 SEL_0:5; // 4:0 Select inputs for unit 0
|
||||
Uint16 SEL_1:5; // 9:5 Select inputs for unit 1
|
||||
Uint16 SEL_2:5; // 14:10 Select inputs for unit 2
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_LUT4_IN3_REG {
|
||||
Uint32 all;
|
||||
struct CLB_LUT4_IN3_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_FSM_LUT_FN1_0_BITS { // bits description
|
||||
Uint16 FN0:16; // 15:0 FSM LUT output function for unit 0
|
||||
Uint16 FN1:16; // 31:16 FSM LUT output function for unit 1
|
||||
};
|
||||
|
||||
union CLB_FSM_LUT_FN1_0_REG {
|
||||
Uint32 all;
|
||||
struct CLB_FSM_LUT_FN1_0_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_FSM_LUT_FN2_BITS { // bits description
|
||||
Uint16 FN1:16; // 15:0 FSM LUT output function for unit 2
|
||||
Uint16 rsvd1:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_FSM_LUT_FN2_REG {
|
||||
Uint32 all;
|
||||
struct CLB_FSM_LUT_FN2_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LUT4_FN1_0_BITS { // bits description
|
||||
Uint16 FN0:16; // 15:0 LUT4 output function for unit 0
|
||||
Uint16 FN1:16; // 31:16 LUT4 output function for unit 1
|
||||
};
|
||||
|
||||
union CLB_LUT4_FN1_0_REG {
|
||||
Uint32 all;
|
||||
struct CLB_LUT4_FN1_0_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LUT4_FN2_BITS { // bits description
|
||||
Uint16 FN1:16; // 15:0 LUT4 output function for unit 2
|
||||
Uint16 rsvd1:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_LUT4_FN2_REG {
|
||||
Uint32 all;
|
||||
struct CLB_LUT4_FN2_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_FSM_NEXT_STATE_0_BITS { // bits description
|
||||
Uint16 S0:16; // 15:0 FSM next state function for S0
|
||||
Uint16 S1:16; // 31:16 FSM next state function for S1
|
||||
};
|
||||
|
||||
union CLB_FSM_NEXT_STATE_0_REG {
|
||||
Uint32 all;
|
||||
struct CLB_FSM_NEXT_STATE_0_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_FSM_NEXT_STATE_1_BITS { // bits description
|
||||
Uint16 S0:16; // 15:0 FSM next state function for S0
|
||||
Uint16 S1:16; // 31:16 FSM next state function for S1
|
||||
};
|
||||
|
||||
union CLB_FSM_NEXT_STATE_1_REG {
|
||||
Uint32 all;
|
||||
struct CLB_FSM_NEXT_STATE_1_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_FSM_NEXT_STATE_2_BITS { // bits description
|
||||
Uint16 S0:16; // 15:0 FSM next state function for S0
|
||||
Uint16 S1:16; // 31:16 FSM next state function for S1
|
||||
};
|
||||
|
||||
union CLB_FSM_NEXT_STATE_2_REG {
|
||||
Uint32 all;
|
||||
struct CLB_FSM_NEXT_STATE_2_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_MISC_CONTROL_BITS { // bits description
|
||||
Uint16 COUNT_ADD_SHIFT_0:1; // 0 Add/Shift for counter 0
|
||||
Uint16 COUNT_DIR_0:1; // 1 Direction for counter 0
|
||||
Uint16 COUNT_EVENT_CTRL_0:1; // 2 Event control for counter 0
|
||||
Uint16 COUNT_ADD_SHIFT_1:1; // 3 Add/Shift for counter 1
|
||||
Uint16 COUNT_DIR_1:1; // 4 Direction for counter 1
|
||||
Uint16 COUNT_EVENT_CTRL_1:1; // 5 Event control for counter 1
|
||||
Uint16 COUNT_ADD_SHIFT_2:1; // 6 Add/Shift for counter 2
|
||||
Uint16 COUNT_DIR_2:1; // 7 Direction for counter 2
|
||||
Uint16 COUNT_EVENT_CTRL_2:1; // 8 Event control for counter 2
|
||||
Uint16 COUNT_SERIALIZER_0:1; // 9 Serializer enable 0
|
||||
Uint16 COUNT_SERIALIZER_1:1; // 10 Serializer enable 1
|
||||
Uint16 COUNT_SERIALIZER_2:1; // 11 Serializer enable 2
|
||||
Uint16 FSM_EXTRA_SEL0_0:1; // 12 FSM extra_sel0 for 0
|
||||
Uint16 FSM_EXTRA_SEL1_0:1; // 13 FSM extra_sel1 for 0
|
||||
Uint16 FSM_EXTRA_SEL0_1:1; // 14 FSM extra_sel0 for 1
|
||||
Uint16 FSM_EXTRA_SEL1_1:1; // 15 FSM extra_sel1 for 1
|
||||
Uint16 FSM_EXTRA_SEL0_2:1; // 16 FSM extra_sel0 for 2
|
||||
Uint16 FSM_EXTRA_SEL1_2:1; // 17 FSM extra_sel1 for 2
|
||||
Uint16 rsvd1:14; // 31:18 Reserved
|
||||
};
|
||||
|
||||
union CLB_MISC_CONTROL_REG {
|
||||
Uint32 all;
|
||||
struct CLB_MISC_CONTROL_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_OUTPUT_LUT_0_BITS { // bits description
|
||||
Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT
|
||||
Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT
|
||||
Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT
|
||||
Uint32 FN:8; // 22:15 Output function for output LUT
|
||||
Uint16 rsvd1:9; // 31:23 Reserved
|
||||
};
|
||||
|
||||
union CLB_OUTPUT_LUT_0_REG {
|
||||
Uint32 all;
|
||||
struct CLB_OUTPUT_LUT_0_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_OUTPUT_LUT_1_BITS { // bits description
|
||||
Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT
|
||||
Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT
|
||||
Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT
|
||||
Uint32 FN:8; // 22:15 Output function for output LUT
|
||||
Uint16 rsvd1:9; // 31:23 Reserved
|
||||
};
|
||||
|
||||
union CLB_OUTPUT_LUT_1_REG {
|
||||
Uint32 all;
|
||||
struct CLB_OUTPUT_LUT_1_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_OUTPUT_LUT_2_BITS { // bits description
|
||||
Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT
|
||||
Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT
|
||||
Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT
|
||||
Uint32 FN:8; // 22:15 Output function for output LUT
|
||||
Uint16 rsvd1:9; // 31:23 Reserved
|
||||
};
|
||||
|
||||
union CLB_OUTPUT_LUT_2_REG {
|
||||
Uint32 all;
|
||||
struct CLB_OUTPUT_LUT_2_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_OUTPUT_LUT_3_BITS { // bits description
|
||||
Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT
|
||||
Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT
|
||||
Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT
|
||||
Uint32 FN:8; // 22:15 Output function for output LUT
|
||||
Uint16 rsvd1:9; // 31:23 Reserved
|
||||
};
|
||||
|
||||
union CLB_OUTPUT_LUT_3_REG {
|
||||
Uint32 all;
|
||||
struct CLB_OUTPUT_LUT_3_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_OUTPUT_LUT_4_BITS { // bits description
|
||||
Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT
|
||||
Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT
|
||||
Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT
|
||||
Uint32 FN:8; // 22:15 Output function for output LUT
|
||||
Uint16 rsvd1:9; // 31:23 Reserved
|
||||
};
|
||||
|
||||
union CLB_OUTPUT_LUT_4_REG {
|
||||
Uint32 all;
|
||||
struct CLB_OUTPUT_LUT_4_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_OUTPUT_LUT_5_BITS { // bits description
|
||||
Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT
|
||||
Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT
|
||||
Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT
|
||||
Uint32 FN:8; // 22:15 Output function for output LUT
|
||||
Uint16 rsvd1:9; // 31:23 Reserved
|
||||
};
|
||||
|
||||
union CLB_OUTPUT_LUT_5_REG {
|
||||
Uint32 all;
|
||||
struct CLB_OUTPUT_LUT_5_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_OUTPUT_LUT_6_BITS { // bits description
|
||||
Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT
|
||||
Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT
|
||||
Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT
|
||||
Uint32 FN:8; // 22:15 Output function for output LUT
|
||||
Uint16 rsvd1:9; // 31:23 Reserved
|
||||
};
|
||||
|
||||
union CLB_OUTPUT_LUT_6_REG {
|
||||
Uint32 all;
|
||||
struct CLB_OUTPUT_LUT_6_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_OUTPUT_LUT_7_BITS { // bits description
|
||||
Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT
|
||||
Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT
|
||||
Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT
|
||||
Uint32 FN:8; // 22:15 Output function for output LUT
|
||||
Uint16 rsvd1:9; // 31:23 Reserved
|
||||
};
|
||||
|
||||
union CLB_OUTPUT_LUT_7_REG {
|
||||
Uint32 all;
|
||||
struct CLB_OUTPUT_LUT_7_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_HLC_EVENT_SEL_BITS { // bits description
|
||||
Uint16 EVENT0_SEL:5; // 4:0 Event Select 0
|
||||
Uint16 EVENT1_SEL:5; // 9:5 Event Select 1
|
||||
Uint16 EVENT2_SEL:5; // 14:10 Event Select 2
|
||||
Uint32 EVENT3_SEL:5; // 19:15 Event Select 3
|
||||
Uint16 rsvd1:12; // 31:20 Reserved
|
||||
};
|
||||
|
||||
union CLB_HLC_EVENT_SEL_REG {
|
||||
Uint32 all;
|
||||
struct CLB_HLC_EVENT_SEL_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LOGIC_CONFIG_REGS {
|
||||
Uint16 rsvd1[2]; // Reserved
|
||||
union CLB_COUNT_RESET_REG CLB_COUNT_RESET; // Counter Block RESET
|
||||
union CLB_COUNT_MODE_1_REG CLB_COUNT_MODE_1; // Counter Block MODE_1
|
||||
union CLB_COUNT_MODE_0_REG CLB_COUNT_MODE_0; // Counter Block MODE_0
|
||||
union CLB_COUNT_EVENT_REG CLB_COUNT_EVENT; // Counter Block EVENT
|
||||
union CLB_FSM_EXTRA_IN0_REG CLB_FSM_EXTRA_IN0; // FSM Extra EXT_IN0
|
||||
union CLB_FSM_EXTERNAL_IN0_REG CLB_FSM_EXTERNAL_IN0; // FSM EXT_IN0
|
||||
union CLB_FSM_EXTERNAL_IN1_REG CLB_FSM_EXTERNAL_IN1; // FSM_EXT_IN1
|
||||
union CLB_FSM_EXTRA_IN1_REG CLB_FSM_EXTRA_IN1; // FSM Extra_EXT_IN1
|
||||
union CLB_LUT4_IN0_REG CLB_LUT4_IN0; // LUT4_0/1/2 IN0 input source
|
||||
union CLB_LUT4_IN1_REG CLB_LUT4_IN1; // LUT4_0/1/2 IN1 input source
|
||||
union CLB_LUT4_IN2_REG CLB_LUT4_IN2; // LUT4_0/1/2 IN2 input source
|
||||
union CLB_LUT4_IN3_REG CLB_LUT4_IN3; // LUT4_0/1/2 IN3 input source
|
||||
Uint16 rsvd2[2]; // Reserved
|
||||
union CLB_FSM_LUT_FN1_0_REG CLB_FSM_LUT_FN1_0; // LUT function for FSM Unit 1 and Unit 0
|
||||
union CLB_FSM_LUT_FN2_REG CLB_FSM_LUT_FN2; // LUT function for FSM Unit 2
|
||||
union CLB_LUT4_FN1_0_REG CLB_LUT4_FN1_0; // LUT function for LUT4 block of Unit 1 and 0
|
||||
union CLB_LUT4_FN2_REG CLB_LUT4_FN2; // LUT function for LUT4 block of Unit 2
|
||||
union CLB_FSM_NEXT_STATE_0_REG CLB_FSM_NEXT_STATE_0; // FSM Next state equations for Unit 0
|
||||
union CLB_FSM_NEXT_STATE_1_REG CLB_FSM_NEXT_STATE_1; // FSM Next state equations for Unit 1
|
||||
union CLB_FSM_NEXT_STATE_2_REG CLB_FSM_NEXT_STATE_2; // FSM Next state equations for Unit 2
|
||||
union CLB_MISC_CONTROL_REG CLB_MISC_CONTROL; // Static controls for Ctr,FSM
|
||||
union CLB_OUTPUT_LUT_0_REG CLB_OUTPUT_LUT_0; // Inp Sel, LUT fns for Out0
|
||||
union CLB_OUTPUT_LUT_1_REG CLB_OUTPUT_LUT_1; // Inp Sel, LUT fns for Out1
|
||||
union CLB_OUTPUT_LUT_2_REG CLB_OUTPUT_LUT_2; // Inp Sel, LUT fns for Out2
|
||||
union CLB_OUTPUT_LUT_3_REG CLB_OUTPUT_LUT_3; // Inp Sel, LUT fns for Out3
|
||||
union CLB_OUTPUT_LUT_4_REG CLB_OUTPUT_LUT_4; // Inp Sel, LUT fns for Out4
|
||||
union CLB_OUTPUT_LUT_5_REG CLB_OUTPUT_LUT_5; // Inp Sel, LUT fns for Out5
|
||||
union CLB_OUTPUT_LUT_6_REG CLB_OUTPUT_LUT_6; // Inp Sel, LUT fns for Out6
|
||||
union CLB_OUTPUT_LUT_7_REG CLB_OUTPUT_LUT_7; // Inp Sel, LUT fns for Out7
|
||||
union CLB_HLC_EVENT_SEL_REG CLB_HLC_EVENT_SEL; // Event Selector register for the High Level controller
|
||||
};
|
||||
|
||||
struct CLB_LOAD_EN_BITS { // bits description
|
||||
Uint16 LOAD_EN:1; // 0 Load Enable
|
||||
Uint16 GLOBAL_EN:1; // 1 Global Enable
|
||||
Uint16 STOP:1; // 2 Debug stop control
|
||||
Uint16 rsvd1:13; // 15:3 Reserved
|
||||
};
|
||||
|
||||
union CLB_LOAD_EN_REG {
|
||||
Uint16 all;
|
||||
struct CLB_LOAD_EN_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LOAD_ADDR_BITS { // bits description
|
||||
Uint16 ADDR:6; // 5:0 Indirect Address
|
||||
Uint16 rsvd1:10; // 15:6 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_LOAD_ADDR_REG {
|
||||
Uint32 all;
|
||||
struct CLB_LOAD_ADDR_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_INPUT_FILTER_BITS { // bits description
|
||||
Uint16 FIN0:2; // 1:0 Input filter control 0
|
||||
Uint16 FIN1:2; // 3:2 Input filter control 1
|
||||
Uint16 FIN2:2; // 5:4 Input filter control 2
|
||||
Uint16 FIN3:2; // 7:6 Input filter control 3
|
||||
Uint16 FIN4:2; // 9:8 Input filter control 4
|
||||
Uint16 FIN5:2; // 11:10 Input filter control 5
|
||||
Uint16 FIN6:2; // 13:12 Input filter control 6
|
||||
Uint16 FIN7:2; // 15:14 Input filter control 7
|
||||
Uint16 SYNC0:1; // 16 Synchronizer control 0
|
||||
Uint16 SYNC1:1; // 17 Synchronizer control 1
|
||||
Uint16 SYNC2:1; // 18 Synchronizer control 2
|
||||
Uint16 SYNC3:1; // 19 Synchronizer control 3
|
||||
Uint16 SYNC4:1; // 20 Synchronizer control 4
|
||||
Uint16 SYNC5:1; // 21 Synchronizer control 5
|
||||
Uint16 SYNC6:1; // 22 Synchronizer control 6
|
||||
Uint16 SYNC7:1; // 23 Synchronizer control 7
|
||||
Uint16 rsvd1:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union CLB_INPUT_FILTER_REG {
|
||||
Uint32 all;
|
||||
struct CLB_INPUT_FILTER_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_IN_MUX_SEL_0_BITS { // bits description
|
||||
Uint16 SEL_GP_IN_0:1; // 0 Select GP register 0
|
||||
Uint16 SEL_GP_IN_1:1; // 1 Select GP register 1
|
||||
Uint16 SEL_GP_IN_2:1; // 2 Select GP register 2
|
||||
Uint16 SEL_GP_IN_3:1; // 3 Select GP register 3
|
||||
Uint16 SEL_GP_IN_4:1; // 4 Select GP register 4
|
||||
Uint16 SEL_GP_IN_5:1; // 5 Select GP register 5
|
||||
Uint16 SEL_GP_IN_6:1; // 6 Select GP register 6
|
||||
Uint16 SEL_GP_IN_7:1; // 7 Select GP register 7
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_IN_MUX_SEL_0_REG {
|
||||
Uint32 all;
|
||||
struct CLB_IN_MUX_SEL_0_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LCL_MUX_SEL_1_BITS { // bits description
|
||||
Uint16 LCL_MUX_SEL_IN_0:5; // 4:0 Local Mux select 0
|
||||
Uint16 LCL_MUX_SEL_IN_1:5; // 9:5 Local Mux select 1
|
||||
Uint16 LCL_MUX_SEL_IN_2:5; // 14:10 Local Mux select 2
|
||||
Uint32 LCL_MUX_SEL_IN_3:5; // 19:15 Local Mux select 3
|
||||
Uint16 rsvd1:12; // 31:20 Reserved
|
||||
};
|
||||
|
||||
union CLB_LCL_MUX_SEL_1_REG {
|
||||
Uint32 all;
|
||||
struct CLB_LCL_MUX_SEL_1_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LCL_MUX_SEL_2_BITS { // bits description
|
||||
Uint16 LCL_MUX_SEL_IN_4:5; // 4:0 Local Mux select 4
|
||||
Uint16 LCL_MUX_SEL_IN_5:5; // 9:5 Local Mux select 5
|
||||
Uint16 LCL_MUX_SEL_IN_6:5; // 14:10 Local Mux select 6
|
||||
Uint32 LCL_MUX_SEL_IN_7:5; // 19:15 Local Mux select 7
|
||||
Uint16 rsvd1:12; // 31:20 Reserved
|
||||
};
|
||||
|
||||
union CLB_LCL_MUX_SEL_2_REG {
|
||||
Uint32 all;
|
||||
struct CLB_LCL_MUX_SEL_2_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_BUF_PTR_BITS { // bits description
|
||||
Uint16 PULL:8; // 7:0 Data pointer for pull
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 PUSH:8; // 23:16 Data pointer for pull
|
||||
Uint16 rsvd2:8; // 31:24 Reserved
|
||||
};
|
||||
|
||||
union CLB_BUF_PTR_REG {
|
||||
Uint32 all;
|
||||
struct CLB_BUF_PTR_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_GP_REG_BITS { // bits description
|
||||
Uint16 REG:8; // 7:0 General Purpose bit register
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CLB_GP_REG_REG {
|
||||
Uint32 all;
|
||||
struct CLB_GP_REG_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_GLBL_MUX_SEL_1_BITS { // bits description
|
||||
Uint16 GLBL_MUX_SEL_IN_0:7; // 6:0 Global Mux select 0
|
||||
Uint16 GLBL_MUX_SEL_IN_1:7; // 13:7 Global Mux select 1
|
||||
Uint32 GLBL_MUX_SEL_IN_2:7; // 20:14 Global Mux select 2
|
||||
Uint16 GLBL_MUX_SEL_IN_3:7; // 27:21 Global Mux select 3
|
||||
Uint16 rsvd1:4; // 31:28 Reserved
|
||||
};
|
||||
|
||||
union CLB_GLBL_MUX_SEL_1_REG {
|
||||
Uint32 all;
|
||||
struct CLB_GLBL_MUX_SEL_1_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_GLBL_MUX_SEL_2_BITS { // bits description
|
||||
Uint16 GLBL_MUX_SEL_IN_4:7; // 6:0 Global Mux select 4
|
||||
Uint16 GLBL_MUX_SEL_IN_5:7; // 13:7 Global Mux select 5
|
||||
Uint32 GLBL_MUX_SEL_IN_6:7; // 20:14 Global Mux select 6
|
||||
Uint16 GLBL_MUX_SEL_IN_7:7; // 27:21 Global Mux select 7
|
||||
Uint16 rsvd1:4; // 31:28 Reserved
|
||||
};
|
||||
|
||||
union CLB_GLBL_MUX_SEL_2_REG {
|
||||
Uint32 all;
|
||||
struct CLB_GLBL_MUX_SEL_2_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_INTR_TAG_REG_BITS { // bits description
|
||||
Uint16 TAG:6; // 5:0 Interrupt tag
|
||||
Uint16 rsvd1:10; // 15:6 Reserved
|
||||
};
|
||||
|
||||
union CLB_INTR_TAG_REG_REG {
|
||||
Uint16 all;
|
||||
struct CLB_INTR_TAG_REG_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LOCK_BITS { // bits description
|
||||
Uint16 LOCK:1; // 0 LOCK enable
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
Uint16 KEY:16; // 31:16 Key for enabling write
|
||||
};
|
||||
|
||||
union CLB_LOCK_REG {
|
||||
Uint32 all;
|
||||
struct CLB_LOCK_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_DBG_OUT_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 COUNT0_MATCH2:1; // 1 COUNT_MATCH2 UNIT 0
|
||||
Uint16 COUNT0_ZERO:1; // 2 COUNT_ZERO UNIT 0
|
||||
Uint16 COUNT0_MATCH1:1; // 3 COUNT_MATCH1 UNIT 0
|
||||
Uint16 FSM0_S0:1; // 4 FSM_S0 UNIT 0
|
||||
Uint16 FSM0_S1:1; // 5 FSM_S1 UNIT 0
|
||||
Uint16 FSM0_LUTOUT:1; // 6 FSM_LUT_OUT UNIT 0
|
||||
Uint16 LUT40_OUT:1; // 7 LUT4_OUT UNIT 0
|
||||
Uint16 rsvd2:1; // 8 Reserved
|
||||
Uint16 COUNT1_MATCH2:1; // 9 COUNT_MATCH2 UNIT 1
|
||||
Uint16 COUNT1_ZERO:1; // 10 COUNT_ZERO UNIT 1
|
||||
Uint16 COUNT1_MATCH1:1; // 11 COUNT_MATCH1 UNIT 1
|
||||
Uint16 FSM1_S0:1; // 12 FSM_S0 UNIT 1
|
||||
Uint16 FSM1_S1:1; // 13 FSM_S1 UNIT 1
|
||||
Uint16 FSM1_LUTOUT:1; // 14 FSM_LUT_OUT UNIT 1
|
||||
Uint16 LUT41_OUT:1; // 15 LUT4_OUT UNIT 1
|
||||
Uint16 rsvd3:1; // 16 Reserved
|
||||
Uint16 COUNT2_MATCH2:1; // 17 COUNT_MATCH2 UNIT 2
|
||||
Uint16 COUNT2_ZERO:1; // 18 COUNT_ZERO UNIT 2
|
||||
Uint16 COUNT2_MATCH1:1; // 19 COUNT_MATCH1 UNIT 2
|
||||
Uint16 FSM2_S0:1; // 20 FSM_S0 UNIT 2
|
||||
Uint16 FSM2_S1:1; // 21 FSM_S1 UNIT 2
|
||||
Uint16 FSM2_LUTOUT:1; // 22 FSM_LUT_OUT UNIT 2
|
||||
Uint16 LUT42_OUT:1; // 23 LUT4_OUT UNIT 2
|
||||
Uint16 OUT0:1; // 24 CELL Output 0
|
||||
Uint16 OUT1:1; // 25 CELL Output 1
|
||||
Uint16 OUT2:1; // 26 CELL Output 2
|
||||
Uint16 OUT3:1; // 27 CELL Output 3
|
||||
Uint16 OUT4:1; // 28 CELL Output 4
|
||||
Uint16 OUT5:1; // 29 CELL Output 5
|
||||
Uint16 OUT6:1; // 30 CELL Output 6
|
||||
Uint16 OUT7:1; // 31 CELL Output 7
|
||||
};
|
||||
|
||||
union CLB_DBG_OUT_REG {
|
||||
Uint32 all;
|
||||
struct CLB_DBG_OUT_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_LOGIC_CONTROL_REGS {
|
||||
union CLB_LOAD_EN_REG CLB_LOAD_EN; // Global enable & indirect load enable control
|
||||
Uint16 rsvd1; // Reserved
|
||||
union CLB_LOAD_ADDR_REG CLB_LOAD_ADDR; // Indirect address
|
||||
Uint32 CLB_LOAD_DATA; // Data for indirect loads
|
||||
union CLB_INPUT_FILTER_REG CLB_INPUT_FILTER; // Input filter selection for both edge detection and synchronizers
|
||||
union CLB_IN_MUX_SEL_0_REG CLB_IN_MUX_SEL_0; // Input selection to decide between Signals and GP register
|
||||
union CLB_LCL_MUX_SEL_1_REG CLB_LCL_MUX_SEL_1; // Input Mux selection for local mux
|
||||
union CLB_LCL_MUX_SEL_2_REG CLB_LCL_MUX_SEL_2; // Input Mux selection for local mux
|
||||
union CLB_BUF_PTR_REG CLB_BUF_PTR; // PUSH and PULL pointers
|
||||
union CLB_GP_REG_REG CLB_GP_REG; // General purpose register for CELL inputs
|
||||
Uint32 CLB_OUT_EN; // CELL output enable register
|
||||
union CLB_GLBL_MUX_SEL_1_REG CLB_GLBL_MUX_SEL_1; // Global Mux select for CELL inputs
|
||||
union CLB_GLBL_MUX_SEL_2_REG CLB_GLBL_MUX_SEL_2; // Global Mux select for CELL inputs
|
||||
Uint16 rsvd2[8]; // Reserved
|
||||
union CLB_INTR_TAG_REG_REG CLB_INTR_TAG_REG; // Interrupt Tag register
|
||||
Uint16 rsvd3; // Reserved
|
||||
union CLB_LOCK_REG CLB_LOCK; // Lock control register
|
||||
Uint16 rsvd4[12]; // Reserved
|
||||
Uint32 CLB_DBG_R0; // R0 of High level Controller
|
||||
Uint32 CLB_DBG_R1; // R1 of High level Controller
|
||||
Uint32 CLB_DBG_R2; // R2 of High level Controller
|
||||
Uint32 CLB_DBG_R3; // R3 of High level Controller
|
||||
Uint32 CLB_DBG_C0; // Count of Unit 0
|
||||
Uint32 CLB_DBG_C1; // Count of Unit 1
|
||||
Uint32 CLB_DBG_C2; // Count of Unit 2
|
||||
union CLB_DBG_OUT_REG CLB_DBG_OUT; // Outputs of various units in the Cell
|
||||
};
|
||||
|
||||
struct CLB_DATA_EXCHANGE_REGS {
|
||||
Uint32 CLB_PUSH[4]; // CLB_PUSH FIFO Registers (from HLC)
|
||||
Uint16 rsvd1[248]; // Reserved
|
||||
Uint32 CLB_PULL[4]; // CLB_PULL FIFO Registers (TO HLC)
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CLB External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct CLB_LOGIC_CONFIG_REGS Clb1LogicCfgRegs;
|
||||
extern volatile struct CLB_LOGIC_CONTROL_REGS Clb1LogicCtrlRegs;
|
||||
extern volatile struct CLB_DATA_EXCHANGE_REGS Clb1DataExchRegs;
|
||||
extern volatile struct CLB_LOGIC_CONFIG_REGS Clb2LogicCfgRegs;
|
||||
extern volatile struct CLB_LOGIC_CONTROL_REGS Clb2LogicCtrlRegs;
|
||||
extern volatile struct CLB_DATA_EXCHANGE_REGS Clb2DataExchRegs;
|
||||
extern volatile struct CLB_LOGIC_CONFIG_REGS Clb3LogicCfgRegs;
|
||||
extern volatile struct CLB_LOGIC_CONTROL_REGS Clb3LogicCtrlRegs;
|
||||
extern volatile struct CLB_DATA_EXCHANGE_REGS Clb3DataExchRegs;
|
||||
extern volatile struct CLB_LOGIC_CONFIG_REGS Clb4LogicCfgRegs;
|
||||
extern volatile struct CLB_LOGIC_CONTROL_REGS Clb4LogicCtrlRegs;
|
||||
extern volatile struct CLB_DATA_EXCHANGE_REGS Clb4DataExchRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct CLB_LOGIC_CONFIG_REGS Clb1LogicCfgRegs;
|
||||
extern volatile struct CLB_LOGIC_CONTROL_REGS Clb1LogicCtrlRegs;
|
||||
extern volatile struct CLB_DATA_EXCHANGE_REGS Clb1DataExchRegs;
|
||||
extern volatile struct CLB_LOGIC_CONFIG_REGS Clb2LogicCfgRegs;
|
||||
extern volatile struct CLB_LOGIC_CONTROL_REGS Clb2LogicCtrlRegs;
|
||||
extern volatile struct CLB_DATA_EXCHANGE_REGS Clb2DataExchRegs;
|
||||
extern volatile struct CLB_LOGIC_CONFIG_REGS Clb3LogicCfgRegs;
|
||||
extern volatile struct CLB_LOGIC_CONTROL_REGS Clb3LogicCtrlRegs;
|
||||
extern volatile struct CLB_DATA_EXCHANGE_REGS Clb3DataExchRegs;
|
||||
extern volatile struct CLB_LOGIC_CONFIG_REGS Clb4LogicCfgRegs;
|
||||
extern volatile struct CLB_LOGIC_CONTROL_REGS Clb4LogicCtrlRegs;
|
||||
extern volatile struct CLB_DATA_EXCHANGE_REGS Clb4DataExchRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,832 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_clbxbar.h
|
||||
//
|
||||
// TITLE: Definitions for the CLBXBAR registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_CLBXBAR_H
|
||||
#define F2837xD_CLBXBAR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CLBXBAR Individual Register Bit Definitions:
|
||||
|
||||
struct AUXSIG0MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG0 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG0MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG0MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG0MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG0 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG0MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG0MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG1MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG1 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG1MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG1MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG1MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG1 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG1MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG1MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG2MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG2 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG2MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG2MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG2MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG2 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG2MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG2MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG3MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG3 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG3MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG3MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG3MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG3 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG3MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG3MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG4MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG4 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG4MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG4MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG4MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG4 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG4MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG4MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG5MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG5 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG5MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG5MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG5MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG5 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG5MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG5MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG6MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG6 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG6MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG6MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG6MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG6 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG6MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG6MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG7MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG7 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG7MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG7MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG7MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG7 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG7MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG7MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG0MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG0 of CLB-XBAR
|
||||
Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG0 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG0MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG0MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG1MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG1 of CLB-XBAR
|
||||
Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG1 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG1MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG1MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG2MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG2 of CLB-XBAR
|
||||
Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG2 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG2MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG2MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG3MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG3 of CLB-XBAR
|
||||
Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG3 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG3MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG3MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG4MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG4 of CLB-XBAR
|
||||
Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG4 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG4MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG4MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG5MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG5 of CLB-XBAR
|
||||
Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG5 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG5MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG5MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG6MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG6 of CLB-XBAR
|
||||
Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG6 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG6MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG6MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIG7MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG7 of CLB-XBAR
|
||||
Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG7 of CLB-XBAR
|
||||
};
|
||||
|
||||
union AUXSIG7MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIG7MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIGOUTINV_BITS { // bits description
|
||||
Uint16 OUT0:1; // 0 Selects polarity for AUXSIG0 of CLB-XBAR
|
||||
Uint16 OUT1:1; // 1 Selects polarity for AUXSIG1 of CLB-XBAR
|
||||
Uint16 OUT2:1; // 2 Selects polarity for AUXSIG2 of CLB-XBAR
|
||||
Uint16 OUT3:1; // 3 Selects polarity for AUXSIG3 of CLB-XBAR
|
||||
Uint16 OUT4:1; // 4 Selects polarity for AUXSIG4 of CLB-XBAR
|
||||
Uint16 OUT5:1; // 5 Selects polarity for AUXSIG5 of CLB-XBAR
|
||||
Uint16 OUT6:1; // 6 Selects polarity for AUXSIG6 of CLB-XBAR
|
||||
Uint16 OUT7:1; // 7 Selects polarity for AUXSIG7 of CLB-XBAR
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union AUXSIGOUTINV_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIGOUTINV_BITS bit;
|
||||
};
|
||||
|
||||
struct AUXSIGLOCK_BITS { // bits description
|
||||
Uint16 LOCK:1; // 0 Locks the configuration for CLB-XBAR
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
Uint16 KEY:16; // 31:16 Write Protection KEY
|
||||
};
|
||||
|
||||
union AUXSIGLOCK_REG {
|
||||
Uint32 all;
|
||||
struct AUXSIGLOCK_BITS bit;
|
||||
};
|
||||
|
||||
struct CLB_XBAR_REGS {
|
||||
union AUXSIG0MUX0TO15CFG_REG AUXSIG0MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-0
|
||||
union AUXSIG0MUX16TO31CFG_REG AUXSIG0MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-0
|
||||
union AUXSIG1MUX0TO15CFG_REG AUXSIG1MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-1
|
||||
union AUXSIG1MUX16TO31CFG_REG AUXSIG1MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-1
|
||||
union AUXSIG2MUX0TO15CFG_REG AUXSIG2MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-2
|
||||
union AUXSIG2MUX16TO31CFG_REG AUXSIG2MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-2
|
||||
union AUXSIG3MUX0TO15CFG_REG AUXSIG3MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-3
|
||||
union AUXSIG3MUX16TO31CFG_REG AUXSIG3MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-3
|
||||
union AUXSIG4MUX0TO15CFG_REG AUXSIG4MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-4
|
||||
union AUXSIG4MUX16TO31CFG_REG AUXSIG4MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-4
|
||||
union AUXSIG5MUX0TO15CFG_REG AUXSIG5MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-5
|
||||
union AUXSIG5MUX16TO31CFG_REG AUXSIG5MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-5
|
||||
union AUXSIG6MUX0TO15CFG_REG AUXSIG6MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-6
|
||||
union AUXSIG6MUX16TO31CFG_REG AUXSIG6MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-6
|
||||
union AUXSIG7MUX0TO15CFG_REG AUXSIG7MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-7
|
||||
union AUXSIG7MUX16TO31CFG_REG AUXSIG7MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-7
|
||||
union AUXSIG0MUXENABLE_REG AUXSIG0MUXENABLE; // CLB XBAR Mux Enable Register for Output-0
|
||||
union AUXSIG1MUXENABLE_REG AUXSIG1MUXENABLE; // CLB XBAR Mux Enable Register for Output-1
|
||||
union AUXSIG2MUXENABLE_REG AUXSIG2MUXENABLE; // CLB XBAR Mux Enable Register for Output-2
|
||||
union AUXSIG3MUXENABLE_REG AUXSIG3MUXENABLE; // CLB XBAR Mux Enable Register for Output-3
|
||||
union AUXSIG4MUXENABLE_REG AUXSIG4MUXENABLE; // CLB XBAR Mux Enable Register for Output-4
|
||||
union AUXSIG5MUXENABLE_REG AUXSIG5MUXENABLE; // CLB XBAR Mux Enable Register for Output-5
|
||||
union AUXSIG6MUXENABLE_REG AUXSIG6MUXENABLE; // CLB XBAR Mux Enable Register for Output-6
|
||||
union AUXSIG7MUXENABLE_REG AUXSIG7MUXENABLE; // CLB XBAR Mux Enable Register for Output-7
|
||||
Uint16 rsvd1[8]; // Reserved
|
||||
union AUXSIGOUTINV_REG AUXSIGOUTINV; // CLB XBAR Output Inversion Register
|
||||
Uint16 rsvd2[4]; // Reserved
|
||||
union AUXSIGLOCK_REG AUXSIGLOCK; // ClbXbar Configuration Lock register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CLBXBAR External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct CLB_XBAR_REGS ClbXbarRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,309 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_cmpss.h
|
||||
//
|
||||
// TITLE: Definitions for the CMPSS registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_CMPSS_H
|
||||
#define F2837xD_CMPSS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CMPSS Individual Register Bit Definitions:
|
||||
|
||||
struct COMPCTL_BITS { // bits description
|
||||
Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select
|
||||
Uint16 COMPHINV:1; // 1 High Comparator Invert Select
|
||||
Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select
|
||||
Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select
|
||||
Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable
|
||||
Uint16 rsvd1:1; // 7 Reserved
|
||||
Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select
|
||||
Uint16 COMPLINV:1; // 9 Low Comparator Invert Select
|
||||
Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select
|
||||
Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select
|
||||
Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable
|
||||
Uint16 COMPDACE:1; // 15 Comparator/DAC Enable
|
||||
};
|
||||
|
||||
union COMPCTL_REG {
|
||||
Uint16 all;
|
||||
struct COMPCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct COMPHYSCTL_BITS { // bits description
|
||||
Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim
|
||||
Uint16 rsvd1:13; // 15:3 Reserved
|
||||
};
|
||||
|
||||
union COMPHYSCTL_REG {
|
||||
Uint16 all;
|
||||
struct COMPHYSCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct COMPSTS_BITS { // bits description
|
||||
Uint16 COMPHSTS:1; // 0 High Comparator Status
|
||||
Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status
|
||||
Uint16 rsvd1:6; // 7:2 Reserved
|
||||
Uint16 COMPLSTS:1; // 8 Low Comparator Status
|
||||
Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status
|
||||
Uint16 rsvd2:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union COMPSTS_REG {
|
||||
Uint16 all;
|
||||
struct COMPSTS_BITS bit;
|
||||
};
|
||||
|
||||
struct COMPSTSCLR_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear
|
||||
Uint16 HSYNCCLREN:1; // 2 High Comparator EPWMSYNCPER Clear Enable
|
||||
Uint16 rsvd2:6; // 8:3 Reserved
|
||||
Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear
|
||||
Uint16 LSYNCCLREN:1; // 10 Low Comparator EPWMSYNCPER Clear Enable
|
||||
Uint16 rsvd3:5; // 15:11 Reserved
|
||||
};
|
||||
|
||||
union COMPSTSCLR_REG {
|
||||
Uint16 all;
|
||||
struct COMPSTSCLR_BITS bit;
|
||||
};
|
||||
|
||||
struct COMPDACCTL_BITS { // bits description
|
||||
Uint16 DACSOURCE:1; // 0 DAC Source Control
|
||||
Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control
|
||||
Uint16 SELREF:1; // 5 DAC Reference Select
|
||||
Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select
|
||||
Uint16 SWLOADSEL:1; // 7 Software Load Select
|
||||
Uint16 rsvd1:6; // 13:8 Reserved
|
||||
Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits
|
||||
};
|
||||
|
||||
union COMPDACCTL_REG {
|
||||
Uint16 all;
|
||||
struct COMPDACCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct DACHVALS_BITS { // bits description
|
||||
Uint16 DACVAL:12; // 11:0 DAC Value Control
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union DACHVALS_REG {
|
||||
Uint16 all;
|
||||
struct DACHVALS_BITS bit;
|
||||
};
|
||||
|
||||
struct DACHVALA_BITS { // bits description
|
||||
Uint16 DACVAL:12; // 11:0 DAC Value Control
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union DACHVALA_REG {
|
||||
Uint16 all;
|
||||
struct DACHVALA_BITS bit;
|
||||
};
|
||||
|
||||
struct DACLVALS_BITS { // bits description
|
||||
Uint16 DACVAL:12; // 11:0 DAC Value Control
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union DACLVALS_REG {
|
||||
Uint16 all;
|
||||
struct DACLVALS_BITS bit;
|
||||
};
|
||||
|
||||
struct DACLVALA_BITS { // bits description
|
||||
Uint16 DACVAL:12; // 11:0 DAC Value Control
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union DACLVALA_REG {
|
||||
Uint16 all;
|
||||
struct DACLVALA_BITS bit;
|
||||
};
|
||||
|
||||
struct RAMPDLYA_BITS { // bits description
|
||||
Uint16 DELAY:13; // 12:0 Ramp Delay Value
|
||||
Uint16 rsvd1:3; // 15:13 Reserved
|
||||
};
|
||||
|
||||
union RAMPDLYA_REG {
|
||||
Uint16 all;
|
||||
struct RAMPDLYA_BITS bit;
|
||||
};
|
||||
|
||||
struct RAMPDLYS_BITS { // bits description
|
||||
Uint16 DELAY:13; // 12:0 Ramp Delay Value
|
||||
Uint16 rsvd1:3; // 15:13 Reserved
|
||||
};
|
||||
|
||||
union RAMPDLYS_REG {
|
||||
Uint16 all;
|
||||
struct RAMPDLYS_BITS bit;
|
||||
};
|
||||
|
||||
struct CTRIPLFILCTL_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 Reserved
|
||||
Uint16 SAMPWIN:5; // 8:4 Sample Window
|
||||
Uint16 THRESH:5; // 13:9 Majority Voting Threshold
|
||||
Uint16 rsvd2:1; // 14 Reserved
|
||||
Uint16 FILINIT:1; // 15 Filter Initialization Bit
|
||||
};
|
||||
|
||||
union CTRIPLFILCTL_REG {
|
||||
Uint16 all;
|
||||
struct CTRIPLFILCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct CTRIPLFILCLKCTL_BITS { // bits description
|
||||
Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale
|
||||
Uint16 rsvd1:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union CTRIPLFILCLKCTL_REG {
|
||||
Uint16 all;
|
||||
struct CTRIPLFILCLKCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct CTRIPHFILCTL_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 Reserved
|
||||
Uint16 SAMPWIN:5; // 8:4 Sample Window
|
||||
Uint16 THRESH:5; // 13:9 Majority Voting Threshold
|
||||
Uint16 rsvd2:1; // 14 Reserved
|
||||
Uint16 FILINIT:1; // 15 Filter Initialization Bit
|
||||
};
|
||||
|
||||
union CTRIPHFILCTL_REG {
|
||||
Uint16 all;
|
||||
struct CTRIPHFILCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct CTRIPHFILCLKCTL_BITS { // bits description
|
||||
Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale
|
||||
Uint16 rsvd1:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union CTRIPHFILCLKCTL_REG {
|
||||
Uint16 all;
|
||||
struct CTRIPHFILCLKCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct COMPLOCK_BITS { // bits description
|
||||
Uint16 COMPCTL:1; // 0 COMPCTL Lock
|
||||
Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock
|
||||
Uint16 DACCTL:1; // 2 DACCTL Lock
|
||||
Uint16 CTRIP:1; // 3 CTRIP Lock
|
||||
Uint16 rsvd1:1; // 4 Reserved
|
||||
Uint16 rsvd2:11; // 15:5 Reserved
|
||||
};
|
||||
|
||||
union COMPLOCK_REG {
|
||||
Uint16 all;
|
||||
struct COMPLOCK_BITS bit;
|
||||
};
|
||||
|
||||
struct CMPSS_REGS {
|
||||
union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register
|
||||
union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register
|
||||
union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register
|
||||
union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register
|
||||
union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register
|
||||
Uint16 rsvd1; // Reserved
|
||||
union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register
|
||||
union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register
|
||||
Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register
|
||||
Uint16 rsvd2; // Reserved
|
||||
Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register
|
||||
Uint16 rsvd3; // Reserved
|
||||
Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register
|
||||
Uint16 rsvd4; // Reserved
|
||||
Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register
|
||||
Uint16 rsvd5; // Reserved
|
||||
Uint16 RAMPSTS; // CMPSS Ramp Status Register
|
||||
Uint16 rsvd6; // Reserved
|
||||
union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register
|
||||
union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register
|
||||
union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register
|
||||
union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register
|
||||
union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register
|
||||
union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register
|
||||
union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register
|
||||
union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register
|
||||
union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CMPSS External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct CMPSS_REGS Cmpss1Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss2Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss3Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss4Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss5Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss6Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss7Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss8Regs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct CMPSS_REGS Cmpss1Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss2Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss3Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss4Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss5Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss6Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss7Regs;
|
||||
extern volatile struct CMPSS_REGS Cmpss8Regs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,141 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_cputimer.h
|
||||
//
|
||||
// TITLE: Definitions for the CPUTIMER registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_CPUTIMER_H
|
||||
#define F2837xD_CPUTIMER_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CPUTIMER Individual Register Bit Definitions:
|
||||
|
||||
struct TIM_BITS { // bits description
|
||||
Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers
|
||||
Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High
|
||||
};
|
||||
|
||||
union TIM_REG {
|
||||
Uint32 all;
|
||||
struct TIM_BITS bit;
|
||||
};
|
||||
|
||||
struct PRD_BITS { // bits description
|
||||
Uint16 LSW:16; // 15:0 CPU-Timer Period Registers
|
||||
Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High
|
||||
};
|
||||
|
||||
union PRD_REG {
|
||||
Uint32 all;
|
||||
struct PRD_BITS bit;
|
||||
};
|
||||
|
||||
struct TCR_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 Reserved
|
||||
Uint16 TSS:1; // 4 CPU-Timer stop status bit.
|
||||
Uint16 TRB:1; // 5 Timer reload
|
||||
Uint16 rsvd2:4; // 9:6 Reserved
|
||||
Uint16 SOFT:1; // 10 Emulation modes
|
||||
Uint16 FREE:1; // 11 Emulation modes
|
||||
Uint16 rsvd3:2; // 13:12 Reserved
|
||||
Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable.
|
||||
Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag.
|
||||
};
|
||||
|
||||
union TCR_REG {
|
||||
Uint16 all;
|
||||
struct TCR_BITS bit;
|
||||
};
|
||||
|
||||
struct TPR_BITS { // bits description
|
||||
Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down.
|
||||
Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter.
|
||||
};
|
||||
|
||||
union TPR_REG {
|
||||
Uint16 all;
|
||||
struct TPR_BITS bit;
|
||||
};
|
||||
|
||||
struct TPRH_BITS { // bits description
|
||||
Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down.
|
||||
Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter.
|
||||
};
|
||||
|
||||
union TPRH_REG {
|
||||
Uint16 all;
|
||||
struct TPRH_BITS bit;
|
||||
};
|
||||
|
||||
struct CPUTIMER_REGS {
|
||||
union TIM_REG TIM; // CPU-Timer, Counter Register
|
||||
union PRD_REG PRD; // CPU-Timer, Period Register
|
||||
union TCR_REG TCR; // CPU-Timer, Control Register
|
||||
Uint16 rsvd1; // Reserved
|
||||
union TPR_REG TPR; // CPU-Timer, Prescale Register
|
||||
union TPRH_REG TPRH; // CPU-Timer, Prescale Register High
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// CPUTIMER External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer1Regs;
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer1Regs;
|
||||
extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,163 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_dac.h
|
||||
//
|
||||
// TITLE: Definitions for the DAC registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_DAC_H
|
||||
#define F2837xD_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// DAC Individual Register Bit Definitions:
|
||||
|
||||
struct DACREV_BITS { // bits description
|
||||
Uint16 REV:8; // 7:0 DAC Revision Register
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union DACREV_REG {
|
||||
Uint16 all;
|
||||
struct DACREV_BITS bit;
|
||||
};
|
||||
|
||||
struct DACCTL_BITS { // bits description
|
||||
Uint16 DACREFSEL:1; // 0 DAC Reference Select
|
||||
Uint16 rsvd1:1; // 1 Reserved
|
||||
Uint16 LOADMODE:1; // 2 DACVALA Load Mode
|
||||
Uint16 rsvd2:1; // 3 Reserved
|
||||
Uint16 SYNCSEL:4; // 7:4 DAC EPWMSYNCPER Select
|
||||
Uint16 rsvd3:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union DACCTL_REG {
|
||||
Uint16 all;
|
||||
struct DACCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct DACVALA_BITS { // bits description
|
||||
Uint16 DACVALA:12; // 11:0 DAC Active Output Code
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union DACVALA_REG {
|
||||
Uint16 all;
|
||||
struct DACVALA_BITS bit;
|
||||
};
|
||||
|
||||
struct DACVALS_BITS { // bits description
|
||||
Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union DACVALS_REG {
|
||||
Uint16 all;
|
||||
struct DACVALS_BITS bit;
|
||||
};
|
||||
|
||||
struct DACOUTEN_BITS { // bits description
|
||||
Uint16 DACOUTEN:1; // 0 DAC Output Code
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
};
|
||||
|
||||
union DACOUTEN_REG {
|
||||
Uint16 all;
|
||||
struct DACOUTEN_BITS bit;
|
||||
};
|
||||
|
||||
struct DACLOCK_BITS { // bits description
|
||||
Uint16 DACCTL:1; // 0 DAC Control Register Lock
|
||||
Uint16 DACVAL:1; // 1 DAC Value Register Lock
|
||||
Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock
|
||||
Uint16 rsvd1:9; // 11:3 Reserved
|
||||
Uint16 KEY:4; // 15:12 DAC Register Lock Key
|
||||
};
|
||||
|
||||
union DACLOCK_REG {
|
||||
Uint16 all;
|
||||
struct DACLOCK_BITS bit;
|
||||
};
|
||||
|
||||
struct DACTRIM_BITS { // bits description
|
||||
Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim
|
||||
Uint16 rsvd1:4; // 11:8 Reserved
|
||||
Uint16 rsvd2:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union DACTRIM_REG {
|
||||
Uint16 all;
|
||||
struct DACTRIM_BITS bit;
|
||||
};
|
||||
|
||||
struct DAC_REGS {
|
||||
union DACREV_REG DACREV; // DAC Revision Register
|
||||
union DACCTL_REG DACCTL; // DAC Control Register
|
||||
union DACVALA_REG DACVALA; // DAC Value Register - Active
|
||||
union DACVALS_REG DACVALS; // DAC Value Register - Shadow
|
||||
union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register
|
||||
union DACLOCK_REG DACLOCK; // DAC Lock Register
|
||||
union DACTRIM_REG DACTRIM; // DAC Trim Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// DAC External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct DAC_REGS DacaRegs;
|
||||
extern volatile struct DAC_REGS DacbRegs;
|
||||
extern volatile struct DAC_REGS DaccRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct DAC_REGS DacaRegs;
|
||||
extern volatile struct DAC_REGS DacbRegs;
|
||||
extern volatile struct DAC_REGS DaccRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,446 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_dcsm.h
|
||||
//
|
||||
// TITLE: Definitions for the DCSM registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_DCSM_H
|
||||
#define F2837xD_DCSM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// DCSM Individual Register Bit Definitions:
|
||||
|
||||
struct Z1_LINKPOINTER_BITS { // bits description
|
||||
Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer.
|
||||
Uint16 rsvd1:3; // 31:29 Reserved
|
||||
};
|
||||
|
||||
union Z1_LINKPOINTER_REG {
|
||||
Uint32 all;
|
||||
struct Z1_LINKPOINTER_BITS bit;
|
||||
};
|
||||
|
||||
struct Z1_OTPSECLOCK_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 Reserved
|
||||
Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock.
|
||||
Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock.
|
||||
Uint16 rsvd2:4; // 15:12 Reserved
|
||||
Uint16 rsvd3:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union Z1_OTPSECLOCK_REG {
|
||||
Uint32 all;
|
||||
struct Z1_OTPSECLOCK_BITS bit;
|
||||
};
|
||||
|
||||
struct Z1_BOOTCTRL_BITS { // bits description
|
||||
Uint16 KEY:8; // 7:0 OTP Boot Key
|
||||
Uint16 BMODE:8; // 15:8 OTP Boot Mode
|
||||
Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping
|
||||
Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping
|
||||
};
|
||||
|
||||
union Z1_BOOTCTRL_REG {
|
||||
Uint32 all;
|
||||
struct Z1_BOOTCTRL_BITS bit;
|
||||
};
|
||||
|
||||
struct Z1_CR_BITS { // bits description
|
||||
Uint16 rsvd1:3; // 2:0 Reserved
|
||||
Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros
|
||||
Uint16 ALLONE:1; // 4 CSMPSWD All Ones
|
||||
Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY
|
||||
Uint16 ARMED:1; // 6 CSM Armed
|
||||
Uint16 rsvd2:1; // 7 Reserved
|
||||
Uint16 rsvd3:7; // 14:8 Reserved
|
||||
Uint16 FORCESEC:1; // 15 Force Secure
|
||||
};
|
||||
|
||||
union Z1_CR_REG {
|
||||
Uint16 all;
|
||||
struct Z1_CR_BITS bit;
|
||||
};
|
||||
|
||||
struct Z1_GRABSECTR_BITS { // bits description
|
||||
Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A
|
||||
Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B
|
||||
Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C
|
||||
Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D
|
||||
Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E
|
||||
Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F
|
||||
Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G
|
||||
Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H
|
||||
Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I
|
||||
Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J
|
||||
Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K
|
||||
Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L
|
||||
Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M
|
||||
Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N
|
||||
Uint16 rsvd1:2; // 29:28 Reserved
|
||||
Uint16 rsvd2:2; // 31:30 Reserved
|
||||
};
|
||||
|
||||
union Z1_GRABSECTR_REG {
|
||||
Uint32 all;
|
||||
struct Z1_GRABSECTR_BITS bit;
|
||||
};
|
||||
|
||||
struct Z1_GRABRAMR_BITS { // bits description
|
||||
Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0
|
||||
Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1
|
||||
Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2
|
||||
Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3
|
||||
Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4
|
||||
Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5
|
||||
Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0
|
||||
Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1
|
||||
Uint16 rsvd1:12; // 27:16 Reserved
|
||||
Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1
|
||||
Uint16 rsvd2:2; // 31:30 Reserved
|
||||
};
|
||||
|
||||
union Z1_GRABRAMR_REG {
|
||||
Uint32 all;
|
||||
struct Z1_GRABRAMR_BITS bit;
|
||||
};
|
||||
|
||||
struct Z1_EXEONLYSECTR_BITS { // bits description
|
||||
Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A
|
||||
Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B
|
||||
Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C
|
||||
Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D
|
||||
Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E
|
||||
Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F
|
||||
Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G
|
||||
Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H
|
||||
Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I
|
||||
Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J
|
||||
Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K
|
||||
Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L
|
||||
Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M
|
||||
Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N
|
||||
Uint16 rsvd1:1; // 14 Reserved
|
||||
Uint16 rsvd2:1; // 15 Reserved
|
||||
Uint16 rsvd3:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union Z1_EXEONLYSECTR_REG {
|
||||
Uint32 all;
|
||||
struct Z1_EXEONLYSECTR_BITS bit;
|
||||
};
|
||||
|
||||
struct Z1_EXEONLYRAMR_BITS { // bits description
|
||||
Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0
|
||||
Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1
|
||||
Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2
|
||||
Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3
|
||||
Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4
|
||||
Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5
|
||||
Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0
|
||||
Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union Z1_EXEONLYRAMR_REG {
|
||||
Uint32 all;
|
||||
struct Z1_EXEONLYRAMR_BITS bit;
|
||||
};
|
||||
|
||||
struct DCSM_Z1_REGS {
|
||||
union Z1_LINKPOINTER_REG Z1_LINKPOINTER; // Zone 1 Link Pointer
|
||||
union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure JTAG lock
|
||||
union Z1_BOOTCTRL_REG Z1_BOOTCTRL; // Boot Mode
|
||||
Uint32 Z1_LINKPOINTERERR; // Link Pointer Error
|
||||
Uint16 rsvd1[8]; // Reserved
|
||||
Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0
|
||||
Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1
|
||||
Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2
|
||||
Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3
|
||||
Uint16 rsvd2; // Reserved
|
||||
union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register
|
||||
union Z1_GRABSECTR_REG Z1_GRABSECTR; // Zone 1 Grab Flash Sectors Register
|
||||
union Z1_GRABRAMR_REG Z1_GRABRAMR; // Zone 1 Grab RAM Blocks Register
|
||||
union Z1_EXEONLYSECTR_REG Z1_EXEONLYSECTR; // Zone 1 Flash Execute_Only Sector Register
|
||||
union Z1_EXEONLYRAMR_REG Z1_EXEONLYRAMR; // Zone 1 RAM Execute_Only Block Register
|
||||
};
|
||||
|
||||
struct Z2_LINKPOINTER_BITS { // bits description
|
||||
Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer.
|
||||
Uint16 rsvd1:3; // 31:29 Reserved
|
||||
};
|
||||
|
||||
union Z2_LINKPOINTER_REG {
|
||||
Uint32 all;
|
||||
struct Z2_LINKPOINTER_BITS bit;
|
||||
};
|
||||
|
||||
struct Z2_OTPSECLOCK_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 Reserved
|
||||
Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock.
|
||||
Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock.
|
||||
Uint16 rsvd2:4; // 15:12 Reserved
|
||||
Uint16 rsvd3:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union Z2_OTPSECLOCK_REG {
|
||||
Uint32 all;
|
||||
struct Z2_OTPSECLOCK_BITS bit;
|
||||
};
|
||||
|
||||
struct Z2_BOOTCTRL_BITS { // bits description
|
||||
Uint16 KEY:8; // 7:0 OTP Boot Key
|
||||
Uint16 BMODE:8; // 15:8 OTP Boot Mode
|
||||
Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping
|
||||
Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping
|
||||
};
|
||||
|
||||
union Z2_BOOTCTRL_REG {
|
||||
Uint32 all;
|
||||
struct Z2_BOOTCTRL_BITS bit;
|
||||
};
|
||||
|
||||
struct Z2_CR_BITS { // bits description
|
||||
Uint16 rsvd1:3; // 2:0 Reserved
|
||||
Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros
|
||||
Uint16 ALLONE:1; // 4 CSMPSWD All Ones
|
||||
Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY
|
||||
Uint16 ARMED:1; // 6 CSM Armed
|
||||
Uint16 rsvd2:1; // 7 Reserved
|
||||
Uint16 rsvd3:7; // 14:8 Reserved
|
||||
Uint16 FORCESEC:1; // 15 Force Secure
|
||||
};
|
||||
|
||||
union Z2_CR_REG {
|
||||
Uint16 all;
|
||||
struct Z2_CR_BITS bit;
|
||||
};
|
||||
|
||||
struct Z2_GRABSECTR_BITS { // bits description
|
||||
Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A
|
||||
Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B
|
||||
Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C
|
||||
Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D
|
||||
Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E
|
||||
Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F
|
||||
Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G
|
||||
Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H
|
||||
Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I
|
||||
Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J
|
||||
Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K
|
||||
Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L
|
||||
Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M
|
||||
Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N
|
||||
Uint16 rsvd1:2; // 29:28 Reserved
|
||||
Uint16 rsvd2:2; // 31:30 Reserved
|
||||
};
|
||||
|
||||
union Z2_GRABSECTR_REG {
|
||||
Uint32 all;
|
||||
struct Z2_GRABSECTR_BITS bit;
|
||||
};
|
||||
|
||||
struct Z2_GRABRAMR_BITS { // bits description
|
||||
Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0
|
||||
Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1
|
||||
Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2
|
||||
Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3
|
||||
Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4
|
||||
Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5
|
||||
Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0
|
||||
Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1
|
||||
Uint16 rsvd1:12; // 27:16 Reserved
|
||||
Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1
|
||||
Uint16 rsvd2:2; // 31:30 Reserved
|
||||
};
|
||||
|
||||
union Z2_GRABRAMR_REG {
|
||||
Uint32 all;
|
||||
struct Z2_GRABRAMR_BITS bit;
|
||||
};
|
||||
|
||||
struct Z2_EXEONLYSECTR_BITS { // bits description
|
||||
Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A
|
||||
Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B
|
||||
Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C
|
||||
Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D
|
||||
Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E
|
||||
Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F
|
||||
Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G
|
||||
Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H
|
||||
Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I
|
||||
Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J
|
||||
Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K
|
||||
Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L
|
||||
Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M
|
||||
Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N
|
||||
Uint16 rsvd1:1; // 14 Reserved
|
||||
Uint16 rsvd2:1; // 15 Reserved
|
||||
Uint16 rsvd3:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union Z2_EXEONLYSECTR_REG {
|
||||
Uint32 all;
|
||||
struct Z2_EXEONLYSECTR_BITS bit;
|
||||
};
|
||||
|
||||
struct Z2_EXEONLYRAMR_BITS { // bits description
|
||||
Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0
|
||||
Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1
|
||||
Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2
|
||||
Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3
|
||||
Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4
|
||||
Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5
|
||||
Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0
|
||||
Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union Z2_EXEONLYRAMR_REG {
|
||||
Uint32 all;
|
||||
struct Z2_EXEONLYRAMR_BITS bit;
|
||||
};
|
||||
|
||||
struct DCSM_Z2_REGS {
|
||||
union Z2_LINKPOINTER_REG Z2_LINKPOINTER; // Zone 2 Link Pointer
|
||||
union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure JTAG lock
|
||||
union Z2_BOOTCTRL_REG Z2_BOOTCTRL; // Boot Mode
|
||||
Uint32 Z2_LINKPOINTERERR; // Link Pointer Error
|
||||
Uint16 rsvd1[8]; // Reserved
|
||||
Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0
|
||||
Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1
|
||||
Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2
|
||||
Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3
|
||||
Uint16 rsvd2; // Reserved
|
||||
union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register
|
||||
union Z2_GRABSECTR_REG Z2_GRABSECTR; // Zone 2 Grab Flash Sectors Register
|
||||
union Z2_GRABRAMR_REG Z2_GRABRAMR; // Zone 2 Grab RAM Blocks Register
|
||||
union Z2_EXEONLYSECTR_REG Z2_EXEONLYSECTR; // Zone 2 Flash Execute_Only Sector Register
|
||||
union Z2_EXEONLYRAMR_REG Z2_EXEONLYRAMR; // Zone 2 RAM Execute_Only Block Register
|
||||
};
|
||||
|
||||
struct FLSEM_BITS { // bits description
|
||||
Uint16 SEM:2; // 1:0 Flash Semaphore Bit
|
||||
Uint16 rsvd1:6; // 7:2 Reserved
|
||||
Uint16 KEY:8; // 15:8 Semaphore Key
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union FLSEM_REG {
|
||||
Uint32 all;
|
||||
struct FLSEM_BITS bit;
|
||||
};
|
||||
|
||||
struct SECTSTAT_BITS { // bits description
|
||||
Uint16 STATUS_SECTA:2; // 1:0 Zone Status Flash Sector A
|
||||
Uint16 STATUS_SECTB:2; // 3:2 Zone Status Flash Sector B
|
||||
Uint16 STATUS_SECTC:2; // 5:4 Zone Status Flash Sector C
|
||||
Uint16 STATUS_SECTD:2; // 7:6 Zone Status Flash Sector D
|
||||
Uint16 STATUS_SECTE:2; // 9:8 Zone Status Flash Sector E
|
||||
Uint16 STATUS_SECTF:2; // 11:10 Zone Status Flash Sector F
|
||||
Uint16 STATUS_SECTG:2; // 13:12 Zone Status Flash Sector G
|
||||
Uint16 STATUS_SECTH:2; // 15:14 Zone Status Flash Sector H
|
||||
Uint16 STATUS_SECTI:2; // 17:16 Zone Status Flash Sector I
|
||||
Uint16 STATUS_SECTJ:2; // 19:18 Zone Status Flash Sector J
|
||||
Uint16 STATUS_SECTK:2; // 21:20 Zone Status Flash Sector K
|
||||
Uint16 STATUS_SECTL:2; // 23:22 Zone Status Flash Sector L
|
||||
Uint16 STATUS_SECTM:2; // 25:24 Zone Status Flash Sector M
|
||||
Uint16 STATUS_SECTN:2; // 27:26 Zone Status Flash Sector N
|
||||
Uint16 rsvd1:2; // 29:28 Reserved
|
||||
Uint16 rsvd2:2; // 31:30 Reserved
|
||||
};
|
||||
|
||||
union SECTSTAT_REG {
|
||||
Uint32 all;
|
||||
struct SECTSTAT_BITS bit;
|
||||
};
|
||||
|
||||
struct RAMSTAT_BITS { // bits description
|
||||
Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM LS0
|
||||
Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM LS1
|
||||
Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM LS2
|
||||
Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM LS3
|
||||
Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM LS4
|
||||
Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM LS5
|
||||
Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM D0
|
||||
Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM D1
|
||||
Uint16 rsvd1:12; // 27:16 Reserved
|
||||
Uint16 STATUS_CLA1:2; // 29:28 Zone Status CLA1
|
||||
Uint16 rsvd2:2; // 31:30 Reserved
|
||||
};
|
||||
|
||||
union RAMSTAT_REG {
|
||||
Uint32 all;
|
||||
struct RAMSTAT_BITS bit;
|
||||
};
|
||||
|
||||
struct DCSM_COMMON_REGS {
|
||||
union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register
|
||||
union SECTSTAT_REG SECTSTAT; // Sectors Status Register
|
||||
union RAMSTAT_REG RAMSTAT; // RAM Status Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// DCSM External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct DCSM_Z1_REGS DcsmZ1Regs;
|
||||
extern volatile struct DCSM_Z2_REGS DcsmZ2Regs;
|
||||
extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct DCSM_Z1_REGS DcsmZ1Regs;
|
||||
extern volatile struct DCSM_Z2_REGS DcsmZ2Regs;
|
||||
extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,366 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_device.h
|
||||
//
|
||||
// TITLE: F2837xD Device Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_DEVICE_H
|
||||
#define F2837xD_DEVICE_H
|
||||
|
||||
#if (!defined(CPU1) && !defined(CPU2))
|
||||
#error "You must define CPU1 or CPU2 in your project properties. Otherwise, the offsets in your header files will be inaccurate."
|
||||
#endif
|
||||
|
||||
#if (defined(CPU1) && defined(CPU2))
|
||||
#error "You have defined both CPU1 and CPU2 in your project properties. Only a single CPU should be defined."
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define TARGET 1
|
||||
|
||||
//
|
||||
// User To Select Target Device:
|
||||
//
|
||||
#define F28_2837xD TARGET
|
||||
|
||||
//
|
||||
// Common CPU Definitions:
|
||||
//
|
||||
#ifndef __TMS320C28XX__
|
||||
#define __cregister
|
||||
#endif //__TMS320C28xx__
|
||||
|
||||
extern __cregister volatile unsigned int IFR;
|
||||
extern __cregister volatile unsigned int IER;
|
||||
|
||||
#define EINT __asm(" clrc INTM")
|
||||
#define DINT __asm(" setc INTM")
|
||||
#define ERTM __asm(" clrc DBGM")
|
||||
#define DRTM __asm(" setc DBGM")
|
||||
#ifndef EALLOW
|
||||
#define EALLOW __asm(" EALLOW")
|
||||
#endif
|
||||
#ifndef EDIS
|
||||
#define EDIS __asm(" EDIS")
|
||||
#endif
|
||||
#define ESTOP0 __asm(" ESTOP0")
|
||||
|
||||
#define M_INT1 0x0001
|
||||
#define M_INT2 0x0002
|
||||
#define M_INT3 0x0004
|
||||
#define M_INT4 0x0008
|
||||
#define M_INT5 0x0010
|
||||
#define M_INT6 0x0020
|
||||
#define M_INT7 0x0040
|
||||
#define M_INT8 0x0080
|
||||
#define M_INT9 0x0100
|
||||
#define M_INT10 0x0200
|
||||
#define M_INT11 0x0400
|
||||
#define M_INT12 0x0800
|
||||
#define M_INT13 0x1000
|
||||
#define M_INT14 0x2000
|
||||
#define M_DLOG 0x4000
|
||||
#define M_RTOS 0x8000
|
||||
|
||||
#ifndef C28X_BIT0
|
||||
#define C28X_BIT0 0x00000001
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT1
|
||||
#define C28X_BIT1 0x00000002
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT2
|
||||
#define C28X_BIT2 0x00000004
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT3
|
||||
#define C28X_BIT3 0x00000008
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT4
|
||||
#define C28X_BIT4 0x00000010
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT5
|
||||
#define C28X_BIT5 0x00000020
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT6
|
||||
#define C28X_BIT6 0x00000040
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT7
|
||||
#define C28X_BIT7 0x00000080
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT8
|
||||
#define C28X_BIT8 0x00000100
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT9
|
||||
#define C28X_BIT9 0x00000200
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT10
|
||||
#define C28X_BIT10 0x00000400
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT11
|
||||
#define C28X_BIT11 0x00000800
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT12
|
||||
#define C28X_BIT12 0x00001000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT13
|
||||
#define C28X_BIT13 0x00002000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT14
|
||||
#define C28X_BIT14 0x00004000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT15
|
||||
#define C28X_BIT15 0x00008000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT16
|
||||
#define C28X_BIT16 0x00010000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT17
|
||||
#define C28X_BIT17 0x00020000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT18
|
||||
#define C28X_BIT18 0x00040000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT19
|
||||
#define C28X_BIT19 0x00080000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT20
|
||||
#define C28X_BIT20 0x00100000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT21
|
||||
#define C28X_BIT21 0x00200000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT22
|
||||
#define C28X_BIT22 0x00400000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT23
|
||||
#define C28X_BIT23 0x00800000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT24
|
||||
#define C28X_BIT24 0x01000000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT25
|
||||
#define C28X_BIT25 0x02000000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT26
|
||||
#define C28X_BIT26 0x04000000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT27
|
||||
#define C28X_BIT27 0x08000000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT28
|
||||
#define C28X_BIT28 0x10000000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT29
|
||||
#define C28X_BIT29 0x20000000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT30
|
||||
#define C28X_BIT30 0x40000000
|
||||
#endif
|
||||
|
||||
#ifndef C28X_BIT31
|
||||
#define C28X_BIT31 0x80000000
|
||||
#endif
|
||||
|
||||
//
|
||||
// For Portability, User Is Recommended To Use the C99 Standard integer types
|
||||
//
|
||||
#if !defined(__TMS320C28XX_CLA__)
|
||||
#include <assert.h>
|
||||
#include <stdarg.h>
|
||||
#endif //__TMS320C28XX_CLA__
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
//
|
||||
// C++ Bool Compatibility
|
||||
//
|
||||
#if defined(__cplusplus)
|
||||
typedef bool _Bool;
|
||||
#endif
|
||||
|
||||
//
|
||||
// C99 defines boolean type to be _Bool, but this doesn't match the format of
|
||||
// the other standard integer types. bool_t has been defined to fill this gap.
|
||||
//
|
||||
typedef _Bool bool_t;
|
||||
|
||||
//
|
||||
//used for a bool function return status
|
||||
//
|
||||
typedef _Bool status_t;
|
||||
|
||||
#ifndef SUCCESS
|
||||
#define SUCCESS true
|
||||
#endif
|
||||
|
||||
#ifndef FAIL
|
||||
#define FAIL false
|
||||
#endif
|
||||
|
||||
//
|
||||
// The following data types are included for compatibility with legacy code,
|
||||
// they are not recommended for use in new software. Please use the C99
|
||||
// types included above
|
||||
//
|
||||
#ifndef DSP28_DATA_TYPES
|
||||
#define DSP28_DATA_TYPES
|
||||
|
||||
#ifdef __TMS320C28XX_CLA__
|
||||
typedef short int16;
|
||||
typedef long int32;
|
||||
typedef unsigned char Uint8;
|
||||
typedef unsigned short Uint16;
|
||||
typedef unsigned long Uint32;
|
||||
typedef float float32;
|
||||
typedef long double float64;
|
||||
typedef struct { Uint32 low32; Uint32 high32; } Uint64;
|
||||
typedef struct { int32 low32; int32 high32; } int64;
|
||||
#else // __TMS320C28XX__
|
||||
typedef int int16;
|
||||
typedef long int32;
|
||||
typedef long long int64;
|
||||
typedef unsigned int Uint16;
|
||||
typedef unsigned long Uint32;
|
||||
typedef unsigned long long Uint64;
|
||||
typedef float float32;
|
||||
typedef long double float64;
|
||||
#endif //__TMS320C28XX_CLA__
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// The following data types are for use with byte addressable peripherals.
|
||||
// See compiler documentation on the byte_peripheral type attribute.
|
||||
//
|
||||
#ifndef __TMS320C28XX_CLA__
|
||||
#if __TI_COMPILER_VERSION__ >= 16006000
|
||||
typedef unsigned int bp_16 __attribute__((byte_peripheral));
|
||||
typedef unsigned long bp_32 __attribute__((byte_peripheral));
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//
|
||||
// Include All Peripheral Header Files:
|
||||
//
|
||||
#include "F2837xD_adc.h"
|
||||
#include "F2837xD_analogsubsys.h"
|
||||
#include "F2837xD_cla.h"
|
||||
#include "F2837xD_clb.h"
|
||||
#include "F2837xD_clbxbar.h"
|
||||
#include "F2837xD_cmpss.h"
|
||||
#include "F2837xD_cputimer.h"
|
||||
#include "F2837xD_dac.h"
|
||||
#include "F2837xD_dcsm.h"
|
||||
#include "F2837xD_dma.h"
|
||||
#include "F2837xD_ecap.h"
|
||||
#include "F2837xD_emif.h"
|
||||
#include "F2837xD_epwm.h" // Enhanced PWM
|
||||
#include "F2837xD_epwm_xbar.h"
|
||||
#include "F2837xD_eqep.h"
|
||||
#include "F2837xD_flash.h"
|
||||
#include "F2837xD_gpio.h" // General Purpose I/O Registers
|
||||
#include "F2837xD_i2c.h"
|
||||
#include "F2837xD_input_xbar.h"
|
||||
#include "F2837xD_ipc.h"
|
||||
#include "F2837xD_mcbsp.h"
|
||||
#include "F2837xD_memconfig.h"
|
||||
#include "F2837xD_nmiintrupt.h" // NMI Interrupt Registers
|
||||
#include "F2837xD_otp.h"
|
||||
#include "F2837xD_output_xbar.h"
|
||||
#include "F2837xD_piectrl.h" // PIE Control Registers
|
||||
#include "F2837xD_pievect.h"
|
||||
#include "F2837xD_sci.h"
|
||||
#include "F2837xD_sdfm.h"
|
||||
#include "F2837xD_spi.h"
|
||||
#include "F2837xD_sysctrl.h" // System Control/Power Modes
|
||||
#include "F2837xD_upp.h"
|
||||
#include "F2837xD_xbar.h"
|
||||
#include "F2837xD_xint.h" // External Interrupts
|
||||
|
||||
//
|
||||
// byte_peripheral attribute is only supported on the C28
|
||||
//
|
||||
#ifndef __TMS320C28XX_CLA__
|
||||
#if __TI_COMPILER_VERSION__ >= 16006000
|
||||
#include "F2837xD_can.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif // extern "C"
|
||||
|
||||
#endif // end of F2837xD_DEVICE_H definition
|
||||
|
||||
//
|
||||
// End of file.
|
||||
//
|
||||
@@ -0,0 +1,220 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_dma.h
|
||||
//
|
||||
// TITLE: Definitions for the DMA registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_DMA_H
|
||||
#define F2837xD_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// DMA Individual Register Bit Definitions:
|
||||
|
||||
struct MODE_BITS { // bits description
|
||||
Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select
|
||||
Uint16 rsvd1:2; // 6:5 Reserved
|
||||
Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable
|
||||
Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable
|
||||
Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode
|
||||
Uint16 ONESHOT:1; // 10 One Shot Mode Bit
|
||||
Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit
|
||||
Uint16 rsvd2:1; // 12 Reserved
|
||||
Uint16 rsvd3:1; // 13 Reserved
|
||||
Uint16 DATASIZE:1; // 14 Data Size Mode Bit
|
||||
Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit
|
||||
};
|
||||
|
||||
union MODE_REG {
|
||||
Uint16 all;
|
||||
struct MODE_BITS bit;
|
||||
};
|
||||
|
||||
struct CONTROL_BITS { // bits description
|
||||
Uint16 RUN:1; // 0 Run Bit
|
||||
Uint16 HALT:1; // 1 Halt Bit
|
||||
Uint16 SOFTRESET:1; // 2 Soft Reset Bit
|
||||
Uint16 PERINTFRC:1; // 3 Interrupt Force Bit
|
||||
Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit
|
||||
Uint16 rsvd1:1; // 5 Reserved
|
||||
Uint16 rsvd2:1; // 6 Reserved
|
||||
Uint16 ERRCLR:1; // 7 Error Clear Bit
|
||||
Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit
|
||||
Uint16 rsvd3:1; // 9 Reserved
|
||||
Uint16 rsvd4:1; // 10 Reserved
|
||||
Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit
|
||||
Uint16 BURSTSTS:1; // 12 Burst Status Bit
|
||||
Uint16 RUNSTS:1; // 13 Run Status Bit
|
||||
Uint16 OVRFLG:1; // 14 Overflow Flag Bit
|
||||
Uint16 rsvd5:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union CONTROL_REG {
|
||||
Uint16 all;
|
||||
struct CONTROL_BITS bit;
|
||||
};
|
||||
|
||||
struct BURST_SIZE_BITS { // bits description
|
||||
Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size
|
||||
Uint16 rsvd1:11; // 15:5 Reserved
|
||||
};
|
||||
|
||||
union BURST_SIZE_REG {
|
||||
Uint16 all;
|
||||
struct BURST_SIZE_BITS bit;
|
||||
};
|
||||
|
||||
struct BURST_COUNT_BITS { // bits description
|
||||
Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Size
|
||||
Uint16 rsvd1:11; // 15:5 Reserved
|
||||
};
|
||||
|
||||
union BURST_COUNT_REG {
|
||||
Uint16 all;
|
||||
struct BURST_COUNT_BITS bit;
|
||||
};
|
||||
|
||||
struct CH_REGS {
|
||||
union MODE_REG MODE; // Mode Register
|
||||
union CONTROL_REG CONTROL; // Control Register
|
||||
union BURST_SIZE_REG BURST_SIZE; // Burst Size Register
|
||||
union BURST_COUNT_REG BURST_COUNT; // Burst Count Register
|
||||
int16 SRC_BURST_STEP; // Source Burst Step Register
|
||||
int16 DST_BURST_STEP; // Destination Burst Step Register
|
||||
Uint16 TRANSFER_SIZE; // Transfer Size Register
|
||||
Uint16 TRANSFER_COUNT; // Transfer Count Register
|
||||
int16 SRC_TRANSFER_STEP; // Source Transfer Step Register
|
||||
int16 DST_TRANSFER_STEP; // Destination Transfer Step Register
|
||||
Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register
|
||||
Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register
|
||||
int16 SRC_WRAP_STEP; // Source Wrap Step Register
|
||||
Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register
|
||||
Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register
|
||||
int16 DST_WRAP_STEP; // Destination Wrap Step Register
|
||||
Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register
|
||||
Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register
|
||||
Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register
|
||||
Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register
|
||||
Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register
|
||||
Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register
|
||||
Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register
|
||||
Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register
|
||||
};
|
||||
|
||||
struct DMACTRL_BITS { // bits description
|
||||
Uint16 HARDRESET:1; // 0 Hard Reset Bit
|
||||
Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit
|
||||
Uint16 rsvd1:14; // 15:2 Reserved
|
||||
};
|
||||
|
||||
union DMACTRL_REG {
|
||||
Uint16 all;
|
||||
struct DMACTRL_BITS bit;
|
||||
};
|
||||
|
||||
struct DEBUGCTRL_BITS { // bits description
|
||||
Uint16 rsvd1:15; // 14:0 Reserved
|
||||
Uint16 FREE:1; // 15 Debug Mode Bit
|
||||
};
|
||||
|
||||
union DEBUGCTRL_REG {
|
||||
Uint16 all;
|
||||
struct DEBUGCTRL_BITS bit;
|
||||
};
|
||||
|
||||
struct PRIORITYCTRL1_BITS { // bits description
|
||||
Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
};
|
||||
|
||||
union PRIORITYCTRL1_REG {
|
||||
Uint16 all;
|
||||
struct PRIORITYCTRL1_BITS bit;
|
||||
};
|
||||
|
||||
struct PRIORITYSTAT_BITS { // bits description
|
||||
Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits
|
||||
Uint16 rsvd1:1; // 3 Reserved
|
||||
Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits
|
||||
Uint16 rsvd2:9; // 15:7 Reserved
|
||||
};
|
||||
|
||||
union PRIORITYSTAT_REG {
|
||||
Uint16 all;
|
||||
struct PRIORITYSTAT_BITS bit;
|
||||
};
|
||||
|
||||
struct DMA_REGS {
|
||||
union DMACTRL_REG DMACTRL; // DMA Control Register
|
||||
union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register
|
||||
Uint16 rsvd1[2]; // Reserved
|
||||
union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register
|
||||
Uint16 rsvd2; // Reserved
|
||||
union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register
|
||||
Uint16 rsvd3[25]; // Reserved
|
||||
struct CH_REGS CH1; // DMA Channel 1 Registers
|
||||
struct CH_REGS CH2; // DMA Channel 2 Registers
|
||||
struct CH_REGS CH3; // DMA Channel 3 Registers
|
||||
struct CH_REGS CH4; // DMA Channel 4 Registers
|
||||
struct CH_REGS CH5; // DMA Channel 5 Registers
|
||||
struct CH_REGS CH6; // DMA Channel 6 Registers
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// DMA External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct DMA_REGS DmaRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct DMA_REGS DmaRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,202 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_ecap.h
|
||||
//
|
||||
// TITLE: Definitions for the ECAP registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_ECAP_H
|
||||
#define F2837xD_ECAP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// ECAP Individual Register Bit Definitions:
|
||||
|
||||
struct ECCTL1_BITS { // bits description
|
||||
Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select
|
||||
Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1
|
||||
Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select
|
||||
Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2
|
||||
Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select
|
||||
Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3
|
||||
Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select
|
||||
Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4
|
||||
Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event
|
||||
Uint16 PRESCALE:5; // 13:9 Event Filter prescale select
|
||||
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
|
||||
};
|
||||
|
||||
union ECCTL1_REG {
|
||||
Uint16 all;
|
||||
struct ECCTL1_BITS bit;
|
||||
};
|
||||
|
||||
struct ECCTL2_BITS { // bits description
|
||||
Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot
|
||||
Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous
|
||||
Uint16 REARM:1; // 3 One-shot re-arm
|
||||
Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop
|
||||
Uint16 SYNCI_EN:1; // 5 Counter sync-in select
|
||||
Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode
|
||||
Uint16 SWSYNC:1; // 8 SW forced counter sync
|
||||
Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select
|
||||
Uint16 APWMPOL:1; // 10 APWM output polarity select
|
||||
Uint16 rsvd1:5; // 15:11 Reserved
|
||||
};
|
||||
|
||||
union ECCTL2_REG {
|
||||
Uint16 all;
|
||||
struct ECCTL2_BITS bit;
|
||||
};
|
||||
|
||||
struct ECEINT_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable
|
||||
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable
|
||||
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable
|
||||
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable
|
||||
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable
|
||||
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable
|
||||
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable
|
||||
Uint16 rsvd2:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union ECEINT_REG {
|
||||
Uint16 all;
|
||||
struct ECEINT_BITS bit;
|
||||
};
|
||||
|
||||
struct ECFLG_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global Flag
|
||||
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag
|
||||
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag
|
||||
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag
|
||||
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag
|
||||
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag
|
||||
Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag
|
||||
Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union ECFLG_REG {
|
||||
Uint16 all;
|
||||
struct ECFLG_BITS bit;
|
||||
};
|
||||
|
||||
struct ECCLR_BITS { // bits description
|
||||
Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear
|
||||
Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear
|
||||
Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear
|
||||
Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear
|
||||
Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear
|
||||
Uint16 CTROVF:1; // 5 Counter Overflow Status Clear
|
||||
Uint16 CTR_PRD:1; // 6 Period Equal Status Clear
|
||||
Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union ECCLR_REG {
|
||||
Uint16 all;
|
||||
struct ECCLR_BITS bit;
|
||||
};
|
||||
|
||||
struct ECFRC_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt
|
||||
Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt
|
||||
Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt
|
||||
Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt
|
||||
Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt
|
||||
Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt
|
||||
Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt
|
||||
Uint16 rsvd2:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union ECFRC_REG {
|
||||
Uint16 all;
|
||||
struct ECFRC_BITS bit;
|
||||
};
|
||||
|
||||
struct ECAP_REGS {
|
||||
Uint32 TSCTR; // Time-Stamp Counter
|
||||
Uint32 CTRPHS; // Counter Phase Offset Value Register
|
||||
Uint32 CAP1; // Capture 1 Register
|
||||
Uint32 CAP2; // Capture 2 Register
|
||||
Uint32 CAP3; // Capture 3 Register
|
||||
Uint32 CAP4; // Capture 4 Register
|
||||
Uint16 rsvd1[8]; // Reserved
|
||||
union ECCTL1_REG ECCTL1; // Capture Control Register 1
|
||||
union ECCTL2_REG ECCTL2; // Capture Control Register 2
|
||||
union ECEINT_REG ECEINT; // Capture Interrupt Enable Register
|
||||
union ECFLG_REG ECFLG; // Capture Interrupt Flag Register
|
||||
union ECCLR_REG ECCLR; // Capture Interrupt Clear Register
|
||||
union ECFRC_REG ECFRC; // Capture Interrupt Force Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// ECAP External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct ECAP_REGS ECap1Regs;
|
||||
extern volatile struct ECAP_REGS ECap2Regs;
|
||||
extern volatile struct ECAP_REGS ECap3Regs;
|
||||
extern volatile struct ECAP_REGS ECap4Regs;
|
||||
extern volatile struct ECAP_REGS ECap5Regs;
|
||||
extern volatile struct ECAP_REGS ECap6Regs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct ECAP_REGS ECap1Regs;
|
||||
extern volatile struct ECAP_REGS ECap2Regs;
|
||||
extern volatile struct ECAP_REGS ECap3Regs;
|
||||
extern volatile struct ECAP_REGS ECap4Regs;
|
||||
extern volatile struct ECAP_REGS ECap5Regs;
|
||||
extern volatile struct ECAP_REGS ECap6Regs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,300 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_emif.h
|
||||
//
|
||||
// TITLE: Definitions for the EMIF registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_EMIF_H
|
||||
#define F2837xD_EMIF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// EMIF Individual Register Bit Definitions:
|
||||
|
||||
struct RCSR_BITS { // bits description
|
||||
Uint16 MINOR_REVISION:8; // 7:0 Minor Revision.
|
||||
Uint16 MAJOR_REVISION:8; // 15:8 Major Revision.
|
||||
Uint16 MODULE_ID:14; // 29:16 EMIF module ID.
|
||||
Uint16 FR:1; // 30 EMIF is running in full rate or half rate.
|
||||
Uint16 BE:1; // 31 EMIF endian mode.
|
||||
};
|
||||
|
||||
union RCSR_REG {
|
||||
Uint32 all;
|
||||
struct RCSR_BITS bit;
|
||||
};
|
||||
|
||||
struct ASYNC_WCCR_BITS { // bits description
|
||||
Uint16 MAX_EXT_WAIT:8; // 7:0 Maximum Extended Wait cycles.
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:2; // 17:16 Reserved
|
||||
Uint16 rsvd3:2; // 19:18 Reserved
|
||||
Uint16 rsvd4:2; // 21:20 Reserved
|
||||
Uint16 rsvd5:2; // 23:22 Reserved
|
||||
Uint16 rsvd6:4; // 27:24 Reserved
|
||||
Uint16 WP0:1; // 28 Polarity for EMxWAIT.
|
||||
Uint16 rsvd7:1; // 29 Reserved
|
||||
Uint16 rsvd8:1; // 30 Reserved
|
||||
Uint16 rsvd9:1; // 31 Reserved
|
||||
};
|
||||
|
||||
union ASYNC_WCCR_REG {
|
||||
Uint32 all;
|
||||
struct ASYNC_WCCR_BITS bit;
|
||||
};
|
||||
|
||||
struct SDRAM_CR_BITS { // bits description
|
||||
Uint16 PAGESIGE:3; // 2:0 Page Size.
|
||||
Uint16 rsvd1:1; // 3 Reserved
|
||||
Uint16 IBANK:3; // 6:4 Internal Bank setup of SDRAM devices.
|
||||
Uint16 rsvd2:1; // 7 Reserved
|
||||
Uint16 BIT_11_9_LOCK:1; // 8 Bits 11 to 9 are writable only if this bit is set.
|
||||
Uint16 CL:3; // 11:9 CAS Latency.
|
||||
Uint16 rsvd3:1; // 12 Reserved
|
||||
Uint16 rsvd4:1; // 13 Reserved
|
||||
Uint16 NM:1; // 14 Narrow Mode.
|
||||
Uint16 rsvd5:1; // 15 Reserved
|
||||
Uint16 rsvd6:1; // 16 Reserved
|
||||
Uint16 rsvd7:2; // 18:17 Reserved
|
||||
Uint16 rsvd8:1; // 19 Reserved
|
||||
Uint16 rsvd9:3; // 22:20 Reserved
|
||||
Uint16 rsvd10:3; // 25:23 Reserved
|
||||
Uint16 rsvd11:3; // 28:26 Reserved
|
||||
Uint16 PDWR:1; // 29 Perform refreshes during Power Down.
|
||||
Uint16 PD:1; // 30 Power Down.
|
||||
Uint16 SR:1; // 31 Self Refresh.
|
||||
};
|
||||
|
||||
union SDRAM_CR_REG {
|
||||
Uint32 all;
|
||||
struct SDRAM_CR_BITS bit;
|
||||
};
|
||||
|
||||
struct SDRAM_RCR_BITS { // bits description
|
||||
Uint16 REFRESH_RATE:13; // 12:0 Refresh Rate.
|
||||
Uint16 rsvd1:3; // 15:13 Reserved
|
||||
Uint16 rsvd2:3; // 18:16 Reserved
|
||||
Uint16 rsvd3:13; // 31:19 Reserved
|
||||
};
|
||||
|
||||
union SDRAM_RCR_REG {
|
||||
Uint32 all;
|
||||
struct SDRAM_RCR_BITS bit;
|
||||
};
|
||||
|
||||
struct ASYNC_CS2_CR_BITS { // bits description
|
||||
Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size.
|
||||
Uint16 TA:2; // 3:2 Turn Around cycles.
|
||||
Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles.
|
||||
Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles.
|
||||
Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles.
|
||||
Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles.
|
||||
Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles.
|
||||
Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles.
|
||||
Uint16 EW:1; // 30 Extend Wait mode.
|
||||
Uint16 SS:1; // 31 Select Strobe mode.
|
||||
};
|
||||
|
||||
union ASYNC_CS2_CR_REG {
|
||||
Uint32 all;
|
||||
struct ASYNC_CS2_CR_BITS bit;
|
||||
};
|
||||
|
||||
struct ASYNC_CS3_CR_BITS { // bits description
|
||||
Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size.
|
||||
Uint16 TA:2; // 3:2 Turn Around cycles.
|
||||
Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles.
|
||||
Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles.
|
||||
Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles.
|
||||
Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles.
|
||||
Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles.
|
||||
Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles.
|
||||
Uint16 EW:1; // 30 Extend Wait mode.
|
||||
Uint16 SS:1; // 31 Select Strobe mode.
|
||||
};
|
||||
|
||||
union ASYNC_CS3_CR_REG {
|
||||
Uint32 all;
|
||||
struct ASYNC_CS3_CR_BITS bit;
|
||||
};
|
||||
|
||||
struct ASYNC_CS4_CR_BITS { // bits description
|
||||
Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size.
|
||||
Uint16 TA:2; // 3:2 Turn Around cycles.
|
||||
Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles.
|
||||
Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles.
|
||||
Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles.
|
||||
Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles.
|
||||
Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles.
|
||||
Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles.
|
||||
Uint16 EW:1; // 30 Extend Wait mode.
|
||||
Uint16 SS:1; // 31 Select Strobe mode.
|
||||
};
|
||||
|
||||
union ASYNC_CS4_CR_REG {
|
||||
Uint32 all;
|
||||
struct ASYNC_CS4_CR_BITS bit;
|
||||
};
|
||||
|
||||
struct SDRAM_TR_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 Reserved
|
||||
Uint16 T_RRD:3; // 6:4 Activate to Activate timing for different bank.
|
||||
Uint16 rsvd2:1; // 7 Reserved
|
||||
Uint16 T_RC:4; // 11:8 Activate to Activate timing .
|
||||
Uint16 T_RAS:4; // 15:12 Activate to Precharge timing.
|
||||
Uint16 T_WR:3; // 18:16 Last Write to Precharge timing.
|
||||
Uint16 rsvd3:1; // 19 Reserved
|
||||
Uint16 T_RCD:3; // 22:20 Activate to Read/Write timing.
|
||||
Uint16 rsvd4:1; // 23 Reserved
|
||||
Uint16 T_RP:3; // 26:24 Precharge to Activate/Refresh timing.
|
||||
Uint16 T_RFC:5; // 31:27 Refresh/Load Mode to Refresh/Activate timing
|
||||
};
|
||||
|
||||
union SDRAM_TR_REG {
|
||||
Uint32 all;
|
||||
struct SDRAM_TR_BITS bit;
|
||||
};
|
||||
|
||||
struct SDR_EXT_TMNG_BITS { // bits description
|
||||
Uint16 T_XS:5; // 4:0 Self Refresh exit to new command timing.
|
||||
Uint16 rsvd1:11; // 15:5 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union SDR_EXT_TMNG_REG {
|
||||
Uint32 all;
|
||||
struct SDR_EXT_TMNG_BITS bit;
|
||||
};
|
||||
|
||||
struct INT_RAW_BITS { // bits description
|
||||
Uint16 AT:1; // 0 Asynchronous Timeout.
|
||||
Uint16 LT:1; // 1 Line Trap.
|
||||
Uint16 WR:4; // 5:2 Wait Rise.
|
||||
Uint16 rsvd1:10; // 15:6 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union INT_RAW_REG {
|
||||
Uint32 all;
|
||||
struct INT_RAW_BITS bit;
|
||||
};
|
||||
|
||||
struct INT_MSK_BITS { // bits description
|
||||
Uint16 AT_MASKED:1; // 0 Asynchronous Timeout.
|
||||
Uint16 LT_MASKED:1; // 1 Line Trap.
|
||||
Uint16 WR_MASKED:4; // 5:2 Wait Rise.
|
||||
Uint16 rsvd1:10; // 15:6 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union INT_MSK_REG {
|
||||
Uint32 all;
|
||||
struct INT_MSK_BITS bit;
|
||||
};
|
||||
|
||||
struct INT_MSK_SET_BITS { // bits description
|
||||
Uint16 AT_MASK_SET:1; // 0 Asynchronous Timeout.
|
||||
Uint16 LT_MASK_SET:1; // 1 Line Trap.
|
||||
Uint16 WR_MASK_SET:4; // 5:2 Wait Rise.
|
||||
Uint16 rsvd1:10; // 15:6 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union INT_MSK_SET_REG {
|
||||
Uint32 all;
|
||||
struct INT_MSK_SET_BITS bit;
|
||||
};
|
||||
|
||||
struct INT_MSK_CLR_BITS { // bits description
|
||||
Uint16 AT_MASK_CLR:1; // 0 Asynchronous Timeout.
|
||||
Uint16 LT_MASK_CLR:1; // 1 Line Trap.
|
||||
Uint16 WR_MASK_CLR:4; // 5:2 Wait Rise.
|
||||
Uint16 rsvd1:10; // 15:6 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union INT_MSK_CLR_REG {
|
||||
Uint32 all;
|
||||
struct INT_MSK_CLR_BITS bit;
|
||||
};
|
||||
|
||||
struct EMIF_REGS {
|
||||
union RCSR_REG RCSR; // Revision Code and Status Register
|
||||
union ASYNC_WCCR_REG ASYNC_WCCR; // Async Wait Cycle Config Register
|
||||
union SDRAM_CR_REG SDRAM_CR; // SDRAM (EMxCS0n) Config Register
|
||||
union SDRAM_RCR_REG SDRAM_RCR; // SDRAM Refresh Control Register
|
||||
union ASYNC_CS2_CR_REG ASYNC_CS2_CR; // Async 1 (EMxCS2n) Config Register
|
||||
union ASYNC_CS3_CR_REG ASYNC_CS3_CR; // Async 2 (EMxCS3n) Config Register
|
||||
union ASYNC_CS4_CR_REG ASYNC_CS4_CR; // Async 3 (EMxCS4n) Config Register
|
||||
Uint16 rsvd1[2]; // Reserved
|
||||
union SDRAM_TR_REG SDRAM_TR; // SDRAM Timing Register
|
||||
Uint16 rsvd2[6]; // Reserved
|
||||
Uint32 TOTAL_SDRAM_AR; // Total SDRAM Accesses Register
|
||||
Uint32 TOTAL_SDRAM_ACTR; // Total SDRAM Activate Register
|
||||
Uint16 rsvd3[2]; // Reserved
|
||||
union SDR_EXT_TMNG_REG SDR_EXT_TMNG; // SDRAM SR/PD Exit Timing Register
|
||||
union INT_RAW_REG INT_RAW; // Interrupt Raw Register
|
||||
union INT_MSK_REG INT_MSK; // Interrupt Masked Register
|
||||
union INT_MSK_SET_REG INT_MSK_SET; // Interrupt Mask Set Register
|
||||
union INT_MSK_CLR_REG INT_MSK_CLR; // Interrupt Mask Clear Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// EMIF External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct EMIF_REGS Emif1Regs;
|
||||
extern volatile struct EMIF_REGS Emif2Regs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct EMIF_REGS Emif1Regs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,832 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_epwm_xbar.h
|
||||
//
|
||||
// TITLE: Definitions for the EPWM_XBAR registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_EPWM_XBAR_H
|
||||
#define F2837xD_EPWM_XBAR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// EPWM_XBAR Individual Register Bit Definitions:
|
||||
|
||||
struct TRIP4MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP4MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP4MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP4MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP4MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP4MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP5MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP5MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP5MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP5MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP5MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP5MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP7MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP7MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP7MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP7MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP7MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP7MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP8MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP8MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP8MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP8MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP8MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP8MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP9MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP9MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP9MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP9MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP9MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP9MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP10MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP10MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP10MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP10MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP10MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP10MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP11MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP11MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP11MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP11MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP11MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP11MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP12MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP12MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP12MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP12MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP12MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct TRIP12MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP4MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP4MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct TRIP4MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP5MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP5MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct TRIP5MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP7MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP7MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct TRIP7MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP8MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP8MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct TRIP8MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP9MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP9MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct TRIP9MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP10MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP10MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct TRIP10MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP11MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP11MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct TRIP11MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIP12MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR
|
||||
};
|
||||
|
||||
union TRIP12MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct TRIP12MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIPOUTINV_BITS { // bits description
|
||||
Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR
|
||||
Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR
|
||||
Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR
|
||||
Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR
|
||||
Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR
|
||||
Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR
|
||||
Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR
|
||||
Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union TRIPOUTINV_REG {
|
||||
Uint32 all;
|
||||
struct TRIPOUTINV_BITS bit;
|
||||
};
|
||||
|
||||
struct TRIPLOCK_BITS { // bits description
|
||||
Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
Uint16 KEY:16; // 31:16 Write protection KEY
|
||||
};
|
||||
|
||||
union TRIPLOCK_REG {
|
||||
Uint32 all;
|
||||
struct TRIPLOCK_BITS bit;
|
||||
};
|
||||
|
||||
struct EPWM_XBAR_REGS {
|
||||
union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4
|
||||
union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4
|
||||
union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5
|
||||
union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5
|
||||
union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7
|
||||
union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7
|
||||
union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8
|
||||
union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8
|
||||
union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9
|
||||
union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9
|
||||
union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10
|
||||
union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10
|
||||
union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11
|
||||
union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11
|
||||
union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12
|
||||
union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12
|
||||
union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4
|
||||
union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5
|
||||
union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7
|
||||
union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8
|
||||
union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9
|
||||
union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10
|
||||
union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11
|
||||
union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12
|
||||
Uint16 rsvd1[8]; // Reserved
|
||||
union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register
|
||||
Uint16 rsvd2[4]; // Reserved
|
||||
union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// EPWM_XBAR External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,266 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_eqep.h
|
||||
//
|
||||
// TITLE: Definitions for the EQEP registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_EQEP_H
|
||||
#define F2837xD_EQEP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// EQEP Individual Register Bit Definitions:
|
||||
|
||||
struct QDECCTL_BITS { // bits description
|
||||
Uint16 rsvd1:5; // 4:0 Reserved
|
||||
Uint16 QSP:1; // 5 QEPS input polarity
|
||||
Uint16 QIP:1; // 6 QEPI input polarity
|
||||
Uint16 QBP:1; // 7 QEPB input polarity
|
||||
Uint16 QAP:1; // 8 QEPA input polarity
|
||||
Uint16 IGATE:1; // 9 Index pulse gating option
|
||||
Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter
|
||||
Uint16 XCR:1; // 11 External Clock Rate
|
||||
Uint16 SPSEL:1; // 12 Sync output pin selection
|
||||
Uint16 SOEN:1; // 13 Sync output-enable
|
||||
Uint16 QSRC:2; // 15:14 Position-counter source selection
|
||||
};
|
||||
|
||||
union QDECCTL_REG {
|
||||
Uint16 all;
|
||||
struct QDECCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct QEPCTL_BITS { // bits description
|
||||
Uint16 WDE:1; // 0 QEP watchdog enable
|
||||
Uint16 UTE:1; // 1 QEP unit timer enable
|
||||
Uint16 QCLM:1; // 2 QEP capture latch mode
|
||||
Uint16 QPEN:1; // 3 Quadrature postotion counter enable
|
||||
Uint16 IEL:2; // 5:4 Index event latch
|
||||
Uint16 SEL:1; // 6 Strobe event latch
|
||||
Uint16 SWI:1; // 7 Software init position counter
|
||||
Uint16 IEI:2; // 9:8 Index event init of position count
|
||||
Uint16 SEI:2; // 11:10 Strobe event init
|
||||
Uint16 PCRM:2; // 13:12 Postion counter reset
|
||||
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
|
||||
};
|
||||
|
||||
union QEPCTL_REG {
|
||||
Uint16 all;
|
||||
struct QEPCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct QCAPCTL_BITS { // bits description
|
||||
Uint16 UPPS:4; // 3:0 Unit position event prescaler
|
||||
Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler
|
||||
Uint16 rsvd1:8; // 14:7 Reserved
|
||||
Uint16 CEN:1; // 15 Enable eQEP capture
|
||||
};
|
||||
|
||||
union QCAPCTL_REG {
|
||||
Uint16 all;
|
||||
struct QCAPCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct QPOSCTL_BITS { // bits description
|
||||
Uint16 PCSPW:12; // 11:0 Position compare sync pulse width
|
||||
Uint16 PCE:1; // 12 Position compare enable/disable
|
||||
Uint16 PCPOL:1; // 13 Polarity of sync output
|
||||
Uint16 PCLOAD:1; // 14 Position compare of shadow load
|
||||
Uint16 PCSHDW:1; // 15 Position compare of shadow enable
|
||||
};
|
||||
|
||||
union QPOSCTL_REG {
|
||||
Uint16 all;
|
||||
struct QPOSCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct QEINT_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 PCE:1; // 1 Position counter error interrupt enable
|
||||
Uint16 QPE:1; // 2 Quadrature phase error interrupt enable
|
||||
Uint16 QDC:1; // 3 Quadrature direction change interrupt enable
|
||||
Uint16 WTO:1; // 4 Watchdog time out interrupt enable
|
||||
Uint16 PCU:1; // 5 Position counter underflow interrupt enable
|
||||
Uint16 PCO:1; // 6 Position counter overflow interrupt enable
|
||||
Uint16 PCR:1; // 7 Position-compare ready interrupt enable
|
||||
Uint16 PCM:1; // 8 Position-compare match interrupt enable
|
||||
Uint16 SEL:1; // 9 Strobe event latch interrupt enable
|
||||
Uint16 IEL:1; // 10 Index event latch interrupt enable
|
||||
Uint16 UTO:1; // 11 Unit time out interrupt enable
|
||||
Uint16 rsvd2:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union QEINT_REG {
|
||||
Uint16 all;
|
||||
struct QEINT_BITS bit;
|
||||
};
|
||||
|
||||
struct QFLG_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global interrupt status flag
|
||||
Uint16 PCE:1; // 1 Position counter error interrupt flag
|
||||
Uint16 PHE:1; // 2 Quadrature phase error interrupt flag
|
||||
Uint16 QDC:1; // 3 Quadrature direction change interrupt flag
|
||||
Uint16 WTO:1; // 4 Watchdog timeout interrupt flag
|
||||
Uint16 PCU:1; // 5 Position counter underflow interrupt flag
|
||||
Uint16 PCO:1; // 6 Position counter overflow interrupt flag
|
||||
Uint16 PCR:1; // 7 Position-compare ready interrupt flag
|
||||
Uint16 PCM:1; // 8 eQEP compare match event interrupt flag
|
||||
Uint16 SEL:1; // 9 Strobe event latch interrupt flag
|
||||
Uint16 IEL:1; // 10 Index event latch interrupt flag
|
||||
Uint16 UTO:1; // 11 Unit time out interrupt flag
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union QFLG_REG {
|
||||
Uint16 all;
|
||||
struct QFLG_BITS bit;
|
||||
};
|
||||
|
||||
struct QCLR_BITS { // bits description
|
||||
Uint16 INT:1; // 0 Global interrupt clear flag
|
||||
Uint16 PCE:1; // 1 Clear position counter error interrupt flag
|
||||
Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag
|
||||
Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag
|
||||
Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag
|
||||
Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag
|
||||
Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag
|
||||
Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag
|
||||
Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag
|
||||
Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag
|
||||
Uint16 IEL:1; // 10 Clear index event latch interrupt flag
|
||||
Uint16 UTO:1; // 11 Clear unit time out interrupt flag
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union QCLR_REG {
|
||||
Uint16 all;
|
||||
struct QCLR_BITS bit;
|
||||
};
|
||||
|
||||
struct QFRC_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 PCE:1; // 1 Force position counter error interrupt
|
||||
Uint16 PHE:1; // 2 Force quadrature phase error interrupt
|
||||
Uint16 QDC:1; // 3 Force quadrature direction change interrupt
|
||||
Uint16 WTO:1; // 4 Force watchdog time out interrupt
|
||||
Uint16 PCU:1; // 5 Force position counter underflow interrupt
|
||||
Uint16 PCO:1; // 6 Force position counter overflow interrupt
|
||||
Uint16 PCR:1; // 7 Force position-compare ready interrupt
|
||||
Uint16 PCM:1; // 8 Force position-compare match interrupt
|
||||
Uint16 SEL:1; // 9 Force strobe event latch interrupt
|
||||
Uint16 IEL:1; // 10 Force index event latch interrupt
|
||||
Uint16 UTO:1; // 11 Force unit time out interrupt
|
||||
Uint16 rsvd2:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union QFRC_REG {
|
||||
Uint16 all;
|
||||
struct QFRC_BITS bit;
|
||||
};
|
||||
|
||||
struct QEPSTS_BITS { // bits description
|
||||
Uint16 PCEF:1; // 0 Position counter error flag.
|
||||
Uint16 FIMF:1; // 1 First index marker flag
|
||||
Uint16 CDEF:1; // 2 Capture direction error flag
|
||||
Uint16 COEF:1; // 3 Capture overflow error flag
|
||||
Uint16 QDLF:1; // 4 eQEP direction latch flag
|
||||
Uint16 QDF:1; // 5 Quadrature direction flag
|
||||
Uint16 FIDF:1; // 6 The first index marker
|
||||
Uint16 UPEVNT:1; // 7 Unit position event flag
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union QEPSTS_REG {
|
||||
Uint16 all;
|
||||
struct QEPSTS_BITS bit;
|
||||
};
|
||||
|
||||
struct EQEP_REGS {
|
||||
Uint32 QPOSCNT; // Position Counter
|
||||
Uint32 QPOSINIT; // Position Counter Init
|
||||
Uint32 QPOSMAX; // Maximum Position Count
|
||||
Uint32 QPOSCMP; // Position Compare
|
||||
Uint32 QPOSILAT; // Index Position Latch
|
||||
Uint32 QPOSSLAT; // Strobe Position Latch
|
||||
Uint32 QPOSLAT; // Position Latch
|
||||
Uint32 QUTMR; // QEP Unit Timer
|
||||
Uint32 QUPRD; // QEP Unit Period
|
||||
Uint16 QWDTMR; // QEP Watchdog Timer
|
||||
Uint16 QWDPRD; // QEP Watchdog Period
|
||||
union QDECCTL_REG QDECCTL; // Quadrature Decoder Control
|
||||
union QEPCTL_REG QEPCTL; // QEP Control
|
||||
union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control
|
||||
union QPOSCTL_REG QPOSCTL; // Position Compare Control
|
||||
union QEINT_REG QEINT; // QEP Interrupt Control
|
||||
union QFLG_REG QFLG; // QEP Interrupt Flag
|
||||
union QCLR_REG QCLR; // QEP Interrupt Clear
|
||||
union QFRC_REG QFRC; // QEP Interrupt Force
|
||||
union QEPSTS_REG QEPSTS; // QEP Status
|
||||
Uint16 QCTMR; // QEP Capture Timer
|
||||
Uint16 QCPRD; // QEP Capture Period
|
||||
Uint16 QCTMRLAT; // QEP Capture Latch
|
||||
Uint16 QCPRDLAT; // QEP Capture Period Latch
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// EQEP External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct EQEP_REGS EQep1Regs;
|
||||
extern volatile struct EQEP_REGS EQep2Regs;
|
||||
extern volatile struct EQEP_REGS EQep3Regs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct EQEP_REGS EQep1Regs;
|
||||
extern volatile struct EQEP_REGS EQep2Regs;
|
||||
extern volatile struct EQEP_REGS EQep3Regs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,376 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_flash.h
|
||||
//
|
||||
// TITLE: Definitions for the FLASH registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_FLASH_H
|
||||
#define F2837xD_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// FLASH Individual Register Bit Definitions:
|
||||
|
||||
struct FRDCNTL_BITS { // bits description
|
||||
Uint16 rsvd1:8; // 7:0 Reserved
|
||||
Uint16 RWAIT:4; // 11:8 Random Read Waitstate
|
||||
Uint16 rsvd2:4; // 15:12 Reserved
|
||||
Uint16 rsvd3:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union FRDCNTL_REG {
|
||||
Uint32 all;
|
||||
struct FRDCNTL_BITS bit;
|
||||
};
|
||||
|
||||
struct FBAC_BITS { // bits description
|
||||
Uint16 VREADST:8; // 7:0 VREAD Setup Time Count
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union FBAC_REG {
|
||||
Uint32 all;
|
||||
struct FBAC_BITS bit;
|
||||
};
|
||||
|
||||
struct FBFALLBACK_BITS { // bits description
|
||||
Uint16 BNKPWR0:2; // 1:0 Bank Power Mode
|
||||
Uint16 rsvd1:14; // 15:2 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union FBFALLBACK_REG {
|
||||
Uint32 all;
|
||||
struct FBFALLBACK_BITS bit;
|
||||
};
|
||||
|
||||
struct FBPRDY_BITS { // bits description
|
||||
Uint16 BANKRDY:1; // 0 Flash Bank Active Power State
|
||||
Uint16 rsvd1:14; // 14:1 Reserved
|
||||
Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union FBPRDY_REG {
|
||||
Uint32 all;
|
||||
struct FBPRDY_BITS bit;
|
||||
};
|
||||
|
||||
struct FPAC1_BITS { // bits description
|
||||
Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count
|
||||
Uint16 rsvd2:4; // 31:28 Reserved
|
||||
};
|
||||
|
||||
union FPAC1_REG {
|
||||
Uint32 all;
|
||||
struct FPAC1_BITS bit;
|
||||
};
|
||||
|
||||
struct FMSTAT_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 PSUSP:1; // 1 Program Suspend.
|
||||
Uint16 ESUSP:1; // 2 Erase Suspend.
|
||||
Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status
|
||||
Uint16 CSTAT:1; // 4 Command Fail Status
|
||||
Uint16 INVDAT:1; // 5 Invalid Data
|
||||
Uint16 PGM:1; // 6 Program Operation Status
|
||||
Uint16 ERS:1; // 7 Erase Operation Status
|
||||
Uint16 BUSY:1; // 8 Busy Bit
|
||||
Uint16 rsvd2:1; // 9 Reserved
|
||||
Uint16 EV:1; // 10 Erase Verify Status
|
||||
Uint16 rsvd3:1; // 11 Reserved
|
||||
Uint16 PGV:1; // 12 Programming Verify Status
|
||||
Uint16 rsvd4:1; // 13 Reserved
|
||||
Uint16 rsvd5:1; // 14 Reserved
|
||||
Uint16 rsvd6:1; // 15 Reserved
|
||||
Uint16 rsvd7:1; // 16 Reserved
|
||||
Uint16 rsvd8:1; // 17 Reserved
|
||||
Uint16 rsvd9:14; // 31:18 Reserved
|
||||
};
|
||||
|
||||
union FMSTAT_REG {
|
||||
Uint32 all;
|
||||
struct FMSTAT_BITS bit;
|
||||
};
|
||||
|
||||
struct FRD_INTF_CTRL_BITS { // bits description
|
||||
Uint16 PREFETCH_EN:1; // 0 Prefetch Enable
|
||||
Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable
|
||||
Uint16 rsvd1:14; // 15:2 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union FRD_INTF_CTRL_REG {
|
||||
Uint32 all;
|
||||
struct FRD_INTF_CTRL_BITS bit;
|
||||
};
|
||||
|
||||
struct FLASH_CTRL_REGS {
|
||||
union FRDCNTL_REG FRDCNTL; // Flash Read Control Register
|
||||
Uint16 rsvd1[28]; // Reserved
|
||||
union FBAC_REG FBAC; // Flash Bank Access Control Register
|
||||
union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register
|
||||
union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register
|
||||
union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1
|
||||
Uint16 rsvd2[4]; // Reserved
|
||||
union FMSTAT_REG FMSTAT; // Flash Module Status Register
|
||||
Uint16 rsvd3[340]; // Reserved
|
||||
union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register
|
||||
};
|
||||
|
||||
struct ECC_ENABLE_BITS { // bits description
|
||||
Uint16 ENABLE:4; // 3:0 Enable ECC
|
||||
Uint16 rsvd1:12; // 15:4 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union ECC_ENABLE_REG {
|
||||
Uint32 all;
|
||||
struct ECC_ENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct ERR_STATUS_BITS { // bits description
|
||||
Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0
|
||||
Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1
|
||||
Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred
|
||||
Uint16 rsvd1:13; // 15:3 Reserved
|
||||
Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0
|
||||
Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1
|
||||
Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred
|
||||
Uint16 rsvd2:13; // 31:19 Reserved
|
||||
};
|
||||
|
||||
union ERR_STATUS_REG {
|
||||
Uint32 all;
|
||||
struct ERR_STATUS_BITS bit;
|
||||
};
|
||||
|
||||
struct ERR_POS_BITS { // bits description
|
||||
Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits
|
||||
Uint16 rsvd1:2; // 7:6 Reserved
|
||||
Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits
|
||||
Uint16 rsvd2:7; // 15:9 Reserved
|
||||
Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits
|
||||
Uint16 rsvd3:2; // 23:22 Reserved
|
||||
Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits
|
||||
Uint16 rsvd4:7; // 31:25 Reserved
|
||||
};
|
||||
|
||||
union ERR_POS_REG {
|
||||
Uint32 all;
|
||||
struct ERR_POS_BITS bit;
|
||||
};
|
||||
|
||||
struct ERR_STATUS_CLR_BITS { // bits description
|
||||
Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear
|
||||
Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear
|
||||
Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear
|
||||
Uint16 rsvd1:13; // 15:3 Reserved
|
||||
Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear
|
||||
Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear
|
||||
Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear
|
||||
Uint16 rsvd2:13; // 31:19 Reserved
|
||||
};
|
||||
|
||||
union ERR_STATUS_CLR_REG {
|
||||
Uint32 all;
|
||||
struct ERR_STATUS_CLR_BITS bit;
|
||||
};
|
||||
|
||||
struct ERR_CNT_BITS { // bits description
|
||||
Uint16 ERR_CNT:16; // 15:0 Error counter
|
||||
Uint16 rsvd1:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union ERR_CNT_REG {
|
||||
Uint32 all;
|
||||
struct ERR_CNT_BITS bit;
|
||||
};
|
||||
|
||||
struct ERR_THRESHOLD_BITS { // bits description
|
||||
Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold
|
||||
Uint16 rsvd1:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union ERR_THRESHOLD_REG {
|
||||
Uint32 all;
|
||||
struct ERR_THRESHOLD_BITS bit;
|
||||
};
|
||||
|
||||
struct ERR_INTFLG_BITS { // bits description
|
||||
Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag
|
||||
Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag
|
||||
Uint16 rsvd1:14; // 15:2 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union ERR_INTFLG_REG {
|
||||
Uint32 all;
|
||||
struct ERR_INTFLG_BITS bit;
|
||||
};
|
||||
|
||||
struct ERR_INTCLR_BITS { // bits description
|
||||
Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear
|
||||
Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear
|
||||
Uint16 rsvd1:14; // 15:2 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union ERR_INTCLR_REG {
|
||||
Uint32 all;
|
||||
struct ERR_INTCLR_BITS bit;
|
||||
};
|
||||
|
||||
struct FADDR_TEST_BITS { // bits description
|
||||
Uint16 rsvd1:3; // 2:0 Reserved
|
||||
Uint16 ADDRL:13; // 15:3 ECC Address Low
|
||||
Uint16 ADDRH:6; // 21:16 ECC Address High
|
||||
Uint16 rsvd2:10; // 31:22 Reserved
|
||||
};
|
||||
|
||||
union FADDR_TEST_REG {
|
||||
Uint32 all;
|
||||
struct FADDR_TEST_BITS bit;
|
||||
};
|
||||
|
||||
struct FECC_TEST_BITS { // bits description
|
||||
Uint16 ECC:8; // 7:0 ECC Control Bits
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union FECC_TEST_REG {
|
||||
Uint32 all;
|
||||
struct FECC_TEST_BITS bit;
|
||||
};
|
||||
|
||||
struct FECC_CTRL_BITS { // bits description
|
||||
Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic
|
||||
Uint16 ECC_SELECT:1; // 1 ECC Bit Select
|
||||
Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation
|
||||
Uint16 rsvd1:13; // 15:3 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union FECC_CTRL_REG {
|
||||
Uint32 all;
|
||||
struct FECC_CTRL_BITS bit;
|
||||
};
|
||||
|
||||
struct FECC_STATUS_BITS { // bits description
|
||||
Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error
|
||||
Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error
|
||||
Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error
|
||||
Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error
|
||||
Uint16 rsvd1:7; // 15:9 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union FECC_STATUS_REG {
|
||||
Uint32 all;
|
||||
struct FECC_STATUS_BITS bit;
|
||||
};
|
||||
|
||||
struct FLASH_ECC_REGS {
|
||||
union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable
|
||||
Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low
|
||||
Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High
|
||||
Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low
|
||||
Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High
|
||||
union ERR_STATUS_REG ERR_STATUS; // Error Status
|
||||
union ERR_POS_REG ERR_POS; // Error Position
|
||||
union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear
|
||||
union ERR_CNT_REG ERR_CNT; // Error Control
|
||||
union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold
|
||||
union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag
|
||||
union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear
|
||||
Uint32 FDATAH_TEST; // Data High Test
|
||||
Uint32 FDATAL_TEST; // Data Low Test
|
||||
union FADDR_TEST_REG FADDR_TEST; // ECC Test Address
|
||||
union FECC_TEST_REG FECC_TEST; // ECC Test Address
|
||||
union FECC_CTRL_REG FECC_CTRL; // ECC Control
|
||||
Uint32 FOUTH_TEST; // Test Data Out High
|
||||
Uint32 FOUTL_TEST; // Test Data Out Low
|
||||
union FECC_STATUS_REG FECC_STATUS; // ECC Status
|
||||
};
|
||||
|
||||
struct PUMPREQUEST_BITS { // bits description
|
||||
Uint16 PUMP_OWNERSHIP:2; // 1:0 Flash Pump Request Semaphore between CPU1 and CPU2
|
||||
Uint16 rsvd1:14; // 15:2 Reserved
|
||||
Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register
|
||||
};
|
||||
|
||||
union PUMPREQUEST_REG {
|
||||
Uint32 all;
|
||||
struct PUMPREQUEST_BITS bit;
|
||||
};
|
||||
|
||||
struct FLASH_PUMP_SEMAPHORE_REGS {
|
||||
union PUMPREQUEST_REG PUMPREQUEST; // Flash programming semaphore PUMP request register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// FLASH External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs;
|
||||
extern volatile struct FLASH_ECC_REGS Flash0EccRegs;
|
||||
extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs;
|
||||
extern volatile struct FLASH_ECC_REGS Flash0EccRegs;
|
||||
extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,256 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_i2c.h
|
||||
//
|
||||
// TITLE: Definitions for the I2C registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_I2C_H
|
||||
#define F2837xD_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// I2C Individual Register Bit Definitions:
|
||||
|
||||
struct I2COAR_BITS { // bits description
|
||||
Uint16 OAR:10; // 9:0 I2C Own address
|
||||
Uint16 rsvd1:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union I2COAR_REG {
|
||||
Uint16 all;
|
||||
struct I2COAR_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CIER_BITS { // bits description
|
||||
Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable
|
||||
Uint16 NACK:1; // 1 No-acknowledgment interrupt enable
|
||||
Uint16 ARDY:1; // 2 Register-access-ready interrupt enable
|
||||
Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable
|
||||
Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable
|
||||
Uint16 SCD:1; // 5 Stop condition detected interrupt enable
|
||||
Uint16 AAS:1; // 6 Addressed as slave interrupt enable
|
||||
Uint16 rsvd1:9; // 15:7 Reserved
|
||||
};
|
||||
|
||||
union I2CIER_REG {
|
||||
Uint16 all;
|
||||
struct I2CIER_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CSTR_BITS { // bits description
|
||||
Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit
|
||||
Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit.
|
||||
Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit
|
||||
Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit.
|
||||
Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit.
|
||||
Uint16 SCD:1; // 5 Stop condition detected bit.
|
||||
Uint16 rsvd1:2; // 7:6 Reserved
|
||||
Uint16 AD0:1; // 8 Address 0 bits
|
||||
Uint16 AAS:1; // 9 Addressed-as-slave bit
|
||||
Uint16 XSMT:1; // 10 Transmit shift register empty bit.
|
||||
Uint16 RSFULL:1; // 11 Receive shift register full bit.
|
||||
Uint16 BB:1; // 12 Bus busy bit.
|
||||
Uint16 NACKSNT:1; // 13 NACK sent bit.
|
||||
Uint16 SDIR:1; // 14 Slave direction bit
|
||||
Uint16 rsvd2:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union I2CSTR_REG {
|
||||
Uint16 all;
|
||||
struct I2CSTR_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CDRR_BITS { // bits description
|
||||
Uint16 DATA:8; // 7:0 Receive data
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union I2CDRR_REG {
|
||||
Uint16 all;
|
||||
struct I2CDRR_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CSAR_BITS { // bits description
|
||||
Uint16 SAR:10; // 9:0 Slave Address
|
||||
Uint16 rsvd1:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union I2CSAR_REG {
|
||||
Uint16 all;
|
||||
struct I2CSAR_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CDXR_BITS { // bits description
|
||||
Uint16 DATA:8; // 7:0 Transmit data
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union I2CDXR_REG {
|
||||
Uint16 all;
|
||||
struct I2CDXR_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CMDR_BITS { // bits description
|
||||
Uint16 BC:3; // 2:0 Bit count bits.
|
||||
Uint16 FDF:1; // 3 Free Data Format
|
||||
Uint16 STB:1; // 4 START Byte Mode
|
||||
Uint16 IRS:1; // 5 I2C Module Reset
|
||||
Uint16 DLB:1; // 6 Digital Loopback Mode
|
||||
Uint16 RM:1; // 7 Repeat Mode
|
||||
Uint16 XA:1; // 8 Expanded Address Mode
|
||||
Uint16 TRX:1; // 9 Transmitter Mode
|
||||
Uint16 MST:1; // 10 Master Mode
|
||||
Uint16 STP:1; // 11 STOP Condition
|
||||
Uint16 rsvd1:1; // 12 Reserved
|
||||
Uint16 STT:1; // 13 START condition bit
|
||||
Uint16 FREE:1; // 14 Debug Action
|
||||
Uint16 NACKMOD:1; // 15 NACK mode bit
|
||||
};
|
||||
|
||||
union I2CMDR_REG {
|
||||
Uint16 all;
|
||||
struct I2CMDR_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CISRC_BITS { // bits description
|
||||
Uint16 INTCODE:3; // 2:0 Interrupt code bits.
|
||||
Uint16 rsvd1:5; // 7:3 Reserved
|
||||
Uint16 WRITE_ZEROS:4; // 11:8 Always write all 0s to this field
|
||||
Uint16 rsvd2:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union I2CISRC_REG {
|
||||
Uint16 all;
|
||||
struct I2CISRC_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CEMDR_BITS { // bits description
|
||||
Uint16 BC:1; // 0 Backwards compatibility mode
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
};
|
||||
|
||||
union I2CEMDR_REG {
|
||||
Uint16 all;
|
||||
struct I2CEMDR_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CPSC_BITS { // bits description
|
||||
Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union I2CPSC_REG {
|
||||
Uint16 all;
|
||||
struct I2CPSC_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CFFTX_BITS { // bits description
|
||||
Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level
|
||||
Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable
|
||||
Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear
|
||||
Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag
|
||||
Uint16 TXFFST:5; // 12:8 Transmit FIFO Status
|
||||
Uint16 TXFFRST:1; // 13 Transmit FIFO Reset
|
||||
Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union I2CFFTX_REG {
|
||||
Uint16 all;
|
||||
struct I2CFFTX_BITS bit;
|
||||
};
|
||||
|
||||
struct I2CFFRX_BITS { // bits description
|
||||
Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level
|
||||
Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable
|
||||
Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear
|
||||
Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag
|
||||
Uint16 RXFFST:5; // 12:8 Receive FIFO Status
|
||||
Uint16 RXFFRST:1; // 13 Receive FIFO Reset
|
||||
Uint16 rsvd1:2; // 15:14 Reserved
|
||||
};
|
||||
|
||||
union I2CFFRX_REG {
|
||||
Uint16 all;
|
||||
struct I2CFFRX_BITS bit;
|
||||
};
|
||||
|
||||
struct I2C_REGS {
|
||||
union I2COAR_REG I2COAR; // I2C Own address
|
||||
union I2CIER_REG I2CIER; // I2C Interrupt Enable
|
||||
union I2CSTR_REG I2CSTR; // I2C Status
|
||||
Uint16 I2CCLKL; // I2C Clock low-time divider
|
||||
Uint16 I2CCLKH; // I2C Clock high-time divider
|
||||
Uint16 I2CCNT; // I2C Data count
|
||||
union I2CDRR_REG I2CDRR; // I2C Data receive
|
||||
union I2CSAR_REG I2CSAR; // I2C Slave address
|
||||
union I2CDXR_REG I2CDXR; // I2C Data Transmit
|
||||
union I2CMDR_REG I2CMDR; // I2C Mode
|
||||
union I2CISRC_REG I2CISRC; // I2C Interrupt Source
|
||||
union I2CEMDR_REG I2CEMDR; // I2C Extended Mode
|
||||
union I2CPSC_REG I2CPSC; // I2C Prescaler
|
||||
Uint16 rsvd1[19]; // Reserved
|
||||
union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit
|
||||
union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// I2C External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct I2C_REGS I2caRegs;
|
||||
extern volatile struct I2C_REGS I2cbRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct I2C_REGS I2caRegs;
|
||||
extern volatile struct I2C_REGS I2cbRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,112 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_input_xbar.h
|
||||
//
|
||||
// TITLE: Definitions for the INPUT_XBAR registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_INPUT_XBAR_H
|
||||
#define F2837xD_INPUT_XBAR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// INPUT_XBAR Individual Register Bit Definitions:
|
||||
|
||||
struct INPUTSELECTLOCK_BITS { // bits description
|
||||
Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SELECT Register
|
||||
Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SELECT Register
|
||||
Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SELECT Register
|
||||
Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SELECT Register
|
||||
Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SELECT Register
|
||||
Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT6SELECT Register
|
||||
Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT7SELECT Register
|
||||
Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT8SELECT Register
|
||||
Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT9SELECT Register
|
||||
Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT10SELECT Register
|
||||
Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SELECT Register
|
||||
Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SELECT Register
|
||||
Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SELECT Register
|
||||
Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SELECT Register
|
||||
Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SELECT Register
|
||||
Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SELECT Register
|
||||
Uint16 rsvd1:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union INPUTSELECTLOCK_REG {
|
||||
Uint32 all;
|
||||
struct INPUTSELECTLOCK_BITS bit;
|
||||
};
|
||||
|
||||
struct INPUT_XBAR_REGS {
|
||||
Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x)
|
||||
Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x)
|
||||
Uint16 rsvd1[16]; // Reserved
|
||||
union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// INPUT_XBAR External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct INPUT_XBAR_REGS InputXbarRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,313 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_ipc.h
|
||||
//
|
||||
// TITLE: Definitions for the IPC registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_IPC_H
|
||||
#define F2837xD_IPC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// IPC Individual Register Bit Definitions:
|
||||
|
||||
struct IPCACK_BITS { // bits description
|
||||
Uint16 IPC0:1; // 0 Local IPC Flag 0 Acknowledgement
|
||||
Uint16 IPC1:1; // 1 Local IPC Flag 1 Acknowledgement
|
||||
Uint16 IPC2:1; // 2 Local IPC Flag 2 Acknowledgement
|
||||
Uint16 IPC3:1; // 3 Local IPC Flag 3 Acknowledgement
|
||||
Uint16 IPC4:1; // 4 Local IPC Flag 4 Acknowledgement
|
||||
Uint16 IPC5:1; // 5 Local IPC Flag 5 Acknowledgement
|
||||
Uint16 IPC6:1; // 6 Local IPC Flag 6 Acknowledgement
|
||||
Uint16 IPC7:1; // 7 Local IPC Flag 7 Acknowledgement
|
||||
Uint16 IPC8:1; // 8 Local IPC Flag 8 Acknowledgement
|
||||
Uint16 IPC9:1; // 9 Local IPC Flag 9 Acknowledgement
|
||||
Uint16 IPC10:1; // 10 Local IPC Flag 10 Acknowledgement
|
||||
Uint16 IPC11:1; // 11 Local IPC Flag 11 Acknowledgement
|
||||
Uint16 IPC12:1; // 12 Local IPC Flag 12 Acknowledgement
|
||||
Uint16 IPC13:1; // 13 Local IPC Flag 13 Acknowledgement
|
||||
Uint16 IPC14:1; // 14 Local IPC Flag 14 Acknowledgement
|
||||
Uint16 IPC15:1; // 15 Local IPC Flag 15 Acknowledgement
|
||||
Uint16 IPC16:1; // 16 Local IPC Flag 16 Acknowledgement
|
||||
Uint16 IPC17:1; // 17 Local IPC Flag 17 Acknowledgement
|
||||
Uint16 IPC18:1; // 18 Local IPC Flag 18 Acknowledgement
|
||||
Uint16 IPC19:1; // 19 Local IPC Flag 19 Acknowledgement
|
||||
Uint16 IPC20:1; // 20 Local IPC Flag 20 Acknowledgement
|
||||
Uint16 IPC21:1; // 21 Local IPC Flag 21 Acknowledgement
|
||||
Uint16 IPC22:1; // 22 Local IPC Flag 22 Acknowledgement
|
||||
Uint16 IPC23:1; // 23 Local IPC Flag 23 Acknowledgement
|
||||
Uint16 IPC24:1; // 24 Local IPC Flag 24 Acknowledgement
|
||||
Uint16 IPC25:1; // 25 Local IPC Flag 25 Acknowledgement
|
||||
Uint16 IPC26:1; // 26 Local IPC Flag 26 Acknowledgement
|
||||
Uint16 IPC27:1; // 27 Local IPC Flag 27 Acknowledgement
|
||||
Uint16 IPC28:1; // 28 Local IPC Flag 28 Acknowledgement
|
||||
Uint16 IPC29:1; // 29 Local IPC Flag 29 Acknowledgement
|
||||
Uint16 IPC30:1; // 30 Local IPC Flag 30 Acknowledgement
|
||||
Uint16 IPC31:1; // 31 Local IPC Flag 31 Acknowledgement
|
||||
};
|
||||
|
||||
union IPCACK_REG {
|
||||
Uint32 all;
|
||||
struct IPCACK_BITS bit;
|
||||
};
|
||||
|
||||
struct IPCSTS_BITS { // bits description
|
||||
Uint16 IPC0:1; // 0 Local IPC Flag 0 Status
|
||||
Uint16 IPC1:1; // 1 Local IPC Flag 1 Status
|
||||
Uint16 IPC2:1; // 2 Local IPC Flag 2 Status
|
||||
Uint16 IPC3:1; // 3 Local IPC Flag 3 Status
|
||||
Uint16 IPC4:1; // 4 Local IPC Flag 4 Status
|
||||
Uint16 IPC5:1; // 5 Local IPC Flag 5 Status
|
||||
Uint16 IPC6:1; // 6 Local IPC Flag 6 Status
|
||||
Uint16 IPC7:1; // 7 Local IPC Flag 7 Status
|
||||
Uint16 IPC8:1; // 8 Local IPC Flag 8 Status
|
||||
Uint16 IPC9:1; // 9 Local IPC Flag 9 Status
|
||||
Uint16 IPC10:1; // 10 Local IPC Flag 10 Status
|
||||
Uint16 IPC11:1; // 11 Local IPC Flag 11 Status
|
||||
Uint16 IPC12:1; // 12 Local IPC Flag 12 Status
|
||||
Uint16 IPC13:1; // 13 Local IPC Flag 13 Status
|
||||
Uint16 IPC14:1; // 14 Local IPC Flag 14 Status
|
||||
Uint16 IPC15:1; // 15 Local IPC Flag 15 Status
|
||||
Uint16 IPC16:1; // 16 Local IPC Flag 16 Status
|
||||
Uint16 IPC17:1; // 17 Local IPC Flag 17 Status
|
||||
Uint16 IPC18:1; // 18 Local IPC Flag 18 Status
|
||||
Uint16 IPC19:1; // 19 Local IPC Flag 19 Status
|
||||
Uint16 IPC20:1; // 20 Local IPC Flag 20 Status
|
||||
Uint16 IPC21:1; // 21 Local IPC Flag 21 Status
|
||||
Uint16 IPC22:1; // 22 Local IPC Flag 22 Status
|
||||
Uint16 IPC23:1; // 23 Local IPC Flag 23 Status
|
||||
Uint16 IPC24:1; // 24 Local IPC Flag 24 Status
|
||||
Uint16 IPC25:1; // 25 Local IPC Flag 25 Status
|
||||
Uint16 IPC26:1; // 26 Local IPC Flag 26 Status
|
||||
Uint16 IPC27:1; // 27 Local IPC Flag 27 Status
|
||||
Uint16 IPC28:1; // 28 Local IPC Flag 28 Status
|
||||
Uint16 IPC29:1; // 29 Local IPC Flag 29 Status
|
||||
Uint16 IPC30:1; // 30 Local IPC Flag 30 Status
|
||||
Uint16 IPC31:1; // 31 Local IPC Flag 31 Status
|
||||
};
|
||||
|
||||
union IPCSTS_REG {
|
||||
Uint32 all;
|
||||
struct IPCSTS_BITS bit;
|
||||
};
|
||||
|
||||
struct IPCSET_BITS { // bits description
|
||||
Uint16 IPC0:1; // 0 Set Remote IPC0 Flag
|
||||
Uint16 IPC1:1; // 1 Set Remote IPC1 Flag
|
||||
Uint16 IPC2:1; // 2 Set Remote IPC2 Flag
|
||||
Uint16 IPC3:1; // 3 Set Remote IPC3 Flag
|
||||
Uint16 IPC4:1; // 4 Set Remote IPC4 Flag
|
||||
Uint16 IPC5:1; // 5 Set Remote IPC5 Flag
|
||||
Uint16 IPC6:1; // 6 Set Remote IPC6 Flag
|
||||
Uint16 IPC7:1; // 7 Set Remote IPC7 Flag
|
||||
Uint16 IPC8:1; // 8 Set Remote IPC8 Flag
|
||||
Uint16 IPC9:1; // 9 Set Remote IPC9 Flag
|
||||
Uint16 IPC10:1; // 10 Set Remote IPC10 Flag
|
||||
Uint16 IPC11:1; // 11 Set Remote IPC11 Flag
|
||||
Uint16 IPC12:1; // 12 Set Remote IPC12 Flag
|
||||
Uint16 IPC13:1; // 13 Set Remote IPC13 Flag
|
||||
Uint16 IPC14:1; // 14 Set Remote IPC14 Flag
|
||||
Uint16 IPC15:1; // 15 Set Remote IPC15 Flag
|
||||
Uint16 IPC16:1; // 16 Set Remote IPC16 Flag
|
||||
Uint16 IPC17:1; // 17 Set Remote IPC17 Flag
|
||||
Uint16 IPC18:1; // 18 Set Remote IPC18 Flag
|
||||
Uint16 IPC19:1; // 19 Set Remote IPC19 Flag
|
||||
Uint16 IPC20:1; // 20 Set Remote IPC20 Flag
|
||||
Uint16 IPC21:1; // 21 Set Remote IPC21 Flag
|
||||
Uint16 IPC22:1; // 22 Set Remote IPC22 Flag
|
||||
Uint16 IPC23:1; // 23 Set Remote IPC23 Flag
|
||||
Uint16 IPC24:1; // 24 Set Remote IPC24 Flag
|
||||
Uint16 IPC25:1; // 25 Set Remote IPC25 Flag
|
||||
Uint16 IPC26:1; // 26 Set Remote IPC26 Flag
|
||||
Uint16 IPC27:1; // 27 Set Remote IPC27 Flag
|
||||
Uint16 IPC28:1; // 28 Set Remote IPC28 Flag
|
||||
Uint16 IPC29:1; // 29 Set Remote IPC29 Flag
|
||||
Uint16 IPC30:1; // 30 Set Remote IPC30 Flag
|
||||
Uint16 IPC31:1; // 31 Set Remote IPC31 Flag
|
||||
};
|
||||
|
||||
union IPCSET_REG {
|
||||
Uint32 all;
|
||||
struct IPCSET_BITS bit;
|
||||
};
|
||||
|
||||
struct IPCCLR_BITS { // bits description
|
||||
Uint16 IPC0:1; // 0 Clear Remote IPC0 Flag
|
||||
Uint16 IPC1:1; // 1 Clear Remote IPC1 Flag
|
||||
Uint16 IPC2:1; // 2 Clear Remote IPC2 Flag
|
||||
Uint16 IPC3:1; // 3 Clear Remote IPC3 Flag
|
||||
Uint16 IPC4:1; // 4 Clear Remote IPC4 Flag
|
||||
Uint16 IPC5:1; // 5 Clear Remote IPC5 Flag
|
||||
Uint16 IPC6:1; // 6 Clear Remote IPC6 Flag
|
||||
Uint16 IPC7:1; // 7 Clear Remote IPC7 Flag
|
||||
Uint16 IPC8:1; // 8 Clear Remote IPC8 Flag
|
||||
Uint16 IPC9:1; // 9 Clear Remote IPC9 Flag
|
||||
Uint16 IPC10:1; // 10 Clear Remote IPC10 Flag
|
||||
Uint16 IPC11:1; // 11 Clear Remote IPC11 Flag
|
||||
Uint16 IPC12:1; // 12 Clear Remote IPC12 Flag
|
||||
Uint16 IPC13:1; // 13 Clear Remote IPC13 Flag
|
||||
Uint16 IPC14:1; // 14 Clear Remote IPC14 Flag
|
||||
Uint16 IPC15:1; // 15 Clear Remote IPC15 Flag
|
||||
Uint16 IPC16:1; // 16 Clear Remote IPC16 Flag
|
||||
Uint16 IPC17:1; // 17 Clear Remote IPC17 Flag
|
||||
Uint16 IPC18:1; // 18 Clear Remote IPC18 Flag
|
||||
Uint16 IPC19:1; // 19 Clear Remote IPC19 Flag
|
||||
Uint16 IPC20:1; // 20 Clear Remote IPC20 Flag
|
||||
Uint16 IPC21:1; // 21 Clear Remote IPC21 Flag
|
||||
Uint16 IPC22:1; // 22 Clear Remote IPC22 Flag
|
||||
Uint16 IPC23:1; // 23 Clear Remote IPC23 Flag
|
||||
Uint16 IPC24:1; // 24 Clear Remote IPC24 Flag
|
||||
Uint16 IPC25:1; // 25 Clear Remote IPC25 Flag
|
||||
Uint16 IPC26:1; // 26 Clear Remote IPC26 Flag
|
||||
Uint16 IPC27:1; // 27 Clear Remote IPC27 Flag
|
||||
Uint16 IPC28:1; // 28 Clear Remote IPC28 Flag
|
||||
Uint16 IPC29:1; // 29 Clear Remote IPC29 Flag
|
||||
Uint16 IPC30:1; // 30 Clear Remote IPC30 Flag
|
||||
Uint16 IPC31:1; // 31 Clear Remote IPC31 Flag
|
||||
};
|
||||
|
||||
union IPCCLR_REG {
|
||||
Uint32 all;
|
||||
struct IPCCLR_BITS bit;
|
||||
};
|
||||
|
||||
struct IPCFLG_BITS { // bits description
|
||||
Uint16 IPC0:1; // 0 Remote IPC0 Flag Status
|
||||
Uint16 IPC1:1; // 1 Remote IPC1 Flag Status
|
||||
Uint16 IPC2:1; // 2 Remote IPC2 Flag Status
|
||||
Uint16 IPC3:1; // 3 Remote IPC3 Flag Status
|
||||
Uint16 IPC4:1; // 4 Remote IPC4 Flag Status
|
||||
Uint16 IPC5:1; // 5 Remote IPC5 Flag Status
|
||||
Uint16 IPC6:1; // 6 Remote IPC6 Flag Status
|
||||
Uint16 IPC7:1; // 7 Remote IPC7 Flag Status
|
||||
Uint16 IPC8:1; // 8 Remote IPC8 Flag Status
|
||||
Uint16 IPC9:1; // 9 Remote IPC9 Flag Status
|
||||
Uint16 IPC10:1; // 10 Remote IPC10 Flag Status
|
||||
Uint16 IPC11:1; // 11 Remote IPC11 Flag Status
|
||||
Uint16 IPC12:1; // 12 Remote IPC12 Flag Status
|
||||
Uint16 IPC13:1; // 13 Remote IPC13 Flag Status
|
||||
Uint16 IPC14:1; // 14 Remote IPC14 Flag Status
|
||||
Uint16 IPC15:1; // 15 Remote IPC15 Flag Status
|
||||
Uint16 IPC16:1; // 16 Remote IPC16 Flag Status
|
||||
Uint16 IPC17:1; // 17 Remote IPC17 Flag Status
|
||||
Uint16 IPC18:1; // 18 Remote IPC18 Flag Status
|
||||
Uint16 IPC19:1; // 19 Remote IPC19 Flag Status
|
||||
Uint16 IPC20:1; // 20 Remote IPC20 Flag Status
|
||||
Uint16 IPC21:1; // 21 Remote IPC21 Flag Status
|
||||
Uint16 IPC22:1; // 22 Remote IPC22 Flag Status
|
||||
Uint16 IPC23:1; // 23 Remote IPC23 Flag Status
|
||||
Uint16 IPC24:1; // 24 Remote IPC24 Flag Status
|
||||
Uint16 IPC25:1; // 25 Remote IPC25 Flag Status
|
||||
Uint16 IPC26:1; // 26 Remote IPC26 Flag Status
|
||||
Uint16 IPC27:1; // 27 Remote IPC27 Flag Status
|
||||
Uint16 IPC28:1; // 28 Remote IPC28 Flag Status
|
||||
Uint16 IPC29:1; // 29 Remote IPC29 Flag Status
|
||||
Uint16 IPC30:1; // 30 Remote IPC30 Flag Status
|
||||
Uint16 IPC31:1; // 31 Remote IPC31 Flag Status
|
||||
};
|
||||
|
||||
union IPCFLG_REG {
|
||||
Uint32 all;
|
||||
struct IPCFLG_BITS bit;
|
||||
};
|
||||
|
||||
struct IPC_REGS_CPU1 {
|
||||
union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register
|
||||
union IPCSTS_REG IPCSTS; // IPC incoming flag status register
|
||||
union IPCSET_REG IPCSET; // IPC remote flag set register
|
||||
union IPCCLR_REG IPCCLR; // IPC remote flag clear register
|
||||
union IPCFLG_REG IPCFLG; // IPC remote flag status register
|
||||
Uint16 rsvd1[2]; // Reserved
|
||||
Uint32 IPCCOUNTERL; // IPC Counter Low Register
|
||||
Uint32 IPCCOUNTERH; // IPC Counter High Register
|
||||
Uint32 IPCSENDCOM; // Local to Remote IPC Command Register
|
||||
Uint32 IPCSENDADDR; // Local to Remote IPC Address Register
|
||||
Uint32 IPCSENDDATA; // Local to Remote IPC Data Register
|
||||
Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register
|
||||
Uint32 IPCRECVCOM; // Remote to Local IPC Command Register
|
||||
Uint32 IPCRECVADDR; // Remote to Local IPC Address Register
|
||||
Uint32 IPCRECVDATA; // Remote to Local IPC Data Register
|
||||
Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register
|
||||
Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register
|
||||
Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register
|
||||
};
|
||||
|
||||
struct IPC_REGS_CPU2 {
|
||||
union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register
|
||||
union IPCSTS_REG IPCSTS; // IPC incoming flag status register
|
||||
union IPCSET_REG IPCSET; // IPC remote flag set register
|
||||
union IPCCLR_REG IPCCLR; // IPC remote flag clear register
|
||||
union IPCFLG_REG IPCFLG; // IPC remote flag status register
|
||||
Uint16 rsvd1[2]; // Reserved
|
||||
Uint32 IPCCOUNTERL; // IPC Counter Low Register
|
||||
Uint32 IPCCOUNTERH; // IPC Counter High Register
|
||||
Uint32 IPCRECVCOM; // Remote to Local IPC Command Register
|
||||
Uint32 IPCRECVADDR; // Remote to Local IPC Address Register
|
||||
Uint32 IPCRECVDATA; // Remote to Local IPC Data Register
|
||||
Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register
|
||||
Uint32 IPCSENDCOM; // Local to Remote IPC Command Register
|
||||
Uint32 IPCSENDADDR; // Local to Remote IPC Address Register
|
||||
Uint32 IPCSENDDATA; // Local to Remote IPC Data Register
|
||||
Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register
|
||||
Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register
|
||||
Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// IPC External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct IPC_REGS_CPU1 IpcRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct IPC_REGS_CPU2 IpcRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,323 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_mcbsp.h
|
||||
//
|
||||
// TITLE: Definitions for the MCBSP registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_MCBSP_H
|
||||
#define F2837xD_MCBSP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// MCBSP Individual Register Bit Definitions:
|
||||
|
||||
struct DRR2_BITS { // bits description
|
||||
Uint16 HWLB:8; // 7:0 High word low byte
|
||||
Uint16 HWHB:8; // 15:8 High word high byte
|
||||
};
|
||||
|
||||
union DRR2_REG {
|
||||
Uint16 all;
|
||||
struct DRR2_BITS bit;
|
||||
};
|
||||
|
||||
struct DRR1_BITS { // bits description
|
||||
Uint16 LWLB:8; // 7:0 Low word low byte
|
||||
Uint16 LWHB:8; // 15:8 Low word high byte
|
||||
};
|
||||
|
||||
union DRR1_REG {
|
||||
Uint16 all;
|
||||
struct DRR1_BITS bit;
|
||||
};
|
||||
|
||||
struct DXR2_BITS { // bits description
|
||||
Uint16 HWLB:8; // 7:0 High word low byte
|
||||
Uint16 HWHB:8; // 15:8 High word high byte
|
||||
};
|
||||
|
||||
union DXR2_REG {
|
||||
Uint16 all;
|
||||
struct DXR2_BITS bit;
|
||||
};
|
||||
|
||||
struct DXR1_BITS { // bits description
|
||||
Uint16 LWLB:8; // 7:0 Low word low byte
|
||||
Uint16 LWHB:8; // 15:8 Low word high byte
|
||||
};
|
||||
|
||||
union DXR1_REG {
|
||||
Uint16 all;
|
||||
struct DXR1_BITS bit;
|
||||
};
|
||||
|
||||
struct SPCR2_BITS { // bits description
|
||||
Uint16 XRST:1; // 0 Transmitter reset
|
||||
Uint16 XRDY:1; // 1 Transmitter ready
|
||||
Uint16 XEMPTY:1; // 2 Transmitter empty
|
||||
Uint16 XSYNCERR:1; // 3 Transmit sync error INT flag
|
||||
Uint16 XINTM:2; // 5:4 Transmit Interupt mode bits
|
||||
Uint16 GRST:1; // 6 Sample rate generator reset
|
||||
Uint16 FRST:1; // 7 Frame sync logic reset
|
||||
Uint16 SOFT:1; // 8 SOFT bit
|
||||
Uint16 FREE:1; // 9 FREE bit
|
||||
Uint16 rsvd1:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union SPCR2_REG {
|
||||
Uint16 all;
|
||||
struct SPCR2_BITS bit;
|
||||
};
|
||||
|
||||
struct SPCR1_BITS { // bits description
|
||||
Uint16 RRST:1; // 0 Receiver reset
|
||||
Uint16 RRDY:1; // 1 Receiver ready
|
||||
Uint16 RFULL:1; // 2 Receiver full
|
||||
Uint16 RSYNCERR:1; // 3 Receive sync error INT flag
|
||||
Uint16 RINTM:2; // 5:4 Receive Interupt mode bits
|
||||
Uint16 rsvd1:1; // 6 Reserved
|
||||
Uint16 DXENA:1; // 7 DX delay enable
|
||||
Uint16 rsvd2:3; // 10:8 Reserved
|
||||
Uint16 CLKSTP:2; // 12:11 Clock stop mode
|
||||
Uint16 RJUST:2; // 14:13 Rx sign extension and justification mode
|
||||
Uint16 DLB:1; // 15 Digital loopback
|
||||
};
|
||||
|
||||
union SPCR1_REG {
|
||||
Uint16 all;
|
||||
struct SPCR1_BITS bit;
|
||||
};
|
||||
|
||||
struct RCR2_BITS { // bits description
|
||||
Uint16 RDATDLY:2; // 1:0 Receive data delay
|
||||
Uint16 RFIG:1; // 2 Receive frame sync ignore
|
||||
Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
|
||||
Uint16 RWDLEN2:3; // 7:5 Receive word length 2
|
||||
Uint16 RFRLEN2:7; // 14:8 Receive Frame length 2
|
||||
Uint16 RPHASE:1; // 15 Receive Phase
|
||||
};
|
||||
|
||||
union RCR2_REG {
|
||||
Uint16 all;
|
||||
struct RCR2_BITS bit;
|
||||
};
|
||||
|
||||
struct RCR1_BITS { // bits description
|
||||
Uint16 rsvd1:5; // 4:0 Reserved
|
||||
Uint16 RWDLEN1:3; // 7:5 Receive word length 1
|
||||
Uint16 RFRLEN1:7; // 14:8 Receive Frame length 1
|
||||
Uint16 rsvd2:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union RCR1_REG {
|
||||
Uint16 all;
|
||||
struct RCR1_BITS bit;
|
||||
};
|
||||
|
||||
struct XCR2_BITS { // bits description
|
||||
Uint16 XDATDLY:2; // 1:0 Transmit data delay
|
||||
Uint16 XFIG:1; // 2 Transmit frame sync ignore
|
||||
Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
|
||||
Uint16 XWDLEN2:3; // 7:5 Transmit word length 2
|
||||
Uint16 XFRLEN2:7; // 14:8 Transmit Frame length 2
|
||||
Uint16 XPHASE:1; // 15 Transmit Phase
|
||||
};
|
||||
|
||||
union XCR2_REG {
|
||||
Uint16 all;
|
||||
struct XCR2_BITS bit;
|
||||
};
|
||||
|
||||
struct XCR1_BITS { // bits description
|
||||
Uint16 rsvd1:5; // 4:0 Reserved
|
||||
Uint16 XWDLEN1:3; // 7:5 Transmit word length 1
|
||||
Uint16 XFRLEN1:7; // 14:8 Transmit Frame length 1
|
||||
Uint16 rsvd2:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union XCR1_REG {
|
||||
Uint16 all;
|
||||
struct XCR1_BITS bit;
|
||||
};
|
||||
|
||||
struct SRGR2_BITS { // bits description
|
||||
Uint16 FPER:12; // 11:0 Frame-sync period
|
||||
Uint16 FSGM:1; // 12 Frame sync generator mode
|
||||
Uint16 CLKSM:1; // 13 Sample rate generator mode
|
||||
Uint16 rsvd1:1; // 14 Reserved
|
||||
Uint16 GSYNC:1; // 15 CLKG sync
|
||||
};
|
||||
|
||||
union SRGR2_REG {
|
||||
Uint16 all;
|
||||
struct SRGR2_BITS bit;
|
||||
};
|
||||
|
||||
struct SRGR1_BITS { // bits description
|
||||
Uint16 CLKGDV:8; // 7:0 CLKG divider
|
||||
Uint16 FWID:8; // 15:8 Frame width
|
||||
};
|
||||
|
||||
union SRGR1_REG {
|
||||
Uint16 all;
|
||||
struct SRGR1_BITS bit;
|
||||
};
|
||||
|
||||
struct MCR2_BITS { // bits description
|
||||
Uint16 XMCM:2; // 1:0 Transmit data delay
|
||||
Uint16 XCBLK:3; // 4:2 Transmit frame sync ignore
|
||||
Uint16 XPABLK:2; // 6:5 Transmit Companding Mode selects
|
||||
Uint16 XPBBLK:2; // 8:7 Transmit word length 2
|
||||
Uint16 XMCME:1; // 9 Transmit Frame length 2
|
||||
Uint16 rsvd1:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union MCR2_REG {
|
||||
Uint16 all;
|
||||
struct MCR2_BITS bit;
|
||||
};
|
||||
|
||||
struct MCR1_BITS { // bits description
|
||||
Uint16 RMCM:1; // 0 Receive multichannel mode
|
||||
Uint16 rsvd1:1; // 1 Reserved
|
||||
Uint16 RCBLK:3; // 4:2 eceive current block
|
||||
Uint16 RPABLK:2; // 6:5 Receive partition A Block
|
||||
Uint16 RPBBLK:2; // 8:7 Receive partition B Block
|
||||
Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
|
||||
Uint16 rsvd2:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union MCR1_REG {
|
||||
Uint16 all;
|
||||
struct MCR1_BITS bit;
|
||||
};
|
||||
|
||||
struct PCR_BITS { // bits description
|
||||
Uint16 CLKRP:1; // 0 Receive Clock polarity
|
||||
Uint16 CLKXP:1; // 1 Transmit clock polarity
|
||||
Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
|
||||
Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
|
||||
Uint16 rsvd1:1; // 4 Reserved
|
||||
Uint16 rsvd2:1; // 5 Reserved
|
||||
Uint16 rsvd3:1; // 6 Reserved
|
||||
Uint16 SCLKME:1; // 7 Sample clock mode selection
|
||||
Uint16 CLKRM:1; // 8 Receiver Clock Mode
|
||||
Uint16 CLKXM:1; // 9 Transmit Clock Mode.
|
||||
Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
|
||||
Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
|
||||
Uint16 rsvd4:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union PCR_REG {
|
||||
Uint16 all;
|
||||
struct PCR_BITS bit;
|
||||
};
|
||||
|
||||
struct MFFINT_BITS { // bits description
|
||||
Uint16 XINT:1; // 0 Enable for Receive Interrupt
|
||||
Uint16 rsvd1:1; // 1 Reserved
|
||||
Uint16 RINT:1; // 2 Enable for transmit Interrupt
|
||||
Uint16 rsvd2:13; // 15:3 Reserved
|
||||
};
|
||||
|
||||
union MFFINT_REG {
|
||||
Uint16 all;
|
||||
struct MFFINT_BITS bit;
|
||||
};
|
||||
|
||||
struct McBSP_REGS {
|
||||
union DRR2_REG DRR2; // Data receive register bits 31-16
|
||||
union DRR1_REG DRR1; // Data receive register bits 15-0
|
||||
union DXR2_REG DXR2; // Data transmit register bits 31-16
|
||||
union DXR1_REG DXR1; // Data transmit register bits 15-0
|
||||
union SPCR2_REG SPCR2; // Serial port control register 2
|
||||
union SPCR1_REG SPCR1; // Serial port control register 1
|
||||
union RCR2_REG RCR2; // Receive Control register 2
|
||||
union RCR1_REG RCR1; // Receive Control register 1
|
||||
union XCR2_REG XCR2; // Transmit Control register 2
|
||||
union XCR1_REG XCR1; // Transmit Control register 1
|
||||
union SRGR2_REG SRGR2; // Sample rate generator register 2
|
||||
union SRGR1_REG SRGR1; // Sample rate generator register 1
|
||||
union MCR2_REG MCR2; // Multi-channel control register 2
|
||||
union MCR1_REG MCR1; // Multi-channel control register 1
|
||||
Uint16 RCERA; // Receive channel enable partition A
|
||||
Uint16 RCERB; // Receive channel enable partition B
|
||||
Uint16 XCERA; // Transmit channel enable partition A
|
||||
Uint16 XCERB; // Transmit channel enable partition B
|
||||
union PCR_REG PCR; // Pin Control register
|
||||
Uint16 RCERC; // Receive channel enable partition C
|
||||
Uint16 RCERD; // Receive channel enable partition D
|
||||
Uint16 XCERC; // Transmit channel enable partition C
|
||||
Uint16 XCERD; // Transmit channel enable partition D
|
||||
Uint16 RCERE; // Receive channel enable partition E
|
||||
Uint16 RCERF; // Receive channel enable partition F
|
||||
Uint16 XCERE; // Transmit channel enable partition E
|
||||
Uint16 XCERF; // Transmit channel enable partition F
|
||||
Uint16 RCERG; // Receive channel enable partition G
|
||||
Uint16 RCERH; // Receive channel enable partition H
|
||||
Uint16 XCERG; // Transmit channel enable partition G
|
||||
Uint16 XCERH; // Transmit channel enable partition H
|
||||
Uint16 rsvd1[4]; // Reserved
|
||||
union MFFINT_REG MFFINT; // Interrupt enable
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// MCBSP External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct McBSP_REGS McbspaRegs;
|
||||
extern volatile struct McBSP_REGS McbspbRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct McBSP_REGS McbspaRegs;
|
||||
extern volatile struct McBSP_REGS McbspbRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,175 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_nmiintrupt.h
|
||||
//
|
||||
// TITLE: Definitions for the NMIINTRUPT registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_NMIINTRUPT_H
|
||||
#define F2837xD_NMIINTRUPT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// NMIINTRUPT Individual Register Bit Definitions:
|
||||
|
||||
struct NMICFG_BITS { // bits description
|
||||
Uint16 NMIE:1; // 0 Global NMI Enable
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
};
|
||||
|
||||
union NMICFG_REG {
|
||||
Uint16 all;
|
||||
struct NMICFG_BITS bit;
|
||||
};
|
||||
|
||||
struct NMIFLG_BITS { // bits description
|
||||
Uint16 NMIINT:1; // 0 NMI Interrupt Flag
|
||||
Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag
|
||||
Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag
|
||||
Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag
|
||||
Uint16 CPU1HWBISTERR:1; // 4 HW BIST Error NMI Flag
|
||||
Uint16 CPU2HWBISTERR:1; // 5 HW BIST Error NMI Flag
|
||||
Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag
|
||||
Uint16 rsvd1:1; // 7 Reserved
|
||||
Uint16 CLBNMI:1; // 8 Configurable Logic Block NMI Flag
|
||||
Uint16 CPU2WDRSn:1; // 9 CPU2 WDRSn Reset Indication Flag
|
||||
Uint16 CPU2NMIWDRSn:1; // 10 CPU2 NMIWDRSn Reset Indication Flag
|
||||
Uint16 rsvd2:1; // 11 Reserved
|
||||
Uint16 rsvd3:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union NMIFLG_REG {
|
||||
Uint16 all;
|
||||
struct NMIFLG_BITS bit;
|
||||
};
|
||||
|
||||
struct NMIFLGCLR_BITS { // bits description
|
||||
Uint16 NMIINT:1; // 0 NMIINT Flag Clear
|
||||
Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear
|
||||
Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear
|
||||
Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear
|
||||
Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Clear
|
||||
Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Clear
|
||||
Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear
|
||||
Uint16 rsvd1:1; // 7 Reserved
|
||||
Uint16 CLBNMI:1; // 8 CLBNMI Flag Clear
|
||||
Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Clear
|
||||
Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Clear
|
||||
Uint16 OVF:1; // 11 OVF Flag Clear
|
||||
Uint16 rsvd2:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union NMIFLGCLR_REG {
|
||||
Uint16 all;
|
||||
struct NMIFLGCLR_BITS bit;
|
||||
};
|
||||
|
||||
struct NMIFLGFRC_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force
|
||||
Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force
|
||||
Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force
|
||||
Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Force
|
||||
Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Force
|
||||
Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force
|
||||
Uint16 rsvd2:1; // 7 Reserved
|
||||
Uint16 CLBNMI:1; // 8 CLBNMI Flag Force
|
||||
Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Force
|
||||
Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Force
|
||||
Uint16 OVF:1; // 11 OVF Flag Force
|
||||
Uint16 rsvd3:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union NMIFLGFRC_REG {
|
||||
Uint16 all;
|
||||
struct NMIFLGFRC_BITS bit;
|
||||
};
|
||||
|
||||
struct NMISHDFLG_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag
|
||||
Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag
|
||||
Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag
|
||||
Uint16 CPU1HWBISTERR:1; // 4 Shadow CPU1HWBISTERR Flag
|
||||
Uint16 CPU2HWBISTERR:1; // 5 Shadow CPU2HWBISTERR Flag
|
||||
Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag
|
||||
Uint16 rsvd2:1; // 7 Reserved
|
||||
Uint16 CLBNMI:1; // 8 Shadow CLBNMI Flag
|
||||
Uint16 CPU2WDRSn:1; // 9 Shadow CPU2WDRSn Flag
|
||||
Uint16 CPU2NMIWDRSn:1; // 10 Shadow CPU2NMIWDRSn Flag
|
||||
Uint16 OVF:1; // 11 Shadow OVF Flag
|
||||
Uint16 rsvd3:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union NMISHDFLG_REG {
|
||||
Uint16 all;
|
||||
struct NMISHDFLG_BITS bit;
|
||||
};
|
||||
|
||||
struct NMI_INTRUPT_REGS {
|
||||
union NMICFG_REG NMICFG; // NMI Configuration Register
|
||||
union NMIFLG_REG NMIFLG; // NMI Flag Register (XRSn Clear)
|
||||
union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register
|
||||
union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register
|
||||
Uint16 NMIWDCNT; // NMI Watchdog Counter Register
|
||||
Uint16 NMIWDPRD; // NMI Watchdog Period Register
|
||||
union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// NMIINTRUPT External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,75 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_otp.h
|
||||
//
|
||||
// TITLE: Definitions for the OTP registers.
|
||||
//
|
||||
//###########################################################################
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_OTP_H
|
||||
#define F2837xD_OTP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// OTP Individual Register Bit Definitions:
|
||||
|
||||
struct UID_REGS {
|
||||
Uint32 UID_PSRAND0; // UID Psuedo-random 160 bit number
|
||||
Uint32 UID_PSRAND1; // UID Psuedo-random 160 bit number
|
||||
Uint32 UID_PSRAND2; // UID Psuedo-random 160 bit number
|
||||
Uint32 UID_PSRAND3; // UID Psuedo-random 160 bit number
|
||||
Uint32 UID_PSRAND4; // UID Psuedo-random 160 bit number
|
||||
Uint32 UID_PSRAND5; // UID Psuedo-random 160 bit number
|
||||
Uint32 UID_UNIQUE; // UID Unique 32 bit number
|
||||
Uint32 UID_CHECKSUM; // UID Checksum
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// OTP External References & Function Declarations:
|
||||
//
|
||||
extern volatile struct UID_REGS UidRegs;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,907 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_output_xbar.h
|
||||
//
|
||||
// TITLE: Definitions for the OUTPUT_XBAR registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_OUTPUT_XBAR_H
|
||||
#define F2837xD_OUTPUT_XBAR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// OUTPUT_XBAR Individual Register Bit Definitions:
|
||||
|
||||
struct OUTPUT1MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT1MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT1MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT1MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT1MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT1MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT2MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT2MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT2MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT2MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT2MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT2MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT3MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT3MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT3MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT3MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT3MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT3MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT4MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT4MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT4MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT4MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT4MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT4MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT5MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT5MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT5MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT5MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT5MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT5MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT6MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT6MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT6MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT6MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT6MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT6MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT7MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT7MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT7MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT7MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT7MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT7MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT8MUX0TO15CFG_BITS { // bits description
|
||||
Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT8MUX0TO15CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT8MUX0TO15CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT8MUX16TO31CFG_BITS { // bits description
|
||||
Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT8MUX16TO31CFG_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT8MUX16TO31CFG_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT1MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT1MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT1MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT2MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT2MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT2MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT3MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT3MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT3MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT4MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT4MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT4MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT5MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT5MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT5MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT6MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT6MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT6MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT7MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT7MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT7MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT8MUXENABLE_BITS { // bits description
|
||||
Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR
|
||||
};
|
||||
|
||||
union OUTPUT8MUXENABLE_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUT8MUXENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUTLATCH_BITS { // bits description
|
||||
Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union OUTPUTLATCH_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUTLATCH_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUTLATCHCLR_BITS { // bits description
|
||||
Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union OUTPUTLATCHCLR_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUTLATCHCLR_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUTLATCHFRC_BITS { // bits description
|
||||
Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union OUTPUTLATCHFRC_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUTLATCHFRC_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUTLATCHENABLE_BITS { // bits description
|
||||
Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR
|
||||
Uint16 OUTPUT2:1; // 1 Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR
|
||||
Uint16 OUTPUT3:1; // 2 Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR
|
||||
Uint16 OUTPUT4:1; // 3 Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR
|
||||
Uint16 OUTPUT5:1; // 4 Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR
|
||||
Uint16 OUTPUT6:1; // 5 Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR
|
||||
Uint16 OUTPUT7:1; // 6 Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR
|
||||
Uint16 OUTPUT8:1; // 7 Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union OUTPUTLATCHENABLE_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUTLATCHENABLE_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUTINV_BITS { // bits description
|
||||
Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR
|
||||
Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union OUTPUTINV_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUTINV_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUTLOCK_BITS { // bits description
|
||||
Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
Uint16 KEY:16; // 31:16 Write Protection KEY
|
||||
};
|
||||
|
||||
union OUTPUTLOCK_REG {
|
||||
Uint32 all;
|
||||
struct OUTPUTLOCK_BITS bit;
|
||||
};
|
||||
|
||||
struct OUTPUT_XBAR_REGS {
|
||||
union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1
|
||||
union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1
|
||||
union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2
|
||||
union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2
|
||||
union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3
|
||||
union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3
|
||||
union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4
|
||||
union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4
|
||||
union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5
|
||||
union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5
|
||||
union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6
|
||||
union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6
|
||||
union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7
|
||||
union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7
|
||||
union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8
|
||||
union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8
|
||||
union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1
|
||||
union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2
|
||||
union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3
|
||||
union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4
|
||||
union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5
|
||||
union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6
|
||||
union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7
|
||||
union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8
|
||||
union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch
|
||||
union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear
|
||||
union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear
|
||||
union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable
|
||||
union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion
|
||||
Uint16 rsvd1[4]; // Reserved
|
||||
union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// OUTPUT_XBAR External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,707 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_piectrl.h
|
||||
//
|
||||
// TITLE: Definitions for the PIECTRL registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_PIECTRL_H
|
||||
#define F2837xD_PIECTRL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// PIECTRL Individual Register Bit Definitions:
|
||||
|
||||
struct PIECTRL_BITS { // bits description
|
||||
Uint16 ENPIE:1; // 0 PIE Enable
|
||||
Uint16 PIEVECT:15; // 15:1 PIE Vector Address
|
||||
};
|
||||
|
||||
union PIECTRL_REG {
|
||||
Uint16 all;
|
||||
struct PIECTRL_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEACK_BITS { // bits description
|
||||
Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1
|
||||
Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2
|
||||
Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3
|
||||
Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4
|
||||
Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5
|
||||
Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6
|
||||
Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7
|
||||
Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8
|
||||
Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9
|
||||
Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10
|
||||
Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11
|
||||
Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12
|
||||
Uint16 rsvd1:4; // 15:12 Reserved
|
||||
};
|
||||
|
||||
union PIEACK_REG {
|
||||
Uint16 all;
|
||||
struct PIEACK_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER1_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 1.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 1.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 1.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 1.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 1.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 1.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 1.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 1.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 1.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 1.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 1.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 1.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 1.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 1.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 1.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 1.16
|
||||
};
|
||||
|
||||
union PIEIER1_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER1_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR1_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 1.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 1.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 1.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 1.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 1.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 1.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 1.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 1.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 1.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 1.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 1.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 1.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 1.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 1.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 1.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 1.16
|
||||
};
|
||||
|
||||
union PIEIFR1_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR1_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER2_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 2.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 2.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 2.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 2.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 2.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 2.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 2.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 2.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 2.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 2.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 2.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 2.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 2.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 2.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 2.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 2.16
|
||||
};
|
||||
|
||||
union PIEIER2_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER2_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR2_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 2.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 2.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 2.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 2.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 2.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 2.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 2.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 2.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 2.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 2.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 2.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 2.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 2.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 2.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 2.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 2.16
|
||||
};
|
||||
|
||||
union PIEIFR2_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR2_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER3_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 3.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 3.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 3.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 3.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 3.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 3.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 3.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 3.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 3.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 3.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 3.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 3.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 3.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 3.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 3.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 3.16
|
||||
};
|
||||
|
||||
union PIEIER3_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER3_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR3_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 3.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 3.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 3.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 3.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 3.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 3.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 3.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 3.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 3.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 3.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 3.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 3.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 3.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 3.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 3.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 3.16
|
||||
};
|
||||
|
||||
union PIEIFR3_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR3_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER4_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 4.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 4.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 4.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 4.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 4.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 4.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 4.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 4.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 4.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 4.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 4.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 4.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 4.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 4.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 4.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 4.16
|
||||
};
|
||||
|
||||
union PIEIER4_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER4_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR4_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 4.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 4.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 4.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 4.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 4.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 4.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 4.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 4.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 4.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 4.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 4.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 4.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 4.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 4.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 4.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 4.16
|
||||
};
|
||||
|
||||
union PIEIFR4_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR4_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER5_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 5.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 5.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 5.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 5.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 5.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 5.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 5.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 5.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 5.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 5.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 5.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 5.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 5.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 5.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 5.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 5.16
|
||||
};
|
||||
|
||||
union PIEIER5_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER5_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR5_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 5.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 5.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 5.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 5.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 5.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 5.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 5.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 5.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 5.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 5.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 5.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 5.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 5.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 5.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 5.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 5.16
|
||||
};
|
||||
|
||||
union PIEIFR5_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR5_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER6_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 6.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 6.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 6.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 6.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 6.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 6.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 6.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 6.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 6.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 6.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 6.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 6.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 6.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 6.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 6.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 6.16
|
||||
};
|
||||
|
||||
union PIEIER6_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER6_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR6_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 6.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 6.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 6.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 6.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 6.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 6.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 6.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 6.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 6.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 6.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 6.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 6.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 6.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 6.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 6.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 6.16
|
||||
};
|
||||
|
||||
union PIEIFR6_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR6_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER7_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 7.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 7.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 7.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 7.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 7.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 7.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 7.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 7.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 7.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 7.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 7.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 7.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 7.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 7.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 7.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 7.16
|
||||
};
|
||||
|
||||
union PIEIER7_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER7_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR7_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 7.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 7.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 7.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 7.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 7.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 7.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 7.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 7.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 7.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 7.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 7.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 7.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 7.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 7.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 7.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 7.16
|
||||
};
|
||||
|
||||
union PIEIFR7_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR7_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER8_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 8.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 8.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 8.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 8.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 8.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 8.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 8.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 8.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 8.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 8.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 8.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 8.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 8.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 8.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 8.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 8.16
|
||||
};
|
||||
|
||||
union PIEIER8_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER8_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR8_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 8.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 8.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 8.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 8.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 8.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 8.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 8.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 8.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 8.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 8.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 8.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 8.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 8.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 8.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 8.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 8.16
|
||||
};
|
||||
|
||||
union PIEIFR8_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR8_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER9_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 9.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 9.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 9.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 9.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 9.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 9.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 9.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 9.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 9.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 9.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 9.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 9.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 9.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 9.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 9.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 9.16
|
||||
};
|
||||
|
||||
union PIEIER9_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER9_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR9_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 9.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 9.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 9.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 9.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 9.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 9.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 9.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 9.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 9.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 9.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 9.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 9.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 9.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 9.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 9.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 9.16
|
||||
};
|
||||
|
||||
union PIEIFR9_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR9_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER10_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 10.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 10.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 10.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 10.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 10.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 10.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 10.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 10.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 10.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 10.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 10.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 10.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 10.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 10.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 10.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 10.16
|
||||
};
|
||||
|
||||
union PIEIER10_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER10_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR10_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 10.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 10.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 10.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 10.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 10.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 10.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 10.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 10.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 10.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 10.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 10.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 10.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 10.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 10.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 10.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 10.16
|
||||
};
|
||||
|
||||
union PIEIFR10_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR10_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER11_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 11.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 11.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 11.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 11.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 11.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 11.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 11.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 11.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 11.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 11.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 11.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 11.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 11.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 11.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 11.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 11.16
|
||||
};
|
||||
|
||||
union PIEIER11_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER11_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR11_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 11.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 11.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 11.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 11.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 11.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 11.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 11.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 11.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 11.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 11.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 11.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 11.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 11.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 11.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 11.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 11.16
|
||||
};
|
||||
|
||||
union PIEIFR11_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR11_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIER12_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Enable for Interrupt 12.1
|
||||
Uint16 INTx2:1; // 1 Enable for Interrupt 12.2
|
||||
Uint16 INTx3:1; // 2 Enable for Interrupt 12.3
|
||||
Uint16 INTx4:1; // 3 Enable for Interrupt 12.4
|
||||
Uint16 INTx5:1; // 4 Enable for Interrupt 12.5
|
||||
Uint16 INTx6:1; // 5 Enable for Interrupt 12.6
|
||||
Uint16 INTx7:1; // 6 Enable for Interrupt 12.7
|
||||
Uint16 INTx8:1; // 7 Enable for Interrupt 12.8
|
||||
Uint16 INTx9:1; // 8 Enable for Interrupt 12.9
|
||||
Uint16 INTx10:1; // 9 Enable for Interrupt 12.10
|
||||
Uint16 INTx11:1; // 10 Enable for Interrupt 12.11
|
||||
Uint16 INTx12:1; // 11 Enable for Interrupt 12.12
|
||||
Uint16 INTx13:1; // 12 Enable for Interrupt 12.13
|
||||
Uint16 INTx14:1; // 13 Enable for Interrupt 12.14
|
||||
Uint16 INTx15:1; // 14 Enable for Interrupt 12.15
|
||||
Uint16 INTx16:1; // 15 Enable for Interrupt 12.16
|
||||
};
|
||||
|
||||
union PIEIER12_REG {
|
||||
Uint16 all;
|
||||
struct PIEIER12_BITS bit;
|
||||
};
|
||||
|
||||
struct PIEIFR12_BITS { // bits description
|
||||
Uint16 INTx1:1; // 0 Flag for Interrupt 12.1
|
||||
Uint16 INTx2:1; // 1 Flag for Interrupt 12.2
|
||||
Uint16 INTx3:1; // 2 Flag for Interrupt 12.3
|
||||
Uint16 INTx4:1; // 3 Flag for Interrupt 12.4
|
||||
Uint16 INTx5:1; // 4 Flag for Interrupt 12.5
|
||||
Uint16 INTx6:1; // 5 Flag for Interrupt 12.6
|
||||
Uint16 INTx7:1; // 6 Flag for Interrupt 12.7
|
||||
Uint16 INTx8:1; // 7 Flag for Interrupt 12.8
|
||||
Uint16 INTx9:1; // 8 Flag for Interrupt 12.9
|
||||
Uint16 INTx10:1; // 9 Flag for Interrupt 12.10
|
||||
Uint16 INTx11:1; // 10 Flag for Interrupt 12.11
|
||||
Uint16 INTx12:1; // 11 Flag for Interrupt 12.12
|
||||
Uint16 INTx13:1; // 12 Flag for Interrupt 12.13
|
||||
Uint16 INTx14:1; // 13 Flag for Interrupt 12.14
|
||||
Uint16 INTx15:1; // 14 Flag for Interrupt 12.15
|
||||
Uint16 INTx16:1; // 15 Flag for Interrupt 12.16
|
||||
};
|
||||
|
||||
union PIEIFR12_REG {
|
||||
Uint16 all;
|
||||
struct PIEIFR12_BITS bit;
|
||||
};
|
||||
|
||||
struct PIE_CTRL_REGS {
|
||||
union PIECTRL_REG PIECTRL; // ePIE Control Register
|
||||
union PIEACK_REG PIEACK; // Interrupt Acknowledge Register
|
||||
union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register
|
||||
union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register
|
||||
union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register
|
||||
union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register
|
||||
union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register
|
||||
union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register
|
||||
union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register
|
||||
union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register
|
||||
union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register
|
||||
union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register
|
||||
union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register
|
||||
union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register
|
||||
union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register
|
||||
union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register
|
||||
union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register
|
||||
union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register
|
||||
union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register
|
||||
union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register
|
||||
union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register
|
||||
union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register
|
||||
union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register
|
||||
union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register
|
||||
union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register
|
||||
union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// PIECTRL External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,306 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_pievect.h
|
||||
//
|
||||
// TITLE: F2837xD Device PIE Vector Table Definitions
|
||||
//
|
||||
//###########################################################################
|
||||
// $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_PIE_VECT_H
|
||||
#define F2837xD_PIE_VECT_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// PIE Interrupt Vector Table Definition:
|
||||
// Create a user type called PINT (pointer to interrupt):
|
||||
|
||||
typedef __interrupt void (*PINT)(void);
|
||||
|
||||
// Define Vector Table:
|
||||
struct PIE_VECT_TABLE {
|
||||
PINT PIE1_RESERVED_INT; // Reserved
|
||||
PINT PIE2_RESERVED_INT; // Reserved
|
||||
PINT PIE3_RESERVED_INT; // Reserved
|
||||
PINT PIE4_RESERVED_INT; // Reserved
|
||||
PINT PIE5_RESERVED_INT; // Reserved
|
||||
PINT PIE6_RESERVED_INT; // Reserved
|
||||
PINT PIE7_RESERVED_INT; // Reserved
|
||||
PINT PIE8_RESERVED_INT; // Reserved
|
||||
PINT PIE9_RESERVED_INT; // Reserved
|
||||
PINT PIE10_RESERVED_INT; // Reserved
|
||||
PINT PIE11_RESERVED_INT; // Reserved
|
||||
PINT PIE12_RESERVED_INT; // Reserved
|
||||
PINT PIE13_RESERVED_INT; // Reserved
|
||||
PINT TIMER1_INT; // CPU Timer 1 Interrupt
|
||||
PINT TIMER2_INT; // CPU Timer 2 Interrupt
|
||||
PINT DATALOG_INT; // Datalogging Interrupt
|
||||
PINT RTOS_INT; // RTOS Interrupt
|
||||
PINT EMU_INT; // Emulation Interrupt
|
||||
PINT NMI_INT; // Non-Maskable Interrupt
|
||||
PINT ILLEGAL_INT; // Illegal Operation Trap
|
||||
PINT USER1_INT; // User Defined Trap 1
|
||||
PINT USER2_INT; // User Defined Trap 2
|
||||
PINT USER3_INT; // User Defined Trap 3
|
||||
PINT USER4_INT; // User Defined Trap 4
|
||||
PINT USER5_INT; // User Defined Trap 5
|
||||
PINT USER6_INT; // User Defined Trap 6
|
||||
PINT USER7_INT; // User Defined Trap 7
|
||||
PINT USER8_INT; // User Defined Trap 8
|
||||
PINT USER9_INT; // User Defined Trap 9
|
||||
PINT USER10_INT; // User Defined Trap 10
|
||||
PINT USER11_INT; // User Defined Trap 11
|
||||
PINT USER12_INT; // User Defined Trap 12
|
||||
PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1
|
||||
PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1
|
||||
PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1
|
||||
PINT XINT1_INT; // 1.4 - XINT1 Interrupt
|
||||
PINT XINT2_INT; // 1.5 - XINT2 Interrupt
|
||||
PINT ADCD1_INT; // 1.6 - ADCD Interrupt 1
|
||||
PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt
|
||||
PINT WAKE_INT; // 1.8 - Standby and Halt Wakeup Interrupt
|
||||
PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt
|
||||
PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt
|
||||
PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt
|
||||
PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt
|
||||
PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt
|
||||
PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt
|
||||
PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt
|
||||
PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt
|
||||
PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt
|
||||
PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt
|
||||
PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt
|
||||
PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt
|
||||
PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt
|
||||
PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt
|
||||
PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt
|
||||
PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt
|
||||
PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt
|
||||
PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt
|
||||
PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt
|
||||
PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt
|
||||
PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt
|
||||
PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt
|
||||
PINT PIE14_RESERVED_INT; // 4.7 - Reserved
|
||||
PINT PIE15_RESERVED_INT; // 4.8 - Reserved
|
||||
PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt
|
||||
PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt
|
||||
PINT EQEP3_INT; // 5.3 - eQEP3 Interrupt
|
||||
PINT PIE16_RESERVED_INT; // 5.4 - Reserved
|
||||
PINT PIE17_RESERVED_INT; // 5.5 - Reserved
|
||||
PINT PIE18_RESERVED_INT; // 5.6 - Reserved
|
||||
PINT PIE19_RESERVED_INT; // 5.7 - Reserved
|
||||
PINT PIE20_RESERVED_INT; // 5.8 - Reserved
|
||||
PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt
|
||||
PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt
|
||||
PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt
|
||||
PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt
|
||||
PINT MCBSPA_RX_INT; // 6.5 - McBSPA Receive Interrupt
|
||||
PINT MCBSPA_TX_INT; // 6.6 - McBSPA Transmit Interrupt
|
||||
PINT MCBSPB_RX_INT; // 6.7 - McBSPB Receive Interrupt
|
||||
PINT MCBSPB_TX_INT; // 6.8 - McBSPB Transmit Interrupt
|
||||
PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt
|
||||
PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt
|
||||
PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt
|
||||
PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt
|
||||
PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt
|
||||
PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt
|
||||
PINT PIE21_RESERVED_INT; // 7.7 - Reserved
|
||||
PINT PIE22_RESERVED_INT; // 7.8 - Reserved
|
||||
PINT I2CA_INT; // 8.1 - I2CA Interrupt 1
|
||||
PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2
|
||||
PINT I2CB_INT; // 8.3 - I2CB Interrupt 1
|
||||
PINT I2CB_FIFO_INT; // 8.4 - I2CB Interrupt 2
|
||||
PINT SCIC_RX_INT; // 8.5 - SCIC Receive Interrupt
|
||||
PINT SCIC_TX_INT; // 8.6 - SCIC Transmit Interrupt
|
||||
PINT SCID_RX_INT; // 8.7 - SCID Receive Interrupt
|
||||
PINT SCID_TX_INT; // 8.8 - SCID Transmit Interrupt
|
||||
PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt
|
||||
PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt
|
||||
PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt
|
||||
PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt
|
||||
PINT CANA0_INT; // 9.5 - CANA Interrupt 0
|
||||
PINT CANA1_INT; // 9.6 - CANA Interrupt 1
|
||||
PINT CANB0_INT; // 9.7 - CANB Interrupt 0
|
||||
PINT CANB1_INT; // 9.8 - CANB Interrupt 1
|
||||
PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt
|
||||
PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2
|
||||
PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3
|
||||
PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4
|
||||
PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt
|
||||
PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2
|
||||
PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3
|
||||
PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4
|
||||
PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1
|
||||
PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2
|
||||
PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3
|
||||
PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4
|
||||
PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5
|
||||
PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6
|
||||
PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7
|
||||
PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8
|
||||
PINT XINT3_INT; // 12.1 - XINT3 Interrupt
|
||||
PINT XINT4_INT; // 12.2 - XINT4 Interrupt
|
||||
PINT XINT5_INT; // 12.3 - XINT5 Interrupt
|
||||
PINT PIE23_RESERVED_INT; // 12.4 - Reserved
|
||||
PINT PIE24_RESERVED_INT; // 12.5 - Reserved
|
||||
PINT VCU_INT; // 12.6 - VCU Interrupt
|
||||
PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt
|
||||
PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt
|
||||
PINT PIE25_RESERVED_INT; // 1.9 - Reserved
|
||||
PINT PIE26_RESERVED_INT; // 1.10 - Reserved
|
||||
PINT PIE27_RESERVED_INT; // 1.11 - Reserved
|
||||
PINT PIE28_RESERVED_INT; // 1.12 - Reserved
|
||||
PINT IPC0_INT; // 1.13 - IPC Interrupt 0
|
||||
PINT IPC1_INT; // 1.14 - IPC Interrupt 1
|
||||
PINT IPC2_INT; // 1.15 - IPC Interrupt 2
|
||||
PINT IPC3_INT; // 1.16 - IPC Interrupt 3
|
||||
PINT EPWM9_TZ_INT; // 2.9 - ePWM9 Trip Zone Interrupt
|
||||
PINT EPWM10_TZ_INT; // 2.10 - ePWM10 Trip Zone Interrupt
|
||||
PINT EPWM11_TZ_INT; // 2.11 - ePWM11 Trip Zone Interrupt
|
||||
PINT EPWM12_TZ_INT; // 2.12 - ePWM12 Trip Zone Interrupt
|
||||
PINT PIE29_RESERVED_INT; // 2.13 - Reserved
|
||||
PINT PIE30_RESERVED_INT; // 2.14 - Reserved
|
||||
PINT PIE31_RESERVED_INT; // 2.15 - Reserved
|
||||
PINT PIE32_RESERVED_INT; // 2.16 - Reserved
|
||||
PINT EPWM9_INT; // 3.9 - ePWM9 Interrupt
|
||||
PINT EPWM10_INT; // 3.10 - ePWM10 Interrupt
|
||||
PINT EPWM11_INT; // 3.11 - ePWM11 Interrupt
|
||||
PINT EPWM12_INT; // 3.12 - ePWM12 Interrupt
|
||||
PINT PIE33_RESERVED_INT; // 3.13 - Reserved
|
||||
PINT PIE34_RESERVED_INT; // 3.14 - Reserved
|
||||
PINT PIE35_RESERVED_INT; // 3.15 - Reserved
|
||||
PINT PIE36_RESERVED_INT; // 3.16 - Reserved
|
||||
PINT PIE37_RESERVED_INT; // 4.9 - Reserved
|
||||
PINT PIE38_RESERVED_INT; // 4.10 - Reserved
|
||||
PINT PIE39_RESERVED_INT; // 4.11 - Reserved
|
||||
PINT PIE40_RESERVED_INT; // 4.12 - Reserved
|
||||
PINT PIE41_RESERVED_INT; // 4.13 - Reserved
|
||||
PINT PIE42_RESERVED_INT; // 4.14 - Reserved
|
||||
PINT PIE43_RESERVED_INT; // 4.15 - Reserved
|
||||
PINT PIE44_RESERVED_INT; // 4.16 - Reserved
|
||||
PINT SD1_INT; // 5.9 - SD1 Interrupt
|
||||
PINT SD2_INT; // 5.10 - SD2 Interrupt
|
||||
PINT PIE45_RESERVED_INT; // 5.11 - Reserved
|
||||
PINT PIE46_RESERVED_INT; // 5.12 - Reserved
|
||||
PINT PIE47_RESERVED_INT; // 5.13 - Reserved
|
||||
PINT PIE48_RESERVED_INT; // 5.14 - Reserved
|
||||
PINT PIE49_RESERVED_INT; // 5.15 - Reserved
|
||||
PINT PIE50_RESERVED_INT; // 5.16 - Reserved
|
||||
PINT SPIC_RX_INT; // 6.9 - SPIC Receive Interrupt
|
||||
PINT SPIC_TX_INT; // 6.10 - SPIC Transmit Interrupt
|
||||
PINT PIE51_RESERVED_INT; // 6.11 - Reserved
|
||||
PINT PIE52_RESERVED_INT; // 6.12 - Reserved
|
||||
PINT PIE53_RESERVED_INT; // 6.13 - Reserved
|
||||
PINT PIE54_RESERVED_INT; // 6.14 - Reserved
|
||||
PINT PIE55_RESERVED_INT; // 6.15 - Reserved
|
||||
PINT PIE56_RESERVED_INT; // 6.16 - Reserved
|
||||
PINT PIE57_RESERVED_INT; // 7.9 - Reserved
|
||||
PINT PIE58_RESERVED_INT; // 7.10 - Reserved
|
||||
PINT PIE59_RESERVED_INT; // 7.11 - Reserved
|
||||
PINT PIE60_RESERVED_INT; // 7.12 - Reserved
|
||||
PINT PIE61_RESERVED_INT; // 7.13 - Reserved
|
||||
PINT PIE62_RESERVED_INT; // 7.14 - Reserved
|
||||
PINT PIE63_RESERVED_INT; // 7.15 - Reserved
|
||||
PINT PIE64_RESERVED_INT; // 7.16 - Reserved
|
||||
PINT PIE65_RESERVED_INT; // 8.9 - Reserved
|
||||
PINT PIE66_RESERVED_INT; // 8.10 - Reserved
|
||||
PINT PIE67_RESERVED_INT; // 8.11 - Reserved
|
||||
PINT PIE68_RESERVED_INT; // 8.12 - Reserved
|
||||
PINT PIE69_RESERVED_INT; // 8.13 - Reserved
|
||||
PINT PIE70_RESERVED_INT; // 8.14 - Reserved
|
||||
#ifdef CPU1
|
||||
PINT UPPA_INT; // 8.15 - uPPA Interrupt
|
||||
PINT PIE72_RESERVED_INT; // 8.16 - Reserved
|
||||
#elif defined(CPU2)
|
||||
PINT PIE71_RESERVED_INT; // 8.15 - Reserved
|
||||
PINT PIE72_RESERVED_INT; // 8.16 - Reserved
|
||||
#endif
|
||||
PINT PIE73_RESERVED_INT; // 9.9 - Reserved
|
||||
PINT PIE74_RESERVED_INT; // 9.10 - Reserved
|
||||
PINT PIE75_RESERVED_INT; // 9.11 - Reserved
|
||||
PINT PIE76_RESERVED_INT; // 9.12 - Reserved
|
||||
PINT PIE77_RESERVED_INT; // 9.13 - Reserved
|
||||
PINT PIE78_RESERVED_INT; // 9.14 - Reserved
|
||||
#ifdef CPU1
|
||||
PINT USBA_INT; // 9.15 - USBA Interrupt
|
||||
#elif defined(CPU2)
|
||||
PINT PIE79_RESERVED_INT; // 9.15 - Reserved
|
||||
#endif
|
||||
PINT PIE80_RESERVED_INT; // 9.16 - Reserved
|
||||
PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt
|
||||
PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2
|
||||
PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3
|
||||
PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4
|
||||
PINT ADCD_EVT_INT; // 10.13 - ADCD Event Interrupt
|
||||
PINT ADCD2_INT; // 10.14 - ADCD Interrupt 2
|
||||
PINT ADCD3_INT; // 10.15 - ADCD Interrupt 3
|
||||
PINT ADCD4_INT; // 10.16 - ADCD Interrupt 4
|
||||
PINT PIE81_RESERVED_INT; // 11.9 - Reserved
|
||||
PINT PIE82_RESERVED_INT; // 11.10 - Reserved
|
||||
PINT PIE83_RESERVED_INT; // 11.11 - Reserved
|
||||
PINT PIE84_RESERVED_INT; // 11.12 - Reserved
|
||||
PINT PIE85_RESERVED_INT; // 11.13 - Reserved
|
||||
PINT PIE86_RESERVED_INT; // 11.14 - Reserved
|
||||
PINT PIE87_RESERVED_INT; // 11.15 - Reserved
|
||||
PINT PIE88_RESERVED_INT; // 11.16 - Reserved
|
||||
PINT EMIF_ERROR_INT; // 12.9 - EMIF Error Interrupt
|
||||
PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt
|
||||
PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt
|
||||
PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt
|
||||
PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt
|
||||
PINT AUX_PLL_SLIP_INT; // 12.14 - Auxiliary PLL Slip Interrupt
|
||||
PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt
|
||||
PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// PieVect External References & Function Declarations:
|
||||
//
|
||||
|
||||
extern volatile struct PIE_VECT_TABLE PieVectTable;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
|
||||
#endif // end of F2837xD_PIEVECT_H definition
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,266 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_sci.h
|
||||
//
|
||||
// TITLE: Definitions for the SCI registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_SCI_H
|
||||
#define F2837xD_SCI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// SCI Individual Register Bit Definitions:
|
||||
|
||||
struct SCICCR_BITS { // bits description
|
||||
Uint16 SCICHAR:3; // 2:0 Character length control
|
||||
Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
|
||||
Uint16 LOOPBKENA:1; // 4 Loop Back enable
|
||||
Uint16 PARITYENA:1; // 5 Parity enable
|
||||
Uint16 PARITY:1; // 6 Even or Odd Parity
|
||||
Uint16 STOPBITS:1; // 7 Number of Stop Bits
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SCICCR_REG {
|
||||
Uint16 all;
|
||||
struct SCICCR_BITS bit;
|
||||
};
|
||||
|
||||
struct SCICTL1_BITS { // bits description
|
||||
Uint16 RXENA:1; // 0 SCI receiver enable
|
||||
Uint16 TXENA:1; // 1 SCI transmitter enable
|
||||
Uint16 SLEEP:1; // 2 SCI sleep
|
||||
Uint16 TXWAKE:1; // 3 Transmitter wakeup method
|
||||
Uint16 rsvd1:1; // 4 Reserved
|
||||
Uint16 SWRESET:1; // 5 Software reset
|
||||
Uint16 RXERRINTENA:1; // 6 Receive error interrupt enable
|
||||
Uint16 rsvd2:9; // 15:7 Reserved
|
||||
};
|
||||
|
||||
union SCICTL1_REG {
|
||||
Uint16 all;
|
||||
struct SCICTL1_BITS bit;
|
||||
};
|
||||
|
||||
struct SCIHBAUD_BITS { // bits description
|
||||
Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SCIHBAUD_REG {
|
||||
Uint16 all;
|
||||
struct SCIHBAUD_BITS bit;
|
||||
};
|
||||
|
||||
struct SCILBAUD_BITS { // bits description
|
||||
Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SCILBAUD_REG {
|
||||
Uint16 all;
|
||||
struct SCILBAUD_BITS bit;
|
||||
};
|
||||
|
||||
struct SCICTL2_BITS { // bits description
|
||||
Uint16 TXINTENA:1; // 0 Transmit __interrupt enable
|
||||
Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
|
||||
Uint16 rsvd1:4; // 5:2 Reserved
|
||||
Uint16 TXEMPTY:1; // 6 Transmitter empty flag
|
||||
Uint16 TXRDY:1; // 7 Transmitter ready flag
|
||||
Uint16 rsvd2:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SCICTL2_REG {
|
||||
Uint16 all;
|
||||
struct SCICTL2_BITS bit;
|
||||
};
|
||||
|
||||
struct SCIRXST_BITS { // bits description
|
||||
Uint16 rsvd1:1; // 0 Reserved
|
||||
Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
|
||||
Uint16 PE:1; // 2 Parity error flag
|
||||
Uint16 OE:1; // 3 Overrun error flag
|
||||
Uint16 FE:1; // 4 Framing error flag
|
||||
Uint16 BRKDT:1; // 5 Break-detect flag
|
||||
Uint16 RXRDY:1; // 6 Receiver ready flag
|
||||
Uint16 RXERROR:1; // 7 Receiver error flag
|
||||
Uint16 rsvd2:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SCIRXST_REG {
|
||||
Uint16 all;
|
||||
struct SCIRXST_BITS bit;
|
||||
};
|
||||
|
||||
struct SCIRXEMU_BITS { // bits description
|
||||
Uint16 ERXDT:8; // 7:0 Receive emulation buffer data
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SCIRXEMU_REG {
|
||||
Uint16 all;
|
||||
struct SCIRXEMU_BITS bit;
|
||||
};
|
||||
|
||||
struct SCIRXBUF_BITS { // bits description
|
||||
Uint16 SAR:8; // 7:0 Receive Character bits
|
||||
Uint16 rsvd1:6; // 13:8 Reserved
|
||||
Uint16 SCIFFPE:1; // 14 Receiver error flag
|
||||
Uint16 SCIFFFE:1; // 15 Receiver error flag
|
||||
};
|
||||
|
||||
union SCIRXBUF_REG {
|
||||
Uint16 all;
|
||||
struct SCIRXBUF_BITS bit;
|
||||
};
|
||||
|
||||
struct SCITXBUF_BITS { // bits description
|
||||
Uint16 TXDT:8; // 7:0 Transmit data buffer
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SCITXBUF_REG {
|
||||
Uint16 all;
|
||||
struct SCITXBUF_BITS bit;
|
||||
};
|
||||
|
||||
struct SCIFFTX_BITS { // bits description
|
||||
Uint16 TXFFIL:5; // 4:0 Interrupt level
|
||||
Uint16 TXFFIENA:1; // 5 Interrupt enable
|
||||
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
|
||||
Uint16 TXFFINT:1; // 7 INT flag
|
||||
Uint16 TXFFST:5; // 12:8 FIFO status
|
||||
Uint16 TXFIFORESET:1; // 13 FIFO reset
|
||||
Uint16 SCIFFENA:1; // 14 Enhancement enable
|
||||
Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
|
||||
};
|
||||
|
||||
union SCIFFTX_REG {
|
||||
Uint16 all;
|
||||
struct SCIFFTX_BITS bit;
|
||||
};
|
||||
|
||||
struct SCIFFRX_BITS { // bits description
|
||||
Uint16 RXFFIL:5; // 4:0 Interrupt level
|
||||
Uint16 RXFFIENA:1; // 5 Interrupt enable
|
||||
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
|
||||
Uint16 RXFFINT:1; // 7 INT flag
|
||||
Uint16 RXFFST:5; // 12:8 FIFO status
|
||||
Uint16 RXFIFORESET:1; // 13 FIFO reset
|
||||
Uint16 RXFFOVRCLR:1; // 14 Clear overflow
|
||||
Uint16 RXFFOVF:1; // 15 FIFO overflow
|
||||
};
|
||||
|
||||
union SCIFFRX_REG {
|
||||
Uint16 all;
|
||||
struct SCIFFRX_BITS bit;
|
||||
};
|
||||
|
||||
struct SCIFFCT_BITS { // bits description
|
||||
Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
|
||||
Uint16 rsvd1:5; // 12:8 Reserved
|
||||
Uint16 CDC:1; // 13 Auto baud mode enable
|
||||
Uint16 ABDCLR:1; // 14 Auto baud clear
|
||||
Uint16 ABD:1; // 15 Auto baud detect
|
||||
};
|
||||
|
||||
union SCIFFCT_REG {
|
||||
Uint16 all;
|
||||
struct SCIFFCT_BITS bit;
|
||||
};
|
||||
|
||||
struct SCIPRI_BITS { // bits description
|
||||
Uint16 rsvd1:3; // 2:0 Reserved
|
||||
Uint16 FREESOFT:2; // 4:3 Emulation modes
|
||||
Uint16 rsvd2:3; // 7:5 Reserved
|
||||
Uint16 rsvd3:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SCIPRI_REG {
|
||||
Uint16 all;
|
||||
struct SCIPRI_BITS bit;
|
||||
};
|
||||
|
||||
struct SCI_REGS {
|
||||
union SCICCR_REG SCICCR; // Communications control register
|
||||
union SCICTL1_REG SCICTL1; // Control register 1
|
||||
union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register
|
||||
union SCILBAUD_REG SCILBAUD; // Baud rate (low) register
|
||||
union SCICTL2_REG SCICTL2; // Control register 2
|
||||
union SCIRXST_REG SCIRXST; // Receive status register
|
||||
union SCIRXEMU_REG SCIRXEMU; // Receive emulation buffer register
|
||||
union SCIRXBUF_REG SCIRXBUF; // Receive data buffer
|
||||
Uint16 rsvd1; // Reserved
|
||||
union SCITXBUF_REG SCITXBUF; // Transmit data buffer
|
||||
union SCIFFTX_REG SCIFFTX; // FIFO transmit register
|
||||
union SCIFFRX_REG SCIFFRX; // FIFO receive register
|
||||
union SCIFFCT_REG SCIFFCT; // FIFO control register
|
||||
Uint16 rsvd2[2]; // Reserved
|
||||
union SCIPRI_REG SCIPRI; // SCI priority control
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// SCI External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct SCI_REGS SciaRegs;
|
||||
extern volatile struct SCI_REGS ScibRegs;
|
||||
extern volatile struct SCI_REGS ScicRegs;
|
||||
extern volatile struct SCI_REGS ScidRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct SCI_REGS SciaRegs;
|
||||
extern volatile struct SCI_REGS ScibRegs;
|
||||
extern volatile struct SCI_REGS ScicRegs;
|
||||
extern volatile struct SCI_REGS ScidRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,533 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_sdfm.h
|
||||
//
|
||||
// TITLE: Definitions for the SDFM registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_SDFM_H
|
||||
#define F2837xD_SDFM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// SDFM Individual Register Bit Definitions:
|
||||
|
||||
struct SDIFLG_BITS { // bits description
|
||||
Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1
|
||||
Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1
|
||||
Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2
|
||||
Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2
|
||||
Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3
|
||||
Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3
|
||||
Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4
|
||||
Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4
|
||||
Uint16 MF1:1; // 8 Modulator Failure for Filter 1
|
||||
Uint16 MF2:1; // 9 Modulator Failure for Filter 2
|
||||
Uint16 MF3:1; // 10 Modulator Failure for Filter 3
|
||||
Uint16 MF4:1; // 11 Modulator Failure for Filter 4
|
||||
Uint16 AF1:1; // 12 Acknowledge flag for Filter 1
|
||||
Uint16 AF2:1; // 13 Acknowledge flag for Filter 2
|
||||
Uint16 AF3:1; // 14 Acknowledge flag for Filter 3
|
||||
Uint16 AF4:1; // 15 Acknowledge flag for Filter 4
|
||||
Uint16 rsvd1:15; // 30:16 Reserved
|
||||
Uint16 MIF:1; // 31 Master Interrupt Flag
|
||||
};
|
||||
|
||||
union SDIFLG_REG {
|
||||
Uint32 all;
|
||||
struct SDIFLG_BITS bit;
|
||||
};
|
||||
|
||||
struct SDIFLGCLR_BITS { // bits description
|
||||
Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1
|
||||
Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1
|
||||
Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2
|
||||
Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2
|
||||
Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3
|
||||
Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3
|
||||
Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4
|
||||
Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4
|
||||
Uint16 MF1:1; // 8 Modulator Failure for Filter 1
|
||||
Uint16 MF2:1; // 9 Modulator Failure for Filter 2
|
||||
Uint16 MF3:1; // 10 Modulator Failure for Filter 3
|
||||
Uint16 MF4:1; // 11 Modulator Failure for Filter 4
|
||||
Uint16 AF1:1; // 12 Acknowledge flag for Filter 1
|
||||
Uint16 AF2:1; // 13 Acknowledge flag for Filter 2
|
||||
Uint16 AF3:1; // 14 Acknowledge flag for Filter 3
|
||||
Uint16 AF4:1; // 15 Acknowledge flag for Filter 4
|
||||
Uint16 rsvd1:15; // 30:16 Reserved
|
||||
Uint16 MIF:1; // 31 Master Interrupt Flag
|
||||
};
|
||||
|
||||
union SDIFLGCLR_REG {
|
||||
Uint32 all;
|
||||
struct SDIFLGCLR_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCTL_BITS { // bits description
|
||||
Uint16 rsvd1:13; // 12:0 Reserved
|
||||
Uint16 MIE:1; // 13 Master Interrupt enable
|
||||
Uint16 rsvd2:1; // 14 Reserved
|
||||
Uint16 rsvd3:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union SDCTL_REG {
|
||||
Uint16 all;
|
||||
struct SDCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct SDMFILEN_BITS { // bits description
|
||||
Uint16 rsvd1:4; // 3:0 Reserved
|
||||
Uint16 rsvd2:3; // 6:4 Reserved
|
||||
Uint16 rsvd3:2; // 8:7 Reserved
|
||||
Uint16 rsvd4:1; // 9 Reserved
|
||||
Uint16 rsvd5:1; // 10 Reserved
|
||||
Uint16 MFE:1; // 11 Master Filter Enable.
|
||||
Uint16 rsvd6:1; // 12 Reserved
|
||||
Uint16 rsvd7:3; // 15:13 Reserved
|
||||
};
|
||||
|
||||
union SDMFILEN_REG {
|
||||
Uint16 all;
|
||||
struct SDMFILEN_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCTLPARM1_BITS { // bits description
|
||||
Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode
|
||||
Uint16 rsvd1:1; // 2 Reserved
|
||||
Uint16 rsvd2:1; // 3 Reserved
|
||||
Uint16 rsvd3:1; // 4 Reserved
|
||||
Uint16 rsvd4:11; // 15:5 Reserved
|
||||
};
|
||||
|
||||
union SDCTLPARM1_REG {
|
||||
Uint16 all;
|
||||
struct SDCTLPARM1_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDFPARM1_BITS { // bits description
|
||||
Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1
|
||||
Uint16 FEN:1; // 8 Filter Enable
|
||||
Uint16 AE:1; // 9 Ack Enable
|
||||
Uint16 SST:2; // 11:10 Data Filter Structure (DataFast/1/2/3)
|
||||
Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable
|
||||
Uint16 rsvd1:3; // 15:13 Reserved
|
||||
};
|
||||
|
||||
union SDDFPARM1_REG {
|
||||
Uint16 all;
|
||||
struct SDDFPARM1_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDPARM1_BITS { // bits description
|
||||
Uint16 rsvd1:7; // 6:0 Reserved
|
||||
Uint16 rsvd2:1; // 7 Reserved
|
||||
Uint16 rsvd3:1; // 8 Reserved
|
||||
Uint16 rsvd4:1; // 9 Reserved
|
||||
Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement)
|
||||
Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode)
|
||||
};
|
||||
|
||||
union SDDPARM1_REG {
|
||||
Uint16 all;
|
||||
struct SDDPARM1_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCMPH1_BITS { // bits description
|
||||
Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output.
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union SDCMPH1_REG {
|
||||
Uint16 all;
|
||||
struct SDCMPH1_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCMPL1_BITS { // bits description
|
||||
Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output.
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union SDCMPL1_REG {
|
||||
Uint16 all;
|
||||
struct SDCMPL1_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCPARM1_BITS { // bits description
|
||||
Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1
|
||||
Uint16 IEH:1; // 5 High-level interrupt enable
|
||||
Uint16 IEL:1; // 6 Low-level interrupt enable
|
||||
Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3
|
||||
Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable
|
||||
Uint16 rsvd1:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union SDCPARM1_REG {
|
||||
Uint16 all;
|
||||
struct SDCPARM1_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDATA1_BITS { // bits description
|
||||
Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode
|
||||
Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode
|
||||
};
|
||||
|
||||
union SDDATA1_REG {
|
||||
Uint32 all;
|
||||
struct SDDATA1_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCTLPARM2_BITS { // bits description
|
||||
Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode
|
||||
Uint16 rsvd1:1; // 2 Reserved
|
||||
Uint16 rsvd2:1; // 3 Reserved
|
||||
Uint16 rsvd3:1; // 4 Reserved
|
||||
Uint16 rsvd4:11; // 15:5 Reserved
|
||||
};
|
||||
|
||||
union SDCTLPARM2_REG {
|
||||
Uint16 all;
|
||||
struct SDCTLPARM2_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDFPARM2_BITS { // bits description
|
||||
Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1
|
||||
Uint16 FEN:1; // 8 Filter Enable
|
||||
Uint16 AE:1; // 9 Ack Enable
|
||||
Uint16 SST:2; // 11:10 Data Filter Structure (SincFast/1/2/3)
|
||||
Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable
|
||||
Uint16 rsvd1:3; // 15:13 Reserved
|
||||
};
|
||||
|
||||
union SDDFPARM2_REG {
|
||||
Uint16 all;
|
||||
struct SDDFPARM2_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDPARM2_BITS { // bits description
|
||||
Uint16 rsvd1:7; // 6:0 Reserved
|
||||
Uint16 rsvd2:1; // 7 Reserved
|
||||
Uint16 rsvd3:1; // 8 Reserved
|
||||
Uint16 rsvd4:1; // 9 Reserved
|
||||
Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement)
|
||||
Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode)
|
||||
};
|
||||
|
||||
union SDDPARM2_REG {
|
||||
Uint16 all;
|
||||
struct SDDPARM2_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCMPH2_BITS { // bits description
|
||||
Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output.
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union SDCMPH2_REG {
|
||||
Uint16 all;
|
||||
struct SDCMPH2_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCMPL2_BITS { // bits description
|
||||
Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output.
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union SDCMPL2_REG {
|
||||
Uint16 all;
|
||||
struct SDCMPL2_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCPARM2_BITS { // bits description
|
||||
Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1
|
||||
Uint16 IEH:1; // 5 High-level interrupt enable
|
||||
Uint16 IEL:1; // 6 Low-level interrupt enable
|
||||
Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3
|
||||
Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable
|
||||
Uint16 rsvd1:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union SDCPARM2_REG {
|
||||
Uint16 all;
|
||||
struct SDCPARM2_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDATA2_BITS { // bits description
|
||||
Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode
|
||||
Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode
|
||||
};
|
||||
|
||||
union SDDATA2_REG {
|
||||
Uint32 all;
|
||||
struct SDDATA2_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCTLPARM3_BITS { // bits description
|
||||
Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode
|
||||
Uint16 rsvd1:1; // 2 Reserved
|
||||
Uint16 rsvd2:1; // 3 Reserved
|
||||
Uint16 rsvd3:1; // 4 Reserved
|
||||
Uint16 rsvd4:11; // 15:5 Reserved
|
||||
};
|
||||
|
||||
union SDCTLPARM3_REG {
|
||||
Uint16 all;
|
||||
struct SDCTLPARM3_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDFPARM3_BITS { // bits description
|
||||
Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1
|
||||
Uint16 FEN:1; // 8 Filter Enable
|
||||
Uint16 AE:1; // 9 Ack Enable
|
||||
Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3)
|
||||
Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable
|
||||
Uint16 rsvd1:3; // 15:13 Reserved
|
||||
};
|
||||
|
||||
union SDDFPARM3_REG {
|
||||
Uint16 all;
|
||||
struct SDDFPARM3_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDPARM3_BITS { // bits description
|
||||
Uint16 rsvd1:7; // 6:0 Reserved
|
||||
Uint16 rsvd2:1; // 7 Reserved
|
||||
Uint16 rsvd3:1; // 8 Reserved
|
||||
Uint16 rsvd4:1; // 9 Reserved
|
||||
Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement)
|
||||
Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode)
|
||||
};
|
||||
|
||||
union SDDPARM3_REG {
|
||||
Uint16 all;
|
||||
struct SDDPARM3_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCMPH3_BITS { // bits description
|
||||
Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output.
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union SDCMPH3_REG {
|
||||
Uint16 all;
|
||||
struct SDCMPH3_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCMPL3_BITS { // bits description
|
||||
Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output.
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union SDCMPL3_REG {
|
||||
Uint16 all;
|
||||
struct SDCMPL3_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCPARM3_BITS { // bits description
|
||||
Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1
|
||||
Uint16 IEH:1; // 5 High-level interrupt enable
|
||||
Uint16 IEL:1; // 6 Low-level interrupt enable
|
||||
Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3
|
||||
Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable
|
||||
Uint16 rsvd1:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union SDCPARM3_REG {
|
||||
Uint16 all;
|
||||
struct SDCPARM3_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDATA3_BITS { // bits description
|
||||
Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode
|
||||
Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode
|
||||
};
|
||||
|
||||
union SDDATA3_REG {
|
||||
Uint32 all;
|
||||
struct SDDATA3_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCTLPARM4_BITS { // bits description
|
||||
Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode
|
||||
Uint16 rsvd1:1; // 2 Reserved
|
||||
Uint16 rsvd2:1; // 3 Reserved
|
||||
Uint16 rsvd3:1; // 4 Reserved
|
||||
Uint16 rsvd4:11; // 15:5 Reserved
|
||||
};
|
||||
|
||||
union SDCTLPARM4_REG {
|
||||
Uint16 all;
|
||||
struct SDCTLPARM4_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDFPARM4_BITS { // bits description
|
||||
Uint16 DOSR:8; // 7:0 SINC Filter Oversample Ratio= DOSR+1
|
||||
Uint16 FEN:1; // 8 Filter Enable
|
||||
Uint16 AE:1; // 9 Ack Enable
|
||||
Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3)
|
||||
Uint16 SDSYNCEN:1; // 12 SINC FILTER Reset Enable
|
||||
Uint16 rsvd1:3; // 15:13 Reserved
|
||||
};
|
||||
|
||||
union SDDFPARM4_REG {
|
||||
Uint16 all;
|
||||
struct SDDFPARM4_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDPARM4_BITS { // bits description
|
||||
Uint16 rsvd1:7; // 6:0 Reserved
|
||||
Uint16 rsvd2:1; // 7 Reserved
|
||||
Uint16 rsvd3:1; // 8 Reserved
|
||||
Uint16 rsvd4:1; // 9 Reserved
|
||||
Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement)
|
||||
Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode)
|
||||
};
|
||||
|
||||
union SDDPARM4_REG {
|
||||
Uint16 all;
|
||||
struct SDDPARM4_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCMPH4_BITS { // bits description
|
||||
Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output.
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union SDCMPH4_REG {
|
||||
Uint16 all;
|
||||
struct SDCMPH4_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCMPL4_BITS { // bits description
|
||||
Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output.
|
||||
Uint16 rsvd1:1; // 15 Reserved
|
||||
};
|
||||
|
||||
union SDCMPL4_REG {
|
||||
Uint16 all;
|
||||
struct SDCMPL4_BITS bit;
|
||||
};
|
||||
|
||||
struct SDCPARM4_BITS { // bits description
|
||||
Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1
|
||||
Uint16 IEH:1; // 5 High-level interrupt enable
|
||||
Uint16 IEL:1; // 6 Low-level interrupt enable
|
||||
Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3
|
||||
Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable
|
||||
Uint16 rsvd1:6; // 15:10 Reserved
|
||||
};
|
||||
|
||||
union SDCPARM4_REG {
|
||||
Uint16 all;
|
||||
struct SDCPARM4_BITS bit;
|
||||
};
|
||||
|
||||
struct SDDATA4_BITS { // bits description
|
||||
Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode
|
||||
Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode
|
||||
};
|
||||
|
||||
union SDDATA4_REG {
|
||||
Uint32 all;
|
||||
struct SDDATA4_BITS bit;
|
||||
};
|
||||
|
||||
struct SDFM_REGS {
|
||||
union SDIFLG_REG SDIFLG; // Interrupt Flag Register
|
||||
union SDIFLGCLR_REG SDIFLGCLR; // Interrupt Flag Clear Register
|
||||
union SDCTL_REG SDCTL; // SD Control Register
|
||||
Uint16 rsvd1; // Reserved
|
||||
union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable
|
||||
Uint16 rsvd2[9]; // Reserved
|
||||
union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1
|
||||
union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1
|
||||
union SDDPARM1_REG SDDPARM1; // Integer Parameter Register for Ch1
|
||||
union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1
|
||||
union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1
|
||||
union SDCPARM1_REG SDCPARM1; // Comparator Parameter Register for Ch1
|
||||
union SDDATA1_REG SDDATA1; // Filter Data Register (16 or 32bit) for Ch1
|
||||
Uint16 rsvd3[8]; // Reserved
|
||||
union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2
|
||||
union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2
|
||||
union SDDPARM2_REG SDDPARM2; // Integer Parameter Register for Ch2
|
||||
union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2
|
||||
union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2
|
||||
union SDCPARM2_REG SDCPARM2; // Comparator Parameter Register for Ch2
|
||||
union SDDATA2_REG SDDATA2; // Filter Data Register (16 or 32bit) for Ch2
|
||||
Uint16 rsvd4[8]; // Reserved
|
||||
union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3
|
||||
union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3
|
||||
union SDDPARM3_REG SDDPARM3; // Integer Parameter Register for Ch3
|
||||
union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3
|
||||
union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3
|
||||
union SDCPARM3_REG SDCPARM3; // Comparator Parameter Register for Ch3
|
||||
union SDDATA3_REG SDDATA3; // Filter Data Register (16 or 32bit) for Ch3
|
||||
Uint16 rsvd5[8]; // Reserved
|
||||
union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4
|
||||
union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4
|
||||
union SDDPARM4_REG SDDPARM4; // Integer Parameter Register for Ch4
|
||||
union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4
|
||||
union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4
|
||||
union SDCPARM4_REG SDCPARM4; // Comparator Parameter Register for Ch4
|
||||
union SDDATA4_REG SDDATA4; // Filter Data Register (16 or 32bit) for Ch4
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// SDFM External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct SDFM_REGS Sdfm1Regs;
|
||||
extern volatile struct SDFM_REGS Sdfm2Regs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct SDFM_REGS Sdfm1Regs;
|
||||
extern volatile struct SDFM_REGS Sdfm2Regs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,201 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_spi.h
|
||||
//
|
||||
// TITLE: Definitions for the SPI registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_SPI_H
|
||||
#define F2837xD_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// SPI Individual Register Bit Definitions:
|
||||
|
||||
struct SPICCR_BITS { // bits description
|
||||
Uint16 SPICHAR:4; // 3:0 Character Length Control
|
||||
Uint16 SPILBK:1; // 4 SPI Loopback
|
||||
Uint16 HS_MODE:1; // 5 High Speed mode control
|
||||
Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity
|
||||
Uint16 SPISWRESET:1; // 7 SPI Software Reset
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SPICCR_REG {
|
||||
Uint16 all;
|
||||
struct SPICCR_BITS bit;
|
||||
};
|
||||
|
||||
struct SPICTL_BITS { // bits description
|
||||
Uint16 SPIINTENA:1; // 0 SPI Interupt Enable
|
||||
Uint16 TALK:1; // 1 Master/Slave Transmit Enable
|
||||
Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control
|
||||
Uint16 CLK_PHASE:1; // 3 SPI Clock Phase
|
||||
Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable
|
||||
Uint16 rsvd1:11; // 15:5 Reserved
|
||||
};
|
||||
|
||||
union SPICTL_REG {
|
||||
Uint16 all;
|
||||
struct SPICTL_BITS bit;
|
||||
};
|
||||
|
||||
struct SPISTS_BITS { // bits description
|
||||
Uint16 rsvd1:5; // 4:0 Reserved
|
||||
Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag
|
||||
Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag
|
||||
Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag
|
||||
Uint16 rsvd2:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SPISTS_REG {
|
||||
Uint16 all;
|
||||
struct SPISTS_BITS bit;
|
||||
};
|
||||
|
||||
struct SPIBRR_BITS { // bits description
|
||||
Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control
|
||||
Uint16 rsvd1:9; // 15:7 Reserved
|
||||
};
|
||||
|
||||
union SPIBRR_REG {
|
||||
Uint16 all;
|
||||
struct SPIBRR_BITS bit;
|
||||
};
|
||||
|
||||
struct SPIFFTX_BITS { // bits description
|
||||
Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level
|
||||
Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable
|
||||
Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear
|
||||
Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag
|
||||
Uint16 TXFFST:5; // 12:8 Transmit FIFO Status
|
||||
Uint16 TXFIFO:1; // 13 TXFIFO Reset
|
||||
Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable
|
||||
Uint16 SPIRST:1; // 15 SPI Reset
|
||||
};
|
||||
|
||||
union SPIFFTX_REG {
|
||||
Uint16 all;
|
||||
struct SPIFFTX_BITS bit;
|
||||
};
|
||||
|
||||
struct SPIFFRX_BITS { // bits description
|
||||
Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level
|
||||
Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable
|
||||
Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear
|
||||
Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag
|
||||
Uint16 RXFFST:5; // 12:8 Receive FIFO Status
|
||||
Uint16 RXFIFORESET:1; // 13 RXFIFO Reset
|
||||
Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear
|
||||
Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag
|
||||
};
|
||||
|
||||
union SPIFFRX_REG {
|
||||
Uint16 all;
|
||||
struct SPIFFRX_BITS bit;
|
||||
};
|
||||
|
||||
struct SPIFFCT_BITS { // bits description
|
||||
Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits
|
||||
Uint16 rsvd1:8; // 15:8 Reserved
|
||||
};
|
||||
|
||||
union SPIFFCT_REG {
|
||||
Uint16 all;
|
||||
struct SPIFFCT_BITS bit;
|
||||
};
|
||||
|
||||
struct SPIPRI_BITS { // bits description
|
||||
Uint16 TRIWIRE:1; // 0 3-wire mode select bit
|
||||
Uint16 STEINV:1; // 1 SPISTE inversion bit
|
||||
Uint16 rsvd1:2; // 3:2 Reserved
|
||||
Uint16 FREE:1; // 4 Free emulation mode
|
||||
Uint16 SOFT:1; // 5 Soft emulation mode
|
||||
Uint16 rsvd2:1; // 6 Reserved
|
||||
Uint16 rsvd3:9; // 15:7 Reserved
|
||||
};
|
||||
|
||||
union SPIPRI_REG {
|
||||
Uint16 all;
|
||||
struct SPIPRI_BITS bit;
|
||||
};
|
||||
|
||||
struct SPI_REGS {
|
||||
union SPICCR_REG SPICCR; // SPI Configuration Control Register
|
||||
union SPICTL_REG SPICTL; // SPI Operation Control Register
|
||||
union SPISTS_REG SPISTS; // SPI Status Register
|
||||
Uint16 rsvd1; // Reserved
|
||||
union SPIBRR_REG SPIBRR; // SPI Baud Rate Register
|
||||
Uint16 rsvd2; // Reserved
|
||||
Uint16 SPIRXEMU; // SPI Emulation Buffer Register
|
||||
Uint16 SPIRXBUF; // SPI Serial Input Buffer Register
|
||||
Uint16 SPITXBUF; // SPI Serial Output Buffer Register
|
||||
Uint16 SPIDAT; // SPI Serial Data Register
|
||||
union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register
|
||||
union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register
|
||||
union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register
|
||||
Uint16 rsvd3[2]; // Reserved
|
||||
union SPIPRI_REG SPIPRI; // SPI Priority Control Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// SPI External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct SPI_REGS SpiaRegs;
|
||||
extern volatile struct SPI_REGS SpibRegs;
|
||||
extern volatile struct SPI_REGS SpicRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct SPI_REGS SpiaRegs;
|
||||
extern volatile struct SPI_REGS SpibRegs;
|
||||
extern volatile struct SPI_REGS SpicRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,403 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_upp.h
|
||||
//
|
||||
// TITLE: Definitions for the UPP registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_UPP_H
|
||||
#define F2837xD_UPP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// UPP Individual Register Bit Definitions:
|
||||
|
||||
struct PERCTL_BITS { // bits description
|
||||
Uint16 FREE:1; // 0 Emulation control.
|
||||
Uint16 SOFT:1; // 1 Emulation control.
|
||||
Uint16 RTEMU:1; // 2 Realtime emulation control.
|
||||
Uint16 PEREN:1; // 3 Peripheral Enable
|
||||
Uint16 SOFTRST:1; // 4 Software Reset
|
||||
Uint16 rsvd1:2; // 6:5 Reserved
|
||||
Uint16 DMAST:1; // 7 DMA Burst transaction status
|
||||
Uint16 rsvd2:8; // 15:8 Reserved
|
||||
Uint16 rsvd3:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union PERCTL_REG {
|
||||
Uint32 all;
|
||||
struct PERCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct CHCTL_BITS { // bits description
|
||||
Uint16 MODE:2; // 1:0 Operating mode
|
||||
Uint16 rsvd1:1; // 2 Reserved
|
||||
Uint16 SDRTXILA:1; // 3 SDR TX Interleve mode
|
||||
Uint16 DEMUXA:1; // 4 DDR de-multiplexing mode
|
||||
Uint16 rsvd2:11; // 15:5 Reserved
|
||||
Uint16 DRA:1; // 16 Data rate
|
||||
Uint16 rsvd3:14; // 30:17 Reserved
|
||||
Uint16 rsvd4:1; // 31 Reserved
|
||||
};
|
||||
|
||||
union CHCTL_REG {
|
||||
Uint32 all;
|
||||
struct CHCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct IFCFG_BITS { // bits description
|
||||
Uint16 STARTPOLA:1; // 0 Polarity of START(SELECT) signal
|
||||
Uint16 ENAPOLA:1; // 1 Polarity of ENABLE(WRITE) signal
|
||||
Uint16 WAITPOLA:1; // 2 Polarity of WAIT signal.
|
||||
Uint16 STARTA:1; // 3 Enable Usage of START (SELECT) signal
|
||||
Uint16 ENAA:1; // 4 Enable Usage of ENABLE (WRITE) signal
|
||||
Uint16 WAITA:1; // 5 Enable Usage of WAIT signal
|
||||
Uint16 rsvd1:2; // 7:6 Reserved
|
||||
Uint16 CLKDIVA:4; // 11:8 Clock divider for tx mode
|
||||
Uint16 CLKINVA:1; // 12 Clock inversion
|
||||
Uint16 TRISENA:1; // 13 Pin Tri-state Control
|
||||
Uint16 rsvd2:2; // 15:14 Reserved
|
||||
Uint16 rsvd3:6; // 21:16 Reserved
|
||||
Uint16 rsvd4:2; // 23:22 Reserved
|
||||
Uint16 rsvd5:6; // 29:24 Reserved
|
||||
Uint16 rsvd6:2; // 31:30 Reserved
|
||||
};
|
||||
|
||||
union IFCFG_REG {
|
||||
Uint32 all;
|
||||
struct IFCFG_BITS bit;
|
||||
};
|
||||
|
||||
struct IFIVAL_BITS { // bits description
|
||||
Uint16 VALA:9; // 8:0 Idle Value
|
||||
Uint16 rsvd1:7; // 15:9 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union IFIVAL_REG {
|
||||
Uint32 all;
|
||||
struct IFIVAL_BITS bit;
|
||||
};
|
||||
|
||||
struct THCFG_BITS { // bits description
|
||||
Uint16 RDSIZEI:2; // 1:0 DMA Read Threshold for DMA Channel I
|
||||
Uint16 rsvd1:6; // 7:2 Reserved
|
||||
Uint16 RDSIZEQ:2; // 9:8 DMA Read Threshold for DMA Channel Q
|
||||
Uint16 rsvd2:6; // 15:10 Reserved
|
||||
Uint16 TXSIZEA:2; // 17:16 I/O Transmit Threshold Value
|
||||
Uint16 rsvd3:6; // 23:18 Reserved
|
||||
Uint16 rsvd4:2; // 25:24 Reserved
|
||||
Uint16 rsvd5:6; // 31:26 Reserved
|
||||
};
|
||||
|
||||
union THCFG_REG {
|
||||
Uint32 all;
|
||||
struct THCFG_BITS bit;
|
||||
};
|
||||
|
||||
struct RAWINTST_BITS { // bits description
|
||||
Uint16 DPEI:1; // 0 Interrupt raw status for DMA programming error
|
||||
Uint16 UOEI:1; // 1 Interrupt raw status for DMA under-run or over-run
|
||||
Uint16 rsvd1:1; // 2 Reserved
|
||||
Uint16 EOWI:1; // 3 Interrupt raw status for end-of window condition
|
||||
Uint16 EOLI:1; // 4 Interrupt raw status for end-of-line condition
|
||||
Uint16 rsvd2:3; // 7:5 Reserved
|
||||
Uint16 DPEQ:1; // 8 Interrupt raw status for DMA programming error
|
||||
Uint16 UOEQ:1; // 9 Interrupt raw status for DMA under-run or over-run
|
||||
Uint16 rsvd3:1; // 10 Reserved
|
||||
Uint16 EOWQ:1; // 11 Interrupt raw status for end-of window condition
|
||||
Uint16 EOLQ:1; // 12 Interrupt raw status for end-of-line condition
|
||||
Uint16 rsvd4:3; // 15:13 Reserved
|
||||
Uint16 rsvd5:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union RAWINTST_REG {
|
||||
Uint32 all;
|
||||
struct RAWINTST_BITS bit;
|
||||
};
|
||||
|
||||
struct ENINTST_BITS { // bits description
|
||||
Uint16 DPEI:1; // 0 Interrupt enable status for DMA programming error
|
||||
Uint16 UOEI:1; // 1 Interrupt enable status for DMA under-run or over-run
|
||||
Uint16 rsvd1:1; // 2 Reserved
|
||||
Uint16 EOWI:1; // 3 Interrupt enable status for end-of window condition
|
||||
Uint16 EOLI:1; // 4 Interrupt enable status for end-of-line condition
|
||||
Uint16 rsvd2:3; // 7:5 Reserved
|
||||
Uint16 DPEQ:1; // 8 Interrupt enable status for DMA programming error
|
||||
Uint16 UOEQ:1; // 9 Interrupt enable status for DMA under-run or over-run
|
||||
Uint16 rsvd3:1; // 10 Reserved
|
||||
Uint16 EOWQ:1; // 11 Interrupt enable status for end-of window condition
|
||||
Uint16 EOLQ:1; // 12 Interrupt enable status for end-of-line condition
|
||||
Uint16 rsvd4:3; // 15:13 Reserved
|
||||
Uint16 rsvd5:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union ENINTST_REG {
|
||||
Uint32 all;
|
||||
struct ENINTST_BITS bit;
|
||||
};
|
||||
|
||||
struct INTENSET_BITS { // bits description
|
||||
Uint16 DPEI:1; // 0 Interrupt enable for DMA programming error
|
||||
Uint16 UOEI:1; // 1 Interrupt enable for DMA under-run or over-run
|
||||
Uint16 rsvd1:1; // 2 Reserved
|
||||
Uint16 EOWI:1; // 3 Interrupt enable for end-of window condition
|
||||
Uint16 EOLI:1; // 4 Interrupt enable for end-of-line condition
|
||||
Uint16 rsvd2:3; // 7:5 Reserved
|
||||
Uint16 DPEQ:1; // 8 Interrupt enable for DMA programming error
|
||||
Uint16 UOEQ:1; // 9 Interrupt enable for DMA under-run or over-run
|
||||
Uint16 rsvd3:1; // 10 Reserved
|
||||
Uint16 EOWQ:1; // 11 Interrupt enable for end-of window condition
|
||||
Uint16 EOLQ:1; // 12 Interrupt enable for end-of-line condition
|
||||
Uint16 rsvd4:3; // 15:13 Reserved
|
||||
Uint16 rsvd5:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union INTENSET_REG {
|
||||
Uint32 all;
|
||||
struct INTENSET_BITS bit;
|
||||
};
|
||||
|
||||
struct INTENCLR_BITS { // bits description
|
||||
Uint16 DPEI:1; // 0 Interrupt clear for DMA programming error
|
||||
Uint16 UOEI:1; // 1 Interrupt clear for DMA under-run or over-run
|
||||
Uint16 rsvd1:1; // 2 Reserved
|
||||
Uint16 EOWI:1; // 3 Interrupt clear for end-of window condition
|
||||
Uint16 EOLI:1; // 4 Interrupt clear for end-of-line condition
|
||||
Uint16 rsvd2:3; // 7:5 Reserved
|
||||
Uint16 DPEQ:1; // 8 Interrupt clear for DMA programming error
|
||||
Uint16 UOEQ:1; // 9 Interrupt clear for DMA under-run or over-run
|
||||
Uint16 rsvd3:1; // 10 Reserved
|
||||
Uint16 EOWQ:1; // 11 Interrupt clear for end-of window condition
|
||||
Uint16 EOLQ:1; // 12 Interrupt clear for end-of-line condition
|
||||
Uint16 rsvd4:3; // 15:13 Reserved
|
||||
Uint16 rsvd5:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union INTENCLR_REG {
|
||||
Uint32 all;
|
||||
struct INTENCLR_BITS bit;
|
||||
};
|
||||
|
||||
struct CHIDESC1_BITS { // bits description
|
||||
Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel I transfer.
|
||||
Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel I transfer.
|
||||
};
|
||||
|
||||
union CHIDESC1_REG {
|
||||
Uint32 all;
|
||||
struct CHIDESC1_BITS bit;
|
||||
};
|
||||
|
||||
struct CHIDESC2_BITS { // bits description
|
||||
Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset.
|
||||
Uint16 rsvd1:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CHIDESC2_REG {
|
||||
Uint32 all;
|
||||
struct CHIDESC2_BITS bit;
|
||||
};
|
||||
|
||||
struct CHIST1_BITS { // bits description
|
||||
Uint16 BCNT:16; // 15:0 Current byte number.
|
||||
Uint16 LCNT:16; // 31:16 Current line number.
|
||||
};
|
||||
|
||||
union CHIST1_REG {
|
||||
Uint32 all;
|
||||
struct CHIST1_BITS bit;
|
||||
};
|
||||
|
||||
struct CHIST2_BITS { // bits description
|
||||
Uint16 ACT:1; // 0 Status of DMA descriptor.
|
||||
Uint16 PEND:1; // 1 Status of DMA.
|
||||
Uint16 rsvd1:2; // 3:2 Reserved
|
||||
Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel I tranfer.
|
||||
Uint16 rsvd2:8; // 15:8 Reserved
|
||||
Uint16 rsvd3:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CHIST2_REG {
|
||||
Uint32 all;
|
||||
struct CHIST2_BITS bit;
|
||||
};
|
||||
|
||||
struct CHQDESC1_BITS { // bits description
|
||||
Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel Q transfer.
|
||||
Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel Q transfer.
|
||||
};
|
||||
|
||||
union CHQDESC1_REG {
|
||||
Uint32 all;
|
||||
struct CHQDESC1_BITS bit;
|
||||
};
|
||||
|
||||
struct CHQDESC2_BITS { // bits description
|
||||
Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset.
|
||||
Uint16 rsvd1:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CHQDESC2_REG {
|
||||
Uint32 all;
|
||||
struct CHQDESC2_BITS bit;
|
||||
};
|
||||
|
||||
struct CHQST1_BITS { // bits description
|
||||
Uint16 BCNT:16; // 15:0 Current byte number.
|
||||
Uint16 LCNT:16; // 31:16 Current line number.
|
||||
};
|
||||
|
||||
union CHQST1_REG {
|
||||
Uint32 all;
|
||||
struct CHQST1_BITS bit;
|
||||
};
|
||||
|
||||
struct CHQST2_BITS { // bits description
|
||||
Uint16 ACT:1; // 0 Status of DMA descriptor.
|
||||
Uint16 PEND:1; // 1 Status of DMA.
|
||||
Uint16 rsvd1:2; // 3:2 Reserved
|
||||
Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel Q tranfer.
|
||||
Uint16 rsvd2:8; // 15:8 Reserved
|
||||
Uint16 rsvd3:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union CHQST2_REG {
|
||||
Uint32 all;
|
||||
struct CHQST2_BITS bit;
|
||||
};
|
||||
|
||||
struct GINTEN_BITS { // bits description
|
||||
Uint16 GINTEN:1; // 0 Global Interrupt Enable
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union GINTEN_REG {
|
||||
Uint32 all;
|
||||
struct GINTEN_BITS bit;
|
||||
};
|
||||
|
||||
struct GINTFLG_BITS { // bits description
|
||||
Uint16 GINTFLG:1; // 0 Global Interrupt Flag
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union GINTFLG_REG {
|
||||
Uint32 all;
|
||||
struct GINTFLG_BITS bit;
|
||||
};
|
||||
|
||||
struct GINTCLR_BITS { // bits description
|
||||
Uint16 GINTCLR:1; // 0 Global Interrupt Clear
|
||||
Uint16 rsvd1:15; // 15:1 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union GINTCLR_REG {
|
||||
Uint32 all;
|
||||
struct GINTCLR_BITS bit;
|
||||
};
|
||||
|
||||
struct DLYCTL_BITS { // bits description
|
||||
Uint16 DLYDIS:1; // 0 IO dealy control disable.
|
||||
Uint16 DLYCTL:2; // 2:1 IO delay control.
|
||||
Uint16 rsvd1:13; // 15:3 Reserved
|
||||
Uint16 rsvd2:16; // 31:16 Reserved
|
||||
};
|
||||
|
||||
union DLYCTL_REG {
|
||||
Uint32 all;
|
||||
struct DLYCTL_BITS bit;
|
||||
};
|
||||
|
||||
struct UPP_REGS {
|
||||
Uint32 PID; // Peripheral ID Register
|
||||
union PERCTL_REG PERCTL; // Peripheral Control Register
|
||||
Uint16 rsvd1[4]; // Reserved
|
||||
union CHCTL_REG CHCTL; // General Control Register
|
||||
union IFCFG_REG IFCFG; // Interface Configuration Register
|
||||
union IFIVAL_REG IFIVAL; // Interface Idle Value Register
|
||||
union THCFG_REG THCFG; // Threshold Configuration Register
|
||||
union RAWINTST_REG RAWINTST; // Raw Interrupt Status Register
|
||||
union ENINTST_REG ENINTST; // Enable Interrupt Status Register
|
||||
union INTENSET_REG INTENSET; // Interrupt Enable Set Register
|
||||
union INTENCLR_REG INTENCLR; // Interrupt Enable Clear Register
|
||||
Uint16 rsvd2[8]; // Reserved
|
||||
Uint32 CHIDESC0; // DMA Channel I Descriptor 0 Register
|
||||
union CHIDESC1_REG CHIDESC1; // DMA Channel I Descriptor 1 Register
|
||||
union CHIDESC2_REG CHIDESC2; // DMA Channel I Descriptor 2 Register
|
||||
Uint16 rsvd3[2]; // Reserved
|
||||
Uint32 CHIST0; // DMA Channel I Status 0 Register
|
||||
union CHIST1_REG CHIST1; // DMA Channel I Status 1 Register
|
||||
union CHIST2_REG CHIST2; // DMA Channel I Status 2 Register
|
||||
Uint16 rsvd4[2]; // Reserved
|
||||
Uint32 CHQDESC0; // DMA Channel Q Descriptor 0 Register
|
||||
union CHQDESC1_REG CHQDESC1; // DMA Channel Q Descriptor 1 Register
|
||||
union CHQDESC2_REG CHQDESC2; // DMA Channel Q Descriptor 2 Register
|
||||
Uint16 rsvd5[2]; // Reserved
|
||||
Uint32 CHQST0; // DMA Channel Q Status 0 Register
|
||||
union CHQST1_REG CHQST1; // DMA Channel Q Status 1 Register
|
||||
union CHQST2_REG CHQST2; // DMA Channel Q Status 2 Register
|
||||
Uint16 rsvd6[2]; // Reserved
|
||||
union GINTEN_REG GINTEN; // Global Peripheral Interrupt Enable Register
|
||||
union GINTFLG_REG GINTFLG; // Global Peripheral Interrupt Flag Register
|
||||
union GINTCLR_REG GINTCLR; // Global Peripheral Interrupt Clear Register
|
||||
union DLYCTL_REG DLYCTL; // IO clock data skew control Register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// UPP External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct UPP_REGS UppRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,302 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_xbar.h
|
||||
//
|
||||
// TITLE: Definitions for the XBAR registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_XBAR_H
|
||||
#define F2837xD_XBAR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// XBAR Individual Register Bit Definitions:
|
||||
|
||||
struct XBARFLG1_BITS { // bits description
|
||||
Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal
|
||||
Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal
|
||||
Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal
|
||||
Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal
|
||||
Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal
|
||||
Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal
|
||||
Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal
|
||||
Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal
|
||||
Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal
|
||||
Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal
|
||||
Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal
|
||||
Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal
|
||||
Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal
|
||||
Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal
|
||||
Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal
|
||||
Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal
|
||||
Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal
|
||||
Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal
|
||||
Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal
|
||||
Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal
|
||||
Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal
|
||||
Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal
|
||||
Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal
|
||||
Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal
|
||||
Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal
|
||||
Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal
|
||||
Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal
|
||||
Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal
|
||||
Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal
|
||||
Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal
|
||||
Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal
|
||||
Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal
|
||||
};
|
||||
|
||||
union XBARFLG1_REG {
|
||||
Uint32 all;
|
||||
struct XBARFLG1_BITS bit;
|
||||
};
|
||||
|
||||
struct XBARFLG2_BITS { // bits description
|
||||
Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal
|
||||
Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal
|
||||
Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal
|
||||
Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal
|
||||
Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal
|
||||
Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal
|
||||
Uint16 ADCSOCAO:1; // 6 Input Flag for ADCSOCAO Signal
|
||||
Uint16 ADCSOCBO:1; // 7 Input Flag for ADCSOCBO Signal
|
||||
Uint16 CLB1_OUT4:1; // 8 Input Flag for CLB1_OUT4 Signal
|
||||
Uint16 CLB1_OUT5:1; // 9 Input Flag for CLB1_OUT5 Signal
|
||||
Uint16 CLB2_OUT4:1; // 10 Input Flag for CLB2_OUT4 Signal
|
||||
Uint16 CLB2_OUT5:1; // 11 Input Flag for CLB2_OUT5 Signal
|
||||
Uint16 CLB3_OUT4:1; // 12 Input Flag for CLB3_OUT4 Signal
|
||||
Uint16 CLB3_OUT5:1; // 13 Input Flag for CLB3_OUT5 Signal
|
||||
Uint16 CLB4_OUT4:1; // 14 Input Flag for CLB4_OUT4 Signal
|
||||
Uint16 CLB4_OUT5:1; // 15 Input Flag for CLB4_OUT5 Signal
|
||||
Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal
|
||||
Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal
|
||||
Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal
|
||||
Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal
|
||||
Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal
|
||||
Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal
|
||||
Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal
|
||||
Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal
|
||||
Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal
|
||||
Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal
|
||||
Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal
|
||||
Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal
|
||||
Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal
|
||||
Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal
|
||||
Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal
|
||||
Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal
|
||||
};
|
||||
|
||||
union XBARFLG2_REG {
|
||||
Uint32 all;
|
||||
struct XBARFLG2_BITS bit;
|
||||
};
|
||||
|
||||
struct XBARFLG3_BITS { // bits description
|
||||
Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal
|
||||
Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal
|
||||
Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal
|
||||
Uint16 ADCDEVT1:1; // 3 Input Flag for ADCDEVT1 Signal
|
||||
Uint16 ADCDEVT2:1; // 4 Input Flag for ADCDEVT2 Signal
|
||||
Uint16 ADCDEVT3:1; // 5 Input Flag for ADCDEVT3 Signal
|
||||
Uint16 ADCDEVT4:1; // 6 Input Flag for ADCDEVT4 Signal
|
||||
Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal
|
||||
Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal
|
||||
Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal
|
||||
Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal
|
||||
Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal
|
||||
Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal
|
||||
Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal
|
||||
Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal
|
||||
Uint16 SD2FLT1_COMPL:1; // 15 Input Flag for SD2FLT1.COMPL Signal
|
||||
Uint16 SD2FLT1_COMPH:1; // 16 Input Flag for SD2FLT1.COMPH Signal
|
||||
Uint16 SD2FLT2_COMPL:1; // 17 Input Flag for SD2FLT2.COMPL Signal
|
||||
Uint16 SD2FLT2_COMPH:1; // 18 Input Flag for SD2FLT2.COMPH Signal
|
||||
Uint16 SD2FLT3_COMPL:1; // 19 Input Flag for SD2FLT3.COMPL Signal
|
||||
Uint16 SD2FLT3_COMPH:1; // 20 Input Flag for SD2FLT3.COMPH Signal
|
||||
Uint16 SD2FLT4_COMPL:1; // 21 Input Flag for SD2FLT4.COMPL Signal
|
||||
Uint16 SD2FLT4_COMPH:1; // 22 Input Flag for SD2FLT4.COMPH Signal
|
||||
Uint16 rsvd1:9; // 31:23 Reserved
|
||||
};
|
||||
|
||||
union XBARFLG3_REG {
|
||||
Uint32 all;
|
||||
struct XBARFLG3_BITS bit;
|
||||
};
|
||||
|
||||
struct XBARCLR1_BITS { // bits description
|
||||
Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal
|
||||
Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal
|
||||
Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal
|
||||
Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal
|
||||
Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal
|
||||
Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal
|
||||
Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal
|
||||
Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal
|
||||
Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal
|
||||
Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal
|
||||
Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal
|
||||
Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal
|
||||
Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal
|
||||
Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal
|
||||
Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal
|
||||
Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal
|
||||
Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal
|
||||
Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal
|
||||
Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal
|
||||
Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal
|
||||
Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal
|
||||
Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal
|
||||
Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal
|
||||
Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal
|
||||
Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal
|
||||
Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal
|
||||
Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal
|
||||
Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal
|
||||
Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal
|
||||
Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal
|
||||
Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal
|
||||
Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal
|
||||
};
|
||||
|
||||
union XBARCLR1_REG {
|
||||
Uint32 all;
|
||||
struct XBARCLR1_BITS bit;
|
||||
};
|
||||
|
||||
struct XBARCLR2_BITS { // bits description
|
||||
Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal
|
||||
Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal
|
||||
Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal
|
||||
Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal
|
||||
Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal
|
||||
Uint16 INPUT7:1; // 5 Input Flag Clear for INPUT7 Signal
|
||||
Uint16 ADCSOCAO:1; // 6 Input Flag Clear for ADCSOCAO Signal
|
||||
Uint16 ADCSOCBO:1; // 7 Input Flag Clear for ADCSOCBO Signal
|
||||
Uint16 CLB1_OUT4:1; // 8 Input Flag Clear for CLB1_OUT4 Signal
|
||||
Uint16 CLB1_OUT5:1; // 9 Input Flag Clear for CLB1_OUT5 Signal
|
||||
Uint16 CLB2_OUT4:1; // 10 Input Flag Clear for CLB2_OUT4 Signal
|
||||
Uint16 CLB2_OUT5:1; // 11 Input Flag Clear for CLB2_OUT5 Signal
|
||||
Uint16 CLB3_OUT4:1; // 12 Input Flag Clear for CLB3_OUT4 Signal
|
||||
Uint16 CLB3_OUT5:1; // 13 Input Flag Clear for CLB3_OUT5 Signal
|
||||
Uint16 CLB4_OUT4:1; // 14 Input Flag Clear for CLB4_OUT4 Signal
|
||||
Uint16 CLB4_OUT5:1; // 15 Input Flag Clear for CLB4_OUT5 Signal
|
||||
Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal
|
||||
Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal
|
||||
Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal
|
||||
Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal
|
||||
Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal
|
||||
Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal
|
||||
Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal
|
||||
Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal
|
||||
Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal
|
||||
Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal
|
||||
Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal
|
||||
Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal
|
||||
Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal
|
||||
Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal
|
||||
Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal
|
||||
Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal
|
||||
};
|
||||
|
||||
union XBARCLR2_REG {
|
||||
Uint32 all;
|
||||
struct XBARCLR2_BITS bit;
|
||||
};
|
||||
|
||||
struct XBARCLR3_BITS { // bits description
|
||||
Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal
|
||||
Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal
|
||||
Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal
|
||||
Uint16 ADCDEVT1:1; // 3 Input Flag Clear for ADCDEVT1 Signal
|
||||
Uint16 ADCDEVT2:1; // 4 Input Flag Clear for ADCDEVT2 Signal
|
||||
Uint16 ADCDEVT3:1; // 5 Input Flag Clear for ADCDEVT3 Signal
|
||||
Uint16 ADCDEVT4:1; // 6 Input Flag Clear for ADCDEVT4 Signal
|
||||
Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal
|
||||
Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal
|
||||
Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal
|
||||
Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal
|
||||
Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal
|
||||
Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal
|
||||
Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal
|
||||
Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal
|
||||
Uint16 SD2FLT1_COMPL:1; // 15 Input Flag Clear for SD2FLT1.COMPL Signal
|
||||
Uint16 SD2FLT1_COMPH:1; // 16 Input Flag Clear for SD2FLT1.COMPH Signal
|
||||
Uint16 SD2FLT2_COMPL:1; // 17 Input Flag Clear for SD2FLT2.COMPL Signal
|
||||
Uint16 SD2FLT2_COMPH:1; // 18 Input Flag Clear for SD2FLT2.COMPH Signal
|
||||
Uint16 SD2FLT3_COMPL:1; // 19 Input Flag Clear for SD2FLT3.COMPL Signal
|
||||
Uint16 SD2FLT3_COMPH:1; // 20 Input Flag Clear for SD2FLT3.COMPH Signal
|
||||
Uint16 SD2FLT4_COMPL:1; // 21 Input Flag Clear for SD2FLT4.COMPL Signal
|
||||
Uint16 SD2FLT4_COMPH:1; // 22 Input Flag Clear for SD2FLT4.COMPH Signal
|
||||
Uint16 rsvd1:9; // 31:23 Reserved
|
||||
};
|
||||
|
||||
union XBARCLR3_REG {
|
||||
Uint32 all;
|
||||
struct XBARCLR3_BITS bit;
|
||||
};
|
||||
|
||||
struct XBAR_REGS {
|
||||
union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1
|
||||
union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2
|
||||
union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3
|
||||
Uint16 rsvd1[2]; // Reserved
|
||||
union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1
|
||||
union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2
|
||||
union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// XBAR External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct XBAR_REGS XbarRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,143 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_xint.h
|
||||
//
|
||||
// TITLE: Definitions for the XINT registers.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_XINT_H
|
||||
#define F2837xD_XINT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// XINT Individual Register Bit Definitions:
|
||||
|
||||
struct XINT1CR_BITS { // bits description
|
||||
Uint16 ENABLE:1; // 0 XINT1 Enable
|
||||
Uint16 rsvd1:1; // 1 Reserved
|
||||
Uint16 POLARITY:2; // 3:2 XINT1 Polarity
|
||||
Uint16 rsvd2:12; // 15:4 Reserved
|
||||
};
|
||||
|
||||
union XINT1CR_REG {
|
||||
Uint16 all;
|
||||
struct XINT1CR_BITS bit;
|
||||
};
|
||||
|
||||
struct XINT2CR_BITS { // bits description
|
||||
Uint16 ENABLE:1; // 0 XINT2 Enable
|
||||
Uint16 rsvd1:1; // 1 Reserved
|
||||
Uint16 POLARITY:2; // 3:2 XINT2 Polarity
|
||||
Uint16 rsvd2:12; // 15:4 Reserved
|
||||
};
|
||||
|
||||
union XINT2CR_REG {
|
||||
Uint16 all;
|
||||
struct XINT2CR_BITS bit;
|
||||
};
|
||||
|
||||
struct XINT3CR_BITS { // bits description
|
||||
Uint16 ENABLE:1; // 0 XINT3 Enable
|
||||
Uint16 rsvd1:1; // 1 Reserved
|
||||
Uint16 POLARITY:2; // 3:2 XINT3 Polarity
|
||||
Uint16 rsvd2:12; // 15:4 Reserved
|
||||
};
|
||||
|
||||
union XINT3CR_REG {
|
||||
Uint16 all;
|
||||
struct XINT3CR_BITS bit;
|
||||
};
|
||||
|
||||
struct XINT4CR_BITS { // bits description
|
||||
Uint16 ENABLE:1; // 0 XINT4 Enable
|
||||
Uint16 rsvd1:1; // 1 Reserved
|
||||
Uint16 POLARITY:2; // 3:2 XINT4 Polarity
|
||||
Uint16 rsvd2:12; // 15:4 Reserved
|
||||
};
|
||||
|
||||
union XINT4CR_REG {
|
||||
Uint16 all;
|
||||
struct XINT4CR_BITS bit;
|
||||
};
|
||||
|
||||
struct XINT5CR_BITS { // bits description
|
||||
Uint16 ENABLE:1; // 0 XINT5 Enable
|
||||
Uint16 rsvd1:1; // 1 Reserved
|
||||
Uint16 POLARITY:2; // 3:2 XINT5 Polarity
|
||||
Uint16 rsvd2:12; // 15:4 Reserved
|
||||
};
|
||||
|
||||
union XINT5CR_REG {
|
||||
Uint16 all;
|
||||
struct XINT5CR_BITS bit;
|
||||
};
|
||||
|
||||
struct XINT_REGS {
|
||||
union XINT1CR_REG XINT1CR; // XINT1 configuration register
|
||||
union XINT2CR_REG XINT2CR; // XINT2 configuration register
|
||||
union XINT3CR_REG XINT3CR; // XINT3 configuration register
|
||||
union XINT4CR_REG XINT4CR; // XINT4 configuration register
|
||||
union XINT5CR_REG XINT5CR; // XINT5 configuration register
|
||||
Uint16 rsvd1[3]; // Reserved
|
||||
Uint16 XINT1CTR; // XINT1 counter register
|
||||
Uint16 XINT2CTR; // XINT2 counter register
|
||||
Uint16 XINT3CTR; // XINT3 counter register
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// XINT External References & Function Declarations:
|
||||
//
|
||||
#ifdef CPU1
|
||||
extern volatile struct XINT_REGS XintRegs;
|
||||
#endif
|
||||
#ifdef CPU2
|
||||
extern volatile struct XINT_REGS XintRegs;
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@@ -0,0 +1,961 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_globalvariabledefs.c
|
||||
//
|
||||
// TITLE: F2837xD Global Variables and Data Section Pragmas.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "F2837xD_device.h" // F2837xD Headerfile Include File
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Define Global Peripheral Variables:
|
||||
//
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AccessProtectionRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile");
|
||||
#endif
|
||||
volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_REGS AdcaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_REGS AdcbRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdccRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdccRegs,"AdccRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_REGS AdccRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcdRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcdRegs,"AdcdRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_REGS AdcdRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcaResultRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_RESULT_REGS AdcaResultRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcbResultRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_RESULT_REGS AdcbResultRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdccResultRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdccResultRegs,"AdccResultRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_RESULT_REGS AdccResultRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcdResultRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcdResultRegs,"AdcdResultRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_RESULT_REGS AdcdResultRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AnalogSubsysRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile");
|
||||
#endif
|
||||
volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
#if __TI_COMPILER_VERSION__ >= 16006000
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CanaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CanaRegs,"CanaRegsFile");
|
||||
#endif
|
||||
volatile struct CAN_REGS CanaRegs;
|
||||
#endif // __TI_COMPILER_VERSION__ >= 16006000
|
||||
|
||||
#if __TI_COMPILER_VERSION__ >= 16006000
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CanbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CanbRegs,"CanbRegsFile");
|
||||
#endif
|
||||
volatile struct CAN_REGS CanbRegs;
|
||||
#endif // __TI_COMPILER_VERSION__ >= 16006000
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cla1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile");
|
||||
#endif
|
||||
volatile struct CLA_REGS Cla1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb1DataExchRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb1DataExchRegs,"Clb1DataExchRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_DATA_EXCHANGE_REGS Clb1DataExchRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb2DataExchRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb2DataExchRegs,"Clb2DataExchRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_DATA_EXCHANGE_REGS Clb2DataExchRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb3DataExchRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb3DataExchRegs,"Clb3DataExchRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_DATA_EXCHANGE_REGS Clb3DataExchRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb4DataExchRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb4DataExchRegs,"Clb4DataExchRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_DATA_EXCHANGE_REGS Clb4DataExchRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb1LogicCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb1LogicCfgRegs,"Clb1LogicCfgRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONFIG_REGS Clb1LogicCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb2LogicCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb2LogicCfgRegs,"Clb2LogicCfgRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONFIG_REGS Clb2LogicCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb3LogicCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb3LogicCfgRegs,"Clb3LogicCfgRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONFIG_REGS Clb3LogicCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb4LogicCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb4LogicCfgRegs,"Clb4LogicCfgRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONFIG_REGS Clb4LogicCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb1LogicCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb1LogicCtrlRegs,"Clb1LogicCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONTROL_REGS Clb1LogicCtrlRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb2LogicCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb2LogicCtrlRegs,"Clb2LogicCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONTROL_REGS Clb2LogicCtrlRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb3LogicCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb3LogicCtrlRegs,"Clb3LogicCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONTROL_REGS Clb3LogicCtrlRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Clb4LogicCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Clb4LogicCtrlRegs,"Clb4LogicCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_LOGIC_CONTROL_REGS Clb4LogicCtrlRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ClbXbarRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ClbXbarRegs,"ClbXbarRegsFile");
|
||||
#endif
|
||||
volatile struct CLB_XBAR_REGS ClbXbarRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ClkCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile");
|
||||
#endif
|
||||
volatile struct CLK_CFG_REGS ClkCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss3RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss3Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss4RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss4Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss5RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss5Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss6RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss6Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss7RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss7Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Cmpss8RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile");
|
||||
#endif
|
||||
volatile struct CMPSS_REGS Cmpss8Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuTimer0RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile");
|
||||
#endif
|
||||
volatile struct CPUTIMER_REGS CpuTimer0Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuTimer1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile");
|
||||
#endif
|
||||
volatile struct CPUTIMER_REGS CpuTimer1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuTimer2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile");
|
||||
#endif
|
||||
volatile struct CPUTIMER_REGS CpuTimer2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuSysRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile");
|
||||
#endif
|
||||
volatile struct CPU_SYS_REGS CpuSysRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DacaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DacaRegs,"DacaRegsFile");
|
||||
#endif
|
||||
volatile struct DAC_REGS DacaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DacbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DacbRegs,"DacbRegsFile");
|
||||
#endif
|
||||
volatile struct DAC_REGS DacbRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DaccRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DaccRegs,"DaccRegsFile");
|
||||
#endif
|
||||
volatile struct DAC_REGS DaccRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DcsmCommonRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile");
|
||||
#endif
|
||||
volatile struct DCSM_COMMON_REGS DcsmCommonRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DcsmZ1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile");
|
||||
#endif
|
||||
volatile struct DCSM_Z1_REGS DcsmZ1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DcsmZ2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile");
|
||||
#endif
|
||||
volatile struct DCSM_Z2_REGS DcsmZ2Regs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DevCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile");
|
||||
#endif
|
||||
volatile struct DEV_CFG_REGS DevCfgRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DmaClaSrcSelRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile");
|
||||
#endif
|
||||
volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DmaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DmaRegs,"DmaRegsFile");
|
||||
#endif
|
||||
volatile struct DMA_REGS DmaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap3RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap3Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap4RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap4Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap5RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap5Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap6RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap6Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Emif1ConfigRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile");
|
||||
#endif
|
||||
volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Emif2ConfigRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile");
|
||||
#endif
|
||||
volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Emif1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile");
|
||||
#endif
|
||||
volatile struct EMIF_REGS Emif1Regs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Emif2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile");
|
||||
#endif
|
||||
volatile struct EMIF_REGS Emif2Regs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm3RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm3Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm4RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm4Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm5RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm5Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm6RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm6Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm7RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm7Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm8RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm8Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm9RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm9Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm10RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm10Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm11RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm11Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm12RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm12Regs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwmXbarRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_XBAR_REGS EPwmXbarRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EQep1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile");
|
||||
#endif
|
||||
volatile struct EQEP_REGS EQep1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EQep2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile");
|
||||
#endif
|
||||
volatile struct EQEP_REGS EQep2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EQep3RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile");
|
||||
#endif
|
||||
volatile struct EQEP_REGS EQep3Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Flash0CtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile");
|
||||
#endif
|
||||
volatile struct FLASH_CTRL_REGS Flash0CtrlRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Flash0EccRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile");
|
||||
#endif
|
||||
volatile struct FLASH_ECC_REGS Flash0EccRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile");
|
||||
#endif
|
||||
volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("GpioCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("GpioDataRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile");
|
||||
#endif
|
||||
volatile struct GPIO_DATA_REGS GpioDataRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("I2caRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(I2caRegs,"I2caRegsFile");
|
||||
#endif
|
||||
volatile struct I2C_REGS I2caRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("I2cbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile");
|
||||
#endif
|
||||
volatile struct I2C_REGS I2cbRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("InputXbarRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile");
|
||||
#endif
|
||||
volatile struct INPUT_XBAR_REGS InputXbarRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("IpcRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(IpcRegs,"IpcRegsFile");
|
||||
#endif
|
||||
volatile struct IPC_REGS_CPU1 IpcRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
#ifdef CPU2
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("IpcRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(IpcRegs,"IpcRegsFile");
|
||||
#endif
|
||||
volatile struct IPC_REGS_CPU2 IpcRegs;
|
||||
#endif // ifdef CPU2
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("MemoryErrorRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile");
|
||||
#endif
|
||||
volatile struct MEMORY_ERROR_REGS MemoryErrorRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("MemCfgRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile");
|
||||
#endif
|
||||
volatile struct MEM_CFG_REGS MemCfgRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("McbspaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile");
|
||||
#endif
|
||||
volatile struct McBSP_REGS McbspaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("McbspbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile");
|
||||
#endif
|
||||
volatile struct McBSP_REGS McbspbRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("NmiIntruptRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile");
|
||||
#endif
|
||||
volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("OutputXbarRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile");
|
||||
#endif
|
||||
volatile struct OUTPUT_XBAR_REGS OutputXbarRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("PieCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct PIE_CTRL_REGS PieCtrlRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("PieVectTableFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(PieVectTable,"PieVectTableFile");
|
||||
#endif
|
||||
volatile struct PIE_VECT_TABLE PieVectTable;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("RomPrefetchRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile");
|
||||
#endif
|
||||
volatile struct ROM_PREFETCH_REGS RomPrefetchRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("RomWaitStateRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile");
|
||||
#endif
|
||||
volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SciaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SciaRegs,"SciaRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS SciaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ScibRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ScibRegs,"ScibRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS ScibRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ScicRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ScicRegs,"ScicRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS ScicRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ScidRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ScidRegs,"ScidRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS ScidRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Sdfm1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile");
|
||||
#endif
|
||||
volatile struct SDFM_REGS Sdfm1Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("Sdfm2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile");
|
||||
#endif
|
||||
volatile struct SDFM_REGS Sdfm2Regs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SpiaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile");
|
||||
#endif
|
||||
volatile struct SPI_REGS SpiaRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SpibRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SpibRegs,"SpibRegsFile");
|
||||
#endif
|
||||
volatile struct SPI_REGS SpibRegs;
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SpicRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SpicRegs,"SpicRegsFile");
|
||||
#endif
|
||||
volatile struct SPI_REGS SpicRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SyncSocRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile");
|
||||
#endif
|
||||
volatile struct SYNC_SOC_REGS SyncSocRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("UidRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(UidRegs,"UidRegsFile");
|
||||
#endif
|
||||
volatile struct UID_REGS UidRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("UppRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(UppRegs,"UppRegsFile");
|
||||
#endif
|
||||
volatile struct UPP_REGS UppRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("WdRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(WdRegs,"WdRegsFile");
|
||||
#endif
|
||||
volatile struct WD_REGS WdRegs;
|
||||
|
||||
#ifdef CPU1
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("XbarRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(XbarRegs,"XbarRegsFile");
|
||||
#endif
|
||||
volatile struct XBAR_REGS XbarRegs;
|
||||
#endif // ifdef CPU1
|
||||
|
||||
//----------------------------------------
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("XintRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(XintRegs,"XintRegsFile");
|
||||
#endif
|
||||
volatile struct XINT_REGS XintRegs;
|
||||
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
|
||||
|
||||
Reference in New Issue
Block a user