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hangpersonal
2026-08-30 23:04:35 -07:00
parent 749dab5721
commit ce65a0f59a
14950 changed files with 4408250 additions and 1 deletions
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C2000Ware/driverlib/.meta/device/functions_c/BootCM/Boot_CM.xdt
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//*****************************************************************************
//
// Function to boot CM
// Available bootmodes :
// - BOOTMODE_BOOT_TO_FLASH_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_SECTOR4
// - BOOTMODE_BOOT_TO_FLASH_SECTOR8
// - BOOTMODE_BOOT_TO_FLASH_SECTOR13
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13
// - BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_S0RAM
// - BOOTMODE_BOOT_TO_S0RAM
// - BOOTMODE_BOOT_TO_USEROTP
//
// Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM,
// BOOTMODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
//
// This function must be called after Device_init function
//
//*****************************************************************************
void Device_bootCM(uint32_t bootmode)
{
//
// Configure the CPU1TOCMIPCBOOTMODE register
//
IPC_setBootMode(IPC_CPU1_L_CM_R,
(BOOT_KEY | CM_BOOT_FREQ_125MHZ | bootmode));
//
// Set IPC Flag 0
//
IPC_setFlagLtoR(IPC_CPU1_L_CM_R, IPC_FLAG0);
//
// Bring CM out of reset. Wait for CM to go out of reset.
//
SysCtl_controlCMReset(SYSCTL_CORE_DEACTIVE);
while(SysCtl_isCMReset() == 0x1U);
}
C2000Ware/driverlib/.meta/device/functions_c/BootCPU2/Boot_CPU2.xdt
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%%{
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let Common = system.getScript("/driverlib/Common.js");
var Boot_CPU2_Bank0_Bank4 = system.getTemplate('./Boot_CPU2_Bank0_Bank4.xdt');
var Boot_CPU2_Sector0_Sector13 = system.getTemplate('./Boot_CPU2_Sector0_Sector13.xdt');
var Boot_CPU2_Boot_Mode = system.getTemplate('./Boot_CPU2_Boot_Mode.xdt');
const device = device_common.device;
const Boot_CPU2_Type0 = device_common.Boot_CPU2_Type0;
const Boot_CPU2_Type1 = device_common.Boot_CPU2_Type1;
const Boot_CPU2_Boot_Mode_Type0 = device_common.Boot_CPU2_Boot_Mode_Type0;
%%}
% if(Boot_CPU2_Type0.includes(device) && Common.isContextCPU1())
%{
#ifdef CPU1
`Boot_CPU2_Sector0_Sector13()`
%}
% if(Boot_CPU2_Type1.includes(device) && Common.isContextCPU1())
%{
`Boot_CPU2_Bank0_Bank4()`
%}
% if(Boot_CPU2_Boot_Mode_Type0.includes(device) && Common.isContextCPU1())
%{
`Boot_CPU2_Boot_Mode()`
%}
%else{}
C2000Ware/driverlib/.meta/device/functions_c/BootCPU2/Boot_CPU2_Bank0_Bank4.xdt
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#ifdef CPU1
//*****************************************************************************
//
// Function to boot CPU2
// Available bootmodes :
// - BOOTMODE_BOOT_TO_FLASH_BANK0_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_BANK0_SECTOR127_END
// - BOOTMODE_BOOT_TO_FLASH_BANK1_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_BANK2_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_BANK3_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_BANK4_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_BANK4_SECTOR127_END
// - BOOTMODE_BOOT_TO_SECURE_FLASH_BANK0_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_BANK1_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_BANK2_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_BANK3_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_BANK4_SECTOR0
// - BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM
// - BOOTMODE_BOOT_TO_M0RAM
// - BOOTMODE_BOOT_TO_FWU_FLASH
// - BOOTMODE_BOOT_TO_FWU_FLASH_ALT1
// - BOOTMODE_BOOT_TO_FWU_FLASH_ALT2
// - BOOTMODE_BOOT_TO_FWU_FLASH_ALT3
//
// Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM,
// BOOTMODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
//
// This function must be called after Device_init function
//
//*****************************************************************************
void Device_bootCPU2(uint32_t bootmode)
{
//
// Configure the CPU1TOCPU2IPCBOOTMODE register
//
IPC_setBootMode(IPC_CPU1_L_CPU2_R,
(BOOT_KEY | bootmode));
//
// Set IPC Flag 0
//
IPC_setFlagLtoR(IPC_CPU1_L_CPU2_R, IPC_FLAG0);
//
// Bring CPU2 out of reset. Wait for CPU2 to go out of reset.
//
SysCtl_controlCPU2Reset(SYSCTL_CORE_DEACTIVE);
while(SysCtl_isCPU2Reset() == 0x1U);
}
#endif
C2000Ware/driverlib/.meta/device/functions_c/BootCPU2/Boot_CPU2_Boot_Mode.xdt
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//*****************************************************************************
//! Executes a CPU02 control system bootloader.
//!
//! \param bootMode specifies which CPU02 control system boot mode to execute.
//!
//! This function will allow the CPU01 controller system to boot the CPU02 control
//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI,
//! SCI, I2C, or parallel I/O. This function blocks and waits until the
//! control system boot ROM is configured and ready to receive CPU01 to CPU02
//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and
//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the
//! command to execute the selected bootloader.
//!
//! The \e bootMode parameter accepts one of the following values:
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH
//!
//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is
//! invalid and command was not sent.
//
//*****************************************************************************
uint16_t
Device_bootCPU2(uint32_t bootMode)
{
uint32_t bootStatus;
uint16_t pin;
uint16_t returnStatus = STATUS_PASS;
//
// If CPU2 has already booted, return a fail to let the application
// know that something is out of the ordinary.
//
bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & 0x0000000FU;
if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK)
{
//
// Check if MSB is set as well
//
bootStatus = ((uint32_t)(HWREG(IPC_BASE + IPC_O_BOOTSTS) &
0x80000000U)) >> 31U;
if(bootStatus != 0)
{
returnStatus = STATUS_FAIL;
return returnStatus;
}
}
//
// Wait until CPU02 control system boot ROM is ready to receive
// CPU01 to CPU02 INT1 interrupts.
//
do
{
bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) &
C2_BOOTROM_BOOTSTS_SYSTEM_READY;
} while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY));
//
// Loop until CPU02 control system IPC flags 1 and 32 are available
//
while (((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC0) != 0U) ||
((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC31) != 0U))
{
}
if (bootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE)
{
returnStatus = STATUS_FAIL;
}
else
{
//
// Based on boot mode, enable pull-ups on peripheral pins and
// give GPIO pin control to CPU02 control system.
//
switch (bootMode)
{
case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI:
//
//SCIA connected to CPU02
//
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL5_SCI, 1,
SYSCTL_CPUSEL_CPU2);
//
//Allows CPU02 bootrom to take control of clock
//configuration registers
//
EALLOW;
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U;
EDIS;
GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT);
GPIO_setQualificationMode(29, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_29_SCITXDA);
GPIO_setControllerCore(29, GPIO_CORE_CPU2);
GPIO_setDirectionMode(28, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(28, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_28_SCIRXDA);
GPIO_setControllerCore(28, GPIO_CORE_CPU2);
break;
case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI:
//
//SPI-A connected to CPU02
//
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL6_SPI, 1,
SYSCTL_CPUSEL_CPU2);
//
//Allows CPU02 bootrom to take control of clock configuration
// registers
//
EALLOW;
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
EDIS;
GPIO_setDirectionMode(16, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_16_SPISIMOA);
GPIO_setControllerCore(16, GPIO_CORE_CPU2);
GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(17, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_17_SPISOMIA);
GPIO_setControllerCore(17, GPIO_CORE_CPU2);
GPIO_setDirectionMode(18, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(18, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_18_SPICLKA);
GPIO_setControllerCore(18, GPIO_CORE_CPU2);
GPIO_setDirectionMode(19, GPIO_DIR_MODE_OUT);
GPIO_setQualificationMode(19, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_19_GPIO19);
GPIO_setControllerCore(19, GPIO_CORE_CPU2);
break;
case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C:
//
//I2CA connected to CPU02
//
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL7_I2C, 1,
SYSCTL_CPUSEL_CPU2);
//
//Allows CPU2 bootrom to take control of clock
//configuration registers
//
EALLOW;
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U;
EDIS;
GPIO_setDirectionMode(32, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(32, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_32_SDAA);
GPIO_setControllerCore(32, GPIO_CORE_CPU2);
GPIO_setDirectionMode(33, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(33, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_33_SCLA);
GPIO_setControllerCore(33, GPIO_CORE_CPU2);
break;
case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL:
for(pin=58;pin<=65;pin++)
{
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
GPIO_setControllerCore(pin, GPIO_CORE_CPU2);
}
GPIO_setDirectionMode(69, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(69, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_69_GPIO69);
GPIO_setControllerCore(69, GPIO_CORE_CPU2);
GPIO_setDirectionMode(70, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_70_GPIO70);
GPIO_setControllerCore(70, GPIO_CORE_CPU2);
break;
case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN:
//
//Set up the GPIO mux to bring out CANATX on GPIO71
//and CANARX on GPIO70
//
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU);
GPIO_setControllerCore(71, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_71_CANTXA);
GPIO_setQualificationMode(71, GPIO_QUAL_ASYNC);
GPIO_setControllerCore(70, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_70_CANRXA);
GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC);
GPIO_lockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU);
//
// Set CANA Bit-Clock Source Select = SYSCLK and enable CAN
//
EALLOW;
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &=
SYSCTL_CLKSRCCTL2_CANABCLKSEL_M;
EDIS;
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA);
break;
}
//
//CPU01 to CPU02 IPC Boot Mode Register
//
HWREG(IPC_BASE + IPC_O_BOOTMODE) = bootMode;
//
// CPU01 To CPU02 IPC Command Register
//
HWREG(IPC_BASE + IPC_O_SENDCOM) = BROM_IPC_EXECUTE_BOOTMODE_CMD;
//
// CPU01 to CPU02 IPC flag register
//
HWREG(IPC_BASE + IPC_O_SET) = 0x80000001U;
}
return returnStatus;
}
#endif
C2000Ware/driverlib/.meta/device/functions_c/BootCPU2/Boot_CPU2_Sector0_Sector13.xdt
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//*****************************************************************************
//
// Function to boot CPU2
// Available bootmodes :
// - BOOTMODE_BOOT_TO_FLASH_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_SECTOR4
// - BOOTMODE_BOOT_TO_FLASH_SECTOR8
// - BOOTMODE_BOOT_TO_FLASH_SECTOR13
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13
// - BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM
// - BOOTMODE_BOOT_TO_M0RAM
// - BOOTMODE_BOOT_TO_USEROTP
//
// Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM,
// BOOTMODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
//
// This function must be called after Device_init function
//
//*****************************************************************************
void Device_bootCPU2(uint32_t bootmode)
{
//
// Configure the CPU1TOCPU2IPCBOOTMODE register
//
IPC_setBootMode(IPC_CPU1_L_CPU2_R,
(BOOT_KEY | CPU2_BOOT_FREQ_200MHZ | bootmode));
//
// Set IPC Flag 0
//
IPC_setFlagLtoR(IPC_CPU1_L_CPU2_R, IPC_FLAG0);
//
// Bring CPU2 out of reset. Wait for CPU2 to go out of reset.
//
SysCtl_controlCPU2Reset(SYSCTL_CORE_DEACTIVE);
while(SysCtl_isCPU2Reset() == 0x1U);
}
C2000Ware/driverlib/.meta/device/functions_c/Clocktree/Analog_Trim.xdt
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%%{
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let Common = system.getScript("/driverlib/Common.js");
const clocktree_Analog_Trim_Type0 = device_common.clocktree_Analog_Trim_Type0;
const device = device_common.device;
%%}
% if(clocktree_Analog_Trim_Type0.includes(device))
% {
//
// Configure Analog Trim in case of untrimmed or TMX sample
//
if((SysCtl_getDeviceParametric(SYSCTL_DEVICE_QUAL) == 0x0U) &&
(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) == 0x0U))
{
Device_configureTMXAnalogTrim();
}
% }
%else{}
C2000Ware/driverlib/.meta/device/functions_c/Clocktree/Asserts.xdt
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%%{
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let clocktree_common = system.getScript("../../../clocktree/clocktree_common.js");
let Common = system.getScript("/driverlib/Common.js");
var XTAL_OR_X1 = system.clockTree.XTAL_OR_X1;
var OSCCLKSRCSEL = system.clockTree.OSCCLKSRCSEL;
var DIVSRCSEL = system.clockTree.DIVSRCSEL;
var CANASRCSEL = system.clockTree.CANABCLKSEL;
var CANBSRCSEL = system.clockTree.CANBBCLKSEL;
var oscclkSrc = "SYSCTL_OSCSRC_OSC2";
var ecatclkSrc = "SYSCTL_SOURCE_AUXPLL";
var enetclkSrc = "SYSCTL_SOURCE_AUXPLL";
var canAclkSrc
var canBclkSrc
var oscclksource
var oscclk = 10
const clocktree_Asserts_Type0 = device_common.clocktree_Asserts_Type0;
const clocktree_Asserts_Type1 = device_common.clocktree_Asserts_Type1;
const clocktree_Asserts_Type2 = device_common.clocktree_Asserts_Type2;
const clocktree_Asserts_Type3 = device_common.clocktree_Asserts_Type3;
const clocktree_Asserts_Type4 = device_common.clocktree_Asserts_Type4;
const clocktree_Asserts_Type5 = device_common.clocktree_Asserts_Type5;
const xtal_x1_macro = clocktree_common.xtal_x1_macro;
const device = device_common.device;
%%}
% if(clocktree_Asserts_Type0.includes(device))
% {
%if(!system.clockTree.EMIF1CLKDIV){
%console.log("In here")
%var DEVICE_CLK_EMIF_DIV = "SYSCTL_EMIF1CLK_DIV_1";
%}
%else{
%console.log("should not be In here")
%var DEVICE_CLK_EMIF_DIV = system.clockTree.EMIF1CLKDIV.divideValue;
%}
%var DEVICE_CLK_EPWM_DIV = system.clockTree.EPWMCLKDIV.divideValue;
%switch(OSCCLKSRCSEL.inputSelect){
% case "INTOSC1":
% oscclkSrc = "SYSCTL_OSCSRC_OSC1"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "INTOSC2":
% oscclkSrc = "SYSCTL_OSCSRC_OSC2"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "X1_XTAL":
% if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL"
% }
% else
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL_SE"
% }
% oscclksource = XTAL_OR_X1.inputSelect
% oscclk = XTAL_OR_X1.External_Clock
% break
%}
%switch(CANASRCSEL.inputSelect){
% case "SYSCLK":
% canAclkSrc = "CAN_CLOCK_SOURCE_SYS"
% break
% case "XTAL":
% canAclkSrc = "CAN_CLOCK_SOURCE_XTAL"
% break
% case "AUXCLKIN":
% canAclkSrc = "CAN_CLOCK_SOURCE_AUX"
% break
%}
%switch(CANBSRCSEL.inputSelect){
% case "SYSCLK":
% canBclkSrc = "CAN_CLOCK_SOURCE_SYS"
% break
% case "XTAL":
% canBclkSrc = "CAN_CLOCK_SOURCE_XTAL"
% break
% case "AUXCLKIN":
% canBclkSrc = "CAN_CLOCK_SOURCE_AUX"
% break
%}
//
// These asserts will check that the #defines for the clock rates in
// device.h match the actual rates that have been configured. If they do
// not match, check that the calculations of DEVICE_SYSCLK_FREQ and
// DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
// expected if these are not correct.
//
//
// From ClockTree Configurations
//
SysCtl_selectOscSourceAuxPLL(`oscclkSrc`);
CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
CAN_selectClockSource(CANB_BASE, `canBclkSrc`);
SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_`DEVICE_CLK_EPWM_DIV`);
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_`DEVICE_CLK_EMIF_DIV`);
ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
% }
% if(clocktree_Asserts_Type1.includes(device))
% {
%if(!system.clockTree.EMIF1CLKDIV){
%console.log("In here")
%var DEVICE_CLK_EMIF1_DIV = "SYSCTL_EMIF1CLK_DIV_1";
%}
%else{
%console.log("should not be In here")
%var DEVICE_CLK_EMIF1_DIV =system.clockTree.EMIF1CLKDIV.divideValue;
%}
%if(!system.clockTree.EMIF2CLKDIV){
%console.log("In here")
%var DEVICE_CLK_EMIF2_DIV = "SYSCTL_EMIF2CLK_DIV_1";
%}
%else{
%console.log("should not be In here")
%var DEVICE_CLK_EMIF2_DIV =system.clockTree.EMIF2CLKDIV.divideValue;
%}
%if(!system.clockTree.ECATDIV){
%var DEVICE_CLK_ECAT_DIV = 4;
%}
%else{
%var DEVICE_CLK_ECAT_DIV = system.clockTree.ECATDIV.divideValue;
%}
%var DEVICE_CLK_ENET_DIV = system.clockTree.ENETDIV.divideValue;
%var DEVICE_CLK_MCAN_DIV = system.clockTree.MCANACLKDIV.divideValue;
%var DEVICE_CLK_EPWM_DIV = system.clockTree.EPWMCLKDIV.divideValue;
%switch(OSCCLKSRCSEL.inputSelect){
% case "INTOSC1":
% oscclkSrc = "SYSCTL_OSCSRC_OSC1"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "INTOSC2":
% oscclkSrc = "SYSCTL_OSCSRC_OSC2"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "X1_XTAL":
% if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL"
% }
% else
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL_SE"
% }
% oscclksource = XTAL_OR_X1.inputSelect
% oscclk = XTAL_OR_X1.External_Clock
% break
%}
%switch(DIVSRCSEL.inputSelect){
% case "AUXPLLRAWCLK":
% ecatclkSrc = "SYSCTL_SOURCE_AUXPLL"
% enetclkSrc = "SYSCTL_SOURCE_AUXPLL"
% break
% case "PLLSYSCLK":
% ecatclkSrc = "SYSCTL_SOURCE_SYSPLL"
% enetclkSrc = "SYSCTL_SOURCE_SYSPLL"
% break
%}
%switch(CANASRCSEL.inputSelect){
% case "SYSCLK":
% canAclkSrc = "CAN_CLOCK_SOURCE_SYS"
% break
% case "XTAL":
% canAclkSrc = "CAN_CLOCK_SOURCE_XTAL"
% break
% case "AUXCLKIN":
% canAclkSrc = "CAN_CLOCK_SOURCE_AUX"
% break
%}
%switch(CANBSRCSEL.inputSelect){
% case "SYSCLK":
% canBclkSrc = "CAN_CLOCK_SOURCE_SYS"
% break
% case "XTAL":
% canBclkSrc = "CAN_CLOCK_SOURCE_XTAL"
% break
% case "AUXCLKIN":
% canBclkSrc = "CAN_CLOCK_SOURCE_AUX"
% break
%}
//
// These asserts will check that the #defines for the clock rates in
// device.h match the actual rates that have been configured. If they do
// not match, check that the calculations of DEVICE_SYSCLK_FREQ,
// DEVICE_LSPCLK_FREQ and DEVICE_AUXCLK_FREQ are accurate. Some
// examples will not perform as expected if these are not correct.
//
//
// From ClockTree Configurations
//
SysCtl_selectOscSourceAuxPLL(`oscclkSrc`);
CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
CAN_selectClockSource(CANB_BASE, `canBclkSrc`);
SysCtl_setMCANClk(SYSCTL_MCANCLK_DIV_`DEVICE_CLK_MCAN_DIV`);
SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_`DEVICE_CLK_EPWM_DIV`);
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_`DEVICE_CLK_EMIF1_DIV`);
SysCtl_setEMIF2ClockDivider(SYSCTL_EMIF2CLK_DIV_`DEVICE_CLK_EMIF2_DIV`);
SysCtl_setECatClk(SYSCTL_ECATCLKOUT_DIV_`DEVICE_CLK_ECAT_DIV`, `ecatclkSrc`, 0x1U);
SysCtl_setEnetClk(SYSCTL_ENETCLKOUT_DIV_`DEVICE_CLK_ENET_DIV`, `enetclkSrc`);
ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
ASSERT(SysCtl_getAuxClock(DEVICE_OSCSRC_FREQ) == DEVICE_AUXCLK_FREQ);
% }
% if(clocktree_Asserts_Type2.includes(device))
% {
%if(!system.clockTree.EMIF1CLKDIV){
%console.log("In here")
%var DEVICE_CLK_EMIF_DIV = "SYSCTL_EMIF1CLK_DIV_1";
%}
%else{
%console.log("should not be In here")
%var DEVICE_CLK_EMIF_DIV = system.clockTree.EMIF1CLKDIV.divideValue;
%}
%if(!system.clockTree.ECATDIV){
%var DEVICE_CLK_ECAT_DIV = 4;
%}
%else{
%var DEVICE_CLK_ECAT_DIV = system.clockTree.ECATDIV.divideValue;
%}
%if(!system.clockTree.LINACLKDIV){
%var DEVICE_CLK_LINA_DIV = 2;
%}
%else{
%var DEVICE_CLK_LINA_DIV = system.clockTree.LINACLKDIV.divideValue;
%}
%if(!system.clockTree.LINBCLKDIV){
%var DEVICE_CLK_LINB_DIV = 2;
%}
%else{
%var DEVICE_CLK_LINB_DIV = system.clockTree.LINBCLKDIV.divideValue;
%}
%var DEVICE_CLK_MCANA_DIV = system.clockTree.MCANACLKDIV.divideValue;
%var DEVICE_CLK_MCANB_DIV = system.clockTree.MCANBCLKDIV.divideValue;
%var DEVICE_CLK_EPWM_DIV = system.clockTree.EPWMCLKDIV.divideValue;
%switch(OSCCLKSRCSEL.inputSelect){
% case "INTOSC1":
% oscclkSrc = "SYSCTL_OSCSRC_OSC1"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "INTOSC2":
% oscclkSrc = "SYSCTL_OSCSRC_OSC2"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "X1_XTAL":
% if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL"
% }
% else
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL_SE"
% }
% oscclksource = XTAL_OR_X1.inputSelect
% oscclk = XTAL_OR_X1.External_Clock
% break
%}
%switch(DIVSRCSEL.inputSelect){
% case "AUXPLLRAWCLK":
% ecatclkSrc = "SYSCTL_SOURCE_AUXPLL"
% break
% case "PLLSYSCLK":
% ecatclkSrc = "SYSCTL_SOURCE_SYSPLL"
% break
%}
%switch(DIVSRCSEL.inputSelect){
% case "AUXPLLRAWCLK":
% ecatclkSrc = "SYSCTL_SOURCE_AUXPLL"
% break
% case "PLLSYSCLK":
% ecatclkSrc = "SYSCTL_SOURCE_SYSPLL"
% break
%}
%switch(CANASRCSEL.inputSelect){
% case "PERx.SYSCLK":
% canAclkSrc = "CAN_CLOCK_SOURCE_SYS"
% break
% case "XTAL":
% canAclkSrc = "CAN_CLOCK_SOURCE_XTAL"
% break
% case "AUXCLKIN":
% canAclkSrc = "CAN_CLOCK_SOURCE_AUX"
% break
%}
//
// These asserts will check that the #defines for the clock rates in
// device.h match the actual rates that have been configured. If they do
// not match, check that the calculations of DEVICE_SYSCLK_FREQ and
// DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
// expected if these are not correct.
//
//
// From ClockTree Configurations
//
SysCtl_selectOscSourceAuxPLL(`oscclkSrc`);
CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
SysCtl_setMCANClk(SYSCTL_MCANA, SYSCTL_MCANCLK_DIV_`DEVICE_CLK_MCANA_DIV`);
SysCtl_setMCANClk(SYSCTL_MCANB, SYSCTL_MCANCLK_DIV_`DEVICE_CLK_MCANB_DIV`);
SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_`DEVICE_CLK_EPWM_DIV`);
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_`DEVICE_CLK_EMIF_DIV`);
SysCtl_setECatClk(SYSCTL_ECATCLKOUT_DIV_`DEVICE_CLK_ECAT_DIV`, `ecatclkSrc`, 0x1U);
SysCtl_setLINAClockDivider(SYSCTL_LINACLK_DIV_`DEVICE_CLK_LINA_DIV`);
SysCtl_setLINBClockDivider(SYSCTL_LINBCLK_DIV_`DEVICE_CLK_LINB_DIV`);
ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
ASSERT(SysCtl_getAuxClock(DEVICE_OSCSRC_FREQ) == DEVICE_AUXCLK_FREQ);
% }
% if(clocktree_Asserts_Type3.includes(device))
% {
%var DEVICE_CLK_MCANA_DIV = system.clockTree.MCANACLKDIV.divideValue;
%switch(OSCCLKSRCSEL.inputSelect){
% case "INTOSC1":
% oscclkSrc = "SYSCTL_OSCSRC_OSC1"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "INTOSC2":
% oscclkSrc = "SYSCTL_OSCSRC_OSC2"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "X1_XTAL":
% if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL"
% }
% else
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL_SE"
% }
% oscclksource = XTAL_OR_X1.inputSelect
% oscclk = XTAL_OR_X1.External_Clock
% break
%}
%switch(CANASRCSEL.inputSelect){
% case "SYSCLK":
% canAclkSrc = "CAN_CLOCK_SOURCE_SYS"
% break
% case "XTAL":
% canAclkSrc = "CAN_CLOCK_SOURCE_XTAL"
% break
% case "AUXCLKIN":
% canAclkSrc = "CAN_CLOCK_SOURCE_AUX"
% break
%}
//
// These asserts will check that the #defines for the clock rates in
// device.h match the actual rates that have been configured. If they do
// not match, check that the calculations of DEVICE_SYSCLK_FREQ and
// DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
// expected if these are not correct.
//
CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
SysCtl_setMCANClk(SYSCTL_MCANCLK_DIV_`DEVICE_CLK_MCANA_DIV`);
ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
% }
% if(clocktree_Asserts_Type4.includes(device))
% {
%switch(OSCCLKSRCSEL.inputSelect){
% case "INTOSC1":
% oscclkSrc = "SYSCTL_OSCSRC_OSC1"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "INTOSC2":
% oscclkSrc = "SYSCTL_OSCSRC_OSC2"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "X1_XTAL":
% if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL"
% }
% else
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL_SE"
% }
% oscclksource = XTAL_OR_X1.inputSelect
% oscclk = XTAL_OR_X1.External_Clock
% break
%}
%switch(CANASRCSEL.inputSelect){
% case "SYSCLK":
% canAclkSrc = "CAN_CLOCK_SOURCE_SYS"
% break
% case "XTAL":
% canAclkSrc = "CAN_CLOCK_SOURCE_XTAL"
% break
% case "AUXCLKIN":
% canAclkSrc = "CAN_CLOCK_SOURCE_AUX"
% break
%}
//
// These asserts will check that the #defines for the clock rates in
// device.h match the actual rates that have been configured. If they do
// not match, check that the calculations of DEVICE_SYSCLK_FREQ and
// DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
// expected if these are not correct.
//
CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
% }
% if(clocktree_Asserts_Type5.includes(device))
%{
//
// These asserts will check that the #defines for the clock rates in
// device.h match the actual rates that have been configured. If they do
// not match, check that the calculations of DEVICE_SYSCLK_FREQ and
// DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
// expected if these are not correct.
//
ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
% }
C2000Ware/driverlib/.meta/device/functions_c/Clocktree/Device_clocktree_c.xdt
+13
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@@ -0,0 +1,13 @@
%%{
var Flash = system.getTemplate('./Flash.xdt');
var Asserts = system.getTemplate('./Asserts.xdt');
var Analog_Trim = system.getTemplate('./Analog_Trim.xdt');
var PLL_Ctl_Dividers = system.getTemplate('./PLL_Ctl_Dividers.xdt');
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let Common = system.getScript("/driverlib/Common.js");
const device = device_common.device;
%%}
`Analog_Trim()`
`PLL_Ctl_Dividers()`
`Asserts()`
`Flash()`
C2000Ware/driverlib/.meta/device/functions_c/Clocktree/Flash.xdt
+11
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@@ -0,0 +1,11 @@
#ifndef _FLASH
//
// Call Device_cal function when run using debugger
// This function is called as part of the Boot code. The function is called
// in the Device_init function since during debug time resets, the boot code
// will not be executed and the gel script will reinitialize all the
// registers and the calibrated values will be lost.
// Sysctl_deviceCal is a wrapper function for Device_Cal
//
SysCtl_deviceCal();
#endif
C2000Ware/driverlib/.meta/device/functions_c/Clocktree/PLL_Ctl_Dividers.xdt
+50
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@@ -0,0 +1,50 @@
%%{
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let Common = system.getScript("/driverlib/Common.js");
const clocktree_PLL_Ctl_Dividers_Type0 = device_common.clocktree_PLL_Ctl_Dividers_Type0;
const clocktree_PLL_Ctl_Dividers_Type1 = device_common.clocktree_PLL_Ctl_Dividers_Type1;
const clocktree_PLL_Ctl_Dividers_Type2 = device_common.clocktree_PLL_Ctl_Dividers_Type2;
const device = device_common.device;
%%}
% if(clocktree_PLL_Ctl_Dividers_Type0.includes(device))
% {
//
// Set up PLL control and clock dividers
//
SysCtl_setClock(DEVICE_SETCLOCK_CFG);
SysCtl_setLowSpeedClock(DEVICE_LSPCLK_CFG);
% }
% if(clocktree_PLL_Ctl_Dividers_Type1.includes(device))
% {
//
// Set up PLL control and clock dividers
//
SysCtl_setClock(DEVICE_SETCLOCK_CFG);
SysCtl_setLowSpeedClock(DEVICE_LSPCLK_CFG);
//
// Set up AUXPLL control and clock dividers needed for CMCLK
//
SysCtl_setAuxClock(DEVICE_AUXSETCLOCK_CFG);
//
// Set up CMCLK to use AUXPLL as the clock source and set the
// clock divider to 1.
//
SysCtl_setCMClk(SYSCTL_CMCLKOUT_DIV_1,SYSCTL_SOURCE_AUXPLL);
% }
% if(clocktree_PLL_Ctl_Dividers_Type2.includes(device))
% {
//
// Set up PLL control and clock dividers
//
SysCtl_setClock(DEVICE_SETCLOCK_CFG);
SysCtl_setLowSpeedClock(DEVICE_LSPCLK_CFG);
//
// Set up AUXPLL control and clock dividers needed for CMCLK
//
SysCtl_setAuxClock(DEVICE_AUXSETCLOCK_CFG);
% }
C2000Ware/driverlib/.meta/device/functions_c/ConfigureTMXAnalogTrim/Configure_TMX_Analog_Trim.xdt
+25
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@@ -0,0 +1,25 @@
%%{
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let Common = system.getScript("/driverlib/Common.js");
var Configure_TMX_Analog_Trim_ADCA_to_ADCD = system.getTemplate('./Configure_TMX_Analog_Trim_ADCA_to_ADCD.xdt');
var Configure_TMX_Analog_Trim_ADCA_to_ADCD_Type2 = system.getTemplate('./Configure_TMX_Analog_Trim_ADCA_to_ADCD_Type2.xdt');
var Configure_TMX_Analog_Trim_ADCA_ADCB_ADCD = system.getTemplate('./Configure_TMX_Analog_Trim_ADCA_ADCB_ADCD.xdt');
const device = device_common.device;
const Configure_TMX_Analog_Trim_Type0 = device_common.Configure_TMX_Analog_Trim_Type0;
const Configure_TMX_Analog_Trim_Type1 = device_common.Configure_TMX_Analog_Trim_Type1;
const Configure_TMX_Analog_Trim_Type2 = device_common.Configure_TMX_Analog_Trim_Type2;
%%}
% if(Configure_TMX_Analog_Trim_Type0.includes(device) && Common.isContextCPU1())
%{
`Configure_TMX_Analog_Trim_ADCA_ADCB_ADCD()`
%}
% if(Configure_TMX_Analog_Trim_Type1.includes(device))
%{
`Configure_TMX_Analog_Trim_ADCA_to_ADCD()`
%}
% if(Configure_TMX_Analog_Trim_Type2.includes(device) && Common.isContextCPU1())
%{
`Configure_TMX_Analog_Trim_ADCA_to_ADCD_Type2()`
%}
%else{}
C2000Ware/driverlib/.meta/device/functions_c/ConfigureTMXAnalogTrim/Configure_TMX_Analog_Trim_ADCA_ADCB_ADCD.xdt
+57
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@@ -0,0 +1,57 @@
//*****************************************************************************
//
// Function to implement Analog trim of TMX devices
//
//*****************************************************************************
void Device_configureTMXAnalogTrim(void)
{
//
// Enable ADC clock
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
//
// Configure ADC reference trim for TMX devices
//
EALLOW;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) = 0x7BDDU;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMB) = 0x7BDDU;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMD) = 0x7BDDU;
//
// Configure ADC offset trim. The user should generate the trim values
// by following the instructions in the "ADC Zero Offset Calibration"
// section in device TRM. The below lines needs to be uncommented and
// updated with the correct trim values.
//
// HWREGH(ADCA_BASE + ADC_O_OFFTRIM) = 0x0U;
// HWREGH(ADCB_BASE + ADC_O_OFFTRIM) = 0x0U;
// HWREGH(ADCD_BASE + ADC_O_OFFTRIM) = 0x0U;
//
// Configure internal oscillator trim. If the internal oscillator trim
// contains all zeros, the user can adjust the lowest 10 bits of the
// oscillator trim register between 1 (minimum) and 1023 (maximum)
// while observing the system clock on the XCLOCKOUT pin. The below
// lines needs to be uncommented and updated with the correct trim values.
//
// if(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) == 0x0U)
// {
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) = 0x0U;
// }
// if( HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U)
// {
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U;
// }
EDIS;
//
// Disable ADC clock
//
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
}
C2000Ware/driverlib/.meta/device/functions_c/ConfigureTMXAnalogTrim/Configure_TMX_Analog_Trim_ADCA_to_ADCD.xdt
+61
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@@ -0,0 +1,61 @@
//*****************************************************************************
//
// Function to implement Analog trim of TMX devices
//
//*****************************************************************************
void Device_configureTMXAnalogTrim(void)
{
//
// Enable ADC clock
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
//
// Configure ADC reference trim for TMX devices
//
EALLOW;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) = 0x7BDDU;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMB) = 0x7BDDU;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMC) = 0x7BDDU;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMD) = 0x7BDDU;
//
// Configure ADC offset trim. The user should generate the trim values
// by following the instructions in the "ADC Zero Offset Calibration"
// section in device TRM. The below lines needs to be uncommented and
// updated with the correct trim values.
//
// HWREGH(ADCA_BASE + ADC_O_OFFTRIM) = 0x0U;
// HWREGH(ADCB_BASE + ADC_O_OFFTRIM) = 0x0U;
// HWREGH(ADCC_BASE + ADC_O_OFFTRIM) = 0x0U;
// HWREGH(ADCD_BASE + ADC_O_OFFTRIM) = 0x0U;
//
// Configure internal oscillator trim. If the internal oscillator trim
// contains all zeros, the user can adjust the lowest 10 bits of the
// oscillator trim register between 1 (minimum) and 1023 (maximum)
// while observing the system clock on the XCLOCKOUT pin. The below
// lines needs to be uncommented and updated with the correct trim values.
//
// if(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) == 0x0U)
// {
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) = 0x0U;
// }
// if( HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U)
// {
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U;
// }
EDIS;
//
// Disable ADC clock
//
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
}
C2000Ware/driverlib/.meta/device/functions_c/ConfigureTMXAnalogTrim/Configure_TMX_Analog_Trim_ADCA_to_ADCD_Type2.xdt
+62
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@@ -0,0 +1,62 @@
#ifdef CPU1
//*****************************************************************************
//
// Function to implement Analog trim of TMX devices
//
//*****************************************************************************
void Device_configureTMXAnalogTrim(void)
{
//
// Enable ADC clock
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
//
// Configure ADC reference trim for TMX devices
//
EALLOW;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) = 0x7BDDU;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMB) = 0x7BDDU;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMC) = 0x7BDDU;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMD) = 0x7BDDU;
//
// Configure ADC offset trim. The user should generate the trim values
// by following the instructions in the "ADC Zero Offset Calibration"
// section in device TRM. The below lines needs to be uncommented and
// updated with the correct trim values.
//
// HWREGH(ADCA_BASE + ADC_O_OFFTRIM) = 0x0U;
// HWREGH(ADCB_BASE + ADC_O_OFFTRIM) = 0x0U;
// HWREGH(ADCC_BASE + ADC_O_OFFTRIM) = 0x0U;
// HWREGH(ADCD_BASE + ADC_O_OFFTRIM) = 0x0U;
//
// Configure internal oscillator trim. If the internal oscillator trim
// contains all zeros, the user can adjust the lowest 10 bits of the
// oscillator trim register between 1 (minimum) and 1023 (maximum)
// while observing the system clock on the XCLOCKOUT pin. The below
// lines needs to be uncommented and updated with the correct trim values.
//
// if(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) == 0x0U)
// {
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) = 0x0U;
// }
// if( HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U)
// {
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U;
// }
EDIS;
//
// Disable ADC clock
//
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
}
C2000Ware/driverlib/.meta/device/functions_c/Device_bootCM_c.xdt
+47
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@@ -0,0 +1,47 @@
%let Common = system.getScript("/driverlib/Common.js");
%if (["F2838x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
//*****************************************************************************
//
// Function to boot CM
// Available bootmodes :
// - BOOTMODE_BOOT_TO_FLASH_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_SECTOR4
// - BOOTMODE_BOOT_TO_FLASH_SECTOR8
// - BOOTMODE_BOOT_TO_FLASH_SECTOR13
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13
// - BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_S0RAM
// - BOOTMODE_BOOT_TO_S0RAM
// - BOOTMODE_BOOT_TO_USEROTP
//
// Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM,
// BOOTMODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
//
// This function must be called after Device_init function
//
//*****************************************************************************
void Device_bootCM(uint32_t bootmode)
{
//
// Configure the CPU1TOCMIPCBOOTMODE register
//
IPC_setBootMode(IPC_CPU1_L_CM_R,
(BOOT_KEY | CM_BOOT_FREQ_125MHZ | bootmode));
//
// Set IPC Flag 0
//
IPC_setFlagLtoR(IPC_CPU1_L_CM_R, IPC_FLAG0);
//
// Bring CM out of reset. Wait for CM to go out of reset.
//
SysCtl_controlCMReset(SYSCTL_CORE_DEACTIVE);
while(SysCtl_isCMReset() == 0x1U);
}
#endif
%}
%else{
%}
C2000Ware/driverlib/.meta/device/functions_c/Device_bootCPU2_c.xdt
+351
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@@ -0,0 +1,351 @@
%let Common = system.getScript("/driverlib/Common.js");
%if (["F28P65x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#ifdef CPU1
//*****************************************************************************
//
// Function to boot CPU2
// Available bootmodes :
// - BOOTMODE_BOOT_TO_FLASH_BANK0_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_BANK0_SECTOR127_END
// - BOOTMODE_BOOT_TO_FLASH_BANK1_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_BANK2_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_BANK3_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_BANK4_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_BANK4_SECTOR127_END
// - BOOTMODE_BOOT_TO_SECURE_FLASH_BANK0_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_BANK1_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_BANK2_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_BANK3_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_BANK4_SECTOR0
// - BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM
// - BOOTMODE_BOOT_TO_M0RAM
// - BOOTMODE_BOOT_TO_FWU_FLASH
// - BOOTMODE_BOOT_TO_FWU_FLASH_ALT1
// - BOOTMODE_BOOT_TO_FWU_FLASH_ALT2
// - BOOTMODE_BOOT_TO_FWU_FLASH_ALT3
//
// Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM,
// BOOTMODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
//
// This function must be called after Device_init function
//
//*****************************************************************************
void Device_bootCPU2(uint32_t bootmode)
{
//
// Configure the CPU1TOCPU2IPCBOOTMODE register
//
IPC_setBootMode(IPC_CPU1_L_CPU2_R,
(BOOT_KEY | bootmode));
//
// Set IPC Flag 0
//
IPC_setFlagLtoR(IPC_CPU1_L_CPU2_R, IPC_FLAG0);
//
// Bring CPU2 out of reset. Wait for CPU2 to go out of reset.
//
SysCtl_controlCPU2Reset(SYSCTL_CORE_DEACTIVE);
while(SysCtl_isCPU2Reset() == 0x1U);
}
#endif
%}
%if (["F2838x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
//*****************************************************************************
//
// Function to boot CPU2
// Available bootmodes :
// - BOOTMODE_BOOT_TO_FLASH_SECTOR0
// - BOOTMODE_BOOT_TO_FLASH_SECTOR4
// - BOOTMODE_BOOT_TO_FLASH_SECTOR8
// - BOOTMODE_BOOT_TO_FLASH_SECTOR13
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR0
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR4
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR8
// - BOOTMODE_BOOT_TO_SECURE_FLASH_SECTOR13
// - BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM
// - BOOTMODE_BOOT_TO_M0RAM
// - BOOTMODE_BOOT_TO_USEROTP
//
// Note that while using BOOTMODE_IPC_MSGRAM_COPY_BOOT_TO_M1RAM,
// BOOTMODE_IPC_MSGRAM_COPY_LENGTH_xxxW must be ORed with the bootmode parameter
//
// This function must be called after Device_init function
//
//*****************************************************************************
void Device_bootCPU2(uint32_t bootmode)
{
//
// Configure the CPU1TOCPU2IPCBOOTMODE register
//
IPC_setBootMode(IPC_CPU1_L_CPU2_R,
(BOOT_KEY | CPU2_BOOT_FREQ_200MHZ | bootmode));
//
// Set IPC Flag 0
//
IPC_setFlagLtoR(IPC_CPU1_L_CPU2_R, IPC_FLAG0);
//
// Bring CPU2 out of reset. Wait for CPU2 to go out of reset.
//
SysCtl_controlCPU2Reset(SYSCTL_CORE_DEACTIVE);
while(SysCtl_isCPU2Reset() == 0x1U);
}
%}
%else if(["F2837xD"].includes(Common.getDeviceName())){
//*****************************************************************************
//! Executes a CPU02 control system bootloader.
//!
//! \param bootMode specifies which CPU02 control system boot mode to execute.
//!
//! This function will allow the CPU01 controller system to boot the CPU02 control
//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI,
//! SCI, I2C, or parallel I/O. This function blocks and waits until the
//! control system boot ROM is configured and ready to receive CPU01 to CPU02
//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and
//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the
//! command to execute the selected bootloader.
//!
//! The \e bootMode parameter accepts one of the following values:
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH
//!
//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is
//! invalid and command was not sent.
//
//*****************************************************************************
uint16_t
Device_bootCPU2(uint32_t bootMode)
{
uint32_t bootStatus;
uint16_t pin;
uint16_t returnStatus = STATUS_PASS;
//
// If CPU2 has already booted, return a fail to let the application
// know that something is out of the ordinary.
//
bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & 0x0000000FU;
if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK)
{
//
// Check if MSB is set as well
//
bootStatus = ((uint32_t)(HWREG(IPC_BASE + IPC_O_BOOTSTS) &
0x80000000U)) >> 31U;
if(bootStatus != 0)
{
returnStatus = STATUS_FAIL;
return returnStatus;
}
}
//
// Wait until CPU02 control system boot ROM is ready to receive
// CPU01 to CPU02 INT1 interrupts.
//
do
{
bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) &
C2_BOOTROM_BOOTSTS_SYSTEM_READY;
} while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY));
//
// Loop until CPU02 control system IPC flags 1 and 32 are available
//
while (((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC0) != 0U) ||
((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC31) != 0U))
{
}
if (bootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE)
{
returnStatus = STATUS_FAIL;
}
else
{
//
// Based on boot mode, enable pull-ups on peripheral pins and
// give GPIO pin control to CPU02 control system.
//
switch (bootMode)
{
case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI:
//
//SCIA connected to CPU02
//
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL5_SCI, 1,
SYSCTL_CPUSEL_CPU2);
//
//Allows CPU02 bootrom to take control of clock
//configuration registers
//
EALLOW;
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U;
EDIS;
GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT);
GPIO_setQualificationMode(29, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_29_SCITXDA);
GPIO_setControllerCore(29, GPIO_CORE_CPU2);
GPIO_setDirectionMode(28, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(28, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_28_SCIRXDA);
GPIO_setControllerCore(28, GPIO_CORE_CPU2);
break;
case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI:
//
//SPI-A connected to CPU02
//
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL6_SPI, 1,
SYSCTL_CPUSEL_CPU2);
//
//Allows CPU02 bootrom to take control of clock configuration
// registers
//
EALLOW;
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
EDIS;
GPIO_setDirectionMode(16, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_16_SPISIMOA);
GPIO_setControllerCore(16, GPIO_CORE_CPU2);
GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(17, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_17_SPISOMIA);
GPIO_setControllerCore(17, GPIO_CORE_CPU2);
GPIO_setDirectionMode(18, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(18, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_18_SPICLKA);
GPIO_setControllerCore(18, GPIO_CORE_CPU2);
GPIO_setDirectionMode(19, GPIO_DIR_MODE_OUT);
GPIO_setQualificationMode(19, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_19_GPIO19);
GPIO_setControllerCore(19, GPIO_CORE_CPU2);
break;
case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C:
//
//I2CA connected to CPU02
//
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL7_I2C, 1,
SYSCTL_CPUSEL_CPU2);
//
//Allows CPU2 bootrom to take control of clock
//configuration registers
//
EALLOW;
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U;
EDIS;
GPIO_setDirectionMode(32, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(32, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_32_SDAA);
GPIO_setControllerCore(32, GPIO_CORE_CPU2);
GPIO_setDirectionMode(33, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(33, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_33_SCLA);
GPIO_setControllerCore(33, GPIO_CORE_CPU2);
break;
case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL:
for(pin=58;pin<=65;pin++)
{
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
GPIO_setControllerCore(pin, GPIO_CORE_CPU2);
}
GPIO_setDirectionMode(69, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(69, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_69_GPIO69);
GPIO_setControllerCore(69, GPIO_CORE_CPU2);
GPIO_setDirectionMode(70, GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_70_GPIO70);
GPIO_setControllerCore(70, GPIO_CORE_CPU2);
break;
case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN:
//
//Set up the GPIO mux to bring out CANATX on GPIO71
//and CANARX on GPIO70
//
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU);
GPIO_setControllerCore(71, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_71_CANTXA);
GPIO_setQualificationMode(71, GPIO_QUAL_ASYNC);
GPIO_setControllerCore(70, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_70_CANRXA);
GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC);
GPIO_lockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU);
//
// Set CANA Bit-Clock Source Select = SYSCLK and enable CAN
//
EALLOW;
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &=
SYSCTL_CLKSRCCTL2_CANABCLKSEL_M;
EDIS;
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA);
break;
}
//
//CPU01 to CPU02 IPC Boot Mode Register
//
HWREG(IPC_BASE + IPC_O_BOOTMODE) = bootMode;
//
// CPU01 To CPU02 IPC Command Register
//
HWREG(IPC_BASE + IPC_O_SENDCOM) = BROM_IPC_EXECUTE_BOOTMODE_CMD;
//
// CPU01 to CPU02 IPC flag register
//
HWREG(IPC_BASE + IPC_O_SET) = 0x80000001U;
}
return returnStatus;
}
%}
C2000Ware/driverlib/.meta/device/functions_c/Device_clocktree_c.xdt
+256
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%let Common = system.getScript("/driverlib/Common.js");
%let clocktree_common = system.getScript("../../clocktree/clocktree_common.js");
% var nameOfEcatModule = "ecat";
% var nameOfCANModule = "can";
% var ecatModule = system.modules['/driverlib/' + nameOfEcatModule + '.js'];
% var canModule = system.modules['/driverlib/' + nameOfCANModule + '.js']
%const OSCCLK_d = system.clockTree.OSCCLK.in;
%var XTAL_OR_X1 = system.clockTree.XTAL_OR_X1;
%
%const xtal_x1_macro = clocktree_common.xtal_x1_macro;
%const device = system.deviceData.device
%
%var OSCCLKSRCSEL = system.clockTree.OSCCLKSRCSEL;
%var DIVSRCSEL = system.clockTree.DIVSRCSEL;
%var CANASRCSEL = system.clockTree.CANABCLKSEL;
%var CANBSRCSEL = system.clockTree.CANBBCLKSEL;
%//var MCANADIV = system.clockTree.;
%//var MCANADIV = system.clockTree.;
%var oscclkSrc = "SYSCTL_OSCSRC_OSC2";
%var ecatclkSrc = "SYSCTL_SOURCE_AUXPLL";
%var enetclkSrc = "SYSCTL_SOURCE_AUXPLL";
%var canAclkSrc
%var canBclkSrc
%var oscclksource
%var oscclk = 10
%if (["F2838x", "F2837xD", "F2807x", "F2837xS", "F28P65x"].includes(Common.getDeviceName())){
%if(!system.clockTree.EMIF1CLKDIV){
%//console.log("In here")
%var DEVICE_CLK_EMIF_DIV = "SYSCTL_EMIF1CLK_DIV_1";
%}
%else{
%//console.log("should not be In here")
%var DEVICE_CLK_EMIF_DIV = system.clockTree.EMIF1CLKDIV.divideValue;
%}
%}
%if (["F2838x", "F28P65x"].includes(Common.getDeviceName())){
%if(!system.clockTree.ECATDIV){
%var DEVICE_CLK_ECAT_DIV = 4;
%}
%else{
%var DEVICE_CLK_ECAT_DIV = system.clockTree.ECATDIV.divideValue;
%}
%}
%if (["F2838x"].includes(Common.getDeviceName())){
%var DEVICE_CLK_ENET_DIV = 4;//system.clockTree.ENETDIV.divideValue; //FIXME: Needs to be added into ClockTreeResourceFile.xlsx
%}
%if (["F28P65x"].includes(Common.getDeviceName())){
%var DEVICE_CLK_MCANA_DIV = system.clockTree.MCANACLKDIV.divideValue;
%var DEVICE_CLK_MCANB_DIV = system.clockTree.MCANBCLKDIV.divideValue;
%}
%//if (["F2838x", "F28003x", "F280015x"].includes(Common.getDeviceName())){ //FIXME: Uncomment when implemented
%//var DEVICE_CLK_MCAN_DIV = system.clockTree.MCANACLKDIV.divideValue;
%//}
%if (["F2838x","F2807x","F2837xD","F2837xS","F28P65x"].includes(Common.getDeviceName())){
%var DEVICE_CLK_EPWM_DIV = system.clockTree.EPWMCLKDIV.divideValue;
%}
%switch(OSCCLKSRCSEL.inputSelect){
% case "INTOSC1":
% oscclkSrc = "SYSCTL_OSCSRC_OSC1"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "INTOSC2":
% oscclkSrc = "SYSCTL_OSCSRC_OSC2"
% oscclksource = OSCCLKSRCSEL.inputSelect
% oscclk = 10
% break
% case "X1_XTAL":
% if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL"
% }
% else
% {
% oscclkSrc = "SYSCTL_OSCSRC_XTAL_SE"
% }
% oscclksource = XTAL_OR_X1.inputSelect
% oscclk = XTAL_OR_X1.External_Clock
% break
%}
%if (["F2838x"].includes(Common.getDeviceName())){
%switch(DIVSRCSEL.inputSelect){
% case "AUXPLLRAWCLK":
% ecatclkSrc = "SYSCTL_SOURCE_AUXPLL"
% enetclkSrc = "SYSCTL_SOURCE_AUXPLL"
% break
% case "PLLSYSCLK":
% ecatclkSrc = "SYSCTL_SOURCE_SYSPLL"
% enetclkSrc = "SYSCTL_SOURCE_SYSPLL"
% break
%}
%}
%if (["F28P65x"].includes(Common.getDeviceName())){
%switch(DIVSRCSEL.inputSelect){
% case "AUXPLLRAWCLK":
% ecatclkSrc = "SYSCTL_SOURCE_AUXPLL"
% break
% case "PLLSYSCLK":
% ecatclkSrc = "SYSCTL_SOURCE_SYSPLL"
% break
%}
%}
%if (["F28P65x"].includes(Common.getDeviceName())){
%switch(DIVSRCSEL.inputSelect){
% case "AUXPLLRAWCLK":
% ecatclkSrc = "SYSCTL_SOURCE_AUXPLL"
% break
% case "PLLSYSCLK":
% ecatclkSrc = "SYSCTL_SOURCE_SYSPLL"
% break
%}
%}
%if (["F280013x", "F280015x", "F28002x", "F28003x", "F28004x", "F2838x", "F2837xD", "F2807x", "F2837xS"].includes(Common.getDeviceName())){
%switch(CANASRCSEL.inputSelect){
% case "SYSCLK":
% canAclkSrc = "CAN_CLOCK_SOURCE_SYS"
% break
% case "XTAL":
% canAclkSrc = "CAN_CLOCK_SOURCE_XTAL"
% break
% case "AUXCLKIN":
% canAclkSrc = "CAN_CLOCK_SOURCE_AUX"
% break
%}
%}
%if (["F28P65x"].includes(Common.getDeviceName())){
%switch(CANASRCSEL.inputSelect){
% case "PERx.SYSCLK":
% canAclkSrc = "CAN_CLOCK_SOURCE_SYS"
% break
% case "XTAL":
% canAclkSrc = "CAN_CLOCK_SOURCE_XTAL"
% break
% case "AUXCLKIN":
% canAclkSrc = "CAN_CLOCK_SOURCE_AUX"
% break
%}
%}
%if (["F2838x", "F2837xD", "F2807x", "F2837xS"].includes(Common.getDeviceName())){
%switch(CANBSRCSEL.inputSelect){
% case "SYSCLK":
% canBclkSrc = "CAN_CLOCK_SOURCE_SYS"
% break
% case "XTAL":
% canBclkSrc = "CAN_CLOCK_SOURCE_XTAL"
% break
% case "AUXCLKIN":
% canBclkSrc = "CAN_CLOCK_SOURCE_AUX"
% break
%}
%}
%if(["F2807x", "F2837xD", "F2837xS"].includes(Common.getDeviceName())){
//
// Configure Analog Trim in case of untrimmed or TMX sample
//
if((SysCtl_getDeviceParametric(SYSCTL_DEVICE_QUAL) == 0x0U) &&
(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) == 0x0U))
{
Device_configureTMXAnalogTrim();
}
%}
//
// Set up PLL control and clock dividers
//
SysCtl_setClock(DEVICE_SETCLOCK_CFG);
//
// Make sure the LSPCLK divider is set to the default (divide by 4)
//
SysCtl_setLowSpeedClock(DEVICE_LSPCLK_CFG);
%if(["F2838x"].includes(Common.getDeviceName())){
//
// Set up AUXPLL control and clock dividers needed for CMCLK
//
SysCtl_setAuxClock(DEVICE_AUXSETCLOCK_CFG);
//
// Set up CMCLK to use AUXPLL as the clock source and set the
// clock divider to 1.
//
SysCtl_setCMClk(SYSCTL_CMCLKOUT_DIV_1,SYSCTL_SOURCE_AUXPLL);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
//
// Set up AUXPLL control and clock dividers needed for CMCLK
//
SysCtl_setAuxClock(DEVICE_AUXSETCLOCK_CFG);
%}
%if(["F2838x"].includes(Common.getDeviceName())){
// These asserts will check that the #defines for the clock rates in
// device.h match the actual rates that have been configured. If they do
// not match, check that the calculations of DEVICE_SYSCLK_FREQ,
// DEVICE_LSPCLK_FREQ and DEVICE_AUXCLK_FREQ are accurate. Some
// examples will not perform as expected if these are not correct.
//
%}else{
//
// These asserts will check that the #defines for the clock rates in
// device.h match the actual rates that have been configured. If they do
// not match, check that the calculations of DEVICE_SYSCLK_FREQ and
// DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
// expected if these are not correct.
//
%}
%if(["F2838x", "F2837xD", "F2807x", "F2837xS", "F28P65x"].includes(Common.getDeviceName())){
//
// From ClockTree Configurations
//
SysCtl_selectOscSourceAuxPLL(`oscclkSrc`);
%}
%if(["F280013x", "F280015x", "F28002x", "F28003x", "F28004x", "F2838x", "F2837xD", "F2807x", "F2837xS", "F28P65x"].includes(Common.getDeviceName())){
CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
%}
%//if(["F2838x", "F28003x", "F280015x"].includes(Common.getDeviceName())){ //FIXME: Uncomment when implemented
%// SysCtl_setMCANClk(DEVICE_CLK_MCAN_DIV);
%//}
%if(["F28P65x"].includes(Common.getDeviceName())){ //https://jira.itg.ti.com/browse/C2000DRIVERS-2792
SysCtl_setMCANClk(SYSCTL_MCANA, `DEVICE_CLK_MCANA_DIV`);
SysCtl_setMCANClk(SYSCTL_MCANB, `DEVICE_CLK_MCANB_DIV`);
%}
%if(["F2838x", "F2837xD", "F2807x", "F2837xS"].includes(Common.getDeviceName())){
CAN_selectClockSource(CANB_BASE, `canBclkSrc`);
%}
%if(["F2838x", "F2837xD", "F2807x", "F2837xS", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_setEPWMClockDivider(`DEVICE_CLK_EPWM_DIV`);
%}
%if(["F2838x", "F2837xD", "F2807x", "F2837xS", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_setEMIF1ClockDivider(`DEVICE_CLK_EMIF_DIV`);
%}
%if(["F2838x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_setECatClk(`DEVICE_CLK_ECAT_DIV`, `ecatclkSrc`, 0x1U);
%}
%if(["F2838x"].includes(Common.getDeviceName())){
SysCtl_setEnetClk(`DEVICE_CLK_ENET_DIV`, `enetclkSrc`);
%}
ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
%if(["F2838x", "F28P65x"].includes(Common.getDeviceName())){
ASSERT(SysCtl_getAuxClock(DEVICE_OSCSRC_FREQ) == DEVICE_AUXCLK_FREQ);
%}
#ifndef _FLASH
//
// Call Device_cal function when run using debugger
// This function is called as part of the Boot code. The function is called
// in the Device_init function since during debug time resets, the boot code
// will not be executed and the gel script will reinitialize all the
// registers and the calibrated values will be lost.
// Sysctl_deviceCal is a wrapper function for Device_Cal
//
SysCtl_deviceCal();
#endif
C2000Ware/driverlib/.meta/device/functions_c/Device_configureTMXAnalogTrim_c.xdt
+80
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@@ -0,0 +1,80 @@
%let Common = system.getScript("/driverlib/Common.js");
%if(["F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
//*****************************************************************************
//
// Function to implement Analog trim of TMX devices
//
//*****************************************************************************
void Device_configureTMXAnalogTrim(void)
{
//
// Enable ADC clock
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
%if(["F2837xS", "F2837xD"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
%}else{
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
//
// Configure ADC reference trim for TMX devices
//
EALLOW;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) = 0x7BDDU;
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMB) = 0x7BDDU;
%if(["F2837xS", "F2837xD"].includes(Common.getDeviceName())){
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMC) = 0x7BDDU;
%}else{
%}
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMD) = 0x7BDDU;
//
// Configure ADC offset trim. The user should generate the trim values
// by following the instructions in the "ADC Zero Offset Calibration"
// section in device TRM. The below lines needs to be uncommented and
// updated with the correct trim values.
//
// HWREGH(ADCA_BASE + ADC_O_OFFTRIM) = 0x0U;
// HWREGH(ADCB_BASE + ADC_O_OFFTRIM) = 0x0U;
%if(["F2837xS", "F2837xD"].includes(Common.getDeviceName())){
// HWREGH(ADCC_BASE + ADC_O_OFFTRIM) = 0x0U;
%}else{
%}
// HWREGH(ADCD_BASE + ADC_O_OFFTRIM) = 0x0U;
//
// Configure internal oscillator trim. If the internal oscillator trim
// contains all zeros, the user can adjust the lowest 10 bits of the
// oscillator trim register between 1 (minimum) and 1023 (maximum)
// while observing the system clock on the XCLOCKOUT pin. The below
// lines needs to be uncommented and updated with the correct trim values.
//
// if(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) == 0x0U)
// {
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) = 0x0U;
// }
// if( HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U)
// {
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U;
// }
EDIS;
//
// Disable ADC clock
//
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
%if(["F2837xS", "F2837xD"].includes(Common.getDeviceName())){
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
%}else{
%}
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
}
%}
C2000Ware/driverlib/.meta/device/functions_c/Device_enableAllPeripherals_c.xdt
+339
View File
@@ -0,0 +1,339 @@
%let Common = system.getScript("/driverlib/Common.js");
//*****************************************************************************
//
// Function to turn on all peripherals, enabling reads and writes to the
// peripherals' registers.
//
// Note that to reduce power, unused peripherals should be disabled.
//
//*****************************************************************************
void Device_enableAllPeripherals(void)
{
%if(["F2838x", "F28003x", "F28004x", "F2807X", "F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1);
%}
%if(["F2838x", "F28002x", "F28003x", "F28004x", "F2807x", "F2837xD", "F2837xS", "F28P65x" ].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA);
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2);
%if(["F2837xD"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#ifdef CPU1
%}
%if(["F28004x", "F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM);
%}
%if(["F2837xD"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#endif
%}
%if(["F28002x", "F28003x", "F280013x", "F280015x" ].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL);
%}
%if(["F2838x", "F28002x", "F28003x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CPUBGCRC);
%}
%if(["F2838x", "F28003x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1BGCRC);
%}
%if(["F2838x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#ifdef CPU1
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL);
#endif
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
%if(["F2838x", "F28002x", "F28003x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ERAD);
%}
%if(["F2837xD", "F2838x", "F28P65x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#ifdef CPU1
%}
%if(["F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1);
%}
%if(["F2838x", "F2837xD", "F2837xS"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2);
%}
%if(["F2838x", "F2837xD", "F28P65x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#endif
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7);
%if(["F2838x", "F28004x", "F28003x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8);
%}
%if(["F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12);
%}
%if(["F2838x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM13);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM14);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM15);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM16);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM17);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM18);
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2);
%if(["F280015x", "F28002x", "F28003x", "F28004x", "F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3);
%}
%if(["F28004x", "F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6);
%}
%if(["F28004x", "F2838x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP7);
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1);
%if(["F280015x", "F28002x", "F28003x", "F28004x", "F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2);
%}
%if(["F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP4);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP5);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP6);
%}
%if(["F28004x", "F2838x", "F28003x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1);
%}
%if(["F2838x", "F28003x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD3);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD4);
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA);
%if(["F280013x", "F280015x", "F28003x", "F28004x", "F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB);
%}
%if(["F280013x", "F280015x", "F2838x", "F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC);
%}
%if(["F2838x", "F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UARTA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UARTB);
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA);
%if(["F28002x", "F28003x", "F28004x", "F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB);
%}
%if(["F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC);
%}
%if(["F2838x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPID);
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA);
%if(["F28002x", "F28003x", "F280013x", "F280015x", "F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB);
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA);
%if(["F2838x", "F28004x", "F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB);
%}
%if(["F280015x", "F28003x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCANA);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCANB);
%}
%if(["F2838x", "F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB);
%}
%if(["F2838x", "F2837xD"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#ifdef CPU1
%}
%if(["F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA);
%}
%if(["F2837xS", "F2837xD"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA);
%}
%if(["F2838x", "F2837xD"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#endif
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
%if(["F28003x", "F28004x", "F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
%}
%if(["F28002x", "F28003x", "F28004x", "F280013x", "F280015x", "F2838x", "F2837xD", "F2837xS", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
%}
%if(["F2838x", "F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
%}
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4);
%if(["F28004x", "F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7);
%}
%if(["F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS9);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS10);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS11);
%}
%if(["F28004x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PGA1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PGA2);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PGA3);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PGA4);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PGA5);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PGA6);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PGA7);
%}
%if(["F2838x", "F28004x", "F2837xD", "F2837xS", "F2807x", "F28003x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA);
%}
%if(["F2838x", "F2837xD", "F2837xS", "F2807x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC);
%}
%if(["F2838x", "F28002x", "F28003x", "F28004x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB2);
%}
%if(["F2838x", "F28003x", "F28004x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB3);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB4);
%}
%if(["F2838x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB5);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB6);
%}
%if(["F2838x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB7);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB8);
%}
%if(["F280015x", "F28002x", "F28003x", "F28004x", "F2838x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PMBUSA);
%}
%if(["F28002x", "F28003x", "F28004x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSITXA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXA);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSITXB);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXB);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXC);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXD);
%}
%if(["F2838x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSITXA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSITXB);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXB);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXC);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXD);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXE);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXF);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXG);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXH);
%}
%if(["F280015x", "F28002x", "F28003x", "F28004x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_LINA);
%}
%if(["F28002x", "F28003x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_LINB);
%}
%if(["F2838x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#ifdef CPU1
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC0);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC2);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAT);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCANA);
#endif
%}
%if(["F280013x", "F280015x", "F28002x", "F28003x", "F28004x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC0);
%}
%if(["F28002x", "F28003x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC1);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC2);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAT);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL0);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL2);
%}
%if(["F280013x", "F280015x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPG1);
%}
%if(["F28002x", "F28003x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HICA);
%}
%if(["F28003x", "F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_AESA);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPG1);
%}
%if(["F28P65x"].includes(Common.getDeviceName())){
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCCHECKER1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCCHECKER2);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCCHECKER3);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCCHECKER4);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCCHECKER5);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCCHECKER6);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCCHECKER7);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCCHECKER8);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCSEAGGRCPU1);
%}
}
C2000Ware/driverlib/.meta/device/functions_c/Device_enableUnbondedGPIOPullupsFor176Pin_c.xdt
+27
View File
@@ -0,0 +1,27 @@
%let Common = system.getScript("/driverlib/Common.js");
%if (["F2838x", "F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the 176PTP package:
// GPIOs Grp Bits
// 95-132 C 31
// D 31:0
// E 4:0
// 134-168 E 31:6
// F 8:0
//
//*****************************************************************************
void Device_enableUnbondedGPIOPullupsFor176Pin(void)
{
EALLOW;
HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU;
HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU;
EDIS;
}
%}
%else{
%}
C2000Ware/driverlib/.meta/device/functions_c/Device_enableUnbondedGPIOPullups_c.xdt
+70
View File
@@ -0,0 +1,70 @@
%let Common = system.getScript("/driverlib/Common.js");
%if (["F2838x"].includes(Common.getDeviceName())){
//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the
// 176PTP package.
//
//*****************************************************************************
void Device_enableUnbondedGPIOPullups(void)
{
//
// bits 8-10 have pin count
//
uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
(uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >>
SYSCTL_PARTIDL_PIN_COUNT_S);
/*
* 6 = 176 pin
* 7 = 337 pin
*/
if (pinCount == 6)
{
Device_enableUnbondedGPIOPullupsFor176Pin();
}
else
{
//
// Do nothing - this is 337 pin package
//
}
}
%}
%else if(["F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the 100PZ or
// 176PTP package.
//
//*****************************************************************************
void Device_enableUnbondedGPIOPullups(void)
{
//
// bits 8-10 have pin count
//
uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
(uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >>
SYSCTL_PARTIDL_PIN_COUNT_S);
/*
* 5 = 100 pin
* 6 = 176 pin
* 7 = 337 pin
*/
if(pinCount == 5)
{
Device_enableUnbondedGPIOPullupsFor100Pin();
}
else if(pinCount == 6)
{
Device_enableUnbondedGPIOPullupsFor176Pin();
}
else
{
//
// Do nothing - this is 337 pin package
//
}
}
%}else{}
C2000Ware/driverlib/.meta/device/functions_c/Device_enableUnbondedGPIOPullupsfor100Pin_c.xdt
+34
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%let Common = system.getScript("/driverlib/Common.js");
%if (["F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the 100PZ package:
// GPIOs Grp Bits
// 0-1 A 1:0
// 5-9 A 9:5
// 22-40 A 31:22
// B 8:0
// 44-57 B 25:12
// 67-68 C 4:3
// 74-77 C 13:10
// 79-83 C 19:15
// 93-168 C 31:29
// D 31:0
// E 31:0
// F 8:0
//
//*****************************************************************************
void Device_enableUnbondedGPIOPullupsFor100Pin(void)
{
EALLOW;
HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU;
HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU;
HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU;
EDIS;
}
%}
%else{
%}
C2000Ware/driverlib/.meta/device/functions_c/Device_error_c.xdt
+17
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%let Common = system.getScript("/driverlib/Common.js");
%if (["F2807x", "F2837xD", "F2837xS", "F2838x", "F28002x", "F28003x", "F28004x", "F280013x", "F280015x", "F28P65x"].includes(Common.getDeviceName())){
//*****************************************************************************
//
// Error handling function to be called when an ASSERT is violated
//
//*****************************************************************************
void __error__(const char *filename, uint32_t line)
{
//
// An ASSERT condition was evaluated as false. You can use the filename and
// line parameters to determine what went wrong.
//
ESTOP0;
}
%}else
%{}
C2000Ware/driverlib/.meta/device/functions_c/Device_include_c.xdt
+100
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%let Common = system.getScript("/driverlib/Common.js");
//#############################################################################
//
// FILE: device.c
//
// TITLE: Device setup for examples.
//
//#############################################################################
/*
* Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//#############################################################################
//
// Included Files
//
#include "device.h"
#include "board.h"
#include "clocktree.h"
%if (["F2838x"].includes(Common.getDeviceName())){
#ifdef CMDTOOL
#include "device_cmd.h"
#endif
%}
%else if(["F28002x", "F28003x", "F280013x", "F28P65x"].includes(Common.getDeviceName())){
#include "driverlib.h"
#ifdef __cplusplus
using std::memcpy;
#endif
#ifdef CMDTOOL
#include "device_cmd.h"
#endif
%}
%else if(["F28004x"].includes(Common.getDeviceName())){
#include "driverlib.h"
#ifdef __cplusplus
using std::memcpy;
#endif
#ifdef CMDTOOL
#include "device_cmd.h"
#endif
%}
%else if(["F280015x"].includes(Common.getDeviceName())){
#include "driverlib.h"
#include "inc/hw_lcm.h"
#ifdef __cplusplus
using std::memcpy;
#endif
#ifdef CMDTOOL
#include "device_cmd.h"
#endif
%}else if(["F2807x", "F2837xS"].includes(Common.getDeviceName())){
#include "driverlib.h"
#ifdef CMDTOOL
#include "device_cmd.h"
#endif
#ifdef __cplusplus
using std::memcpy;
#endif
%}else if(["F2837xD"].includes(Common.getDeviceName())){
#include "driverlib.h"
#include "inc/hw_ipc.h"
#ifdef CMDTOOL
#include "device_cmd.h"
#endif
#ifdef __cplusplus
using std::memcpy;
#endif
%}
C2000Ware/driverlib/.meta/device/functions_c/Device_initGPIO_c.xdt
+39
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%let Common = system.getScript("/driverlib/Common.js");
//*****************************************************************************
//
// Function to disable pin locks and enable pullups on GPIOs.
//
//*****************************************************************************
void Device_initGPIO(void)
{
//
// Disable pin locks.
//
%if (["F2838x", "F2837xD", "F2837xS", "F2807x"].includes(Common.getDeviceName())){
GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF);
//
// Enable GPIO Pullups
//
Device_enableUnbondedGPIOPullups();
%}
%if (["F28002x", "F28003x", "F28004x", "F280013x", "F280015x"].includes(Common.getDeviceName())){
GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_H, 0xFFFFFFFF);
%}
%if (["F28P65x"].includes(Common.getDeviceName())){
GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_H, 0xFFFFFFFF);
%}
}
C2000Ware/driverlib/.meta/device/functions_c/Device_init_c.xdt
+175
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
%if (["F280013x", "F280015x", "F28004x", "F28003x"].includes(Common.getDeviceName())){
%if (["F280013x", "F280015x"].includes(Common.getDeviceName())){
// The function also configures the AGPIO pins 12, 13, 20, 21, 28 in digital mode.
%}
%if (["F28004x", "F28003x"].includes(Common.getDeviceName())){
// The function also configures the GPIO pins 22 and 23 in digital mode.
%}
%if(["F28P65x"].includes(Common.getDeviceName()))
%{
// The function also configures the GPIO pins 20 and 21 in digital mode.
%}
// To configure these pins as analog pins, use the function GPIO_setAnalogMode
%}if(["F28002x", "F28003x", "F28004x", "F28P65x"].includes(Common.getDeviceName())){
//
// Note : In case XTAL is used as the PLL source, it is recommended to invoke
// the Device_verifyXTAL() before configuring PLL
//
%}
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
%if(["F2838x","F28002x", "F28003x", "F28004x", "F280013x", "F280015x", "F2807x", "F2837xD", "F2837xS", "F28P65x"].includes(Common.getDeviceName())){
#ifdef CMDTOOL
CMD_init();
#endif
%}
#ifdef _FLASH
%if(["F28002x", "F28003x", "F28004x", "F280013x", "F280015x", "F2838x", "F2807x", "F2837xD", "F2837xS", "F28P65x"].includes(Common.getDeviceName())){
#ifndef CMDTOOL
%}
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
%if(["F28002x", "F28003x", "F28004x", "F280013x", "F280015x", "F2838x", "F2807x", "F2837xD", "F2837xS", "F28P65x"].includes(Common.getDeviceName())){
#endif
%}
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
%if(["F2838x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#ifdef CPU1
//
// Verify the crystal frequency.
// Note: This check can be removed if you are not using XTAL as the PLL
// source
//
if( ((DEVICE_SETCLOCK_CFG & SYSCTL_OSCSRC_M) == SYSCTL_OSCSRC_XTAL) ||
((DEVICE_SETCLOCK_CFG & SYSCTL_OSCSRC_M) == SYSCTL_OSCSRC_XTAL_SE))
{
if(!Device_verifyXTAL(DEVICE_OSCSRC_FREQ / 1000000))
{
//
// The actual XTAL frequency does not match DEVICE_OSCSRC_FREQ!!
// Please check the XTAL frequency used.
//
// By default, the Device_init function assumes 25MHz XTAL.
// If a 20MHz crystal is used, please add a predefined symbol
// "USE_20MHZ_XTAL" in your CCS project.
// If a different XTAL is used, please update the DEVICE_SETCLOCK_CFG
// macro accordingly.
//
// Note that the latest F2838x controlCARDs (Rev.B and later) have been
// updated to use 25MHz XTAL by default. If you have an older 20MHz XTAL
// controlCARD (E1, E2, or Rev.A), refer to the controlCARD
// documentation on steps to reconfigure the controlCARD from 20MHz to
// 25MHz.
//
ESTOP0;
while(1);
}
}
%}
%if(["F2837xD", "F2837xS"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#ifdef CPU1
%}
%if (!Common.isContextCPU2()){
`Clock_tree_template()`
%}
%if(["F2837xD", "F2837xS"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#endif
%}
%if(["F2838x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#endif
%}
%if(["F28002x","F28003x","F280013x","F280015x", "F28P65x"].includes(Common.getDeviceName())){
//
// Lock VREGCTL Register
// The register VREGCTL is not supported in this device. It is locked to
// prevent any writes to this register
//
ASysCtl_lockVREG();
%}else if(["F28004x"].includes(Common.getDeviceName())){
//
//Disable DC DC in Analog block
//
ASysCtl_disableDCDC();
//
//Configure GPIO in Push Pull,Output Mode
//
GPIO_setPadConfig(22U, GPIO_PIN_TYPE_STD);
GPIO_setPadConfig(23U, GPIO_PIN_TYPE_STD);
GPIO_setDirectionMode(22U, GPIO_DIR_MODE_OUT);
GPIO_setDirectionMode(23U, GPIO_DIR_MODE_OUT);
//
// Configure GPIO22 and GPIO23 as digital pins
//
GPIO_setAnalogMode(22U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(23U, GPIO_ANALOG_DISABLED);
%}else if(["F2838x"].includes(Common.getDeviceName())){
Device_initGPIO();
%}
%if(["F28003x"].includes(Common.getDeviceName())){
//
// Configure GPIO20 and GPIO21 as digital pins
//
GPIO_setAnalogMode(20U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(21U, GPIO_ANALOG_DISABLED);
%} else if(["F280013x","F280015x"].includes(Common.getDeviceName())){
//
// Configure the portA AGPIOs as digital pins
//
GPIO_setAnalogMode(12U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(13U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(20U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(21U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(28U, GPIO_ANALOG_DISABLED);
%}
%if(["F280015x"].includes(Common.getDeviceName())){
//
// Enable lockstep compare module
//
HWREG_BP(LCM_CPU1_BASE + LCM_O_CONTROL) |= LCM_CONTROL_CMPEN;
%}
}
C2000Ware/driverlib/.meta/device/functions_c/Device_verifyXTAL_c.xdt
+95
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%let Common = system.getScript("/driverlib/Common.js");
%if(["F2838x", "F28002x", "F28003x", "F28004x", "F28P65x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
//*****************************************************************************
//
// Function to verify the XTAL frequency
// freq is the XTAL frequency in MHz
// The function return true if the the actual XTAL frequency matches with the
// input value
//
// Note that this function assumes that the PLL is not already configured and
// hence uses SysClk freq = 10MHz for DCC calculation
//
//*****************************************************************************
%}
%if(["F2838x"].includes(Common.getDeviceName()) && Common.isContextCPU1()){
#ifdef CPU1
bool Device_verifyXTAL(float freq)
{
//
// Use DCC to verify the XTAL frequency using INTOSC2 as reference clock
//
//
// Enable DCC0 clock
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC0);
//
// Insert atleast 5 cycles delay after enabling the peripheral clock
//
asm(" RPT #5 || NOP");
//
// Configures XTAL as CLKSRC0 and INTOSC2 as CLKSRC1
// Fclk0 = XTAL frequency (input parameter)
// Fclk1 = INTOSC2 frequency = 10MHz
//
// Configuring DCC error tolerance of +/-1%
// INTOSC2 can have a variance in frequency of +/-10%
//
// Assuming PLL is not already configured, SysClk freq = 10MHz
//
// Note : Update the tolerance and INTOSC2 frequency variance as necessary.
//
return (DCC_verifyClockFrequency(DCC0_BASE,
DCC_COUNT1SRC_INTOSC2, 10.0F,
DCC_COUNT0SRC_XTAL, freq,
1.0F, 10.0F, 10.0F));
}
#endif
%}
%if(["F28002x", "F28003x", "F28004x", "F28P65x"].includes(Common.getDeviceName())){
bool Device_verifyXTAL(float freq)
{
//
// Use DCC to verify the XTAL frequency using INTOSC2 as reference clock
//
//
// Turn on XTAL and wait for it to power up using X1CNT
//
SysCtl_turnOnOsc(SYSCTL_OSCSRC_XTAL);
SysCtl_clearExternalOscCounterValue();
while(SysCtl_getExternalOscCounterValue() != SYSCTL_X1CNT_X1CNT_M);
//
// Enable DCC0 clock
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC0);
//
// Insert atleast 5 cycles delay after enabling the peripheral clock
//
asm(" RPT #5 || NOP");
//
// Configures XTAL as CLKSRC0 and INTOSC2 as CLKSRC1
// Fclk0 = XTAL frequency (input parameter)
// Fclk1 = INTOSC2 frequency = 10MHz
//
// Configuring DCC error tolerance of +/-1%
// INTOSC2 can have a variance in frequency of +/-10%
//
// Assuming PLL is not already configured, SysClk freq = 10MHz
//
// Note : Update the tolerance and INTOSC2 frequency variance as necessary.
//
return (DCC_verifyClockFrequency(DCC0_BASE,
DCC_COUNT1SRC_INTOSC2, 10.0F,
DCC_COUNT0SRC_XTAL, freq,
1.0F, 10.0F, 10.0F));
}
%}
C2000Ware/driverlib/.meta/device/functions_c/EnableAllPeripherals/Enable_All_Peripherals.xdt
+144
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@@ -0,0 +1,144 @@
%%{
let Common = system.getScript("/driverlib/Common.js");
let device_driverlib_peripheral = system.getScript("/driverlib/device_driverlib_peripherals/" +
Common.getDeviceName().toLowerCase() + "_sysctl.js");
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
const device = device_common.device;
const EnableAllPeripherals_CLK_HRCAL = device_common.EnableAllPeripherals_CLK_HRCAL;
const EnableAllPeripherals_CLK_HRPWM = device_common.EnableAllPeripherals_CLK_HRPWM;
const EnableAllPeripherals_CLK_EMIF_With_If = device_common.EnableAllPeripherals_CLK_EMIF_With_If;
const EnableAllPeripherals_CLK_EMIF1 = device_common.EnableAllPeripherals_CLK_EMIF1;
const EnableAllPeripherals_CLK_EMIF2 = device_common.EnableAllPeripherals_CLK_EMIF2;
const EnableAllPeripherals_CLK_USB_UPPA = device_common.EnableAllPeripherals_CLK_USB_UPPA;
const EnableAllPeripherals_CLK_USBA = device_common.EnableAllPeripherals_CLK_USBA;
const EnableAllPeripherals_CLK_UPPA = device_common.EnableAllPeripherals_CLK_UPPA;
const EnableAllPeripherals_CLK_DCC_ECAT_MCAN = device_common.EnableAllPeripherals_CLK_DCC_ECAT_MCAN;
const EnableAllPeripherals_CLK_CLA1BGCRC = device_common.EnableAllPeripherals_CLK_CLA1BGCRC;
const EnableAllPeripherals_CLK_PMBUSA = device_common.EnableAllPeripherals_CLK_PMBUSA;
const EnableAllPeripherals_CLK_CLA1 = device_common.EnableAllPeripherals_CLK_CLA1;
%%}
//*****************************************************************************
//
// Function to turn on all peripherals, enabling reads and writes to the
// peripherals' registers.
//
// Note that to reduce power, unused peripherals should be disabled.
//
//*****************************************************************************
void Device_enableAllPeripherals(void)
{
% for (let perphEnable of device_driverlib_peripheral.SysCtl_PeripheralPCLOCKCR)
% {
% if (!["SYSCTL_PERIPH_CLK_GTBCLKSYNC","SYSCTL_PERIPH_CLK_CLA1BGCRC","SYSCTL_PERIPH_CLK_MPOST0",
%"SYSCTL_PERIPH_CLK_PMBUSA","SYSCTL_PERIPH_CLK_CLA1","SYSCTL_PERIPH_CLK_PBIST","SYSCTL_PERIPH_CLK_HRCAL","SYSCTL_PERIPH_CLK_HRPWM",
%"SYSCTL_PERIPH_CLK_EMIF1","SYSCTL_PERIPH_CLK_EMIF2","SYSCTL_PERIPH_CLK_USBA","SYSCTL_PERIPH_CLK_UPPA",
%"SYSCTL_PERIPH_CLK_DCC0","SYSCTL_PERIPH_CLK_DCC1","SYSCTL_PERIPH_CLK_DCC2","SYSCTL_PERIPH_CLK_ECAT",
%"SYSCTL_PERIPH_CLK_MCANA"].includes(perphEnable.name)) {
SysCtl_enablePeripheral(`perphEnable.name`);
% }
% if(["SYSCTL_PERIPH_CLK_CLA1BGCRC"].includes(perphEnable.name) && EnableAllPeripherals_CLK_CLA1BGCRC.includes(device))
%{
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1BGCRC);
%}
% if(["SYSCTL_PERIPH_CLK_PMBUSA"].includes(perphEnable.name) && EnableAllPeripherals_CLK_PMBUSA.includes(device))
%{
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PMBUSA);
%}
% if(["SYSCTL_PERIPH_CLK_CLA1"].includes(perphEnable.name) && EnableAllPeripherals_CLK_CLA1.includes(device))
%{
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1);
%}
% if(["SYSCTL_PERIPH_CLK_HRCAL"].includes(perphEnable.name))
%{
% if (EnableAllPeripherals_CLK_HRCAL.includes(device)&& (Common.isContextCPU1()))
%{
#ifdef CPU1
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL);
#endif
%}
% else
%{
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL);
%}
%}
% if(["SYSCTL_PERIPH_CLK_HRPWM"].includes(perphEnable.name))
%{
% if (EnableAllPeripherals_CLK_HRPWM.includes(device)&& (Common.isContextCPU1()))
%{
#ifdef CPU1
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM);
#endif
%}
% else
%{
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM);
%}
%}
% if(["SYSCTL_PERIPH_CLK_EMIF1"].includes(perphEnable.name))
%{
% if (EnableAllPeripherals_CLK_EMIF_With_If.includes(device)&& (Common.isContextCPU1()))
%{
#ifdef CPU1
SysCtl_enablePeripheral(`perphEnable.name`);
#endif
%}
% if (EnableAllPeripherals_CLK_EMIF1.includes(device)&& (Common.isContextCPU1()))
%{
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1);
%}
%}
% if(["SYSCTL_PERIPH_CLK_EMIF2"].includes(perphEnable.name))
%{
% if (EnableAllPeripherals_CLK_EMIF_With_If.includes(device)&& (Common.isContextCPU1()))
%{
#ifdef CPU1
SysCtl_enablePeripheral(`perphEnable.name`);
#endif
%}
% if (EnableAllPeripherals_CLK_EMIF2.includes(device)&& (Common.isContextCPU1()))
%{
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2);
%}
%}
% if(["SYSCTL_PERIPH_CLK_USBA"].includes(perphEnable.name))
%{
% if (EnableAllPeripherals_CLK_USB_UPPA.includes(device)&& (Common.isContextCPU1()))
%{
#ifdef CPU1
SysCtl_enablePeripheral(`perphEnable.name`);
#endif
%}
% if (EnableAllPeripherals_CLK_USBA.includes(device)&& (Common.isContextCPU1()))
%{
SysCtl_enablePeripheral(`perphEnable.name`);
%}
%}
% if(["SYSCTL_PERIPH_CLK_UPPA"].includes(perphEnable.name))
%{
% if (EnableAllPeripherals_CLK_USB_UPPA.includes(device)&& (Common.isContextCPU1()))
%{
#ifdef CPU1
SysCtl_enablePeripheral(`perphEnable.name`);
#endif
%}
% if (EnableAllPeripherals_CLK_UPPA.includes(device))
%{
SysCtl_enablePeripheral(`perphEnable.name`);
%}
%}
% if(["SYSCTL_PERIPH_CLK_DCC0","SYSCTL_PERIPH_CLK_DCC1","SYSCTL_PERIPH_CLK_DCC2","SYSCTL_PERIPH_CLK_ECAT","SYSCTL_PERIPH_CLK_MCANA"].includes(perphEnable.name))
%{
% if (EnableAllPeripherals_CLK_DCC_ECAT_MCAN.includes(device)&& (Common.isContextCPU1()))
%{
#ifdef CPU1
SysCtl_enablePeripheral(`perphEnable.name`);
#endif
%}
% else
%{
SysCtl_enablePeripheral(`perphEnable.name`);
%}
%}
% }
}
C2000Ware/driverlib/.meta/device/functions_c/EnableUnboundedGPIOPullups/Enable_Unbounded_GPIO_Pullups.xdt
+18
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@@ -0,0 +1,18 @@
%%{
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let Common = system.getScript("/driverlib/Common.js");
var Enable_Unbounded_GPIO_Pullups_176PTP = system.getTemplate('./Enable_Unbounded_GPIO_Pullups_176PTP.xdt');
var Enable_Unbounded_GPIO_Pullups_100PZ_176PTP = system.getTemplate('./Enable_Unbounded_GPIO_Pullups_100PZ_176PTP.xdt');
const device = device_common.device;
const Enable_Unbounded_GPIO_Pullups_100PZ_176PTP_Type0 = device_common.Enable_Unbounded_GPIO_Pullups_100PZ_176PTP_Type0;
const Enable_Unbounded_GPIO_Pullups_176PTP_Type0 = device_common.Enable_Unbounded_GPIO_Pullups_176PTP_Type0;
%%}
% if(Enable_Unbounded_GPIO_Pullups_100PZ_176PTP_Type0.includes(device))
%{
`Enable_Unbounded_GPIO_Pullups_100PZ_176PTP()`
%}
% if(Enable_Unbounded_GPIO_Pullups_176PTP_Type0.includes(device))
%{
`Enable_Unbounded_GPIO_Pullups_176PTP()`
%}
C2000Ware/driverlib/.meta/device/functions_c/EnableUnboundedGPIOPullups/Enable_Unbounded_GPIO_Pullups_100PZ_176PTP.xdt
+88
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//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the 100PZ package:
// GPIOs Grp Bits
// 0-1 A 1:0
// 5-9 A 9:5
// 22-40 A 31:22
// B 8:0
// 44-57 B 25:12
// 67-68 C 4:3
// 74-77 C 13:10
// 79-83 C 19:15
// 93-168 C 31:29
// D 31:0
// E 31:0
// F 8:0
//
//*****************************************************************************
void Device_enableUnbondedGPIOPullupsFor100Pin(void)
{
EALLOW;
HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU;
HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU;
HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU;
EDIS;
}
//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the 176PTP package:
// GPIOs Grp Bits
// 95-132 C 31
// D 31:0
// E 4:0
// 134-168 E 31:6
// F 8:0
//
//*****************************************************************************
void Device_enableUnbondedGPIOPullupsFor176Pin(void)
{
EALLOW;
HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU;
HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU;
EDIS;
}
//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the 100PZ or
// 176PTP package.
//
//*****************************************************************************
void Device_enableUnbondedGPIOPullups(void)
{
//
// bits 8-10 have pin count
//
uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
(uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >>
SYSCTL_PARTIDL_PIN_COUNT_S);
/*
* 5 = 100 pin
* 6 = 176 pin
* 7 = 337 pin
*/
if(pinCount == 5)
{
Device_enableUnbondedGPIOPullupsFor100Pin();
}
else if(pinCount == 6)
{
Device_enableUnbondedGPIOPullupsFor176Pin();
}
else
{
//
// Do nothing - this is 337 pin package
//
}
}
C2000Ware/driverlib/.meta/device/functions_c/EnableUnboundedGPIOPullups/Enable_Unbounded_GPIO_Pullups_176PTP.xdt
+53
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//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the 176PTP package:
// GPIOs Grp Bits
// 95-132 C 31
// D 31:0
// E 4:0
// 134-168 E 31:6
// F 8:0
//
//*****************************************************************************
void Device_enableUnbondedGPIOPullupsFor176Pin(void)
{
EALLOW;
HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U;
HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU;
HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU;
EDIS;
}
//*****************************************************************************
//
// Function to enable pullups for the unbonded GPIOs on the
// 176PTP package.
//
//*****************************************************************************
void Device_enableUnbondedGPIOPullups(void)
{
//
// bits 8-10 have pin count
//
uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
(uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >>
SYSCTL_PARTIDL_PIN_COUNT_S);
/*
* 6 = 176 pin
* 7 = 337 pin
*/
if (pinCount == 6)
{
Device_enableUnbondedGPIOPullupsFor176Pin();
}
else
{
//
// Do nothing - this is 337 pin package
//
}
}
C2000Ware/driverlib/.meta/device/functions_c/ErrorChecking/Error_Handling.xdt
+13
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//*****************************************************************************
//
// Error handling function to be called when an ASSERT is violated
//
//*****************************************************************************
void __error__(const char *filename, uint32_t line)
{
//
// An ASSERT condition was evaluated as false. You can use the filename and
// line parameters to determine what went wrong.
//
ESTOP0;
}
C2000Ware/driverlib/.meta/device/functions_c/Include/Include.xdt
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%%{
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let Common = system.getScript("/driverlib/Common.js");
var Include_Headers = system.getTemplate('./Include_Headers.xdt');
var Include_Headers_driverlib = system.getTemplate('./Include_Headers_driverlib.xdt');
var Include_Headers_hw_ipc = system.getTemplate('./Include_Headers_hw_ipc.xdt');
var Include_Headers_hw_lcm = system.getTemplate('./Include_Headers_hw_lcm.xdt');
const multi_core = device_common.multi_core;
const device = device_common.device;
const Include_Headers_Type0 = device_common.Include_Headers_Type0;
const Include_Headers_Type1 = device_common.Include_Headers_Type1;
const Include_Headers_Type2 = device_common.Include_Headers_Type2;
const Include_Headers_Type3 = device_common.Include_Headers_Type3;
%%}
% if(Include_Headers_Type0.includes(device))
%{
`Include_Headers()`
%}
% if(Include_Headers_Type1.includes(device))
%{
`Include_Headers_hw_ipc()`
%}
% if(Include_Headers_Type2.includes(device))
%{
`Include_Headers_hw_lcm()`
%}
% if(Include_Headers_Type3.includes(device))
%{
`Include_Headers_driverlib()`
%}
C2000Ware/driverlib/.meta/device/functions_c/Include/Include_Headers.xdt
+51
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//#############################################################################
//
// FILE: device.c
//
// TITLE: Device setup for examples.
//
//#############################################################################
/*
* Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//#############################################################################
//
// Included Files
//
#include "device.h"
#include "board.h"
#include "clocktree.h"
#ifdef CMDTOOL
#include "device_cmd.h"
#endif
C2000Ware/driverlib/.meta/device/functions_c/Include/Include_Headers_driverlib.xdt
+54
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//#############################################################################
//
// FILE: device.c
//
// TITLE: Device setup for examples.
//
//#############################################################################
/*
* Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//#############################################################################
//
// Included Files
//
#include "device.h"
#include "board.h"
#include "clocktree.h"
#include "driverlib.h"
#ifdef __cplusplus
using std::memcpy;
#endif
#ifdef CMDTOOL
#include "device_cmd.h"
#endif
C2000Ware/driverlib/.meta/device/functions_c/Include/Include_Headers_hw_ipc.xdt
+56
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//#############################################################################
//
// FILE: device.c
//
// TITLE: Device setup for examples.
//
//#############################################################################
/*
* Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//#############################################################################
//
// Included Files
//
#include "device.h"
#include "board.h"
#include "clocktree.h"
#include "driverlib.h"
#include "inc/hw_ipc.h"
#ifdef CMDTOOL
#include "device_cmd.h"
#endif
#ifdef __cplusplus
using std::memcpy;
#endif
C2000Ware/driverlib/.meta/device/functions_c/Include/Include_Headers_hw_lcm.xdt
+56
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@@ -0,0 +1,56 @@
//#############################################################################
//
// FILE: device.c
//
// TITLE: Device setup for examples.
//
//#############################################################################
/*
* Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//#############################################################################
//
// Included Files
//
#include "device.h"
#include "board.h"
#include "clocktree.h"
#include "driverlib.h"
#include "inc/hw_lcm.h"
#ifdef __cplusplus
using std::memcpy;
#endif
#ifdef CMDTOOL
#include "device_cmd.h"
#endif
C2000Ware/driverlib/.meta/device/functions_c/InitGPIO/InitGPIO.xdt
+32
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%%{
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let Common = system.getScript("/driverlib/Common.js");
var InitGPIO_PortA_B_C_D_E_F = system.getTemplate('./InitGPIO_PortA_B_C_D_E_F.xdt');
var InitGPIO_PortA_B_H_Type0 = system.getTemplate('./InitGPIO_PortA_B_H_Type0.xdt');
var InitGPIO_PortA_B_C_D_E_F_H_Type1 = system.getTemplate('./InitGPIO_PortA_B_C_D_E_F_H_Type1.xdt');
var InitGPIO_PortA_B_C_G_H_Type2 = system.getTemplate('./InitGPIO_PortA_B_C_G_H_Type2.xdt');
const multi_core = device_common.multi_core;
const device = device_common.device;
const InitGPIO_PortA_PortF_Type0 = device_common.InitGPIO_PortA_PortF_Type0;
const InitGPIO_PortA_PortH_Type0 = device_common.InitGPIO_PortA_PortH_Type0;
const InitGPIO_PortA_PortH_Type1 = device_common.InitGPIO_PortA_PortH_Type1;
const InitGPIO_PortA_PortH_Type2 = device_common.InitGPIO_PortA_PortH_Type2;
%%}
% if(InitGPIO_PortA_PortF_Type0.includes(device))
%{
`InitGPIO_PortA_B_C_D_E_F()`
%}
% if(InitGPIO_PortA_PortH_Type0.includes(device))
%{
`InitGPIO_PortA_B_H_Type0()`
%}
% if(InitGPIO_PortA_PortH_Type1.includes(device))
%{
`InitGPIO_PortA_B_C_D_E_F_H_Type1()`
%}
% if(InitGPIO_PortA_PortH_Type2.includes(device))
%{
`InitGPIO_PortA_B_C_G_H_Type2()`
%}
C2000Ware/driverlib/.meta/device/functions_c/InitGPIO/InitGPIO_PortA_B_C_D_E_F.xdt
+22
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@@ -0,0 +1,22 @@
//*****************************************************************************
//
// Function to disable pin locks and enable pullups on GPIOs.
//
//*****************************************************************************
void Device_initGPIO(void)
{
//
// Disable pin locks.
//
GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF);
//
// Enable GPIO Pullups
//
Device_enableUnbondedGPIOPullups();
}
C2000Ware/driverlib/.meta/device/functions_c/InitGPIO/InitGPIO_PortA_B_C_D_E_F_H_Type1.xdt
+18
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@@ -0,0 +1,18 @@
//*****************************************************************************
//
// Function to disable pin locks and enable pullups on GPIOs.
//
//*****************************************************************************
void Device_initGPIO(void)
{
//
// Disable pin locks.
//
GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_H, 0xFFFFFFFF);
}
C2000Ware/driverlib/.meta/device/functions_c/InitGPIO/InitGPIO_PortA_B_C_G_H_Type2.xdt
+16
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//*****************************************************************************
//
// Function to disable pin locks and enable pullups on GPIOs.
//
//*****************************************************************************
void Device_initGPIO(void)
{
//
// Disable pin locks.
//
GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_G, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_H, 0xFFFFFFFF);
}
C2000Ware/driverlib/.meta/device/functions_c/InitGPIO/InitGPIO_PortA_B_H_Type0.xdt
+14
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@@ -0,0 +1,14 @@
//*****************************************************************************
//
// Function to disable pin locks and enable pullups on GPIOs.
//
//*****************************************************************************
void Device_initGPIO(void)
{
//
// Disable pin locks.
//
GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
GPIO_unlockPortConfig(GPIO_PORT_H, 0xFFFFFFFF);
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization.xdt
+71
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%%{
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let Common = system.getScript("/driverlib/Common.js");
var Initilization_General = system.getTemplate('./Initilization_General.xdt');
var Initilization_General_Dual_Core = system.getTemplate('./Initilization_General_Dual_Core.xdt');
var Initilization_AGPIO = system.getTemplate('./Initilization_AGPIO.xdt');
var Initilization_AGPIO_Enable_Lockstep = system.getTemplate('./Initilization_AGPIO_Enable_Lockstep.xdt');
var Initilization_GPIO_22_23_Disable_DCDC = system.getTemplate('./Initilization_GPIO_22_23_Disable_DCDC.xdt');
var Initilization_GPIO_20_21_Lock_VREGCTL_Type0 = system.getTemplate('./Initilization_GPIO_20_21_Lock_VREGCTL_Type0.xdt');
var Initilization_Lock_VREGCTL_Dual_Core_Type0 = system.getTemplate('./Initilization_Lock_VREGCTL_Dual_Core_Type0.xdt');
var Initilization_Lock_VREGCTL_EnablePeripherals = system.getTemplate('./Initilization_Lock_VREGCTL_EnablePeripherals.xdt');
var Initilization_XTAL = system.getTemplate('./Initilization_XTAL.xdt');
var Initilization_Device_initGPIO = system.getTemplate('./Initilization_Device_initGPIO.xdt');
const multi_core = device_common.multi_core;
const device = device_common.device;
const Initilization_General_Type0 = device_common.Initilization_General_Type0;
const Initilization_General_Type1 = device_common.Initilization_General_Type1;
const Initilization_AGPIO_Type0 = device_common.Initilization_AGPIO_Type0;
const Initilization_AGPIO_Type1 = device_common.Initilization_AGPIO_Type1;
const Initilization_GPIO_22_23 = device_common.Initilization_GPIO_22_23;
const Initilization_GPIO_20_21_Type0 = device_common.Initilization_GPIO_20_21_Type0;
const Initilization_AGPIO_Dual_Core_Type0 = device_common.Initilization_AGPIO_Dual_Core_Type0;
const Initilization_GPIO_11_28 = device_common.Initilization_GPIO_11_28;
const Initilization_XTAL_Type0 = device_common.Initilization_XTAL_Type0;
const Initilization_Device_initGPIO_Type0 = device_common.Initilization_Device_initGPIO_Type0;
%%}
% if(Initilization_General_Type0.includes(device))
%{
`Initilization_General_Dual_Core()`
%}
% if(Initilization_General_Type1.includes(device))
%{
`Initilization_General()`
%}
% if(Initilization_AGPIO_Type0.includes(device))
%{
`Initilization_AGPIO()`
%}
% if(Initilization_AGPIO_Type1.includes(device))
%{
`Initilization_AGPIO_Enable_Lockstep()`
%}
% if(Initilization_GPIO_22_23.includes(device))
%{
`Initilization_GPIO_22_23_Disable_DCDC()`
%}
% if(Initilization_GPIO_20_21_Type0.includes(device))
%{
`Initilization_GPIO_20_21_Lock_VREGCTL_Type0()`
%}
% if(Initilization_AGPIO_Dual_Core_Type0.includes(device))
%{
`Initilization_Lock_VREGCTL_Dual_Core_Type0()`
%}
% if(Initilization_GPIO_11_28.includes(device))
%{
`Initilization_Lock_VREGCTL_EnablePeripherals()`
%}
% if(Initilization_XTAL_Type0.includes(device))
%{
`Initilization_XTAL()`
%}
% if(Initilization_Device_initGPIO_Type0.includes(device))
%{
`Initilization_Device_initGPIO()`
%}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_AGPIO.xdt
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
// The function also configures the AGPIO pins 12, 13, 20, 21, 28 in digital mode.
// To configure these pins as analog pins, use the function GPIO_setAnalogMode
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
%if (!Common.isContextCPU2()){
`Clock_tree_template()`
%}
//
// Lock VREGCTL Register
// The register VREGCTL is not supported in this device. It is locked to
// prevent any writes to this register
//
ASysCtl_lockVREG();
//
// Configure the portA AGPIOs as digital pins
//
GPIO_setAnalogMode(12U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(13U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(20U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(21U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(28U, GPIO_ANALOG_DISABLED);
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_AGPIO_Enable_Lockstep.xdt
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
// The function also configures the AGPIO pins 12, 13, 20, 21, 28 in digital mode.
// To configure these pins as analog pins, use the function GPIO_setAnalogMode
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
%if (!Common.isContextCPU2()){
`Clock_tree_template()`
%}
//
// Lock VREGCTL Register
// The register VREGCTL is not supported in this device. It is locked to
// prevent any writes to this register
//
ASysCtl_lockVREG();
//
// Configure the portA AGPIOs as digital pins
//
GPIO_setAnalogMode(12U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(13U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(20U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(21U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(28U, GPIO_ANALOG_DISABLED);
//
// Enable lockstep compare module
//
HWREG_BP(LCM_CPU1_BASE + LCM_O_CONTROL) |= LCM_CONTROL_CMPEN;
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_Device_initGPIO.xdt
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% let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
#ifdef CPU1
//
// Verify the crystal frequency.
// Note: This check can be removed if you are not using XTAL as the PLL
// source
//
if( ((DEVICE_SETCLOCK_CFG & SYSCTL_OSCSRC_M) == SYSCTL_OSCSRC_XTAL) ||
((DEVICE_SETCLOCK_CFG & SYSCTL_OSCSRC_M) == SYSCTL_OSCSRC_XTAL_SE))
{
if(!Device_verifyXTAL(DEVICE_OSCSRC_FREQ / 1000000))
{
//
// The actual XTAL frequency does not match DEVICE_OSCSRC_FREQ!!
// Please check the XTAL frequency used.
//
// By default, the Device_init function assumes 25MHz XTAL.
// If a 20MHz crystal is used, please add a predefined symbol
// "USE_20MHZ_XTAL" in your CCS project.
// If a different XTAL is used, please update the DEVICE_SETCLOCK_CFG
// macro accordingly.
//
// Note that the latest F2838x controlCARDs (Rev.B and later) have been
// updated to use 25MHz XTAL by default. If you have an older 20MHz XTAL
// controlCARD (E1, E2, or Rev.A), refer to the controlCARD
// documentation on steps to reconfigure the controlCARD from 20MHz to
// 25MHz.
//
ESTOP0;
while(1);
}
}
%if (!Common.isContextCPU2()){
`Clock_tree_template()`
%}
#endif
Device_initGPIO();
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_GPIO_20_21_Lock_VREGCTL_EnablePeripherals.xdt
+69
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
// The function also configures the GPIO pins 20 and 21 in digital mode.
// To configure these pins as analog pins, use the function GPIO_setAnalogMode
//
// Note : In case XTAL is used as the PLL source, it is recommended to invoke
// the Device_verifyXTAL() before configuring PLL
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
`Clock_tree_template()`
//
// Turn on all peripherals
//
Device_enableAllPeripherals();
//
// Lock VREGCTL Register
// The register VREGCTL is not supported in this device. It is locked to
// prevent any writes to this register
//
ASysCtl_lockVREG();
//
// Configure GPIO20 and GPIO21 as digital pins
//
GPIO_setAnalogMode(20U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(21U, GPIO_ANALOG_DISABLED);
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_GPIO_20_21_Lock_VREGCTL_Type0.xdt
+68
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
// The function also configures the GPIO pins 20 and 21 in digital mode.
// To configure these pins as analog pins, use the function GPIO_setAnalogMode
//
// Note : In case XTAL is used as the PLL source, it is recommended to invoke
// the Device_verifyXTAL() before configuring PLL
//
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
`Clock_tree_template()`
//
// Lock VREGCTL Register
// The register VREGCTL is not supported in this device. It is locked to
// prevent any writes to this register
//
ASysCtl_lockVREG();
//
// Configure GPIO20 and GPIO21 as digital pins
//
GPIO_setAnalogMode(20U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(21U, GPIO_ANALOG_DISABLED);
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_GPIO_20_21_Lock_VREGCTL_Type1.xdt
+70
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
// The function also configures the GPIO pins 20 and 21 in digital mode.
// To configure these pins as analog pins, use the function GPIO_setAnalogMode
//
// Note : In case XTAL is used as the PLL source, it is recommended to invoke
// the Device_verifyXTAL() before configuring PLL
//
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
%if (!Common.isContextCPU2()){
`Clock_tree_template()`
%}
//
// Lock VREGCTL Register
// The register VREGCTL is not supported in this device. It is locked to
// prevent any writes to this register
//
ASysCtl_lockVREG();
//
// Configure GPIO20 and GPIO21 as digital pins
//
GPIO_setAnalogMode(20U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(21U, GPIO_ANALOG_DISABLED);
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_GPIO_22_23_Disable_DCDC.xdt
+76
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
// The function also configures the GPIO pins 22 and 23 in digital mode.
// To configure these pins as analog pins, use the function GPIO_setAnalogMode
//
// Note : In case XTAL is used as the PLL source, it is recommended to invoke
// the Device_verifyXTAL() before configuring PLL
//
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
%if (!Common.isContextCPU2()){
`Clock_tree_template()`
%}
//
//Disable DC DC in Analog block
//
ASysCtl_disableDCDC();
//
//Configure GPIO in Push Pull,Output Mode
//
GPIO_setPadConfig(22U, GPIO_PIN_TYPE_STD);
GPIO_setPadConfig(23U, GPIO_PIN_TYPE_STD);
GPIO_setDirectionMode(22U, GPIO_DIR_MODE_OUT);
GPIO_setDirectionMode(23U, GPIO_DIR_MODE_OUT);
//
// Configure GPIO22 and GPIO23 as digital pins
//
GPIO_setAnalogMode(22U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(23U, GPIO_ANALOG_DISABLED);
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_General.xdt
+51
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
%if (!Common.isContextCPU2()){
`Clock_tree_template()`
%}
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_General_Dual_Core.xdt
+55
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
#ifdef CPU1
%if (!Common.isContextCPU2()){
`Clock_tree_template()`
%}
#endif
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_Lock_VREGCTL_Dual_Core_Type0.xdt
+63
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
// To configure these pins as analog pins, use the function GPIO_setAnalogMode
//
// Note : In case XTAL is used as the PLL source, it is recommended to invoke
// the Device_verifyXTAL() before configuring PLL
//
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
%if (!Common.isContextCPU2()){
`Clock_tree_template()`
%}
//
// Lock VREGCTL Register
// The register VREGCTL is not supported in this device. It is locked to
// prevent any writes to this register
//
ASysCtl_lockVREG();
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_Lock_VREGCTL_EnablePeripherals.xdt
+117
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
// The function also configures the GPIO pins 11, 12, 13, 16, 17, 20, 21, 24,
// and 28 in digital mode. To configure these pins as analog pins, use the
// function GPIO_setAnalogMode().
//
// Note : In case XTAL is used as the PLL source, it is recommended to invoke
// the Device_verifyXTAL() before configuring PLL
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
`Clock_tree_template()`
//
// Turn on all peripherals
//
Device_enableAllPeripherals();
//
// Update the offset trim for PGA2
//
if(HWREG(DEVCFG_BASE + SYSCTL_O_REVID) == 1U)
{
PGA_setOffsetTrimNMOS(PGA2_BASE);
PGA_setOffsetTrimPMOS(PGA2_BASE);
//
//Set bits in ADCCONFIG2 and make ADC OFFTRIM even for all ADCs
//
EALLOW;
HWREG(ADCA_BASE + 0x66U)|=0x00000C00U;
HWREG(ADCB_BASE + 0x66U)|=0x00000C00U;
HWREG(ADCC_BASE + 0x66U)|=0x00000C00U;
HWREG(ADCD_BASE + 0x66U)|=0x00000C00U;
HWREG(ADCE_BASE + 0x66U)|=0x00000C00U;
if(HWREGH(ADCA_BASE + ADC_O_OFFTRIM) % 2U)
{
HWREGH(ADCA_BASE + ADC_O_OFFTRIM) += 1U;
}
if (HWREGH(ADCB_BASE + ADC_O_OFFTRIM) % 2U)
{
HWREGH(ADCB_BASE + ADC_O_OFFTRIM) += 1U;
}
if (HWREGH(ADCC_BASE + ADC_O_OFFTRIM) % 2U)
{
HWREGH(ADCC_BASE + ADC_O_OFFTRIM) += 1U;
}
if (HWREGH(ADCD_BASE + ADC_O_OFFTRIM) % 2U)
{
HWREGH(ADCD_BASE + ADC_O_OFFTRIM) += 1U;
}
if (HWREGH(ADCE_BASE + ADC_O_OFFTRIM) % 2U)
{
HWREGH(ADCE_BASE + ADC_O_OFFTRIM) += 1U;
}
EDIS;
}
//
// Lock VREGCTL Register
// The register VREGCTL is not supported in this device. It is locked to
// prevent any writes to this register
//
ASysCtl_lockVREG();
//
// Configure GPIO 11, 12, 13, 16, 17, 20, 21, 24, and 28 as digital pins
//
GPIO_setAnalogMode(11U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(12U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(13U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(16U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(17U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(20U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(21U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(24U, GPIO_ANALOG_DISABLED);
GPIO_setAnalogMode(28U, GPIO_ANALOG_DISABLED);
}
C2000Ware/driverlib/.meta/device/functions_c/Initilization/Initilization_XTAL.xdt
+62
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%let Common = system.getScript("/driverlib/Common.js");
% var Clock_tree_template = system.getTemplate("/driverlib/device/functions_c/Clocktree/Device_clocktree_c.xdt");
% var nameOfFlashModule = "flash";
% var flashModule = system.modules['/driverlib/' + nameOfFlashModule + '.js'];
//*****************************************************************************
//
// Function to initialize the device. Primarily initializes system control to a
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
// and enabling the clocks to the peripherals.
//
// Note : In case XTAL is used as the PLL source, it is recommended to invoke
// the Device_verifyXTAL() before configuring PLL
//
//
//*****************************************************************************
void Device_init(void)
{
//
// Disable the watchdog
//
SysCtl_disableWatchdog();
#ifdef CMDTOOL
CMD_init();
#endif
#ifdef _FLASH
#ifndef CMDTOOL
//
// Copy time critical code and flash setup code to RAM. This includes the
// following functions: InitFlash();
//
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
// are created by the linker. Refer to the device .cmd file.
//
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
#endif
%if(!flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
%}
#endif
%if(flashModule){
//
// Call Flash Initialization to setup flash waitstates. This function must
// reside in RAM.
//
FLASH_init();
%}
%if (!Common.isContextCPU2()){
`Clock_tree_template()`
%}
//
// Lock VREGCTL Register
// The register VREGCTL is not supported in this device. It is locked to
// prevent any writes to this register
//
ASysCtl_lockVREG();
}
C2000Ware/driverlib/.meta/device/functions_c/VerifyXTAL/VerifyXTAL.xdt
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%%{
let device_common = system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let Common = system.getScript("/driverlib/Common.js");
var VerifyXTAL_General = system.getTemplate('./VerifyXTAL_General.xdt');
var VerifyXTAL_TurnON_XTAL = system.getTemplate('./VerifyXTAL_TurnON_XTAL.xdt');
const device = device_common.device;
const VerifyXTAL_Type0 = device_common.VerifyXTAL_Type0;
const VerifyXTAL_Type1 = device_common.VerifyXTAL_Type1;
%%}
% if(VerifyXTAL_Type0.includes(device)&& Common.isContextCPU1())
%{
`VerifyXTAL_General()`
%}
% if(VerifyXTAL_Type1.includes(device)&& Common.isContextCPU1())
%{
`VerifyXTAL_TurnON_XTAL()`
%}
%else{}
C2000Ware/driverlib/.meta/device/functions_c/VerifyXTAL/VerifyXTAL_General.xdt
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//*****************************************************************************
//
// Function to verify the XTAL frequency
// freq is the XTAL frequency in MHz
// The function return true if the the actual XTAL frequency matches with the
// input value
//
// Note that this function assumes that the PLL is not already configured and
// hence uses SysClk freq = 10MHz for DCC calculation
//
//*****************************************************************************
#ifdef CPU1
bool Device_verifyXTAL(float freq)
{
//
// Use DCC to verify the XTAL frequency using INTOSC2 as reference clock
//
//
// Enable DCC0 clock
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC0);
//
// Insert atleast 5 cycles delay after enabling the peripheral clock
//
asm(" RPT #5 || NOP");
//
// Configures XTAL as CLKSRC0 and INTOSC2 as CLKSRC1
// Fclk0 = XTAL frequency (input parameter)
// Fclk1 = INTOSC2 frequency = 10MHz
//
// Configuring DCC error tolerance of +/-1%
// INTOSC2 can have a variance in frequency of +/-10%
//
// Assuming PLL is not already configured, SysClk freq = 10MHz
//
// Note : Update the tolerance and INTOSC2 frequency variance as necessary.
//
return (DCC_verifyClockFrequency(DCC0_BASE,
DCC_COUNT1SRC_INTOSC2, 10.0F,
DCC_COUNT0SRC_XTAL, freq,
1.0F, 10.0F, 10.0F));
}
#endif
C2000Ware/driverlib/.meta/device/functions_c/VerifyXTAL/VerifyXTAL_TurnON_XTAL.xdt
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//*****************************************************************************
//
// Function to verify the XTAL frequency
// freq is the XTAL frequency in MHz
// The function return true if the the actual XTAL frequency matches with the
// input value
//
// Note that this function assumes that the PLL is not already configured and
// hence uses SysClk freq = 10MHz for DCC calculation
//
//*****************************************************************************
bool Device_verifyXTAL(float freq)
{
//
// Use DCC to verify the XTAL frequency using INTOSC2 as reference clock
//
//
// Turn on XTAL and wait for it to power up using X1CNT
//
SysCtl_turnOnOsc(SYSCTL_OSCSRC_XTAL);
SysCtl_clearExternalOscCounterValue();
while(SysCtl_getExternalOscCounterValue() != SYSCTL_X1CNT_X1CNT_M);
//
// Enable DCC0 clock
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC0);
//
// Insert atleast 5 cycles delay after enabling the peripheral clock
//
asm(" RPT #5 || NOP");
//
// Configures XTAL as CLKSRC0 and INTOSC2 as CLKSRC1
// Fclk0 = XTAL frequency (input parameter)
// Fclk1 = INTOSC2 frequency = 10MHz
//
// Configuring DCC error tolerance of +/-1%
// INTOSC2 can have a variance in frequency of +/-10%
//
// Assuming PLL is not already configured, SysClk freq = 10MHz
//
// Note : Update the tolerance and INTOSC2 frequency variance as necessary.
//
return (DCC_verifyClockFrequency(DCC0_BASE,
DCC_COUNT1SRC_INTOSC2, 10.0F,
DCC_COUNT0SRC_XTAL, freq,
1.0F, 10.0F, 10.0F));
}
C2000Ware/driverlib/.meta/device/functions_c/device_common.js
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const device = system.deviceData.device
/////////////////////////////////////////////Device Specific Functions//////////////////////////
// For a new device, you need to find out which functions are available for the device
// and add it to the list.
// If a new subcategory is needed, just define a new variable and address that in the related function.xdt file.
// For example, if you need a new Include Header type, you can add Include_Headers_Typex to the list and then go to Include folder and add that
//variable to the Include.xdt. Also, you need to copy and past your content to a new file, let's call Include_Headers_xxx.xdt.
// Multi-core devices list
const multi_core = ["F2837xD", "F2838x", "F28P65x"]
//
// Available Include Header
//
// General Include Header
const Include_Headers_Type0 = ["F2838x"]
// Include Header with hw_ipc.h
const Include_Headers_Type1 = ["F2837xD"]
// Include Header with hw_lcm.h
const Include_Headers_Type2 = ["F280015x"]
// Include Header with driverlib.h
const Include_Headers_Type3 = ["F280013x", "F28002x", "F28003x", "F28004x", "F2837xS", "F2807x", "F28P65x", "F28P55x"]
//
// Available Boot_CM
//
// Devices with Boot_CM
const Device_Boot_CM = ["F2838x"]
//
// Available Initilization
//
//Function to initialize the device (suprano dual-core devices, Type0)
const Initilization_General_Type0 = ["F2837xD"]
// Function to initialize the device (suprano single-core device, Type1)
const Initilization_General_Type1 = ["F2807x", "F2837xS"]
//configuring the XTAL for device initilization
const Initilization_XTAL_Type0 = ["F28002x"]
//configuring device initilization with Device_initGPIO()
const Initilization_Device_initGPIO_Type0 = ["F2838x"]
//configuring the AGPIO pins 12, 13, 20, 21, 28 in digital mode for device initilization
const Initilization_AGPIO_Type0 = ["F280013x"]
//configuring the AGPIO pins 12, 13, 20, 21, 28 in digital mode and enabling lockstep module for device initilization
const Initilization_AGPIO_Type1 = ["F280015x"]
//configuring the GPIO pins 22, 23 in digital mode and Disabling DC DC in Analog block for device initilization
const Initilization_GPIO_22_23 = ["F28004x"]
//configuring the GPIO pins 20, 21 in digital mode and Lock VREGCTL Register for device initilization
const Initilization_GPIO_20_21_Type0 = ["F28003x"]
//configuring the Lock VREGCTL Register for device initilization
const Initilization_AGPIO_Dual_Core_Type0 = ["F28P65x"]
//configuring the GPIO pins 11, 12, 13, 16, 17, 20, 21, 24,
// and 28 in digital mode, turn on all peripherals, and Lock VREGCTL Register for device initilization
const Initilization_GPIO_11_28 = ["F28P55x"]
//
// Available InitGPIO
//
// Disabling pin locks and enabling pullups on GPIOs Port A-Port F.
const InitGPIO_PortA_PortF_Type0 = ["F2838x", "F2837xD", "F2837xS", "F2807x"]
// Disabling pin locks and enabling pullups on GPIOs only Ports A, B, and H.
const InitGPIO_PortA_PortH_Type0 = ["F28002x", "F28003x", "F28004x", "F280013x", "F280015x"]
// Disabling pin locks and enabling pullups on GPIOs Ports A, B, C, D, E, F, and H.
const InitGPIO_PortA_PortH_Type1 = ["F28P65x"]
// Disabling pin locks and enabling pullups on GPIOs only Ports A, B, C, G, and H.
const InitGPIO_PortA_PortH_Type2 = ["F28P55x"]
//
// Available VerifyXTAL
//
// verifying the XTAL frequency
const VerifyXTAL_Type0 = ["F2838x"]
// verifying the XTAL frequency with Turning-on XTAL
const VerifyXTAL_Type1 = ["F28002x", "F28003x", "F28004x", "F28P65x", "F28P55x"]
//
// Available BootCPU2
//
// Boot CPU2 to Flash Sector 0 to Sector 13
const Boot_CPU2_Type0 =["F2838x"]
// Boot CPU2 to Flash Bank 0 to Bank 4
const Boot_CPU2_Type1 =["F28P65x"]
// Boot CPU2 with different boot mode. It can be from PARALLEL, SCI, SPI, I2C, CAN, RAM, and FLASH.
const Boot_CPU2_Boot_Mode_Type0 =["F2837xD"]
//
// Available Enable_Unbounded_GPIO_Pullups
//
// enable pullups for the unbonded GPIOs on the 100PZ or 176PTP package.
const Enable_Unbounded_GPIO_Pullups_100PZ_176PTP_Type0 =["F2837xD", "F2837xS", "F2807x"]
// enable pullups for the unbonded GPIOs on the 176PTP package.
const Enable_Unbounded_GPIO_Pullups_176PTP_Type0 =["F2838x"]
//
// Available Configure_TMX_Analog_Trim
//
// Implementing Analog trim of TMX devices with ADC A, ADC B, and ADC D
const Configure_TMX_Analog_Trim_Type0 =["F2807x"]
// Implementing Analog trim of TMX devices with ADC A, ADC B, ADC C, and ADC D
const Configure_TMX_Analog_Trim_Type1 =["F2837xS"]
// Implementing Analog trim of TMX devices with ADC A, ADC B, ADC C, and ADC D starting with If condition
const Configure_TMX_Analog_Trim_Type2 =["F2837xD"]
//
// Available EnableAllPeripherals
//
// Enabling HRCAL for F2838x with checking if context is on CPU1. If enabling HRCAL in your device needs
//to be done only in CPU1, add your device to this list.
const EnableAllPeripherals_CLK_HRCAL = ["F2838x"]
// Enabling HRPWM for F2837xD with checking if context is on CPU1. If enabling HRPWM in your device needs
//to be done only in CPU1, add your device to this list.
const EnableAllPeripherals_CLK_HRPWM = ["F2837xD"]
// Enabling EMIF with checking if context is on CPU1. If enabling EMIF in your device needs
//to be done only in CPU1, add your device to this list.
const EnableAllPeripherals_CLK_EMIF_With_If = ["F2837xD", "F2838x", "F28P65x"]
// Checking devices need enabling peripheral EMIF1. If peripheral EMIF1 needs to be enabled
//in your device, add your device to this list.
const EnableAllPeripherals_CLK_EMIF1 = [ "F2837xS", "F2807x" ]
// Checking devices need enabling peripheral EMIF2. If peripheral EMIF2 needs to be enabled
//in your device, add your device to this list.
const EnableAllPeripherals_CLK_EMIF2 = ["F2837xS"]
// Enabling USB and UPPA with checking if context is on CPU1. If enabling USB or UPPA in your device needs
//to be done only in CPU1, add your device to this list.
const EnableAllPeripherals_CLK_USB_UPPA = ["F2838x", "F2837xD"]
// Checking devices with SysCtl_enablePeripheral for peripheral USBA. If peripheral USBA needs to be enabled
//in your device, add your device to this list.
const EnableAllPeripherals_CLK_USBA = ["F2837xS", "F2807x", "F28P65x", "F28P55x"]
// Checking devices with SysCtl_enablePeripheral for peripheral UPPA. If peripheral UPPA needs to be enabled
//in your device, add your device to this list.
const EnableAllPeripherals_CLK_UPPA = ["F2837xS"]
// Enabling DCC and ECAT, and MCAN with checking if context is on CPU1. If enabling DCC and ECAT, and MCAN
//in your device needs to be done only in CPU1, add your device to this list.
const EnableAllPeripherals_CLK_DCC_ECAT_MCAN = ["F2838x"]
// Enabling CLA1BGCRC with checking if context is on CPU1. If enabling CLA1BGCRC
//in your device needs to be done only in CPU1, add your device to this list.
const EnableAllPeripherals_CLK_CLA1BGCRC = ["F2838x", "F28003x"]
// Enabling PMBUSA with checking if context is on CPU1. If enabling PMBUSA
//in your device needs to be done only in CPU1, add your device to this list.
const EnableAllPeripherals_CLK_PMBUSA = [ "F2838x", "F280015x", "F28002x", "F28003x", "F28004x", "F28P55x"]
// Enabling CLA1 with checking if context is on CPU1. If enabling CLA1
//in your device needs to be done only in CPU1, add your device to this list.
const EnableAllPeripherals_CLK_CLA1 = ["F2838x", "F2837xD", "F2837xS", "F2807x", "F28003x", "F28004x", "F28P55x"]
//
// Clocktree
//
// clocktree Configuring Analog Trim in case of untrimmed or TMX sample
const clocktree_Analog_Trim_Type0 =["F2837xD", "F2807x", "F2837xS"]
// clocktree Setting up PLL control and clock dividers
const clocktree_PLL_Ctl_Dividers_Type0 =["F2837xD", "F2807x", "F2837xS","F280013x", "F280015x", "F28002x", "F28003x", "F28004x", "F28P55x"]
// clocktree Setting up PLL and AUXPLL control and clock dividers
//and AUXPLL control and clock dividers needed for CMCLK
const clocktree_PLL_Ctl_Dividers_Type1 =["F2838x"]
// clocktree Setting up PLL control and clock dividers
//and AUXPLL control and clock dividers needed for CMCLK
const clocktree_PLL_Ctl_Dividers_Type2 =["F28P65x"]
// clocktree asserts will check that the #defines for the clock rates in device.h
//set clock source for CANA, CANB, MCAN peripherals and EPWM and EMIF1 clock divider
const clocktree_Asserts_Type0 =["F2837xD", "F2807x", "F2837xS"]
// clocktree asserts will check that the #defines for the clock rates in device.h
//set clock source for CANA, CANB, MCAN, ECAT, ENET peripherals and EPWM and EMIF1 clock divider
const clocktree_Asserts_Type1 =["F2838x"]
// clocktree asserts will check that the #defines for the clock rates in device.h
//set clock source for CANA, MCANA, MCANB, ECAT peripherals and EPWM and EMIF1 clock divider
const clocktree_Asserts_Type2 =["F28P65x"]
// clocktree asserts will check that the #defines for the clock rates in device.h
//set clock source for CANA and MCAN peripherals
const clocktree_Asserts_Type3 =["F28003x","F280015x"]
// clocktree asserts will check that the #defines for the clock rates in device.h
//set clock source for CANA peripheral
const clocktree_Asserts_Type4 =["F280013x", "F28002x", "F28004x"]
// clocktree asserts will check that the #defines for the clock rates in device.h
const clocktree_Asserts_Type5 =["F28P55x"]
///////////////////////////List of Template Files For Different Functions///////////////////////////
// If you want to add a new sub-function from available functions, you need to create a .xdt file in related function folder
// and add it here.
// Template for General Header
var Include = system.getTemplate('Include/Include.xdt');
// Template for Boot_CM
var Boot_CM = system.getTemplate('BootCM/Boot_CM.xdt');
// Template for device initilization
var Initilization = system.getTemplate('Initilization/Initilization.xdt');
// Template for disabling pin locks and enabling pullups on GPIOs Port A-Port F.
var InitGPIO = system.getTemplate('InitGPIO/InitGPIO.xdt');
// Template for verifying the XTAL frequency
var VerifyXTAL = system.getTemplate('VerifyXTAL/VerifyXTAL.xdt');
// Template for Error handling function
var Error_Handling = system.getTemplate('ErrorChecking/Error_Handling.xdt');
// Template for boot CPU2
var Boot_CPU2 = system.getTemplate('BootCPU2/Boot_CPU2.xdt');
// Template for enable unbounded GPIO pullups
var Enable_Unbounded_GPIO_Pullups = system.getTemplate('EnableUnboundedGPIOPullups/Enable_Unbounded_GPIO_Pullups.xdt');
// Template for implementing Analog trim of TMX devices
var Configure_TMX_Analog_Trim = system.getTemplate('ConfigureTMXAnalogTrim/Configure_TMX_Analog_Trim.xdt');
// Template for enabling all the peripherals
var Enable_All_Peripherals = system.getTemplate('EnableAllPeripherals/Enable_All_Peripherals.xdt');
exports = {
Include : Include ,
Boot_CM : Boot_CM,
Initilization : Initilization,
InitGPIO : InitGPIO,
VerifyXTAL : VerifyXTAL,
Error_Handling : Error_Handling,
Boot_CPU2 : Boot_CPU2,
Enable_Unbounded_GPIO_Pullups : Enable_Unbounded_GPIO_Pullups,
Configure_TMX_Analog_Trim : Configure_TMX_Analog_Trim,
Enable_All_Peripherals : Enable_All_Peripherals,
device : device,
multi_core : multi_core,
Include_Headers_Type0 : Include_Headers_Type0,
Include_Headers_Type1 : Include_Headers_Type1,
Include_Headers_Type2 : Include_Headers_Type2,
Include_Headers_Type3 : Include_Headers_Type3,
Device_Boot_CM : Device_Boot_CM ,
Initilization_General_Type0 : Initilization_General_Type0,
Initilization_General_Type1 : Initilization_General_Type1,
Initilization_AGPIO_Type0 : Initilization_AGPIO_Type0 ,
Initilization_AGPIO_Type1 : Initilization_AGPIO_Type1 ,
Initilization_GPIO_22_23 : Initilization_GPIO_22_23,
Initilization_GPIO_20_21_Type0 : Initilization_GPIO_20_21_Type0,
Initilization_AGPIO_Dual_Core_Type0 : Initilization_AGPIO_Dual_Core_Type0,
Initilization_GPIO_11_28 : Initilization_GPIO_11_28,
Initilization_XTAL_Type0 : Initilization_XTAL_Type0,
Initilization_Device_initGPIO_Type0 : Initilization_Device_initGPIO_Type0,
InitGPIO_PortA_PortF_Type0 : InitGPIO_PortA_PortF_Type0,
InitGPIO_PortA_PortH_Type0 : InitGPIO_PortA_PortH_Type0,
InitGPIO_PortA_PortH_Type1 : InitGPIO_PortA_PortH_Type1,
InitGPIO_PortA_PortH_Type2 : InitGPIO_PortA_PortH_Type2,
VerifyXTAL_Type0 : VerifyXTAL_Type0,
VerifyXTAL_Type1 : VerifyXTAL_Type1,
Boot_CPU2_Type0 : Boot_CPU2_Type0,
Boot_CPU2_Type1 : Boot_CPU2_Type1,
Boot_CPU2_Boot_Mode_Type0 : Boot_CPU2_Boot_Mode_Type0,
Enable_Unbounded_GPIO_Pullups_100PZ_176PTP_Type0 : Enable_Unbounded_GPIO_Pullups_100PZ_176PTP_Type0,
Enable_Unbounded_GPIO_Pullups_176PTP_Type0 : Enable_Unbounded_GPIO_Pullups_176PTP_Type0,
Configure_TMX_Analog_Trim_Type0 : Configure_TMX_Analog_Trim_Type0,
Configure_TMX_Analog_Trim_Type1 : Configure_TMX_Analog_Trim_Type1,
Configure_TMX_Analog_Trim_Type2 : Configure_TMX_Analog_Trim_Type2,
EnableAllPeripherals_CLK_HRCAL : EnableAllPeripherals_CLK_HRCAL,
EnableAllPeripherals_CLK_HRPWM : EnableAllPeripherals_CLK_HRPWM,
EnableAllPeripherals_CLK_EMIF_With_If : EnableAllPeripherals_CLK_EMIF_With_If,
EnableAllPeripherals_CLK_EMIF1 : EnableAllPeripherals_CLK_EMIF1,
EnableAllPeripherals_CLK_EMIF2: EnableAllPeripherals_CLK_EMIF2,
EnableAllPeripherals_CLK_USB_UPPA : EnableAllPeripherals_CLK_USB_UPPA,
EnableAllPeripherals_CLK_USBA : EnableAllPeripherals_CLK_USBA,
EnableAllPeripherals_CLK_UPPA : EnableAllPeripherals_CLK_UPPA,
EnableAllPeripherals_CLK_DCC_ECAT_MCAN : EnableAllPeripherals_CLK_DCC_ECAT_MCAN,
EnableAllPeripherals_CLK_CLA1BGCRC : EnableAllPeripherals_CLK_CLA1BGCRC,
EnableAllPeripherals_CLK_PMBUSA : EnableAllPeripherals_CLK_PMBUSA,
EnableAllPeripherals_CLK_CLA1 : EnableAllPeripherals_CLK_CLA1,
clocktree_Analog_Trim_Type0 : clocktree_Analog_Trim_Type0,
clocktree_PLL_Ctl_Dividers_Type0 : clocktree_PLL_Ctl_Dividers_Type0,
clocktree_PLL_Ctl_Dividers_Type1 : clocktree_PLL_Ctl_Dividers_Type1,
clocktree_PLL_Ctl_Dividers_Type2 : clocktree_PLL_Ctl_Dividers_Type2,
clocktree_Asserts_Type0 : clocktree_Asserts_Type0,
clocktree_Asserts_Type1 : clocktree_Asserts_Type1,
clocktree_Asserts_Type2 : clocktree_Asserts_Type2,
clocktree_Asserts_Type3 : clocktree_Asserts_Type3,
clocktree_Asserts_Type4 : clocktree_Asserts_Type4,
clocktree_Asserts_Type5 : clocktree_Asserts_Type5
}