Update repo
This commit is contained in:
@@ -0,0 +1,594 @@
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let Common = system.getScript("/driverlib/Common.js");
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let Pinmux = system.getScript("/driverlib/pinmux.js");
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let AccProt = system.getScript("/driverlib/mecfgAccProt.js");
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let device_driverlib_peripheral =
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system.getScript("/driverlib/device_driverlib_peripherals/" +
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Common.getDeviceName().toLowerCase() + "_memcfg.js");
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let device_driverlib_memmap =
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system.getScript("/driverlib/device_driverlib_peripherals/" +
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Common.getDeviceName().toLowerCase() + "_memmap.js");
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let device_driverlib_sysctl_registers =
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system.getScript("/driverlib/device_driverlib_peripherals/" +
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Common.getDeviceName().toLowerCase() + "_sysctl_registers.js");
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let device_driverlib_sysctl =
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system.getScript("/driverlib/device_driverlib_peripherals/" +
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Common.getDeviceName().toLowerCase() + "_sysctl.js");
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/* Intro splash on GUI */
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let longDescription = ``;
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longDescription += "* [Device TRM](" + Common.getDeviceTRM() + ") \n - For GSRAM blocks configured to be owned by CPU2: the code for Initialization, Access Protection, and Lock Configs will be generated on CPU2";
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/* Array of MEMCFG configurables that are common across device families */
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let staticConfig = []
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let LSRAMOwnerConfig = []
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let GSRAMOwnerConfig = []
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let DRAMOwnerConfig = []
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let FLASHOwnerConfig = []
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let AccessConfig = []
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let InitRAM = []
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let LockConfig = []
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let ViolIntConfig = []
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let CorrErrIntConfig = []
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let ROMConfig = []
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/* Section : LSRAM Configuration */
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if(device_driverlib_peripheral.MemCfg_LSRAMControllerSel)
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{
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device_driverlib_peripheral.MEMCFG_SECT.
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forEach((element, index) =>
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{
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if ((element.name.includes("MEMCFG_SECT_LS")) && (element.name != "MEMCFG_SECT_LSX_ALL"))
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{
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if (Common.isContextCPU1() || !["F28P65x"].includes(system.deviceData.deviceId)){
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var lsOptions = []
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lsOptions.push({name: "CPU_memory", displayName: "CPU dedicated memory"})
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if (!["F28P65x"].includes(system.deviceData.deviceId) || !(element.name.includes("LS8") || element.name.includes("LS9"))){
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lsOptions.push({name: "CLA_data", displayName: "CPU/CLA shared data memory"})
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}
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lsOptions.push({name: "CLA_prog", displayName: "CLA program memory"})
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LSRAMOwnerConfig.push(
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{
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name: "config_" + element.name,
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displayName : element.displayName,
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options : lsOptions,
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default : "CPU_memory"
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}
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)
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}
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}
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}
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);
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}
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/* Section : GSRAM Configuration */
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if (Common.isContextCPU1())
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{
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if(device_driverlib_peripheral.MemCfg_GSRAMControllerSel)
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{
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device_driverlib_peripheral.MEMCFG_SECT.
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forEach((element, index) =>
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{
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if ((element.name.includes("MEMCFG_SECT_GS")) && (element.name != "MEMCFG_SECT_GSX_ALL"))
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{
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GSRAMOwnerConfig.push(
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{
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name : "config_" + element.name,
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displayName: element.displayName,
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options : device_driverlib_peripheral.MemCfg_GSRAMControllerSel,
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default : device_driverlib_peripheral.MemCfg_GSRAMControllerSel[0].name
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}
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)
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}
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}
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);
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}
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}
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if (device_driverlib_sysctl.SysCtl_CPUSel){
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var SysctlOptions = [];
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device_driverlib_peripheral.MemCfg_GSRAMControllerSel.
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forEach((element, index) =>
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{
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let thisName = device_driverlib_sysctl.SysCtl_CPUSel[index].name;
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let thisDisplayName = device_driverlib_peripheral.MemCfg_GSRAMControllerSel[index].displayName;
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SysctlOptions.push({ name: thisName, displayName: thisDisplayName})
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});
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}
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/* Section : DRAM Configuration */
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if (Common.isContextCPU1() && ["F28P65x"].includes(system.deviceData.deviceId))
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{
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device_driverlib_sysctl.SysCtl_SharedDxRAM.
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forEach((element, index) =>
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{
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DRAMOwnerConfig.push(
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{
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name : "config_" + element.name,
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displayName: element.displayName,
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options : SysctlOptions,
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default : SysctlOptions[0].name
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}
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)
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}
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);
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}
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/* Section : FLASH Configuration */
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if (Common.isContextCPU1() && ["F28P65x"].includes(system.deviceData.deviceId))
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{
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device_driverlib_sysctl.SysCtl_FlashBank.
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forEach((element, index) =>
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{
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FLASHOwnerConfig.push(
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{
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name : "config_" + element.name,
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displayName: element.name,
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options : SysctlOptions,
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default : SysctlOptions[0].name
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}
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)
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}
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);
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}
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/* Section : ROM config */
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if(["F2838x", "F2837xD", "F2837xS", "F2807x","F28P65x"].includes(system.deviceData.deviceId))
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{
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ROMConfig = [
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{
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name : "rom_waitstate",
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displayName: "Enable ROM wait state",
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description: "If enabled, CPU accesses to ROM are 1-wait",
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default : true
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}]
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if(!["F28P65x"].includes(system.deviceData.deviceId)){
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ROMConfig.push(
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{
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name : "rom_prefetch",
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displayName: "Enable ROM prefetch",
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description: "Enable prefetch for secure ROM and boot ROM",
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default : false
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})
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}
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var yesROM = 1;
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}
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/* Section : Access Protection */
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AccProt.AcessProtectionRAMs[system.deviceData.deviceId.toLowerCase()].
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forEach((element, index) =>
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{
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var ramMacro = "MEMCFG_SECT_" + element.name
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if (ramMacro[12]!="G" && ((Common.isContextCPU1() || (ramMacro[12]!="D" && ramMacro[12]!="L")) || !["F28P65x"].includes(system.deviceData.deviceId))) // Global ram has own if statement so description is only on GSRAM
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{
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if(device_driverlib_peripheral.MEMCFG_SECT.map(a=>a.name).includes(ramMacro) && (Common.isContextCPU1() || !ramMacro.includes("TOCM")))
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{
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var AvailableOptions = []
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if(element.access.includes("FETCHPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWCPUFETCH", displayName: "CPU fetch allowed"})
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if(element.access.includes("CPUWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWCPUWRITE", displayName: "CPU write allowed"})
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if(element.access.includes("DMAWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWDMAWRITE", displayName: "DMA write allowed"})
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if(element.access.includes("HICWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWHICWRITE", displayName: "HIC write allowed"})
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if (ramMacro.includes("MSGCPUTOCPU")){
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let ramNumber = ramMacro[23]; // get number from end of ram macro
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AccessConfig.push(
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{
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name : "access_" + ramMacro,
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displayName : "CPU-to-CPU message RAM"+ ramNumber.toString() + " Access",
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minSelections: 0,
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options : AvailableOptions,
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default : AvailableOptions.map(a=>a.name)
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})
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}
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if (ramMacro.includes("MSGCPUTOCM")){ // get number from end of ram macro
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let ramNumber = ramMacro[22];
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AccessConfig.push(
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{
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name : "access_" + ramMacro,
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displayName : "CPU-to-CM message RAM"+ ramNumber.toString() + " Access",
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minSelections: 0,
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options : AvailableOptions,
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default : AvailableOptions.map(a=>a.name)
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})
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}
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if ((!ramMacro.includes("MSGCPUTOCPU")) && (!ramMacro.includes("MSGCPUTOCM"))){
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AccessConfig.push(
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{
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name : "access_" + ramMacro,
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displayName : element.name + " RAM Access",
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minSelections: 0,
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options : AvailableOptions,
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default : AvailableOptions.map(a=>a.name)
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})
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}
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}
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}
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if (ramMacro[12]=="G" && (Common.isContextCPU1()))
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{
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if(device_driverlib_peripheral.MEMCFG_SECT.map(a=>a.name).includes(ramMacro))
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{
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var AvailableOptions = []
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if(element.access.includes("FETCHPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWCPUFETCH", displayName: "CPU fetch allowed"})
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if(element.access.includes("CPUWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWCPUWRITE", displayName: "CPU write allowed"})
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if(element.access.includes("DMAWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWDMAWRITE", displayName: "DMA write allowed"})
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if(element.access.includes("HICWRPROT"))
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AvailableOptions.push({name : "MEMCFG_PROT_ALLOWHICWRITE", displayName: "HIC write allowed"})
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AccessConfig.push(
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{
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name : "access_" + ramMacro,
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displayName : element.name + " RAM Access",
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description: "For GSRAM owned by CPU2: this code will be generated on CPU2",
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minSelections: 0,
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options : AvailableOptions,
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default : AvailableOptions.map(a=>a.name)
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})
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}
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}
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}
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);
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/* Section : RAM Initialization */
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device_driverlib_peripheral.MEMCFG_SECT.
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forEach((element, index) =>
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{
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if (!element.name.includes("_ALL"))
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{
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if (Common.isContextCPU1())
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{
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if (element.name.includes("MEMCFG_SECT_GS"))
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InitRAM.push(
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{
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name : "init_" + element.name,
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displayName: element.displayName,
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default : false
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}
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)
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}
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// only GS/LS/D/M/MSG RAMs. check for MEMCFG_SECT_M covers MSGRAM as well
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if ((((element.name.includes("MEMCFG_SECT_D") || element.name.includes("MEMCFG_SECT_LS")) && (Common.isContextCPU1() || !["F28P65x"].includes(system.deviceData.deviceId))) ||
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element.name.includes("MEMCFG_SECT_M")) && (Common.isContextCPU1() || !element.name.includes("CM")))
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{
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InitRAM.push(
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{
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name : "init_" + element.name,
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displayName: element.displayName,
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default : false
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}
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)
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}
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}
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}
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);
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/* Section : Lock Registers */
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device_driverlib_peripheral.MEMCFG_SECT.
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forEach((element, index) =>
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{
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if (!element.name.includes("_ALL"))
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{
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if((element.name.includes("MEMCFG_SECT_M") ||
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((element.name.includes("MEMCFG_SECT_LS") || element.name.includes("MEMCFG_SECT_D")) &&
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(!["F28P65x"].includes(system.deviceData.deviceId) || Common.isContextCPU1()))) &&
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(Common.isContextCPU1() || !element.name.includes("CM")))
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{
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LockConfig.push(
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{
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name : "lock_" + element.name,
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displayName : "Lock " + element.displayName + " Config Registers",
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options : [
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{name: "NoLock", displayName: "Do not Lock"},
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{name: "Lock", displayName: "Lock"},
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{name: "LockCommit", displayName: "Lock and Commit"},
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],
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default: "NoLock"
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})
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}
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if (Common.isContextCPU1())
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{
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if(element.name.includes("MEMCFG_SECT_GS") && (Common.isContextCPU1() || !element.name.includes("CM")))
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{
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LockConfig.push(
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{
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name : "lock_" + element.name,
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displayName : "Lock " + element.displayName + " Config Registers",
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||||
description: "For GSRAM blocks configured to be owned by CPU2: the code for Initialization, Access Protection, and Lock Configs will be generated on CPU2",
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options : [
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{name: "NoLock", displayName: "Do not Lock"},
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{name: "Lock", displayName: "Lock"},
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{name: "LockCommit", displayName: "Lock and Commit"},
|
||||
],
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default: "NoLock"
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||||
})
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
);
|
||||
|
||||
|
||||
/* Section : Access Violation Interrupt */
|
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device_driverlib_peripheral.MEMCFG_MVIOL. // Controller access violation interrupts
|
||||
forEach((element, index) =>
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{
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ViolIntConfig.push(
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||||
{
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name : "int_" + element.name,
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||||
displayName: "Enable " + element.displayName + " violation interrupt",
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||||
default : false
|
||||
}
|
||||
)
|
||||
}
|
||||
);
|
||||
if(device_driverlib_peripheral.MEMCFG_NMVIOL) // Non-controller access violation interrupts
|
||||
{
|
||||
device_driverlib_peripheral.MEMCFG_NMVIOL.
|
||||
forEach((element, index) =>
|
||||
{
|
||||
ViolIntConfig.push(
|
||||
{
|
||||
name : "int_" + element.name,
|
||||
displayName: "Enable " + element.displayName + " violation interrupt",
|
||||
default : false
|
||||
}
|
||||
)
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/* Section : CorrErr Interrupt */
|
||||
CorrErrIntConfig = [
|
||||
{
|
||||
name : "errInt_enable",
|
||||
displayName: "Enable Correctable Error Interrupt",
|
||||
default : false
|
||||
},
|
||||
{
|
||||
name : "errInt_thres",
|
||||
displayName: "Threshold for Correctable Error Interrupt",
|
||||
default : 0
|
||||
},
|
||||
]
|
||||
|
||||
|
||||
staticConfig.push(
|
||||
{
|
||||
name : "InitRAM",
|
||||
displayName : "RAM Initialization",
|
||||
longDescription: "Initialize the memory block.\n - MULTICORE NOTE: Initialization code for GSRAMs owned by CPU2 will be generated for CPU2",
|
||||
config : InitRAM
|
||||
},
|
||||
{
|
||||
name : "LSRAM_Config",
|
||||
displayName : "LSRAM Configuration",
|
||||
longDescription: "",
|
||||
config : LSRAMOwnerConfig
|
||||
}
|
||||
)
|
||||
|
||||
if (Common.isContextCPU1())
|
||||
{
|
||||
staticConfig.push(
|
||||
{
|
||||
name : "GSRAM_Config",
|
||||
displayName : "GSRAM Configuration",
|
||||
longDescription: "\n - For GSRAM blocks owned by CPU2: the code for Access Protection and Lock Configs will be generated on CPU2",
|
||||
config : GSRAMOwnerConfig
|
||||
}
|
||||
)
|
||||
}
|
||||
|
||||
if (Common.isContextCPU1() && ["F28P65x"].includes(system.deviceData.deviceId))
|
||||
{
|
||||
staticConfig.push(
|
||||
{
|
||||
name : "DRAM_Config",
|
||||
displayName : "DRAM Configuration",
|
||||
longDescription: "\n - For DRAM blocks owned by CPU2: the code for Access Protection and Lock Configs will be generated on CPU2??????",
|
||||
config : DRAMOwnerConfig
|
||||
},
|
||||
{
|
||||
name : "FLASH_Config",
|
||||
displayName : "FLASH Configuration",
|
||||
longDescription: "\n - For FLASH banks owned by CPU2: the code for Access Protection and Lock Configs will be generated on CPU2??????",
|
||||
config : FLASHOwnerConfig
|
||||
}
|
||||
)
|
||||
}
|
||||
|
||||
//["F2838x", "F2837xD", "F2837xS", "F2807x","F28P65x"].includes(system.deviceData.deviceId)
|
||||
if(yesROM)
|
||||
{
|
||||
staticConfig.push(
|
||||
{
|
||||
name : "ROM_Config",
|
||||
displayName : "ROM Access Configuration",
|
||||
longDescription: "",
|
||||
config : ROMConfig
|
||||
}
|
||||
)
|
||||
}
|
||||
|
||||
|
||||
staticConfig.push(
|
||||
{
|
||||
name : "Access_Config",
|
||||
displayName : "Access Protection for RAMs",
|
||||
longDescription: "MULTICORE NOTE: Access Protection code for GSRAMs owned by CPU2 will be generated on CPU2",
|
||||
config : AccessConfig
|
||||
},
|
||||
{
|
||||
name : "Lock_Config",
|
||||
displayName : "Lock RAM Config Registers",
|
||||
longDescription: " - Do not lock : Writes to ACCPROT, TEST, INIT and MSEL fields are allowed\n - Lock : Writes to ACCPROT, TEST, INIT and MSEL fields are blocked. Application can unlock it using the function MemCfg_unlockConfig()\n - Lock and commit : Writes to ACCPROT, TEST, INIT and MSEL fields are permanently blocked.\n - MULTICORE NOTE: Lock Config code for GSRAMs owned by CPU2 will be generated on CPU2",
|
||||
config : LockConfig
|
||||
},
|
||||
{
|
||||
name : "ViolInt_Config",
|
||||
displayName : "Access Violation Interrupt",
|
||||
longDescription: "",
|
||||
config : ViolIntConfig
|
||||
},
|
||||
{
|
||||
name : "CorrError_Int",
|
||||
displayName : "Correctable Error Interrupt",
|
||||
longDescription: "",
|
||||
config : CorrErrIntConfig
|
||||
},
|
||||
{
|
||||
name : "registerInterrupts",
|
||||
displayName: "Register Interrupt Handler",
|
||||
default : false
|
||||
}
|
||||
)
|
||||
|
||||
/* For SYS_ERR interrupt shared across modules */
|
||||
var sharedModuleInstances = undefined
|
||||
|
||||
if(["F2838x", "F280013x", "F280015x", "F28P65x", "F28P55x"].includes(system.deviceData.deviceId))
|
||||
{
|
||||
sharedModuleInstances = function (inst) {
|
||||
if (inst.registerInterrupts)
|
||||
{
|
||||
return (
|
||||
[
|
||||
{
|
||||
name: "sysErrInt",
|
||||
displayName: "Sys Error Interrupt",
|
||||
moduleName: "/driverlib/interrupt/interrupt_sys_err.js",
|
||||
collapsed: true,
|
||||
},
|
||||
]
|
||||
);
|
||||
}
|
||||
return []
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function onValidate(inst, validation)
|
||||
{
|
||||
if(["F2837xS", "F2837xD", "F2807x", "F28004x"].includes(system.deviceData.deviceId))
|
||||
var maxThres = 0xFFFFFFFF
|
||||
else
|
||||
var maxThres = 0xFFFF
|
||||
|
||||
if (inst.errInt_thres > maxThres)
|
||||
{
|
||||
validation.logError("The threshold value must be less than 0x" + maxThres.toString(16).toUpperCase() + "!", inst, "errInt_thres");
|
||||
}
|
||||
|
||||
if (inst.rom_prefetch){
|
||||
if (!inst.rom_waitstate){
|
||||
validation.logWarning("You must enable ROM wait state to properly use the enable ROM prefetch setting", inst, "rom_waitstate");
|
||||
}
|
||||
}
|
||||
|
||||
if (Common.isMultiCoreSysConfig() || (Common.isMultiCoreDevice() && Common.isContextCPU1()))
|
||||
{
|
||||
var contextNames = Common.getContextNames();
|
||||
var context1 = null;
|
||||
var context2 = null;
|
||||
for (var cntx of contextNames)
|
||||
{
|
||||
if (cntx.slice(-1) == "1") // Look for CPU1 Context
|
||||
{
|
||||
context1 = cntx;
|
||||
}
|
||||
|
||||
if (cntx.slice(-1) == "2") // Look for CPU2 Context
|
||||
{
|
||||
context2 = cntx;
|
||||
}
|
||||
}
|
||||
var CPU1_mod = Common.getModuleForCore("/driverlib/memcfg.js", context1); // get module from core 1
|
||||
var CPU2_mod = Common.getModuleForCore("/driverlib/memcfg.js", context2); // get module from core 1
|
||||
if (CPU1_mod != null)
|
||||
{
|
||||
var stat_1 = CPU1_mod.$static;
|
||||
}
|
||||
|
||||
if (Common.isMultiCoreSysConfig() && Common.isContextCPU1())
|
||||
{
|
||||
if (!CPU2_mod){
|
||||
validation.logWarning("Error checking and code generation are limited for single core SysConfig on a multicore device. Add memcfg module on CPU2 for full functionality.", inst, "init_MEMCFG_SECT_M0");
|
||||
}
|
||||
}
|
||||
if (Common.isContextCPU2())
|
||||
{
|
||||
if (!CPU1_mod){
|
||||
validation.logWarning("Error checking and code generation are limited for single core SysConfig on a multicore device. Add memcfg module on CPU1 for full functionality.", inst, "init_MEMCFG_SECT_M0");
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (Common.isContextCPU2()){
|
||||
|
||||
validation.logWarning("Error checking and code generation are limited for single core SysConfig on a multicore device.", inst, "init_MEMCFG_SECT_M0");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
var memcfgModule = {
|
||||
peripheralName : "MEMCFG",
|
||||
displayName : "MEMCFG",
|
||||
longDescription : longDescription,
|
||||
maxInstances : 1,
|
||||
defaultInstanceName: "myMEMCFG",
|
||||
description : "Memory Configuration",
|
||||
moduleStatic : {
|
||||
config : staticConfig,
|
||||
moduleInstances: (inst) => {
|
||||
if (inst.registerInterrupts)
|
||||
{
|
||||
if(!["F2838x", "F280013x", "F280015x", "F28P65x", "F28P55x"].includes(system.deviceData.deviceId))
|
||||
{
|
||||
return [
|
||||
{
|
||||
name: "memcfgAccInt",
|
||||
displayName: "Access Violation Interrupt",
|
||||
moduleName: "/driverlib/interrupt.js",
|
||||
collapsed: true,
|
||||
args: {
|
||||
$name : "RAM_ACC_VIOL_INT",
|
||||
int : "RAM_ACC_VIOL_INT",
|
||||
pinmuxPeripheralModule : "",
|
||||
driverlibInt: "INT_RAM_ACC_VIOL"
|
||||
}
|
||||
},
|
||||
{
|
||||
name: "memcfgCorrErrInt",
|
||||
displayName: "Correctable Error Interrupt",
|
||||
moduleName: "/driverlib/interrupt.js",
|
||||
collapsed: true,
|
||||
args: {
|
||||
$name : "RAM_CORR_ERR_INT",
|
||||
int : "RAM_CORR_ERR_INT",
|
||||
pinmuxPeripheralModule : "",
|
||||
driverlibInt: "INT_RAM_CORR_ERR"
|
||||
}
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
return []
|
||||
},
|
||||
sharedModuleInstances : sharedModuleInstances,
|
||||
validate: onValidate,
|
||||
},
|
||||
templates: {
|
||||
boardc: "/driverlib/memcfg/memcfg.board.c.xdt",
|
||||
boardh: "/driverlib/memcfg/memcfg.board.h.xdt"
|
||||
},
|
||||
};
|
||||
|
||||
exports = memcfgModule;
|
||||
Reference in New Issue
Block a user