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hangpersonal
2026-08-30 23:04:35 -07:00
parent 749dab5721
commit ce65a0f59a
14950 changed files with 4408250 additions and 1 deletions
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C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/CCS/i2c_ex1_loopback.projectspec
+41
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@@ -0,0 +1,41 @@
<projectSpec>
<project
name="i2c_ex1_loopback"
device="TMS320F28377D"
cgtVersion="22.6.0.LTS"
products="sysconfig;C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xD"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG -v28 -ml -mt --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG -v28 -ml -mt --define=CPU1 --define=_FLASH --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<configuration name="CPU1_CLB" postBuildStep="mkdir &quot;${BuildDirectory}/simulation&quot;
;${CLB_SIM_COMPILER}/g++ -c -DCLB_SIM -I${SYSTEMC_INSTALL}/src -I${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/include -I${PROJECT_ROOT} -I${CLB_SIM_COMPILER}/include -Og -g -gdwarf-3 -gstrict-dwarf -Wall -MMD -MP -MF${BuildDirectory}/simulation/clb_sim.d -MT${BuildDirectory}/simulation/clb_sim.o -I${BuildDirectory}/syscfg -fno-threadsafe-statics -o${BuildDirectory}/simulation/clb_sim.o ${BuildDirectory}/syscfg/clb_sim.cpp
;${CLB_SIM_COMPILER}/g++ -DCLB_SIM -Og -g -gdwarf-3 -gstrict-dwarf -Wall -Wl,-Map,${BuildDirectory}/simulation/simulation_output.map -L${SYSTEMC_INSTALL}/build/src -o${BuildDirectory}/simulation/simulation_output.exe ${BuildDirectory}/simulation/clb_sim.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_FSM_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_HLC_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_LUT4_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_OutputLUT_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_counter_SC_model.o -Wl,--start-group -lsystemc -Wl,--end-group;./simulation/simulation_output.exe
;${NODE_TOOL} &quot;${CLB_SYSCFG_ROOT}/dot_file_libraries/clbDotUtility.js&quot; &quot;${CLB_SYSCFG_ROOT}&quot; &quot;${BuildDirectory}/syscfg&quot; &quot;${BuildDirectory}/syscfg/clb.dot&quot;" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG -v28 -ml -mt --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/targetConfigs/TMS320F28377D.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM,CPU1_CLB" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/F2837xD_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../i2c_ex1_loopback.c" targetDirectory="" />
<file action="copy" path="../i2c_ex1_loopback.syscfg" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/CCS/i2c_ex2_eeprom.projectspec
+28
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@@ -0,0 +1,28 @@
<projectSpec>
<project
name="i2c_ex2_eeprom"
device="TMS320F28377D"
cgtVersion="22.6.0.LTS"
products="C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xD"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -ml -mt --float_support=fpu32 --define=DEBUG --define=CPU1 -v28 --float_support=fpu32 --cla_support=cla1 --vcu_support=vcu0 --tmu_support=tmu0 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -ml -mt --float_support=fpu32 --define=DEBUG --define=_FLASH --define=CPU1 -v28 --float_support=fpu32 --cla_support=cla1 --vcu_support=vcu0 --tmu_support=tmu0 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/targetConfigs/TMS320F28377D.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/F2837xD_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True"/>
<file action="copy" path="../i2c_ex2_eeprom.c" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/CCS/i2c_ex3_external_loopback.projectspec
+28
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@@ -0,0 +1,28 @@
<projectSpec>
<project
name="i2c_ex3_external_loopback"
device="TMS320F28377D"
cgtVersion="22.6.0.LTS"
products="C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xD"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --float_support=fpu32 --define=DEBUG --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --float_support=fpu32 --define=DEBUG --define=_FLASH --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/targetConfigs/TMS320F28377D.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/F2837xD_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../i2c_ex3_external_loopback.c" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/CCS/i2c_ex4_eeprom_polling.projectspec
+43
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@@ -0,0 +1,43 @@
<projectSpec>
<project
name="i2c_ex4_eeprom_polling"
device="TMS320F28377D"
cgtVersion="22.6.0.LTS"
products="C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xD"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_SFO_INCLUDE} --define=DEBUG -v28 -ml -mt --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_SFO_INCLUDE} --define=DEBUG -v28 -ml -mt --define=CPU1 --define=_FLASH --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<configuration name="CPU1_CLB" postBuildStep="mkdir &quot;${BuildDirectory}/simulation&quot;
;${CLB_SIM_COMPILER}/g++ -c -DCLB_SIM -I${SYSTEMC_INSTALL}/src -I${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/include -I${PROJECT_ROOT} -I${CLB_SIM_COMPILER}/include -Og -g -gdwarf-3 -gstrict-dwarf -Wall -MMD -MP -MF${BuildDirectory}/simulation/clb_sim.d -MT${BuildDirectory}/simulation/clb_sim.o -I${BuildDirectory}/syscfg -fno-threadsafe-statics -o${BuildDirectory}/simulation/clb_sim.o ${BuildDirectory}/syscfg/clb_sim.cpp
;${CLB_SIM_COMPILER}/g++ -DCLB_SIM -Og -g -gdwarf-3 -gstrict-dwarf -Wall -Wl,-Map,${BuildDirectory}/simulation/simulation_output.map -L${SYSTEMC_INSTALL}/build/src -o${BuildDirectory}/simulation/simulation_output.exe ${BuildDirectory}/simulation/clb_sim.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_FSM_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_HLC_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_LUT4_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_OutputLUT_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_counter_SC_model.o -Wl,--start-group -lsystemc -Wl,--end-group;./simulation/simulation_output.exe
;${NODE_TOOL} &quot;${CLB_SYSCFG_ROOT}/dot_file_libraries/clbDotUtility.js&quot; &quot;${CLB_SYSCFG_ROOT}&quot; &quot;${BuildDirectory}/syscfg&quot; &quot;${BuildDirectory}/syscfg/clb.dot&quot;" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_SFO_INCLUDE} --define=DEBUG -v28 -ml -mt --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<pathVariable name="C2000WARE_SFO_INCLUDE" path="../../../../../../libraries/calibration/hrpwm/F2837xD/include/" scope="project" />
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
<file action="link" path="../../../../../../libraries/calibration/hrpwm/F2837xD/lib/SFO_v8_fpu_lib_build_c28_driverlib.lib" targetDirectory="" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/targetConfigs/TMS320F28377D.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM,CPU1_CLB" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/F2837xD_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../i2c_ex4_eeprom_polling.c" targetDirectory="" />
<file action="copy" path="../i2cLib_FIFO_polling.c" targetDirectory="" />
<file action="copy" path="../i2cLib_FIFO_polling.h" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/CCS/i2c_ex5_master_slave_interrupt.projectspec
+43
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@@ -0,0 +1,43 @@
<projectSpec>
<project
name="i2c_ex5_master_slave_interrupt"
device="TMS320F28377D"
cgtVersion="22.6.0.LTS"
products="C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xD"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_SFO_INCLUDE} --define=DEBUG -v28 -ml -mt --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_SFO_INCLUDE} --define=DEBUG -v28 -ml -mt --define=CPU1 --define=_FLASH --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<configuration name="CPU1_CLB" postBuildStep="mkdir &quot;${BuildDirectory}/simulation&quot;
;${CLB_SIM_COMPILER}/g++ -c -DCLB_SIM -I${SYSTEMC_INSTALL}/src -I${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/include -I${PROJECT_ROOT} -I${CLB_SIM_COMPILER}/include -Og -g -gdwarf-3 -gstrict-dwarf -Wall -MMD -MP -MF${BuildDirectory}/simulation/clb_sim.d -MT${BuildDirectory}/simulation/clb_sim.o -I${BuildDirectory}/syscfg -fno-threadsafe-statics -o${BuildDirectory}/simulation/clb_sim.o ${BuildDirectory}/syscfg/clb_sim.cpp
;${CLB_SIM_COMPILER}/g++ -DCLB_SIM -Og -g -gdwarf-3 -gstrict-dwarf -Wall -Wl,-Map,${BuildDirectory}/simulation/simulation_output.map -L${SYSTEMC_INSTALL}/build/src -o${BuildDirectory}/simulation/simulation_output.exe ${BuildDirectory}/simulation/clb_sim.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_FSM_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_HLC_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_LUT4_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_OutputLUT_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_counter_SC_model.o -Wl,--start-group -lsystemc -Wl,--end-group;./simulation/simulation_output.exe
;${NODE_TOOL} &quot;${CLB_SYSCFG_ROOT}/dot_file_libraries/clbDotUtility.js&quot; &quot;${CLB_SYSCFG_ROOT}&quot; &quot;${BuildDirectory}/syscfg&quot; &quot;${BuildDirectory}/syscfg/clb.dot&quot;" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_SFO_INCLUDE} --define=DEBUG -v28 -ml -mt --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<pathVariable name="C2000WARE_SFO_INCLUDE" path="../../../../../../libraries/calibration/hrpwm/F2837xD/include/" scope="project" />
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
<file action="link" path="../../../../../../libraries/calibration/hrpwm/F2837xD/lib/SFO_v8_fpu_lib_build_c28_driverlib.lib" targetDirectory="" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/targetConfigs/TMS320F28377D.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM,CPU1_CLB" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/F2837xD_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../i2c_ex5_master_slave_interrupt.c" targetDirectory="" />
<file action="copy" path="../i2cLib_FIFO_master_slave_interrupt.c" targetDirectory="" />
<file action="copy" path="../i2cLib_FIFO_master_slave_interrupt.h" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/CCS/i2c_ex6_eeprom_interrupt.projectspec
+43
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@@ -0,0 +1,43 @@
<projectSpec>
<project
name="i2c_ex6_eeprom_interrupt"
device="TMS320F28377D"
cgtVersion="22.6.0.LTS"
products="C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xD"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_SFO_INCLUDE} --define=DEBUG -v28 -ml -mt --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_SFO_INCLUDE} --define=DEBUG -v28 -ml -mt --define=CPU1 --define=_FLASH --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<configuration name="CPU1_CLB" postBuildStep="mkdir &quot;${BuildDirectory}/simulation&quot;
;${CLB_SIM_COMPILER}/g++ -c -DCLB_SIM -I${SYSTEMC_INSTALL}/src -I${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/include -I${PROJECT_ROOT} -I${CLB_SIM_COMPILER}/include -Og -g -gdwarf-3 -gstrict-dwarf -Wall -MMD -MP -MF${BuildDirectory}/simulation/clb_sim.d -MT${BuildDirectory}/simulation/clb_sim.o -I${BuildDirectory}/syscfg -fno-threadsafe-statics -o${BuildDirectory}/simulation/clb_sim.o ${BuildDirectory}/syscfg/clb_sim.cpp
;${CLB_SIM_COMPILER}/g++ -DCLB_SIM -Og -g -gdwarf-3 -gstrict-dwarf -Wall -Wl,-Map,${BuildDirectory}/simulation/simulation_output.map -L${SYSTEMC_INSTALL}/build/src -o${BuildDirectory}/simulation/simulation_output.exe ${BuildDirectory}/simulation/clb_sim.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_FSM_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_HLC_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_LUT4_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_OutputLUT_SC_model.o ${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/systemc/src/CLB_counter_SC_model.o -Wl,--start-group -lsystemc -Wl,--end-group;./simulation/simulation_output.exe
;${NODE_TOOL} &quot;${CLB_SYSCFG_ROOT}/dot_file_libraries/clbDotUtility.js&quot; &quot;${CLB_SYSCFG_ROOT}&quot; &quot;${BuildDirectory}/syscfg&quot; &quot;${BuildDirectory}/syscfg/clb.dot&quot;" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_SFO_INCLUDE} --define=DEBUG -v28 -ml -mt --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<pathVariable name="C2000WARE_SFO_INCLUDE" path="../../../../../../libraries/calibration/hrpwm/F2837xD/include/" scope="project" />
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
<file action="link" path="../../../../../../libraries/calibration/hrpwm/F2837xD/lib/SFO_v8_fpu_lib_build_c28_driverlib.lib" targetDirectory="" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/targetConfigs/TMS320F28377D.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM,CPU1_CLB" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/cmd/2837xD_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../../../../../../device_support/f2837xd/common/source/F2837xD_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../i2c_ex6_eeprom_interrupt.c" targetDirectory="" />
<file action="copy" path="../i2cLib_FIFO_master_interrupt.c" targetDirectory="" />
<file action="copy" path="../i2cLib_FIFO_master_interrupt.h" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2cLib_FIFO_master_interrupt.c
+453
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@@ -0,0 +1,453 @@
//#############################################################################
//
// FILE: i2cLib_FIFO_master_interrupt.c
//
// TITLE: C28x-I2C Library source file for FIFO interrupts
//
//#############################################################################
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#include "driverlib.h"
#include "device.h"
#include "i2cLib_FIFO_master_interrupt.h"
void handleI2C_ErrorCondition(struct I2CHandle *I2C_Params);
void Write_Read_TX_RX_FIFO(struct I2CHandle *I2C_Params);
uint16_t I2CBusScan(uint32_t base, uint16_t *pAvailableI2C_slaves)
{
uint16_t probeSlaveAddress, i;
//Disable interrupts on Stop condition, NACK and arbitration lost condition
I2C_disableInterrupt(base, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
i = 0;
for(probeSlaveAddress=1;probeSlaveAddress<=MAX_10_BIT_ADDRESS;probeSlaveAddress++)
{
//Check I2C bus status
status = checkBusStatus(base);
if(status)
{
ESTOP0;
return status;
}
I2C_setConfig(base, (I2C_MASTER_SEND_MODE | I2C_REPEAT_MODE));
//Enable 10-bit addressing if probeSlaveAddress is greater than 127U
if(probeSlaveAddress > MAX_7_BIT_ADDRESS)
{
//10-bit addressing
I2C_setAddressMode(base, I2C_ADDR_MODE_10BITS);
}
// Setup slave address
I2C_setSlaveAddress(base, probeSlaveAddress);
I2C_sendStartCondition(base);
//Wait for the slave address to be transmitted
while(!(I2C_getStatus(base) & I2C_STS_REG_ACCESS_RDY));
//Generate STOP condition
I2C_sendStopCondition(base);
//Wait for the I2CMDR.STP to be cleared
while(I2C_getStopConditionStatus(base));
//Wait for the Bus busy bit to be cleared
while(I2C_isBusBusy(base));
uint16_t I2CStatus = I2C_getStatus(base);
//If Slave address is acknowledged, store slave address
//in pAvailableI2C_slaves
if(!(I2CStatus & I2C_STS_NO_ACK))
{
pAvailableI2C_slaves[i++] = probeSlaveAddress;
}
//Clear NACK bit in I2CSTR
I2C_clearStatus(base,I2C_STS_NO_ACK|I2C_STS_ARB_LOST|I2C_STS_REG_ACCESS_RDY|I2C_STS_STOP_CONDITION);
}
I2C_setConfig(base, (I2C_MASTER_SEND_MODE));
I2C_setAddressMode(base, I2C_ADDR_MODE_7BITS); //7-bit addressing
I2C_enableInterrupt(base, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
return SUCCESS;
}
uint16_t I2C_TransmitSlaveAddress_ControlBytes(struct I2CHandle *I2C_Params)
{
uint16_t status;
uint32_t base = I2C_Params->base;
status = checkBusStatus(base);
if(status)
{
return status;
}
I2C_disableFIFO(base);
I2C_setConfig(base, (I2C_MASTER_SEND_MODE));
if((I2C_Params->SlaveAddr) > MAX_7_BIT_ADDRESS)
{
//10-bit addressing
I2C_setAddressMode(base, I2C_ADDR_MODE_10BITS);
}
// Setup slave address
I2C_setSlaveAddress(base, I2C_Params->SlaveAddr);
I2C_setDataCount(base, (I2C_Params->NumOfAddrBytes));
I2C_enableFIFO(base);
uint32_t temp = *(I2C_Params->pControlAddr);
temp = temp & 0x00FFFFFF;
temp |= (uint32_t)(I2C_Params->NumOfDataBytes)<<24U;
int16_t i;
i = I2C_Params->NumOfAddrBytes-1;
for(i=I2C_Params->NumOfAddrBytes-1;i>=0;i--)
{
I2C_putData(base, (temp >> (i*8U)) & 0xFF);
}
I2C_sendStartCondition(base);
return SUCCESS;
}
uint16_t I2C_MasterTransmitter(struct I2CHandle *I2C_Params)
{
uint16_t status;
uint32_t base = I2C_Params->base;
I2C_Params->numofSixteenByte = (I2C_Params->NumOfDataBytes) / I2C_FIFO_LEVEL;
I2C_Params->remainingBytes = (I2C_Params->NumOfDataBytes) % I2C_FIFO_LEVEL;
ASSERT(I2C_Params->NumOfDataBytes <= MAX_BUFFER_SIZE);
I2C_enableFIFO(base);
status = I2C_TransmitSlaveAddress_ControlBytes(I2C_Params);
if(status)
{
return status;
}
I2C_setDataCount(base, (I2C_Params->NumOfAddrBytes + I2C_Params->NumOfDataBytes));
//I2C_sendStopCondition(base);
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, I2C_FIFO_RXFULL);
I2C_enableInterrupt(base, (I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
I2C_enableInterrupt(base, I2C_INT_TXFF);
I2C_clearInterruptStatus(base, I2C_INT_TXFF);
return SUCCESS;
}
uint16_t I2C_MasterReceiver(struct I2CHandle *I2C_Params)
{
uint16_t status;
uint32_t base = I2C_Params->base;
I2C_Params->numofSixteenByte = (I2C_Params->NumOfDataBytes) / I2C_FIFO_LEVEL;
I2C_Params->remainingBytes = (I2C_Params->NumOfDataBytes) % I2C_FIFO_LEVEL;
I2C_disableInterrupt(base, I2C_INT_TXFF|I2C_INT_RXFF);
I2C_clearInterruptStatus(base, (I2C_INT_REG_ACCESS_RDY|I2C_INT_TXFF|I2C_INT_RXFF));
I2C_enableInterrupt(base, I2C_INT_REG_ACCESS_RDY);
status = I2C_TransmitSlaveAddress_ControlBytes(I2C_Params);
SysCtl_delay(50); //Adding delay to correctly read I2C bus status
if(status)
{
return status;
}
return SUCCESS;
}
uint16_t checkBusStatus(uint32_t base)
{
if(I2C_isBusBusy(base))
{
return ERROR_BUS_BUSY;
}
if(I2C_getStopConditionStatus(base))
{
return ERROR_STOP_NOT_READY;
}
return SUCCESS;
}
uint16_t handleNACK(uint32_t base)
{
if(I2C_getStatus(base) & I2C_STS_NO_ACK)
{
I2C_clearStatus(base, I2C_STS_NO_ACK);
I2C_disableFIFO(base);
I2C_sendStopCondition(base);
I2C_enableFIFO(base);
return ERROR_NACK_RECEIVED;
}
return SUCCESS;
}
void handleI2C_ErrorCondition(struct I2CHandle *I2C_Params)
{
uint32_t base = I2C_Params->base;
I2C_InterruptSource intSource = I2C_getInterruptSource(base);
switch (intSource)
{
case I2C_INTSRC_ARB_LOST:
//Report Arbitration lost failure
status = ERROR_ARBITRATION_LOST;
break;
case I2C_INTSRC_NO_ACK:
//Clear NACK flag and generate STOP condition on a NACK condition
I2C_clearStatus(base, I2C_STS_NO_ACK);
I2C_sendStopCondition(base);
status = ERROR_NACK_RECEIVED;
break;
case I2C_INTSRC_REG_ACCESS_RDY:
I2C_disableInterrupt(base, I2C_INT_REG_ACCESS_RDY);
I2C_disableInterrupt(base, I2C_INT_TXFF);
I2C_disableFIFO(base);
I2C_enableFIFO(base);
I2C_setConfig(base, (I2C_MASTER_RECEIVE_MODE));
I2C_clearInterruptStatus(base, I2C_INT_TXFF);
if(I2C_Params->numofSixteenByte)
{
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, I2C_FIFO_RXFULL);
}
else
{
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)I2C_Params->remainingBytes);
}
I2C_setDataCount(base, I2C_Params->NumOfDataBytes);
I2C_sendStartCondition(base);
I2C_sendStopCondition(base);
break;
case I2C_INTSRC_RX_DATA_RDY:
break;
case I2C_INTSRC_TX_DATA_RDY:
break;
case I2C_INTSRC_STOP_CONDITION:
I2C_disableInterrupt(base, (I2C_INT_TXFF | I2C_INT_RXFF));
I2C_Params->pTX_MsgBuffer = TX_MsgBuffer;
I2C_Params->pRX_MsgBuffer = RX_MsgBuffer;
//I2C_disableFIFO(base);
break;
case I2C_INTSRC_ADDR_SLAVE:
//Set TX / RX FIFO Level
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)(I2C_Params->NumOfAddrBytes));
if((I2C_getStatus(base) & I2C_STS_SLAVE_DIR))
{
//Slave Transmitter (SDIR = 1)
I2C_setConfig(base, I2C_SLAVE_SEND_MODE);
//Enable TX FIFO interrupt and disable RXFF interrupt
I2C_enableInterrupt(base, I2C_INT_TXFF);
I2C_disableInterrupt(base, I2C_INT_RXFF);
I2C_clearInterruptStatus(base, (I2C_INT_TXFF|I2C_INT_RXFF));
}
else
{
//Slave Receiver (SDIR = 0)
I2C_setConfig(base, I2C_SLAVE_RECEIVE_MODE);
//Fill dummy data in Transmit FIFO to clear pending FIFO interrupt flag
//I2C_putData(base, 0xAA);
//I2C_putData(base, 0x55);
//Enable RX FIFO interrupt and disable TXFF interrupt
I2C_disableInterrupt(base, I2C_INT_TXFF);
I2C_enableInterrupt(base, I2C_INT_RXFF);
I2C_clearInterruptStatus(base, (I2C_INT_TXFF|I2C_INT_RXFF));
}
break;
}
}
void Write_Read_TX_RX_FIFO(struct I2CHandle *I2C_Params)
{
int16_t i;
uint32_t base = I2C_Params->base;
uint16_t numofSixteenByte = I2C_Params->numofSixteenByte;
uint16_t remainingBytes = I2C_Params->remainingBytes;
struct I2CHandle *currentPtr = I2C_Params->currentHandlePtr;
uint32_t intSource = (uint32_t)I2C_getInterruptStatus(base);
uint32_t txFIFOinterruptenabled = HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFIENA;
//Read the Address and Command
if((intSource & I2C_INT_RXFF) && (I2C_Params->pControlAddr) == 0x0)
{
uint32_t Addr_Ctrl = 0;
int16_t NumRX_Bytes = I2C_getRxFIFOStatus(base);
for(i=NumRX_Bytes-1;i>=0;i--)
{
Addr_Ctrl |= (uint32_t)(I2C_getData(base))<<(i*8U);
}
I2C_Params->pControlAddr = (uint32_t *)Addr_Ctrl;
I2C_Params->NumOfDataBytes = Addr_Ctrl >> 24U;
I2C_Params->numofSixteenByte = I2C_Params->NumOfDataBytes / I2C_FIFO_LEVEL;
I2C_Params->remainingBytes = I2C_Params->NumOfDataBytes % I2C_FIFO_LEVEL;
numofSixteenByte = I2C_Params->numofSixteenByte;
remainingBytes = I2C_Params->remainingBytes;
if(numofSixteenByte)
{
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, I2C_FIFO_RXFULL);
}
else
{
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)remainingBytes);
}
I2C_clearInterruptStatus(base,(I2C_INT_RXFF));
}
else
{
if((intSource & I2C_INT_TXFF) || (intSource & I2C_INT_RXFF))
{
//When numofSixteenByte becomes 0, read only remaining bytes
if(remainingBytes && (numofSixteenByte == 0))
{
for(i=0;i<remainingBytes;i++)
{
if((intSource & I2C_INT_TXFF) && txFIFOinterruptenabled)
{
I2C_putData(base, *(currentPtr->pTX_MsgBuffer++));
}
if(intSource & I2C_INT_RXFF)
{
*(currentPtr->pRX_MsgBuffer++) = I2C_getData(base);
}
}
remainingBytes = 0;
}
//When numofSixteenByte greater than 0, read all the 16 bytes in FIFO
if(numofSixteenByte)
{
if((intSource & I2C_INT_TXFF) && txFIFOinterruptenabled)
{
for(i=0;i<I2C_FIFO_TXFULL;i++)
{
I2C_putData(base, *(currentPtr->pTX_MsgBuffer++));
}
numofSixteenByte--;
}
if(intSource & I2C_INT_RXFF)
{
for(i=0;i<I2C_FIFO_RXFULL;i++)
{
*(currentPtr->pRX_MsgBuffer++) = I2C_getData(base);
}
numofSixteenByte--;
}
}
//When numofSixteenByte equal to 0, change RX FIFO level (RXFFIL) to remaining bytes
if((numofSixteenByte == 0) && (remainingBytes))
{
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)remainingBytes);
}
//When number of bytes are 0, then disable TX / RX FIFO interrupts, disable FIFO
//and send STOP condition
if((remainingBytes == 0) && (numofSixteenByte == 0))
{
//I2C_disableInterrupt(base, (I2C_INT_TXFF | I2C_INT_RXFF));
//I2C_disableFIFO(base);
if(HWREGH(I2C_Params->base + I2C_O_MDR) & I2C_MDR_MST)
{
I2C_sendStopCondition(base);
}
}
I2C_clearInterruptStatus(base,(I2C_INT_TXFF | I2C_INT_RXFF));
}
I2C_Params->numofSixteenByte = numofSixteenByte;
I2C_Params->remainingBytes = remainingBytes;
}
}
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2cLib_FIFO_master_interrupt.h
+110
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@@ -0,0 +1,110 @@
//#############################################################################
//
// FILE: i2cLib_FIFO_master_interrupt.h
//
// TITLE: C28x-I2C Library header file for FIFO interrupts
//
//#############################################################################
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#ifndef I2CLIB_FIFO_INTERRUPT_H
#define I2CLIB_FIFO_INTERRUPT_H
#include "device.h"
//
// Error messages for read and write functions
//
#define ERROR_BUS_BUSY 0x1000
#define ERROR_NACK_RECEIVED 0x2000
#define ERROR_ARBITRATION_LOST 0x3000
#define ERROR_STOP_NOT_READY 0x5555
#define SUCCESS 0x0000
#define MAX_BUFFER_SIZE 64
#define I2C_FIFO_LEVEL 16
#define MAX_7_BIT_ADDRESS 127U
#define MAX_10_BIT_ADDRESS 1023U
//
// Typedefs
//
struct I2CHandle
{
uint32_t base;
uint16_t SlaveAddr; // Slave address tied to the message.
uint32_t *pControlAddr;
uint16_t NumOfAddrBytes;
uint16_t *pTX_MsgBuffer; // Pointer to TX message buffer
uint16_t *pRX_MsgBuffer; // Pointer to RX message buffer
uint16_t NumOfDataBytes; // Number of valid bytes in message.
struct I2CHandle *currentHandlePtr;
uint16_t numofSixteenByte;
uint16_t remainingBytes;
uint16_t WriteCycleTime_in_us; // Slave write cycle time. Depends on slave.
// Please check slave device datasheet
};
uint16_t I2C_TransmitSlaveAddress_ControlBytes(struct I2CHandle *I2C_Params);
uint16_t I2CBusScan(uint32_t base, uint16_t *pAvailableI2C_slaves);
uint16_t I2C_MasterTransmitter(struct I2CHandle *I2C_Params);
uint16_t I2C_MasterReceiver(struct I2CHandle *I2C_Params);
uint16_t I2C_SlaveTransmitter(struct I2CHandle *I2C_Params);
uint16_t I2C_SlaveReceiver(struct I2CHandle *I2C_Params);
uint16_t checkBusStatus(uint32_t base);
uint16_t handleNACK(uint32_t base);
extern void handleI2C_ErrorCondition(struct I2CHandle *I2C_Params);
extern void Write_Read_TX_RX_FIFO(struct I2CHandle *I2C_Params);
extern uint16_t TX_MsgBuffer[MAX_BUFFER_SIZE];
extern uint16_t RX_MsgBuffer[MAX_BUFFER_SIZE];
extern uint16_t status;
extern struct I2CHandle *currentSlavePtr;
#endif
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2cLib_FIFO_master_slave_interrupt.c
+452
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@@ -0,0 +1,452 @@
//#############################################################################
//
// FILE: i2cLib_FIFO_master_slave_interrupt.c
//
// TITLE: C28x-I2C Library source file for FIFO interrupts
//
//#############################################################################
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#include "driverlib.h"
#include "device.h"
#include "i2cLib_FIFO_master_slave_interrupt.h"
#define MAX_7_BIT_ADDRESS 127U
void handleI2C_ErrorCondition(struct I2CHandle *I2C_Params);
void Write_Read_TX_RX_FIFO(struct I2CHandle *I2C_Params);
uint16_t I2CBusScan(uint32_t base, uint16_t *pAvailableI2C_slaves)
{
uint16_t probeSlaveAddress, i;
//Disable interrupts on Stop condition, NACK and arbitration lost condition
I2C_disableInterrupt(base, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
i = 0;
for(probeSlaveAddress=1;probeSlaveAddress<=MAX_10_BIT_ADDRESS;probeSlaveAddress++)
{
//Check I2C bus status
status = checkBusStatus(base);
if(status)
{
ESTOP0;
return status;
}
I2C_setConfig(base, (I2C_MASTER_SEND_MODE | I2C_REPEAT_MODE));
//Enable 10-bit addressing if probeSlaveAddress is greater than 127U
if(probeSlaveAddress > MAX_7_BIT_ADDRESS)
{
//10-bit addressing
I2C_setAddressMode(base, I2C_ADDR_MODE_10BITS);
}
// Setup slave address
I2C_setSlaveAddress(base, probeSlaveAddress);
I2C_sendStartCondition(base);
//Wait for the slave address to be transmitted
while(!(I2C_getStatus(base) & I2C_STS_REG_ACCESS_RDY));
//Generate STOP condition
I2C_sendStopCondition(base);
//Wait for the I2CMDR.STP to be cleared
while(I2C_getStopConditionStatus(base));
//Wait for the Bus busy bit to be cleared
while(I2C_isBusBusy(base));
uint16_t I2CStatus = I2C_getStatus(base);
//If Slave address is acknowledged, store slave address
//in pAvailableI2C_slaves
if(!(I2CStatus & I2C_STS_NO_ACK))
{
pAvailableI2C_slaves[i++] = probeSlaveAddress;
}
//Clear NACK bit in I2CSTR
I2C_clearStatus(base,I2C_STS_NO_ACK|I2C_STS_ARB_LOST|I2C_STS_REG_ACCESS_RDY|I2C_STS_STOP_CONDITION);
}
I2C_setConfig(base, (I2C_MASTER_SEND_MODE));
I2C_setAddressMode(base, I2C_ADDR_MODE_7BITS); //7-bit addressing
I2C_enableInterrupt(base, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
return SUCCESS;
}
uint16_t I2C_TransmitSlaveAddress_ControlBytes(struct I2CHandle *I2C_Params)
{
uint16_t status;
uint32_t base = I2C_Params->base;
status = checkBusStatus(base);
if(status)
{
return status;
}
I2C_disableFIFO(base);
I2C_setConfig(base, (I2C_MASTER_SEND_MODE));
if((I2C_Params->SlaveAddr) > MAX_7_BIT_ADDRESS)
{
//10-bit addressing
I2C_setAddressMode(base, I2C_ADDR_MODE_10BITS);
}
// Setup slave address
I2C_setSlaveAddress(base, I2C_Params->SlaveAddr);
I2C_setDataCount(base, (I2C_Params->NumOfAddrBytes));
I2C_enableFIFO(base);
uint32_t temp = *(I2C_Params->pControlAddr);
temp = temp & 0x00FFFFFF;
temp |= (uint32_t)(I2C_Params->NumOfDataBytes)<<24U;
int16_t i;
i = I2C_Params->NumOfAddrBytes-1;
for(i=I2C_Params->NumOfAddrBytes-1;i>=0;i--)
{
I2C_putData(base, (temp >> (i*8U)) & 0xFF);
}
I2C_sendStartCondition(base);
return SUCCESS;
}
uint16_t I2C_MasterTransmitter(struct I2CHandle *I2C_Params)
{
uint16_t status;
uint32_t base = I2C_Params->base;
I2C_Params->numofSixteenByte = (I2C_Params->NumOfDataBytes) / I2C_FIFO_LEVEL;
I2C_Params->remainingBytes = (I2C_Params->NumOfDataBytes) % I2C_FIFO_LEVEL;
ASSERT(I2C_Params->NumOfDataBytes <= MAX_BUFFER_SIZE);
I2C_enableFIFO(base);
status = I2C_TransmitSlaveAddress_ControlBytes(I2C_Params);
if(status)
{
return status;
}
I2C_setDataCount(base, (I2C_Params->NumOfAddrBytes + I2C_Params->NumOfDataBytes));
I2C_sendStopCondition(base);
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, I2C_FIFO_RXFULL);
I2C_enableInterrupt(base, (I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
I2C_enableInterrupt(base, I2C_INT_TXFF);
I2C_clearInterruptStatus(base, I2C_INT_TXFF);
return SUCCESS;
}
uint16_t I2C_MasterReceiver(struct I2CHandle *I2C_Params)
{
uint16_t status;
uint32_t base = I2C_Params->base;
I2C_Params->numofSixteenByte = (I2C_Params->NumOfDataBytes) / I2C_FIFO_LEVEL;
I2C_Params->remainingBytes = (I2C_Params->NumOfDataBytes) % I2C_FIFO_LEVEL;
I2C_disableInterrupt(base, I2C_INT_TXFF|I2C_INT_RXFF);
I2C_clearInterruptStatus(base, (I2C_INT_REG_ACCESS_RDY|I2C_INT_TXFF|I2C_INT_RXFF));
status = I2C_TransmitSlaveAddress_ControlBytes(I2C_Params);
SysCtl_delay(50); //Adding delay to correctly read I2C bus status
if(status)
{
return status;
}
return SUCCESS;
}
uint16_t checkBusStatus(uint32_t base)
{
if(I2C_isBusBusy(base))
{
return ERROR_BUS_BUSY;
}
if(I2C_getStopConditionStatus(base))
{
return ERROR_STOP_NOT_READY;
}
return SUCCESS;
}
uint16_t handleNACK(uint32_t base)
{
if(I2C_getStatus(base) & I2C_STS_NO_ACK)
{
I2C_clearStatus(base, I2C_STS_NO_ACK);
I2C_disableFIFO(base);
I2C_sendStopCondition(base);
I2C_enableFIFO(base);
return ERROR_NACK_RECEIVED;
}
return SUCCESS;
}
void handleI2C_ErrorCondition(struct I2CHandle *I2C_Params)
{
uint32_t base = I2C_Params->base;
I2C_InterruptSource intSource = I2C_getInterruptSource(base);
switch (intSource)
{
case I2C_INTSRC_ARB_LOST:
//Report Arbitration lost failure
status = ERROR_ARBITRATION_LOST;
break;
case I2C_INTSRC_NO_ACK:
//Clear NACK flag and generate STOP condition on a NACK condition
I2C_clearStatus(base, I2C_STS_NO_ACK);
I2C_sendStopCondition(base);
status = ERROR_NACK_RECEIVED;
break;
case I2C_INTSRC_REG_ACCESS_RDY:
I2C_disableInterrupt(base, I2C_INT_REG_ACCESS_RDY);
I2C_disableInterrupt(base, I2C_INT_TXFF);
I2C_disableFIFO(base);
I2C_enableFIFO(base);
I2C_setConfig(base, (I2C_MASTER_RECEIVE_MODE));
I2C_clearInterruptStatus(base, I2C_INT_TXFF);
if(I2C_Params->numofSixteenByte)
{
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, I2C_FIFO_RXFULL);
}
else
{
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)I2C_Params->remainingBytes);
}
I2C_setDataCount(base, I2C_Params->NumOfDataBytes);
I2C_sendStartCondition(base);
I2C_sendStopCondition(base);
break;
case I2C_INTSRC_RX_DATA_RDY:
break;
case I2C_INTSRC_TX_DATA_RDY:
break;
case I2C_INTSRC_STOP_CONDITION:
I2C_disableInterrupt(base, (I2C_INT_TXFF | I2C_INT_RXFF));
//I2C_disableFIFO(base);
break;
case I2C_INTSRC_ADDR_SLAVE:
//Set TX / RX FIFO Level
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)(I2C_Params->NumOfAddrBytes));
if((I2C_getStatus(base) & I2C_STS_SLAVE_DIR))
{
//Slave Transmitter (SDIR = 1)
I2C_setConfig(base, I2C_SLAVE_SEND_MODE);
//Enable TX FIFO interrupt and disable RXFF interrupt
I2C_enableInterrupt(base, I2C_INT_TXFF);
I2C_disableInterrupt(base, I2C_INT_RXFF);
I2C_clearInterruptStatus(base, (I2C_INT_TXFF|I2C_INT_RXFF));
}
else
{
//Slave Receiver (SDIR = 0)
I2C_setConfig(base, I2C_SLAVE_RECEIVE_MODE);
//Fill dummy data in Transmit FIFO to clear pending FIFO interrupt flag
//I2C_putData(base, 0xAA);
//I2C_putData(base, 0x55);
//Enable RX FIFO interrupt and disable TXFF interrupt
I2C_disableInterrupt(base, I2C_INT_TXFF);
I2C_enableInterrupt(base, I2C_INT_RXFF);
I2C_clearInterruptStatus(base, (I2C_INT_TXFF|I2C_INT_RXFF));
}
break;
}
}
void Write_Read_TX_RX_FIFO(struct I2CHandle *I2C_Params)
{
int16_t i;
uint32_t base = I2C_Params->base;
uint16_t numofSixteenByte = I2C_Params->numofSixteenByte;
uint16_t remainingBytes = I2C_Params->remainingBytes;
struct I2CHandle *currentPtr = I2C_Params->currentHandlePtr;
uint32_t intSource = (uint32_t)I2C_getInterruptStatus(base);
uint32_t txFIFOinterruptenabled = HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFIENA;
//Read the Address and Command
if((intSource & I2C_INT_RXFF) && (I2C_Params->pControlAddr) == 0x0)
{
uint32_t Addr_Ctrl = 0;
int16_t NumRX_Bytes = I2C_getRxFIFOStatus(base);
for(i=NumRX_Bytes-1;i>=0;i--)
{
Addr_Ctrl |= (uint32_t)(I2C_getData(base))<<(i*8U);
}
I2C_Params->pControlAddr = (uint32_t *)Addr_Ctrl;
I2C_Params->NumOfDataBytes = Addr_Ctrl >> 24U;
I2C_Params->numofSixteenByte = I2C_Params->NumOfDataBytes / I2C_FIFO_LEVEL;
I2C_Params->remainingBytes = I2C_Params->NumOfDataBytes % I2C_FIFO_LEVEL;
numofSixteenByte = I2C_Params->numofSixteenByte;
remainingBytes = I2C_Params->remainingBytes;
if(numofSixteenByte)
{
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, I2C_FIFO_RXFULL);
}
else
{
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)remainingBytes);
}
I2C_clearInterruptStatus(base,(I2C_INT_RXFF));
}
else
{
if((intSource & I2C_INT_TXFF) || (intSource & I2C_INT_RXFF))
{
//When numofSixteenByte becomes 0, read only remaining bytes
if(remainingBytes && (numofSixteenByte == 0))
{
for(i=0;i<remainingBytes;i++)
{
if((intSource & I2C_INT_TXFF) && txFIFOinterruptenabled)
{
I2C_putData(base, *(currentPtr->pTX_MsgBuffer++));
}
if(intSource & I2C_INT_RXFF)
{
*(currentPtr->pRX_MsgBuffer++) = I2C_getData(base);
}
}
remainingBytes = 0;
}
//When numofSixteenByte greater than 0, read all the 16 bytes in FIFO
if(numofSixteenByte)
{
if((intSource & I2C_INT_TXFF) && txFIFOinterruptenabled)
{
for(i=0;i<I2C_FIFO_TXFULL;i++)
{
I2C_putData(base, *(currentPtr->pTX_MsgBuffer++));
}
numofSixteenByte--;
}
if(intSource & I2C_INT_RXFF)
{
for(i=0;i<I2C_FIFO_RXFULL;i++)
{
*(currentPtr->pRX_MsgBuffer++) = I2C_getData(base);
}
numofSixteenByte--;
}
}
//When numofSixteenByte equal to 0, change RX FIFO level (RXFFIL) to remaining bytes
if((numofSixteenByte == 0) && (remainingBytes))
{
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)remainingBytes);
}
//When number of bytes are 0, then disable TX / RX FIFO interrupts, disable FIFO
//and send STOP condition
if((remainingBytes == 0) && (numofSixteenByte == 0))
{
//I2C_disableInterrupt(base, (I2C_INT_TXFF | I2C_INT_RXFF));
//I2C_disableFIFO(base);
if(HWREGH(I2C_Params->base + I2C_O_MDR) & I2C_MDR_MST)
{
I2C_sendStopCondition(base);
}
}
I2C_clearInterruptStatus(base,(I2C_INT_TXFF | I2C_INT_RXFF));
}
I2C_Params->numofSixteenByte = numofSixteenByte;
I2C_Params->remainingBytes = remainingBytes;
}
}
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2cLib_FIFO_master_slave_interrupt.h
+106
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@@ -0,0 +1,106 @@
//#############################################################################
//
// FILE: i2cLib_FIFO_master_slave_interrupt.h
//
// TITLE: C28x-I2C Library header file for FIFO interrupts
//
//#############################################################################
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#ifndef I2CLIB_FIFO_INTERRUPT_H
#define I2CLIB_FIFO_INTERRUPT_H
#include "device.h"
//
// Error messages for read and write functions
//
#define ERROR_BUS_BUSY 0x1000
#define ERROR_NACK_RECEIVED 0x2000
#define ERROR_ARBITRATION_LOST 0x3000
#define ERROR_STOP_NOT_READY 0x5555
#define SUCCESS 0x0000
#define MAX_BUFFER_SIZE 64
#define I2C_FIFO_LEVEL 16
#define MAX_7_BIT_ADDRESS 127U
#define MAX_10_BIT_ADDRESS 1023U
#define MAX_I2C_IN_NETWORK 20
//
// Typedefs
//
struct I2CHandle
{
uint32_t base;
uint16_t SlaveAddr; // Slave address tied to the message.
uint32_t *pControlAddr;
uint16_t NumOfAddrBytes;
uint16_t *pTX_MsgBuffer; // Pointer to TX message buffer
uint16_t *pRX_MsgBuffer; // Pointer to RX message buffer
uint16_t NumOfDataBytes; // Number of valid bytes in message.
struct I2CHandle *currentHandlePtr;
uint16_t numofSixteenByte;
uint16_t remainingBytes;
};
uint16_t I2C_TransmitSlaveAddress_ControlBytes(struct I2CHandle *I2C_Params);
uint16_t I2CBusScan(uint32_t base, uint16_t *pAvailableI2C_slaves);
uint16_t I2C_MasterTransmitter(struct I2CHandle *I2C_Params);
uint16_t I2C_MasterReceiver(struct I2CHandle *I2C_Params);
uint16_t I2C_SlaveTransmitter(struct I2CHandle *I2C_Params);
uint16_t I2C_SlaveReceiver(struct I2CHandle *I2C_Params);
uint16_t checkBusStatus(uint32_t base);
uint16_t handleNACK(uint32_t base);
extern void handleI2C_ErrorCondition(struct I2CHandle *I2C_Params);
extern void Write_Read_TX_RX_FIFO(struct I2CHandle *I2C_Params);
extern uint16_t status;
extern struct I2CHandle *currentSlavePtr;
#endif
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2cLib_FIFO_polling.c
+375
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@@ -0,0 +1,375 @@
//#############################################################################
//
// FILE: i2cLib_FIFO_polling.c
//
// TITLE: C28x-I2C Library source file for FIFO using polling
//
//#############################################################################
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#include "i2cLib_FIFO_polling.h"
uint16_t I2CBusScan(uint32_t base, uint16_t *pAvailableI2C_slaves)
{
uint16_t probeSlaveAddress, i;
//Disable interrupts on Stop condition, NACK and arbitration lost condition
I2C_disableInterrupt(base, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
i = 0;
for(probeSlaveAddress=1;probeSlaveAddress<=MAX_10_BIT_ADDRESS;probeSlaveAddress++)
{
//Check I2C bus status
status = checkBusStatus(base);
if(status)
{
ESTOP0;
return status;
}
I2C_setConfig(base, (I2C_MASTER_SEND_MODE | I2C_REPEAT_MODE));
//Enable 10-bit addressing if probeSlaveAddress is greater than 127U
if(probeSlaveAddress > MAX_7_BIT_ADDRESS)
{
//10-bit addressing
I2C_setAddressMode(base, I2C_ADDR_MODE_10BITS);
}
// Setup slave address
I2C_setSlaveAddress(base, probeSlaveAddress);
I2C_sendStartCondition(base);
//Wait for the slave address to be transmitted
while(!(I2C_getStatus(base) & I2C_STS_REG_ACCESS_RDY));
//Generate STOP condition
I2C_sendStopCondition(base);
//Wait for the I2CMDR.STP to be cleared
while(I2C_getStopConditionStatus(base));
//Wait for the Bus busy bit to be cleared
while(I2C_isBusBusy(base));
uint16_t I2CStatus = I2C_getStatus(base);
//If Slave address is acknowledged, store slave address
//in pAvailableI2C_slaves
if(!(I2CStatus & I2C_STS_NO_ACK))
{
pAvailableI2C_slaves[i++] = probeSlaveAddress;
}
//Clear NACK bit in I2CSTR
I2C_clearStatus(base,I2C_STS_NO_ACK|I2C_STS_ARB_LOST|I2C_STS_REG_ACCESS_RDY|I2C_STS_STOP_CONDITION);
}
I2C_setConfig(base, (I2C_MASTER_SEND_MODE));
I2C_setAddressMode(base, I2C_ADDR_MODE_7BITS); //7-bit addressing
I2C_enableInterrupt(base, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
return SUCCESS;
}
uint16_t I2C_TransmitSlaveAddress_ControlBytes(struct I2CHandle *I2C_Params)
{
uint16_t status, attemptCount=1;
uint32_t base = I2C_Params->base;
status = 1;
while(status & (attemptCount <= I2C_Params->NumOfAttempts))
{
status = checkBusStatus(base);
attemptCount++;
DEVICE_DELAY_US(I2C_Params->Delay_us);
}
if(status)
{
return status;
}
I2C_setConfig(base, (I2C_MASTER_SEND_MODE|I2C_REPEAT_MODE));
if((I2C_Params->SlaveAddr) > MAX_7_BIT_ADDRESS)
{
//10-bit addressing
I2C_setAddressMode(base, I2C_ADDR_MODE_10BITS);
}
// Setup slave address
I2C_setSlaveAddress(base, I2C_Params->SlaveAddr);
int16_t i;
uint32_t temp = *(I2C_Params->pControlAddr);
for(i=I2C_Params->NumOfAddrBytes-1;i>=0;i--)
{
I2C_putData(base, (temp >> (i*8U)) & 0xFF);
}
I2C_sendStartCondition(base);
DEVICE_DELAY_US(150U);
status = handleNACK(base);
if(status)
{
if(attemptCount <= (I2C_Params->NumOfAttempts))
{
attemptCount++;
I2C_setConfig(base, (I2C_MASTER_SEND_MODE));
I2C_sendStartCondition(base);
DEVICE_DELAY_US(I2C_Params->Delay_us);
}
else
{
return status;
}
}
attemptCount = 1;
while(I2C_getTxFIFOStatus(base) && attemptCount <= 9 * (I2C_Params->NumOfAddrBytes + 2U))
{
status = handleNACK(base);
if(status)
{
return status;
}
attemptCount++;
DEVICE_DELAY_US(I2C_Params->Delay_us);
}
return SUCCESS;
}
uint16_t I2C_MasterTransmitter(struct I2CHandle *I2C_Params)
{
uint16_t status, attemptCount;
uint32_t base = I2C_Params->base;
I2C_disableFIFO(base);
I2C_enableFIFO(base);
status = I2C_TransmitSlaveAddress_ControlBytes(I2C_Params);
if(status)
{
return status;
}
I2C_setDataCount(base, (I2C_Params->NumOfAddrBytes + I2C_Params->NumOfDataBytes));
I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, I2C_FIFO_RXFULL);
I2C_enableInterrupt(base, I2C_INT_TXFF);
uint16_t numofSixteenByte = (I2C_Params->NumOfDataBytes) / I2C_FIFO_LEVEL;
uint16_t remainingBytes = (I2C_Params->NumOfDataBytes) % I2C_FIFO_LEVEL;
uint16_t i,count = 0,buff_pos=0;
while(count < numofSixteenByte)
{
for(i=1;i<=I2C_FIFO_LEVEL;i++)
{
I2C_putData(base, I2C_Params->pTX_MsgBuffer[buff_pos++]);
}
attemptCount = 1;
while(I2C_getTxFIFOStatus(base) && attemptCount <= 9 * (I2C_FIFO_LEVEL + 2U))
{
status = handleNACK(base);
if(status)
{
return status;
}
attemptCount++;
DEVICE_DELAY_US(I2C_Params->Delay_us);
}
count++;
}
for (i=0; i < remainingBytes; i++)
{
I2C_putData(base, I2C_Params->pTX_MsgBuffer[buff_pos++]);
}
attemptCount = 1;
while(I2C_getTxFIFOStatus(base) && attemptCount <= 9 * (remainingBytes + 2U))
{
status = handleNACK(base);
if(status)
{
return status;
}
attemptCount++;
DEVICE_DELAY_US(I2C_Params->Delay_us);
}
I2C_sendStopCondition(base);
attemptCount = 1;
while(I2C_getStopConditionStatus(base) && attemptCount <= 3U)
{
DEVICE_DELAY_US(I2C_Params->Delay_us);
attemptCount++;
}
return SUCCESS;
}
uint16_t I2C_MasterReceiver(struct I2CHandle *I2C_Params)
{
uint16_t status;
uint16_t attemptCount;
uint32_t base = I2C_Params->base;
I2C_disableFIFO(base);
I2C_enableFIFO(base);
status = I2C_TransmitSlaveAddress_ControlBytes(I2C_Params);
if(status)
{
return status;
}
uint16_t numofSixteenByte = (I2C_Params->NumOfDataBytes) / I2C_FIFO_LEVEL;
uint16_t remainingBytes = (I2C_Params->NumOfDataBytes) % I2C_FIFO_LEVEL;
I2C_setConfig(base, (I2C_MASTER_RECEIVE_MODE|I2C_REPEAT_MODE));
I2C_sendStartCondition(base);
uint16_t i,count = 0,buff_pos=0;
while(count < numofSixteenByte)
{
status = handleNACK(base);
if(status)
{
return status;
}
count++;
attemptCount = 1;
while(!(I2C_getRxFIFOStatus(base) == I2C_FIFO_RXFULL) && attemptCount <= 9 * (I2C_FIFO_RXFULL + 2U))
{
DEVICE_DELAY_US(I2C_Params->Delay_us);
attemptCount++;
}
for(i=0; i<I2C_FIFO_LEVEL; i++)
{
I2C_Params->pRX_MsgBuffer[buff_pos++] = I2C_getData(base);
}
}
attemptCount = 1;
while(!(I2C_getRxFIFOStatus(base) == remainingBytes) && attemptCount <= 9 * (remainingBytes + 2U))
{
DEVICE_DELAY_US(I2C_Params->Delay_us);
attemptCount++;
}
I2C_sendStopCondition(base);
for(i=0; i<remainingBytes; i++)
{
I2C_Params->pRX_MsgBuffer[buff_pos++] = I2C_getData(base);
}
status = handleNACK(base);
if(status)
{
return status;
}
I2C_disableFIFO(base);
attemptCount = 1;
while(I2C_getStopConditionStatus(base) && attemptCount <= 3U);
{
DEVICE_DELAY_US(I2C_Params->Delay_us);
attemptCount++;
}
return SUCCESS;
}
uint16_t checkBusStatus(uint32_t base)
{
if(I2C_isBusBusy(base))
{
return ERROR_BUS_BUSY;
}
if(I2C_getStopConditionStatus(base))
{
return ERROR_STOP_NOT_READY;
}
return SUCCESS;
}
uint16_t handleNACK(uint32_t base)
{
if(I2C_getStatus(base) & I2C_STS_NO_ACK)
{
I2C_clearStatus(base, I2C_STS_NO_ACK);
I2C_sendStopCondition(base);
return ERROR_NACK_RECEIVED;
}
return SUCCESS;
}
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2cLib_FIFO_polling.h
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//#############################################################################
//
// FILE: i2cLib_FIFO_polling.h
//
// TITLE: C28x-I2C Library header file for FIFO using polling
//
//#############################################################################
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#ifndef I2CLIB_FIFO_POLLING_H
#define I2CLIB_FIFO_POLLING_H
#include "device.h"
//
// Error messages for read and write functions
//
#define ERROR_BUS_BUSY 0x1000
#define ERROR_NACK_RECEIVED 0x2000
#define ERROR_ARBITRATION_LOST 0x3000
#define ERROR_STOP_NOT_READY 0x5555
#define SUCCESS 0x0000
#define MAX_BUFFER_SIZE 64
#define I2C_FIFO_LEVEL 16
#define MAX_7_BIT_ADDRESS 127U
#define MAX_10_BIT_ADDRESS 1023U
//
// Typedefs
//
struct I2CHandle
{
uint32_t base;
uint16_t SlaveAddr; // Slave address tied to the message.
uint32_t *pControlAddr;
uint16_t NumOfAddrBytes;
uint16_t *pTX_MsgBuffer; // Pointer to TX message buffer
uint16_t *pRX_MsgBuffer; // Pointer to RX message buffer
uint16_t NumOfDataBytes; // Number of valid bytes in message.
struct I2CHandle *currentHandlePtr;
uint16_t numofSixteenByte;
uint16_t remainingBytes;
uint16_t WriteCycleTime_in_us; // Slave write cycle time. Depends on slave.
// Please check slave device datasheet
uint16_t NumOfAttempts; // Number of attempts to make before reporting
// slave not ready (NACK condition)
uint16_t Delay_us; // Delay time in microsecs (us)
};
uint16_t I2C_TransmitSlaveAddress_ControlBytes(struct I2CHandle *I2C_Params);
uint16_t I2CBusScan(uint32_t base, uint16_t *pAvailableI2C_slaves);
uint16_t I2C_MasterTransmitter(struct I2CHandle *I2C_Params);
uint16_t I2C_MasterReceiver(struct I2CHandle *I2C_Params);
uint16_t I2C_SlaveTransmitter(struct I2CHandle *I2C_Params);
uint16_t I2C_SlaveReceiver(struct I2CHandle *I2C_Params);
uint16_t checkBusStatus(uint32_t base);
uint16_t handleNACK(uint32_t base);
extern void handleI2C_ErrorCondition(struct I2CHandle *I2C_Params);
extern void Write_Read_TX_RX_FIFO(struct I2CHandle *I2C_Params);
extern uint16_t TX_MsgBuffer[MAX_BUFFER_SIZE];
extern uint16_t RX_MsgBuffer[MAX_BUFFER_SIZE];
extern uint16_t status;
extern struct I2CHandle *currentSlavePtr;
#endif
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2c_ex1_loopback.c
+249
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//#############################################################################
//
// FILE: i2c_ex1_loopback.c
//
// TITLE: I2C Digital Loopback with FIFO Interrupts
//
//! \addtogroup driver_example_list
//! <h1>I2C Digital Loopback with FIFO Interrupts</h1>
//!
//! This program uses the internal loopback test mode of the I2C module. Both
//! the TX and RX I2C FIFOs and their interrupts are used. The pinmux and I2C
//! initialization is done through the sysconfig file.
//!
//! A stream of data is sent and then compared to the received stream.
//! The sent data looks like this: \n
//! 0000 0001 \n
//! 0001 0002 \n
//! 0002 0003 \n
//! .... \n
//! 00FE 00FF \n
//! 00FF 0000 \n
//! etc.. \n
//! This pattern is repeated forever.
//!
//! \b External \b Connections \n
//! - None
//!
//! \b Watch \b Variables \n
//! - \b sData - Data to send
//! - \b rData - Received data
//! - \b rDataPoint - Used to keep track of the last position in the receive
//! stream for error checking
//!
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
#include "board.h"
//
// Defines
//
#define SLAVE_ADDRESS 0x3C
//
// Globals
//
uint16_t sData[2]; // Send data buffer
uint16_t rData[2]; // Receive data buffer
uint16_t rDataPoint = 0; // To keep track of where we are in the
// data stream to check received data
//
// Function Prototypes
//
__interrupt void i2cFIFOISR(void);
//
// Main
//
void main(void)
{
uint16_t i;
//
// Initialize device clock and peripherals
//
Device_init();
//
// Disable pin locks and enable internal pullups.
//
Device_initGPIO();
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// Board initialization
//
Board_init();
//
// For loopback mode only
//
I2C_setOwnSlaveAddress(myI2C0_BASE, SLAVE_ADDRESS);
//
// Interrupts that are used in this example are re-mapped to ISR functions
// found within this file.
//
Interrupt_register(INT_I2CA_FIFO, &i2cFIFOISR);
//
// Initialize the data buffers
//
for(i = 0; i < 2; i++)
{
sData[i] = i;
rData[i]= 0;
}
//
// Enable interrupts required for this example
//
Interrupt_enable(INT_I2CA_FIFO);
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;
//
// Loop forever. Suspend or place breakpoints to observe the buffers.
//
while(1)
{
// A FIFO interrupt will be generated for each Tx and Rx based
// on the Interrupt levels configured.
// The ISR will handle pushing/pulling data to/from the TX and
// RX FIFOs resp.
}
}
//
// I2C A Transmit & Receive FIFO ISR.
//
__interrupt void i2cFIFOISR(void)
{
uint16_t i;
//
// If receive FIFO interrupt flag is set, read data
//
if((I2C_getInterruptStatus(myI2C0_BASE) & I2C_INT_RXFF) != 0)
{
for(i = 0; i < 2; i++)
{
rData[i] = I2C_getData(myI2C0_BASE);
}
//
// Check received data
//
for(i = 0; i < 2; i++)
{
if(rData[i] != ((rDataPoint + i) & 0xFF))
{
//
// Something went wrong. rData doesn't contain expected data.
//
ESTOP0;
}
}
rDataPoint = (rDataPoint + 1) & 0xFF;
//
// Clear interrupt flag
//
I2C_clearInterruptStatus(myI2C0_BASE, I2C_INT_RXFF);
}
//
// If transmit FIFO interrupt flag is set, put data in the buffer
//
else if((I2C_getInterruptStatus(myI2C0_BASE) & I2C_INT_TXFF) != 0)
{
for(i = 0; i < 2; i++)
{
I2C_putData(myI2C0_BASE, sData[i]);
}
//
// Send the start condition
//
I2C_sendStartCondition(myI2C0_BASE);
//
// Increment data for next cycle
//
for(i = 0; i < 2; i++)
{
sData[i] = (sData[i] + 1) & 0xFF;
}
//
// Clear interrupt flag
//
I2C_clearInterruptStatus(myI2C0_BASE, I2C_INT_TXFF);
}
//
// Issue ACK
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
}
//
// End of File
//
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2c_ex1_loopback.syscfg
+20
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/**
* Import the modules used in this configuration.
*/
const i2c = scripting.addModule("/driverlib/i2c.js", {}, false);
const i2c1 = i2c.addInstance();
/**
* Write custom configuration values to the imported modules.
*/
i2c1.$name = "myI2C0";
i2c1.bitCount = "I2C_BITCOUNT_8";
i2c1.dataCount = 2;
i2c1.slaveAddress = 0x3C;
i2c1.loopback = true;
i2c1.enabledFIFOInterrupts = ["I2C_INT_RXFF","I2C_INT_TXFF"];
i2c1.txFifo = "I2C_FIFO_TX2";
i2c1.rxFifo = "I2C_FIFO_RX2";
i2c1.duty = "I2C_DUTYCYCLE_50";
i2c1.i2c.$name = "MyI2C1";
i2c1.i2c.$assign = "I2CA";
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2c_ex2_eeprom.c
+615
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//#############################################################################
//
// FILE: i2c_ex2_eeprom.c
//
// TITLE: I2C EEPROM
//
//! \addtogroup driver_example_list
//! <h1>I2C EEPROM</h1>
//!
//! This program will write 1-14 words to EEPROM and read them back. The data
//! written and the EEPROM address written to are contained in the message
//! structure, i2cMsgOut. The data read back will be contained in the message
//! structure i2cMsgIn.
//!
//! \b External \b Connections \n
//! - Connect external I2C EEPROM at address 0x50
//! - Connect GPIO32/SDAA to external EEPROM SDA (serial data) pin
//! - Connect GPIO33/SCLA to external EEPROM SCL (serial clock) pin
//!
//! \b Watch \b Variables \n
//! - \b i2cMsgOut - Message containing data to write to EEPROM
//! - \b i2cMsgIn - Message containing data read from EEPROM
//!
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
//
// Defines
//
#define SLAVE_ADDRESS 0x50
#define EEPROM_HIGH_ADDR 0x00
#define EEPROM_LOW_ADDR 0x30
#define NUM_BYTES 8
#define MAX_BUFFER_SIZE 14 // Max is currently 14 because of
// 2 address bytes and the 16-byte
// FIFO
//
// I2C message states for I2CMsg struct
//
#define MSG_STATUS_INACTIVE 0x0000 // Message not in use, do not send
#define MSG_STATUS_SEND_WITHSTOP 0x0010 // Send message with stop bit
#define MSG_STATUS_WRITE_BUSY 0x0011 // Message sent, wait for stop
#define MSG_STATUS_SEND_NOSTOP 0x0020 // Send message without stop bit
#define MSG_STATUS_SEND_NOSTOP_BUSY 0x0021 // Message sent, wait for ARDY
#define MSG_STATUS_RESTART 0x0022 // Ready to become master-receiver
#define MSG_STATUS_READ_BUSY 0x0023 // Wait for stop before reading data
//
// Error messages for read and write functions
//
#define ERROR_BUS_BUSY 0x1000
#define ERROR_STOP_NOT_READY 0x5555
#define SUCCESS 0x0000
//
// Typedefs
//
struct I2CMsg
{
uint16_t msgStatus; // Word stating what state msg is in.
// See MSG_STATUS_* defines above.
uint16_t slaveAddr; // Slave address tied to the message.
uint16_t numBytes; // Number of valid bytes in message.
uint16_t memoryHighAddr; // EEPROM address of data associated
// with message (high byte).
uint16_t memoryLowAddr; // EEPROM address of data associated
// with message (low byte).
uint16_t msgBuffer[MAX_BUFFER_SIZE]; // Array holding message data.
};
//
// Globals
//
struct I2CMsg i2cMsgOut = {MSG_STATUS_SEND_WITHSTOP,
SLAVE_ADDRESS,
NUM_BYTES,
EEPROM_HIGH_ADDR,
EEPROM_LOW_ADDR,
0x01, // Message bytes
0x23,
0x45,
0x67,
0x89,
0xAB,
0xCD,
0xEF};
struct I2CMsg i2cMsgIn = {MSG_STATUS_SEND_NOSTOP,
SLAVE_ADDRESS,
NUM_BYTES,
EEPROM_HIGH_ADDR,
EEPROM_LOW_ADDR};
struct I2CMsg *currentMsgPtr; // Used in interrupt
uint16_t passCount = 0;
uint16_t failCount = 0;
//
// Function Prototypes
//
void initI2C(void);
uint16_t readData(struct I2CMsg *msg);
uint16_t writeData(struct I2CMsg *msg);
void fail(void);
void pass(void);
__interrupt void i2cAISR(void);
//
// Main
//
void main(void)
{
uint16_t error;
uint16_t i;
//
// Initialize device clock and peripherals
//
Device_init();
//
// Disable pin locks and enable internal pullups.
//
Device_initGPIO();
//
// Initialize GPIOs 32 and 33 for use as SDA A and SCL A respectively
//
GPIO_setPinConfig(GPIO_32_SDAA);
GPIO_setPadConfig(32, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(32, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_33_SCLA);
GPIO_setPadConfig(33, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(33, GPIO_QUAL_ASYNC);
//
// Initialize PIE and clear PIE registers. Disable CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// Interrupts that are used in this example are re-mapped to ISR functions
// found within this file.
//
Interrupt_register(INT_I2CA, &i2cAISR);
//
// Set I2C use, initializing it for FIFO mode
//
initI2C();
//
// Clear incoming message buffer
//
for (i = 0; i < MAX_BUFFER_SIZE; i++)
{
i2cMsgIn.msgBuffer[i] = 0x0000;
}
//
// Set message pointer used in interrupt to point to outgoing message
//
currentMsgPtr = &i2cMsgOut;
//
// Enable interrupts required for this example
//
Interrupt_enable(INT_I2CA);
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;
//
// Loop indefinitely
//
while(1)
{
//
// **** Write data to EEPROM section ****
//
// Check the outgoing message to see if it should be sent. In this
// example it is initialized to send with a stop bit.
//
if(i2cMsgOut.msgStatus == MSG_STATUS_SEND_WITHSTOP)
{
//
// Send the data to the EEPROM
//
error = writeData(&i2cMsgOut);
//
// If communication is correctly initiated, set msg status to busy
// and update currentMsgPtr for the interrupt service routine.
// Otherwise, do nothing and try again next loop. Once message is
// initiated, the I2C interrupts will handle the rest. See the
// function i2cAISR().
//
if(error == SUCCESS)
{
currentMsgPtr = &i2cMsgOut;
i2cMsgOut.msgStatus = MSG_STATUS_WRITE_BUSY;
}
}
//
// **** Read data from EEPROM section ****
//
// Check outgoing message status. Bypass read section if status is
// not inactive.
//
if (i2cMsgOut.msgStatus == MSG_STATUS_INACTIVE)
{
//
// Check incoming message status
//
if(i2cMsgIn.msgStatus == MSG_STATUS_SEND_NOSTOP)
{
//
// Send EEPROM address setup
//
while(readData(&i2cMsgIn) != SUCCESS)
{
//
// Maybe setup an attempt counter to break an infinite
// while loop. The EEPROM will send back a NACK while it is
// performing a write operation. Even though the write
// is complete at this point, the EEPROM could still be
// busy programming the data. Therefore, multiple
// attempts are necessary.
//
}
//
// Update current message pointer and message status
//
currentMsgPtr = &i2cMsgIn;
i2cMsgIn.msgStatus = MSG_STATUS_SEND_NOSTOP_BUSY;
}
//
// Once message has progressed past setting up the internal address
// of the EEPROM, send a restart to read the data bytes from the
// EEPROM. Complete the communique with a stop bit. msgStatus is
// updated in the interrupt service routine.
//
else if(i2cMsgIn.msgStatus == MSG_STATUS_RESTART)
{
//
// Read data portion
//
while(readData(&i2cMsgIn) != SUCCESS)
{
//
// Maybe setup an attempt counter to break an infinite
// while loop.
//
}
//
// Update current message pointer and message status
//
currentMsgPtr = &i2cMsgIn;
i2cMsgIn.msgStatus = MSG_STATUS_READ_BUSY;
}
}
}
}
//
// initI2C - Function to configure I2C A in FIFO mode.
//
void
initI2C()
{
//
// Must put I2C into reset before configuring it
//
I2C_disableModule(I2CA_BASE);
//
// I2C configuration. Use a 400kHz I2CCLK with a 33% duty cycle.
//
I2C_initMaster(I2CA_BASE, DEVICE_SYSCLK_FREQ, 400000, I2C_DUTYCYCLE_33);
I2C_setBitCount(I2CA_BASE, I2C_BITCOUNT_8);
I2C_setSlaveAddress(I2CA_BASE, SLAVE_ADDRESS);
I2C_setEmulationMode(I2CA_BASE, I2C_EMULATION_FREE_RUN);
//
// Enable stop condition and register-access-ready interrupts
//
I2C_enableInterrupt(I2CA_BASE, I2C_INT_STOP_CONDITION |
I2C_INT_REG_ACCESS_RDY);
//
// FIFO configuration
//
I2C_enableFIFO(I2CA_BASE);
I2C_clearInterruptStatus(I2CA_BASE, I2C_INT_RXFF | I2C_INT_TXFF);
//
// Configuration complete. Enable the module.
//
I2C_enableModule(I2CA_BASE);
}
//
// writeData - Function to send the data that is to be written to the EEPROM
//
uint16_t
writeData(struct I2CMsg *msg)
{
uint16_t i;
//
// Wait until the STP bit is cleared from any previous master
// communication. Clearing of this bit by the module is delayed until after
// the SCD bit is set. If this bit is not checked prior to initiating a new
// message, the I2C could get confused.
//
if(I2C_getStopConditionStatus(I2CA_BASE))
{
return(ERROR_STOP_NOT_READY);
}
//
// Setup slave address
//
I2C_setSlaveAddress(I2CA_BASE, SLAVE_ADDRESS);
//
// Check if bus busy
//
if(I2C_isBusBusy(I2CA_BASE))
{
return(ERROR_BUS_BUSY);
}
//
// Setup number of bytes to send msgBuffer and address
//
I2C_setDataCount(I2CA_BASE, (msg->numBytes + 2));
//
// Setup data to send
//
I2C_putData(I2CA_BASE, msg->memoryHighAddr);
I2C_putData(I2CA_BASE, msg->memoryLowAddr);
for (i = 0; i < msg->numBytes; i++)
{
I2C_putData(I2CA_BASE, msg->msgBuffer[i]);
}
//
// Send start as master transmitter
//
I2C_setConfig(I2CA_BASE, I2C_MASTER_SEND_MODE);
I2C_sendStartCondition(I2CA_BASE);
I2C_sendStopCondition(I2CA_BASE);
return(SUCCESS);
}
//
// readData - Function to prepare for the data that is to be read from the EEPROM
//
uint16_t
readData(struct I2CMsg *msg)
{
//
// Wait until the STP bit is cleared from any previous master
// communication. Clearing of this bit by the module is delayed until after
// the SCD bit is set. If this bit is not checked prior to initiating a new
// message, the I2C could get confused.
//
if(I2C_getStopConditionStatus(I2CA_BASE))
{
return(ERROR_STOP_NOT_READY);
}
//
// Setup slave address
//
I2C_setSlaveAddress(I2CA_BASE, SLAVE_ADDRESS);
//
// If we are in the the address setup phase, send the address without a
// stop condition.
//
if(msg->msgStatus == MSG_STATUS_SEND_NOSTOP)
{
//
// Check if bus busy
//
if(I2C_isBusBusy(I2CA_BASE))
{
return(ERROR_BUS_BUSY);
}
//
// Send data to setup EEPROM address
//
I2C_setDataCount(I2CA_BASE, 2);
I2C_putData(I2CA_BASE, msg->memoryHighAddr);
I2C_putData(I2CA_BASE, msg->memoryLowAddr);
I2C_setConfig(I2CA_BASE, I2C_MASTER_SEND_MODE);
I2C_sendStartCondition(I2CA_BASE);
}
else if(msg->msgStatus == MSG_STATUS_RESTART)
{
//
// Address setup phase has completed. Now setup how many bytes expected
// and send restart as master-receiver.
//
I2C_setDataCount(I2CA_BASE, (msg->numBytes));
I2C_setConfig(I2CA_BASE, I2C_MASTER_RECEIVE_MODE);
I2C_sendStartCondition(I2CA_BASE);
I2C_sendStopCondition(I2CA_BASE);
}
return(SUCCESS);
}
//
// i2cAISR - I2C A ISR (non-FIFO)
//
__interrupt void
i2cAISR(void)
{
I2C_InterruptSource intSource;
uint16_t i;
//
// Read interrupt source
//
intSource = I2C_getInterruptSource(I2CA_BASE);
//
// Interrupt source = stop condition detected
//
if(intSource == I2C_INTSRC_STOP_CONDITION)
{
//
// If completed message was writing data, reset msg to inactive state
//
if(currentMsgPtr->msgStatus == MSG_STATUS_WRITE_BUSY)
{
currentMsgPtr->msgStatus = MSG_STATUS_INACTIVE;
}
else
{
//
// If a message receives a NACK during the address setup portion of
// the EEPROM read, the code further below included in the register
// access ready interrupt source code will generate a stop
// condition. After the stop condition is received (here), set the
// message status to try again. User may want to limit the number
// of retries before generating an error.
//
if(currentMsgPtr->msgStatus == MSG_STATUS_SEND_NOSTOP_BUSY)
{
currentMsgPtr->msgStatus = MSG_STATUS_SEND_NOSTOP;
}
//
// If completed message was reading EEPROM data, reset message to
// inactive state and read data from FIFO.
//
else if(currentMsgPtr->msgStatus == MSG_STATUS_READ_BUSY)
{
currentMsgPtr->msgStatus = MSG_STATUS_INACTIVE;
for(i=0; i < NUM_BYTES; i++)
{
currentMsgPtr->msgBuffer[i] = I2C_getData(I2CA_BASE);
}
//
// Check received data
//
for(i=0; i < NUM_BYTES; i++)
{
if(i2cMsgIn.msgBuffer[i] == i2cMsgOut.msgBuffer[i])
{
passCount++;
}
else
{
failCount++;
}
}
if(passCount == NUM_BYTES)
{
pass();
}
else
{
fail();
}
}
}
}
//
// Interrupt source = Register Access Ready
//
// This interrupt is used to determine when the EEPROM address setup
// portion of the read data communication is complete. Since no stop bit
// is commanded, this flag tells us when the message has been sent
// instead of the SCD flag.
//
else if(intSource == I2C_INTSRC_REG_ACCESS_RDY)
{
//
// If a NACK is received, clear the NACK bit and command a stop.
// Otherwise, move on to the read data portion of the communication.
//
if((I2C_getStatus(I2CA_BASE) & I2C_STS_NO_ACK) != 0)
{
I2C_sendStopCondition(I2CA_BASE);
I2C_clearStatus(I2CA_BASE, I2C_STS_NO_ACK);
}
else if(currentMsgPtr->msgStatus == MSG_STATUS_SEND_NOSTOP_BUSY)
{
currentMsgPtr->msgStatus = MSG_STATUS_RESTART;
}
}
else
{
//
// Generate some error from invalid interrupt source
//
asm(" ESTOP0");
}
//
// Issue ACK to enable future group 8 interrupts
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
}
//
// pass - Function to be called if data written matches data read
//
void
pass(void)
{
asm(" ESTOP0");
for(;;);
}
//
// fail - Function to be called if data written does NOT match data read
//
void fail(void)
{
asm(" ESTOP0");
for(;;);
}
//
// End of File
//
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2c_ex3_external_loopback.c
+353
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@@ -0,0 +1,353 @@
//#############################################################################
//
// FILE: i2c_ex3_external_loopback.c
//
// TITLE: I2C Digital External Loopback with FIFO Interrupts
//
//! \addtogroup driver_example_list
//! <h1>I2C Digital External Loopback with FIFO Interrupts</h1>
//!
//! This program uses the I2CA and I2CB modules for achieving external
//! loopback. The I2CA TX FIFO and the I2CB RX FIFO are used along with
//! their interrupts.
//!
//! A stream of data is sent on I2CA and then compared to the received stream
//! on I2CB.
//! The sent data looks like this: \n
//! 0000 0001 \n
//! 0001 0002 \n
//! 0002 0003 \n
//! .... \n
//! 00FE 00FF \n
//! 00FF 0000 \n
//! etc.. \n
//! This pattern is repeated forever.
//!
//! \b External \b Connections \n
//! - Connect SCLA(GPIO33) to SCLB (GPIO35) and SDAA(GPIO32) to SDAB (GPIO34)
//! - Connect GPIO31 to an LED used to depict data transfers.
//!
//! \b Watch \b Variables \n
//! - \b sData - Data to send
//! - \b rData - Received data
//! - \b rDataPoint - Used to keep track of the last position in the receive
//! stream for error checking
//!
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
//
// Defines
//
#define SLAVE_ADDRESS 0x3C
//
// Globals
//
uint16_t sData[2] = {0,0}; // Send data buffer
uint16_t rData[2] = {0,0}; // Receive data buffer
uint16_t rDataPoint = 0; // To keep track of where we are in the
// data stream to check received data
//
// Function Prototypes
//
void initI2CFIFO(void);
__interrupt void i2cFIFOISR(void);
//
// Main
//
void main(void)
{
uint16_t i;
//
// Initialize device clock and peripherals
//
Device_init();
//
// Disable pin locks and enable internal pullups.
//
Device_initGPIO();
//
// Initialize GPIOs 32 and 33 for use as SDA A and SCL A respectively
//
GPIO_setPinConfig(GPIO_32_SDAA);
GPIO_setPadConfig(32, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(32, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_33_SCLA);
GPIO_setPadConfig(33, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(33, GPIO_QUAL_ASYNC);
//
// Initialize GPIOs 34 and 35 for use as SDA B and SCL B respectively
//
GPIO_setPinConfig(GPIO_34_SDAB);
GPIO_setPadConfig(34, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(34, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_35_SCLB);
GPIO_setPadConfig(35, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(35, GPIO_QUAL_ASYNC);
GPIO_setPadConfig(DEVICE_GPIO_PIN_LED1, GPIO_PIN_TYPE_STD);
GPIO_setDirectionMode(DEVICE_GPIO_PIN_LED1, GPIO_DIR_MODE_OUT);
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// Interrupts that are used in this example are re-mapped to ISR functions
// found within this file.
//
Interrupt_register(INT_I2CA_FIFO, &i2cFIFOISR);
Interrupt_register(INT_I2CB_FIFO, &i2cFIFOISR);
//
// Set I2C use, initializing it for FIFO mode
//
initI2CFIFO();
//
// Initialize the data buffers
//
for(i = 0; i < 2; i++)
{
sData[i] = i;
rData[i]= 0;
}
//
// Enable interrupts required for this example
//
Interrupt_enable(INT_I2CA_FIFO);
Interrupt_enable(INT_I2CB_FIFO);
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;
//
// Loop forever. Suspend or place breakpoints to observe the buffers.
//
while(1)
{
// A FIFO interrupt will be generated for each Tx and Rx based
// on the Interrupt levels configured.
// The ISR will handle pushing/pulling data to/from the TX and
// RX FIFOs resp.
}
}
//
// Function to configure I2C A in FIFO mode.
//
void initI2CFIFO()
{
//
// Must put I2C into reset before configuring it
//
I2C_disableModule(I2CA_BASE);
I2C_disableModule(I2CB_BASE);
//
// I2C configuration. Use a 400kHz I2CCLK with a 50% duty cycle.
//
I2C_initMaster(I2CA_BASE, DEVICE_SYSCLK_FREQ, 400000, I2C_DUTYCYCLE_50);
I2C_setConfig(I2CA_BASE, I2C_MASTER_SEND_MODE);
I2C_setDataCount(I2CA_BASE, 2);
I2C_setBitCount(I2CA_BASE, I2C_BITCOUNT_8);
//
// I2C slave configuration
//
I2C_setConfig(I2CB_BASE, I2C_SLAVE_RECEIVE_MODE);
I2C_setDataCount(I2CB_BASE, 2);
I2C_setBitCount(I2CB_BASE, I2C_BITCOUNT_8);
//
// Configure for external loopback
//
I2C_setSlaveAddress(I2CA_BASE, SLAVE_ADDRESS);
I2C_setOwnSlaveAddress(I2CB_BASE, SLAVE_ADDRESS);
I2C_setEmulationMode(I2CA_BASE, I2C_EMULATION_FREE_RUN);
I2C_setEmulationMode(I2CB_BASE, I2C_EMULATION_FREE_RUN);
//
// FIFO and interrupt configuration
//
I2C_enableFIFO(I2CA_BASE);
I2C_clearInterruptStatus(I2CA_BASE, I2C_INT_TXFF);
//
// Transmit FIFO interrupt levels are set to generate an interrupt
// when the 16 byte TX fifo contains 2 or lesser bytes of data.
//
I2C_setFIFOInterruptLevel(I2CA_BASE, I2C_FIFO_TX2, I2C_FIFO_RX2);
I2C_enableInterrupt(I2CA_BASE, I2C_INT_TXFF | I2C_INT_STOP_CONDITION);
I2C_enableFIFO(I2CB_BASE);
I2C_clearInterruptStatus(I2CB_BASE, I2C_INT_RXFF);
//
// Receive FIFO interrupt levels are set to generate an interrupt
// when the 16 byte RX fifo contains 2 or greater bytes of data.
//
I2C_setFIFOInterruptLevel(I2CB_BASE, I2C_FIFO_TX2, I2C_FIFO_RX2);
I2C_enableInterrupt(I2CB_BASE, I2C_INT_RXFF | I2C_INT_STOP_CONDITION);
//
// Configuration complete. Enable the module.
//
I2C_enableModule(I2CA_BASE);
I2C_enableModule(I2CB_BASE);
}
//
// I2C TX and Receive FIFO ISR
//
__interrupt void i2cFIFOISR(void)
{
uint16_t i;
//
// If receive FIFO interrupt flag is set, read data
//
if((I2C_getInterruptStatus(I2CB_BASE) & I2C_INT_RXFF) != 0)
{
for(i = 0; i < 2; i++)
{
rData[i] = I2C_getData(I2CB_BASE);
}
//
// Check received data
//
for(i = 0; i < 2; i++)
{
if(rData[i] != ((rDataPoint + i) & 0xFF))
{
//
// Something went wrong. rData doesn't contain expected data.
//
Example_Fail = 1;
ESTOP0;
}
}
//
// Used to keep track of the last position in the receive
// stream for error checking
//
rDataPoint = (rDataPoint + 1) & 0xFF;
//
// Turn On an LED to depict data transfer
//
GPIO_writePin(DEVICE_GPIO_PIN_LED1, 0);
//
// Clear interrupt flag
//
I2C_clearInterruptStatus(I2CB_BASE, I2C_INT_RXFF);
Example_PassCount++;
}
//
// If transmit FIFO interrupt flag is set, put data in the buffer
//
else if((I2C_getInterruptStatus(I2CA_BASE) & I2C_INT_TXFF) != 0)
{
for(i = 0; i < 2; i++)
{
I2C_putData(I2CA_BASE, sData[i]);
}
//
// Send the start condition
//
I2C_sendStartCondition(I2CA_BASE);
//
// Increment data for next cycle
//
for(i = 0; i < 2; i++)
{
sData[i] = (sData[i] + 1) & 0xFF;
}
//
// Clear interrupt flag
//
I2C_clearInterruptStatus(I2CA_BASE, I2C_INT_TXFF);
//
// Turn Off an LED to depict data transfer
//
GPIO_writePin(DEVICE_GPIO_PIN_LED1, 1);
}
//
// Issue ACK
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
}
//
// End of File
//
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2c_ex4_eeprom_polling.c
+350
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@@ -0,0 +1,350 @@
//#############################################################################
//
// FILE: i2c_ex4_eeprom_polling.c
//
// TITLE: I2C EEPROM Write / Read using polling
//
//! \addtogroup driver_example_list
//! <h1>I2C EEPROM</h1>
//!
//! This program will shows how to perform different EEPROM write and read
//! commands using I2C polling method
//! EEPROM used for this example is AT24C256
//!
//! \b External \b Connections \n
//! - Connect external I2C EEPROM at address 0x50
//! --------------------------------
//! Signal | I2CA | EEPROM
//! --------------------------------
//! SCL | GPIO105 | SCL
//! SDA | GPIO104 | SDA
//! Make sure to connect GND pins if EEPROM and C2000 device are in different board.
//! --------------------------------
//! //Example 1: EEPROM Byte Write
//! //Example 2: EEPROM Byte Read
//! //Example 3: EEPROM word (16-bit) write
//! //Example 4: EEPROM word (16-bit) read
//! //Example 5: EEPROM Page write
//! //Example 6: EEPROM word Paged read
//!
//! \b Watch \b Variables \n
//! - \b TX_MsgBuffer - Message buffer which stores the data to be transmitted
//! - \b RX_MsgBuffer - Message buffer which stores the data to be received
//!
//!
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
#include "i2cLib_FIFO_polling.h"
//
// Globals
//
struct I2CHandle EEPROM;
struct I2CHandle *currentMsgPtr; // Used in interrupt
//! --------------------------------
//! Signal | I2CA | EEPROM
//! --------------------------------
//! SCL | GPIO105 | SCL
//! SDA | GPIO104 | SDA
//! --------------------------------
uint16_t passCount = 0;
uint16_t failCount = 0;
uint16_t AvailableI2C_slaves[20];
uint16_t TX_MsgBuffer[MAX_BUFFER_SIZE];
uint16_t RX_MsgBuffer[MAX_BUFFER_SIZE];
uint32_t ControlAddr;
uint16_t status;
void fail(void);
void pass(void);
void I2C_GPIO_init(void);
void I2Cinit(void);
void verifyEEPROMRead(void);
//
// Main
//
void main(void)
{
//
// Initialize device clock and peripherals
//
Device_init();
//
// Disable pin locks and enable internal pullups.
//
Device_initGPIO();
//
// Initialize I2C pins
//
I2C_GPIO_init();
//
// Initialize PIE and clear PIE registers. Disable CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
I2Cinit();
//I2Cs connected to I2CA will be found in AvailableI2C_slaves buffer
//after you run I2CBusScan function.
uint16_t *pAvailableI2C_slaves = AvailableI2C_slaves;
status = I2CBusScan(I2CA_BASE, pAvailableI2C_slaves);
uint16_t i;
for(i=0;i<MAX_BUFFER_SIZE;i++)
{
TX_MsgBuffer[i] = 0;
RX_MsgBuffer[i] = 0;
}
EEPROM.SlaveAddr = 0x50;
EEPROM.base = I2CA_BASE;
EEPROM.pControlAddr = &ControlAddr;
EEPROM.NumOfAddrBytes = 2;
EEPROM.pTX_MsgBuffer = TX_MsgBuffer;
EEPROM.pRX_MsgBuffer = RX_MsgBuffer;
EEPROM.NumOfAttempts = 5;
EEPROM.Delay_us = 10;
EEPROM.WriteCycleTime_in_us = 6000; //10ms for EEPROM this code was tested
//Example 1: EEPROM Byte Write
//Write 11 to EEPROM address 0x0
ControlAddr = 0;
EEPROM.NumOfDataBytes = 1;
TX_MsgBuffer[0] = 11;
status = I2C_MasterTransmitter(&EEPROM);
//Wait for EEPROM write cycle time
//This delay is not mandatory. User can run their application code instead.
//It is however important to wait for EEPROM write cycle time before you initiate
//another read / write transaction
DEVICE_DELAY_US(EEPROM.WriteCycleTime_in_us);
//Example 2: EEPROM Byte Read
//Make sure 11 is written to EEPROM address 0x0
ControlAddr = 0;
EEPROM.pControlAddr = &ControlAddr;
EEPROM.NumOfDataBytes = 1;
status = I2C_MasterReceiver(&EEPROM);
while(I2C_getStatus(EEPROM.base) & I2C_STS_BUS_BUSY);
verifyEEPROMRead();
//Example 3: EEPROM word (16-bit) write
//EEPROM address 0x1 = 22 & 0x2 = 33
ControlAddr = 1; //EEPROM address to write
EEPROM.NumOfDataBytes = 2;
TX_MsgBuffer[0] = 0x11;
TX_MsgBuffer[1] = 0x22;
EEPROM.pTX_MsgBuffer = TX_MsgBuffer;
status = I2C_MasterTransmitter(&EEPROM);
//Wait for EEPROM write cycle time
//This delay is not mandatory. User can run their application code instead.
//It is however important to wait for EEPROM write cycle time before you initiate
//another read / write transaction
DEVICE_DELAY_US(EEPROM.WriteCycleTime_in_us);
//Example 4: EEPROM word (16-bit) read
//Make sure EEPROM address 1 has 0x11 and 2 has 0x22
ControlAddr = 1;
EEPROM.pControlAddr = &ControlAddr;
EEPROM.pRX_MsgBuffer = RX_MsgBuffer;
EEPROM.NumOfDataBytes = 2;
status = I2C_MasterReceiver(&EEPROM);
verifyEEPROMRead();
//Example 5: EEPROM Page write
//Program address = data pattern from address 64
for(i=0;i<MAX_BUFFER_SIZE;i++)
{
TX_MsgBuffer[i] = i+64;
}
ControlAddr = 64; //EEPROM address to write
EEPROM.NumOfDataBytes = MAX_BUFFER_SIZE;
EEPROM.pTX_MsgBuffer = TX_MsgBuffer;
status = I2C_MasterTransmitter(&EEPROM);
//Wait for EEPROM write cycle time
//This delay is not mandatory. User can run their application code instead.
//It is however important to wait for EEPROM write cycle time before you initiate
//another read / write transaction
DEVICE_DELAY_US(EEPROM.WriteCycleTime_in_us);
//Example 6: EEPROM word Paged read
ControlAddr = 64;
EEPROM.pControlAddr = &ControlAddr;
EEPROM.pRX_MsgBuffer = RX_MsgBuffer;
EEPROM.NumOfDataBytes = MAX_BUFFER_SIZE;
status = I2C_MasterReceiver(&EEPROM);
verifyEEPROMRead();
if(status)
{
fail();
}
else
{
pass();
}
if(status)
{
fail();
}
else
{
pass();
}
}
//
// pass - Function to be called if data written matches data read
//
void
pass(void)
{
asm(" ESTOP0");
for(;;);
}
//
// fail - Function to be called if data written does NOT match data read
//
void fail(void)
{
asm(" ESTOP0");
for(;;);
}
void verifyEEPROMRead(void)
{
uint16_t i;
while(I2C_getStatus(EEPROM.base) & I2C_STS_BUS_BUSY);
for(i=0;i<EEPROM.NumOfDataBytes;i++)
{
if(RX_MsgBuffer[i] != TX_MsgBuffer[i])
{
//Transmitted data doesn't match received data
//Fail condition. PC shouldn't reach here
ESTOP0;
fail();
}
}
}
void I2C_GPIO_init(void)
{
// I2CA pins (SDAA / SCLA)
GPIO_setDirectionMode(DEVICE_GPIO_PIN_SDAA, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(DEVICE_GPIO_PIN_SDAA, GPIO_PIN_TYPE_PULLUP);
GPIO_setMasterCore(DEVICE_GPIO_PIN_SDAA, GPIO_CORE_CPU1);
GPIO_setQualificationMode(DEVICE_GPIO_PIN_SDAA, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(DEVICE_GPIO_PIN_SCLA, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(DEVICE_GPIO_PIN_SCLA, GPIO_PIN_TYPE_PULLUP);
GPIO_setMasterCore(DEVICE_GPIO_PIN_SCLA, GPIO_CORE_CPU1);
GPIO_setQualificationMode(DEVICE_GPIO_PIN_SCLA, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(DEVICE_GPIO_CFG_SDAA);
GPIO_setPinConfig(DEVICE_GPIO_CFG_SCLA);
}
void I2Cinit(void)
{
//myI2CA initialization
I2C_disableModule(I2CA_BASE);
I2C_initMaster(I2CA_BASE, DEVICE_SYSCLK_FREQ, 100000, I2C_DUTYCYCLE_50);
I2C_setConfig(I2CA_BASE, I2C_MASTER_SEND_MODE);
I2C_setSlaveAddress(I2CA_BASE, 80);
I2C_setOwnSlaveAddress(I2CA_BASE, 96); //I2CA address
I2C_disableLoopback(I2CA_BASE);
I2C_setBitCount(I2CA_BASE, I2C_BITCOUNT_8);
I2C_setDataCount(I2CA_BASE, 2);
I2C_setAddressMode(I2CA_BASE, I2C_ADDR_MODE_7BITS);
I2C_enableFIFO(I2CA_BASE);
I2C_clearInterruptStatus(I2CA_BASE, I2C_INT_ARB_LOST | I2C_INT_NO_ACK);
I2C_setFIFOInterruptLevel(I2CA_BASE, I2C_FIFO_TXEMPTY, I2C_FIFO_RX2);
I2C_enableInterrupt(I2CA_BASE, I2C_INT_ADDR_SLAVE | I2C_INT_ARB_LOST | I2C_INT_NO_ACK | I2C_INT_STOP_CONDITION);
I2C_setEmulationMode(I2CA_BASE, I2C_EMULATION_FREE_RUN);
I2C_enableModule(I2CA_BASE);
}
//
// End of File
//
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2c_ex5_master_slave_interrupt.c
+719
View File
@@ -0,0 +1,719 @@
//#############################################################################
//
// FILE: i2c_ex5_master_slave_interrupt.c
//
// TITLE: I2C master slave communication using FIFO interrupts
//
//! \addtogroup driver_example_list
//! <h1>I2C master slave communication using FIFO interrupts</h1>
//!
//! This program shows how to use I2CA and I2CB modules in both master and slave
//! configuration This example uses I2C FIFO interrupts and doesn't using polling
//!
//! Example1: I2CA as Master Transmitter and I2CB working Slave Receiver
//! Example2: I2CA as Master Receiver and I2CB working Slave Transmitter
//! Example3: I2CB as Master Transmitter and I2CA working Slave Receiver
//! Example4: I2CB as Master Receiver and I2CA working Slave Transmitter
//!
//! \b External \b Connections on launchpad should be made as shown below \n
//! --------------------------------
//! Signal | I2CA | I2CB
//! --------------------------------
//! SCL | GPIO105 | GPIO41
//! SDA | GPIO104 | GPIO40
//! --------------------------------
//!
//! \b Watch \b Variables in memory window\n
//! - \b I2CA_TXdata
//! - \b I2CA_RXdata
//! - \b I2CB_TXdata
//! - \b I2CB_RXdata
//! stream for error checking
//!
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
#include "i2cLib_FIFO_master_slave_interrupt.h"
//
// Defines
//
#define I2CA_ADDRESS 0x30
#define I2CB_ADDRESS 0x40
//! --------------------------------
//! Signal | I2CA | I2CB
//! --------------------------------
//! SCL | GPIO105 | GPIO41
//! SDA | GPIO104 | GPIO40
//! --------------------------------
//
// Globals
//
uint16_t status = 0;
struct I2CHandle I2CA;
struct I2CHandle I2CB;
//
// Function Prototypes
//
__interrupt void i2cAISR(void);
__interrupt void i2cAFIFOISR(void);
__interrupt void i2cBISR(void);
__interrupt void i2cBFIFOISR(void);
uint16_t AvailableI2C_slaves[MAX_I2C_IN_NETWORK];
uint16_t I2CA_TXdata[MAX_BUFFER_SIZE];
uint16_t I2CB_TXdata[MAX_BUFFER_SIZE];
uint16_t I2CA_RXdata[MAX_BUFFER_SIZE];
uint16_t I2CB_RXdata[MAX_BUFFER_SIZE];
uint32_t I2CA_ControlAddr;
uint32_t I2CB_ControlAddr;
uint16_t status;
void I2C_GPIO_init(void);
void I2Cinit(void);
//
// Main
//
void main(void)
{
//
// Initialize device clock and peripherals
//
Device_init();
//
// Disable pin locks and enable internal pullups.
//
Device_initGPIO();
//
// Board initialization
//
I2C_GPIO_init();
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
I2Cinit();
I2C_setOwnSlaveAddress(I2CA_BASE, I2CA_ADDRESS);
I2C_setOwnSlaveAddress(I2CB_BASE, I2CB_ADDRESS);
//I2Cs connected to I2CA will be found in AvailableI2C_slaves buffer
//after you run I2CBusScan function.
//When you run I2C BusScan you need to disable I2C interrupts and clear
//the flag set during I2CBusScan
uint16_t i;
for(i=0;i<MAX_I2C_IN_NETWORK;i++)
{
AvailableI2C_slaves[i] = 0;
}
I2C_disableInterrupt(I2CA_BASE, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
I2C_disableInterrupt(I2CB_BASE, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
uint16_t *pAvailableI2C_slaves = AvailableI2C_slaves;
status = I2CBusScan(I2CA_BASE, pAvailableI2C_slaves);
I2C_clearStatus(I2CA_BASE,I2C_STS_NO_ACK|I2C_STS_ARB_LOST|I2C_STS_REG_ACCESS_RDY|I2C_STS_STOP_CONDITION);
I2C_clearStatus(I2CB_BASE,I2C_STS_NO_ACK|I2C_STS_ARB_LOST|I2C_STS_REG_ACCESS_RDY|I2C_STS_STOP_CONDITION);
ESTOP0;
I2C_disableInterrupt(I2CA_BASE, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
I2C_disableInterrupt(I2CB_BASE, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
status = I2CBusScan(I2CB_BASE, pAvailableI2C_slaves);
I2C_clearStatus(I2CA_BASE,I2C_STS_NO_ACK|I2C_STS_ARB_LOST|I2C_STS_REG_ACCESS_RDY|I2C_STS_STOP_CONDITION);
I2C_clearStatus(I2CB_BASE,I2C_STS_NO_ACK|I2C_STS_ARB_LOST|I2C_STS_REG_ACCESS_RDY|I2C_STS_STOP_CONDITION);
I2C_enableInterrupt(I2CA_BASE, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
I2C_enableInterrupt(I2CB_BASE, (I2C_INT_ADDR_SLAVE|I2C_INT_STOP_CONDITION | I2C_INT_ARB_LOST | I2C_INT_NO_ACK));
//
// Set I2C use, initializing it for FIFO mode
//
Interrupt_register(INT_I2CA, &i2cAISR);
Interrupt_enable(INT_I2CA);
Interrupt_register(INT_I2CB, &i2cBISR);
Interrupt_enable(INT_I2CB);
Interrupt_register(INT_I2CA_FIFO, &i2cAFIFOISR);
Interrupt_enable(INT_I2CA_FIFO);
Interrupt_register(INT_I2CB_FIFO, &i2cBFIFOISR);
Interrupt_enable(INT_I2CB_FIFO);
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;
for(i=0;i<MAX_BUFFER_SIZE;i++)
{
I2CA_TXdata[i] = i+1;
I2CA_RXdata[i] = 0;
I2CB_TXdata[i] = 0;
I2CB_RXdata[i] = 0;
}
I2CA.currentHandlePtr = &I2CA;
I2CA.base = I2CA_BASE;
I2CA.SlaveAddr = I2CB_ADDRESS;
I2CA.pControlAddr = &I2CA_ControlAddr;
I2CA.NumOfAddrBytes = 4;
I2CA.pTX_MsgBuffer = I2CA_TXdata;
I2CA.pRX_MsgBuffer = I2CA_RXdata;
I2CA.NumOfDataBytes = 64;
I2CB.currentHandlePtr = &I2CB;
I2CB.base = I2CB_BASE;
I2CB.SlaveAddr = I2CB_ADDRESS;
I2CB.NumOfAddrBytes = 4;
I2CB.pControlAddr = (uint32_t *)0;
I2CB.pTX_MsgBuffer = (uint16_t *)0;
I2CB.pRX_MsgBuffer = (uint16_t *)0;
// Example1: I2CA as Master Transmitter and I2CB working Slave Receiver //
// I2CA = Master Transmitter
// I2CB = Slave Receiver
// I2CA generates
// 1) START condition
// 2) I2CB address (Slave address) + Write mode
// 3) Transmit start address of I2CB_RXdata
// 4) Transmit contents of I2CA_TXdata array
// 5) I2CB received data is stored in I2CB_RXdata array
// 6) Contents of I2CA_TXdata and I2CB_RXdata should match
//Slave pControlAddr should be 0 proper operation.
//Slave pControlAddr is transmitted by I2CA master
I2CB.pControlAddr = (uint32_t *)0;
I2CA_ControlAddr = (uint32_t)I2CB_RXdata;
status = I2C_MasterTransmitter(&I2CA);
// Wait for I2CA to be complete transmission of data
while(I2C_getStatus(I2CA.base) & I2C_STS_BUS_BUSY);
for(i=0;i<I2CA.NumOfDataBytes;i++)
{
if((I2CB_RXdata[i] != I2CA_TXdata[i]) || (status != 0))
{
//Fail condition. Code shouldn't reach here
//Check status (global variable) for I2C errors
ESTOP0;
}
}
//If code reached below ESTOP0, I2CA as master transmitter and
//I2CB as slave receiver worked correctly
//Observe the contents of I2CA_TXdata and I2CB_RXdata in memory browser
// Example1: I2CA as Master Transmitter and I2CB working Slave Receiver - PASSED//
ESTOP0;
// Example2: I2CA as Master Receiver and I2CB working Slave Transmitter //
// I2CA = Master Receiver
// I2CB = Slave Transmitter
// I2CA generates
// 1) START condition
// 2) I2CB address (Slave address) + Write mode
// 3) Transmit start address of I2CB_TXdata
// 4) I2CA generates repeated START condition + Read mode
// 4) I2CB (slave) transmits contents of I2CB_TXdata
// 5) I2CA received data is stored in I2CA_RXdata array
// 6) Contents of I2CB_TXdata and I2CA_RXdata should match
for(i=0;i<MAX_BUFFER_SIZE;i++)
{
I2CA_TXdata[i] = 0;
I2CA_RXdata[i] = 0;
I2CB_TXdata[i] = i+1;
I2CB_RXdata[i] = 0;
}
//Slave pControlAddr should be 0 proper operation.
//Slave pControlAddr is transmitted by I2CA master
I2CB.pControlAddr = (uint32_t *)0;
I2CA_ControlAddr = (uint32_t)I2CB_TXdata;
status = I2C_MasterReceiver(&I2CA);
// Wait for I2CA to be complete transmission of data
while(I2C_getStatus(I2CA.base) & I2C_STS_BUS_BUSY);
for(i=0;i<I2CA.NumOfDataBytes;i++)
{
if((I2CB_TXdata[i] != I2CA_RXdata[i]) || (status != 0))
{
//Fail condition. Code shouldn't reach here
//Check status (global variable) for I2C errors
ESTOP0;
}
}
//If code reached below ESTOP0, then I2CA as master receiver and
//I2CB as slave transmitter worked correctly
//Observe the contents of I2CB_TXdata and I2CA_RXdata in memory browser
// Example2: I2CA as Master Receiver and I2CB working Slave Transmitter - PASSED//
ESTOP0;
// Example3: I2CB as Master Transmitter and I2CA working Slave Receiver //
// I2CB = Master Transmitter
// I2CA = Slave Receiver
// I2CB generates
// 1) START condition
// 2) I2CA address (Slave address) + Write mode
// 3) Transmit start address of I2CA_RXdata
// 4) Transmit contents of I2CB_TXdata array
// 5) I2CA received data is stored in I2CA_RXdata array
// 6) Contents of I2CB_TXdata and I2CA_RXdata should match
for(i=0;i<MAX_BUFFER_SIZE;i++)
{
I2CA_TXdata[i] = 0;
I2CA_RXdata[i] = 0;
I2CB_TXdata[i] = i+1;
I2CB_RXdata[i] = 0;
}
I2CB.currentHandlePtr = &I2CB;
I2CB.base = I2CB_BASE;
I2CB.SlaveAddr = I2CA_ADDRESS;
I2CB.pControlAddr = &I2CB_ControlAddr;
I2CB.NumOfAddrBytes = 4;
I2CB.pTX_MsgBuffer = I2CB_TXdata;
I2CB.pRX_MsgBuffer = I2CB_RXdata;
I2CB.NumOfDataBytes = 64;
I2CA.currentHandlePtr = &I2CA;
I2CA.base = I2CA_BASE;
I2CA.SlaveAddr = I2CB_ADDRESS;
I2CA.NumOfAddrBytes = 4;
I2CA.pControlAddr = (uint32_t *)0;
I2CA.pTX_MsgBuffer = (uint16_t *)0;
I2CA.pRX_MsgBuffer = (uint16_t *)0;
//Slave pControlAddr should be 0 proper operation.
//Slave pControlAddr is transmitted by I2CB master
I2CA.pControlAddr = (uint32_t *)0;
I2CB_ControlAddr = (uint32_t)I2CA_RXdata;
status = I2C_MasterTransmitter(&I2CB);
// Wait for I2CB to be complete transmission of data
while(I2C_getStatus(I2CB.base) & I2C_STS_BUS_BUSY);
for(i=0;i<I2CB.NumOfDataBytes;i++)
{
if((I2CB_TXdata[i] != I2CA_RXdata[i]) || (status != 0))
{
//Fail condition. Code shouldn't reach here
//Check status (global variable) for I2C errors
ESTOP0;
}
}
//If code reached below ESTOP0, I2CB as master transmitter and
//I2CA as slave receiver worked correctly
//Observe the contents of I2CB_TXdata and I2CA_RXdata in memory browser
// Example3: I2CB as Master Transmitter and I2CA working Slave Receiver - PASSED//
ESTOP0;
// Example4: I2CB as Master Receiver and I2CA working Slave Transmitter //
// I2CB = Master Receiver
// I2CA = Slave Transmitter
// I2CB generates
// 1) START condition
// 2) I2CA address (Slave address) + Write mode
// 3) Transmit start address of I2CA_TXdata
// 4) I2CB generates repeated START condition + Read mode
// 4) I2CA (slave) transmits contents of I2CA_TXdata
// 5) I2CB received data is stored in I2CB_RXdata array
// 6) Contents of I2CA_TXdata and I2CB_RXdata should match
for(i=0;i<MAX_BUFFER_SIZE;i++)
{
I2CA_TXdata[i] = i+1;
I2CA_RXdata[i] = 0;
I2CB_TXdata[i] = 0;
I2CB_RXdata[i] = 0;
}
//Slave pControlAddr should be 0 proper operation.
//Slave pControlAddr is transmitted by I2CA master
I2CA.pControlAddr = (uint32_t *)0;
I2CB_ControlAddr = (uint32_t)I2CA_TXdata;
status = I2C_MasterReceiver(&I2CB);
// Wait for I2CA to be complete transmission of data
while(I2C_getStatus(I2CB.base) & I2C_STS_BUS_BUSY);
for(i=0;i<I2CB.NumOfDataBytes;i++)
{
if((I2CA_TXdata[i] != I2CB_RXdata[i]) || (status != 0))
{
//Fail condition. Code shouldn't reach here
//Check status (global variable) for I2C errors
ESTOP0;
}
}
//If code reached below ESTOP0, I2CB as Master Receiver and
//I2CA as Slave Transmitter worked correctly
//Observe the contents of I2CA_TXdata and I2CB_RXdata in memory browser
// Example4: I2CB as Master Receiver and I2CA working Slave Transmitter - PASSED//
ESTOP0;
//
// Loop forever. Suspend or place breakpoints to observe the buffers.
//
while(1)
{
// A FIFO interrupt will be generated for each Tx and Rx based
// on the Interrupt levels configured.
// The ISR will handle pushing/pulling data to/from the TX and
// RX FIFOs resp.
}
}
//
// pass condition
//
void
pass(void)
{
asm(" ESTOP0");
for(;;);
}
//
// fail condition
//
void fail(void)
{
asm(" ESTOP0");
for(;;);
}
//
// I2CA ISR
//
__interrupt void i2cAISR(void)
{
uint16_t MasterSlave = I2C_getStatus(I2CA.base) & I2C_STS_ADDR_SLAVE;
if(MasterSlave)
{
//I2CA working as slave
//Disable I2CB FIFO interrupt to first trigger I2CA FIFO interrupt to read control address
I2C_disableInterrupt(I2CB.base, (I2C_INT_TXFF));
}
handleI2C_ErrorCondition(&I2CA);
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
}
//
// I2CA FIFO ISR
//
__interrupt void i2cAFIFOISR(void)
{
Write_Read_TX_RX_FIFO(&I2CA);
uint16_t MasterSlave = HWREGH(I2CA.base + I2C_O_MDR);
if(MasterSlave & I2C_MDR_MST)
{
//I2CA working in master configuration
if(MasterSlave & I2C_MDR_TRX)
{
//I2CA working as Master Transmitter
I2C_disableInterrupt(I2CA.base, (I2C_INT_TXFF));
}
else
{
//I2CA working as Master Receiver
I2C_enableInterrupt(I2CB.base, (I2C_INT_TXFF));
I2C_clearInterruptStatus(I2CB.base,(I2C_INT_TXFF));
}
}
else
{
//I2CA working in slave configuration
if(MasterSlave & I2C_MDR_TRX)
{
//I2CA = Slave Transmitter & I2CB = Master Receiver
//So, I2CB RXFIFO interrupt is enabled &
// I2CB TXFIFO interrupt is disabled
I2C_enableInterrupt(I2CB.base, (I2C_INT_RXFF));
I2C_disableInterrupt(I2CB.base, (I2C_INT_TXFF));
I2C_clearInterruptStatus(I2CB.base,(I2C_INT_RXFF));
I2C_disableInterrupt(I2CA.base, (I2C_INT_TXFF));
}
else
{
//I2CA working as slave receiver
if(HWREGH(I2CB.base + I2C_O_CNT) == I2CB.NumOfAddrBytes)
{
//Enable I2CB Register Access Ready interrupt to change
//to master receiver
I2C_enableInterrupt(I2CB.base, I2C_INT_REG_ACCESS_RDY);
if(I2CA.pTX_MsgBuffer == 0x0)
{
I2CA.pTX_MsgBuffer = (uint16_t *)((uint32_t)(I2CA.pControlAddr) & 0x00FFFFFF);
I2CA.pRX_MsgBuffer = (uint16_t *)0;
}
}
else
{
//Continue with I2CB master transmitter mode
I2C_enableInterrupt(I2CB.base, (I2C_INT_TXFF));
I2C_disableInterrupt(I2CB.base, (I2C_INT_RXFF));
I2C_clearInterruptStatus(I2CB.base,(I2C_INT_TXFF | I2C_INT_RXFF));
if(I2CA.pRX_MsgBuffer == 0x0)
{
I2CA.pRX_MsgBuffer = (uint16_t *)((uint32_t)(I2CA.pControlAddr) & 0x00FFFFFF);
I2CA.pTX_MsgBuffer = (uint16_t *)0;
}
}
}
}
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
}
//
// I2CB ISR
//
__interrupt void i2cBISR(void)
{
uint16_t MasterSlave = I2C_getStatus(I2CB.base) & I2C_STS_ADDR_SLAVE;
if(MasterSlave)
{
//I2CB working as slave
//Disable I2CA FIFO interrupt to first trigger I2CB FIFO interrupt to read control address
I2C_disableInterrupt(I2CA.base, (I2C_INT_TXFF));
}
handleI2C_ErrorCondition(&I2CB);
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
}
//
// I2CB FIFO ISR
//
__interrupt void i2cBFIFOISR(void)
{
Write_Read_TX_RX_FIFO(&I2CB);
uint16_t MasterSlave = HWREGH(I2CB.base + I2C_O_MDR);
if(MasterSlave & I2C_MDR_MST)
{
//I2CB working in master configuration
if(MasterSlave & I2C_MDR_TRX)
{
//I2CB working as Master Transmitter
I2C_disableInterrupt(I2CB.base, (I2C_INT_TXFF));
}
else
{
//I2CB working as Master Receiver
I2C_enableInterrupt(I2CA.base, (I2C_INT_TXFF));
I2C_clearInterruptStatus(I2CA.base,(I2C_INT_TXFF));
}
}
else
{
//I2CB working in slave configuration
if(MasterSlave & I2C_MDR_TRX)
{
//I2CA = Master Receiver & I2CB = Slave Transmitter
//So, I2CA RXFIFO interrupt is enabled &
// I2CA TXFIFO interrupt is disabled
I2C_enableInterrupt(I2CA.base, (I2C_INT_RXFF));
I2C_disableInterrupt(I2CA.base, (I2C_INT_TXFF));
I2C_clearInterruptStatus(I2CA.base,(I2C_INT_RXFF));
I2C_disableInterrupt(I2CB.base, (I2C_INT_TXFF));
}
else
{
//I2CB working as slave receiver
if(HWREGH(I2CA.base + I2C_O_CNT) == I2CA.NumOfAddrBytes)
{
//Enable I2CA Register Access Ready interrupt to change
//to master receiver
I2C_enableInterrupt(I2CA.base, I2C_INT_REG_ACCESS_RDY);
if(I2CB.pTX_MsgBuffer == 0x0)
{
I2CB.pTX_MsgBuffer = (uint16_t *)((uint32_t)(I2CB.pControlAddr) & 0x00FFFFFF);
I2CB.pRX_MsgBuffer = (uint16_t *)0;
}
}
else
{
//Continue with I2CA master transmitter mode
I2C_enableInterrupt(I2CA.base, (I2C_INT_TXFF));
I2C_disableInterrupt(I2CA.base, (I2C_INT_RXFF));
I2C_clearInterruptStatus(I2CA.base,(I2C_INT_TXFF | I2C_INT_RXFF));
if(I2CB.pRX_MsgBuffer == 0x0)
{
I2CB.pRX_MsgBuffer = (uint16_t *)((uint32_t)(I2CB.pControlAddr) & 0x00FFFFFF);
I2CB.pTX_MsgBuffer = (uint16_t *)0;
}
}
}
}
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
}
void I2C_GPIO_init(void)
{
// I2CA pins (SDAA / SCLA)
GPIO_setDirectionMode(DEVICE_GPIO_PIN_SDAA, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(DEVICE_GPIO_PIN_SDAA, GPIO_PIN_TYPE_PULLUP);
GPIO_setMasterCore(DEVICE_GPIO_PIN_SDAA, GPIO_CORE_CPU1);
GPIO_setQualificationMode(DEVICE_GPIO_PIN_SDAA, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(DEVICE_GPIO_PIN_SCLA, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(DEVICE_GPIO_PIN_SCLA, GPIO_PIN_TYPE_PULLUP);
GPIO_setMasterCore(DEVICE_GPIO_PIN_SCLA, GPIO_CORE_CPU1);
GPIO_setQualificationMode(DEVICE_GPIO_PIN_SCLA, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(DEVICE_GPIO_CFG_SDAA);
GPIO_setPinConfig(DEVICE_GPIO_CFG_SCLA);
// I2CB pins (SDAB / SCLB)
GPIO_setDirectionMode(DEVICE_GPIO_PIN_SDAB, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(DEVICE_GPIO_PIN_SDAB, GPIO_PIN_TYPE_PULLUP);
GPIO_setMasterCore(DEVICE_GPIO_PIN_SDAB, GPIO_CORE_CPU1);
GPIO_setQualificationMode(DEVICE_GPIO_PIN_SDAB, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(DEVICE_GPIO_PIN_SCLB, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(DEVICE_GPIO_PIN_SCLB, GPIO_PIN_TYPE_PULLUP);
GPIO_setMasterCore(DEVICE_GPIO_PIN_SCLB, GPIO_CORE_CPU1);
GPIO_setQualificationMode(DEVICE_GPIO_PIN_SCLB, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(DEVICE_GPIO_CFG_SDAB);
GPIO_setPinConfig(DEVICE_GPIO_CFG_SCLB);
}
void I2Cinit(void)
{
//I2CA initialization
I2C_disableModule(I2CA_BASE);
I2C_initMaster(I2CA_BASE, DEVICE_SYSCLK_FREQ, 100000, I2C_DUTYCYCLE_50);
I2C_setConfig(I2CA_BASE, I2C_MASTER_SEND_MODE);
I2C_setSlaveAddress(I2CA_BASE, 80);
I2C_disableLoopback(I2CA_BASE);
I2C_setBitCount(I2CA_BASE, I2C_BITCOUNT_8);
I2C_setDataCount(I2CA_BASE, 2);
I2C_setAddressMode(I2CA_BASE, I2C_ADDR_MODE_7BITS);
I2C_enableFIFO(I2CA_BASE);
I2C_clearInterruptStatus(I2CA_BASE, I2C_INT_ADDR_SLAVE | I2C_INT_ARB_LOST | I2C_INT_NO_ACK | I2C_INT_STOP_CONDITION);
I2C_setFIFOInterruptLevel(I2CA_BASE, I2C_FIFO_TXEMPTY, I2C_FIFO_RX16);
I2C_enableInterrupt(I2CA_BASE, I2C_INT_ADDR_SLAVE | I2C_INT_ARB_LOST | I2C_INT_NO_ACK | I2C_INT_STOP_CONDITION);
I2C_setEmulationMode(I2CA_BASE, I2C_EMULATION_FREE_RUN);
I2C_enableModule(I2CA_BASE);
//I2CB initialization
I2C_disableModule(I2CB_BASE);
I2C_initMaster(I2CB_BASE, DEVICE_SYSCLK_FREQ, 100000, I2C_DUTYCYCLE_50);
I2C_setConfig(I2CB_BASE, I2C_MASTER_SEND_MODE);
I2C_setSlaveAddress(I2CB_BASE, 80);
I2C_disableLoopback(I2CB_BASE);
I2C_setBitCount(I2CB_BASE, I2C_BITCOUNT_8);
I2C_setDataCount(I2CB_BASE, 2);
I2C_setAddressMode(I2CB_BASE, I2C_ADDR_MODE_7BITS);
I2C_enableFIFO(I2CB_BASE);
I2C_clearInterruptStatus(I2CB_BASE, I2C_INT_ADDR_SLAVE | I2C_INT_ARB_LOST | I2C_INT_NO_ACK | I2C_INT_STOP_CONDITION);
I2C_setFIFOInterruptLevel(I2CB_BASE, I2C_FIFO_TXEMPTY, I2C_FIFO_RX16);
I2C_enableInterrupt(I2CB_BASE, I2C_INT_ADDR_SLAVE | I2C_INT_ARB_LOST | I2C_INT_NO_ACK | I2C_INT_STOP_CONDITION);
I2C_setEmulationMode(I2CB_BASE, I2C_EMULATION_FREE_RUN);
I2C_enableModule(I2CB_BASE);
}
//
// End of File
//
C2000Ware/driverlib/f2837xd/examples/cpu1/i2c/i2c_ex6_eeprom_interrupt.c
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//#############################################################################
//
// FILE: i2c_ex6_eeprom_interrupt.c
//
// TITLE: I2C EEPROM Write / Read using interrupt
//
//! \addtogroup driver_example_list
//! <h1>I2C EEPROM</h1>
//!
//! This program will shows how to perform different EEPROM write and read commands using I2C interrupts
//! EEPROM used for this example is AT24C256
//!
//! \b External \b Connections \n
//! - Connect external I2C EEPROM at address 0x50
//! --------------------------------
//! Signal | I2CA | EEPROM
//! --------------------------------
//! SCL | GPIO105 | SCL
//! SDA | GPIO104 | SDA
//! Make sure to connect GND pins if EEPROM and C2000 device are in different board.
//! --------------------------------
//! //Example 1: EEPROM Byte Write
//! //Example 2: EEPROM Byte Read
//! //Example 3: EEPROM word (16-bit) write
//! //Example 4: EEPROM word (16-bit) read
//! //Example 5: EEPROM Page write
//! //Example 6: EEPROM word Paged read
//!
//! \b Watch \b Variables \n
//! - \b TX_MsgBuffer - Message buffer which stores the data to be transmitted
//! - \b RX_MsgBuffer - Message buffer which stores the data to be received
//!
//!
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
#include "i2cLib_FIFO_master_interrupt.h"
//
// Defines
//
#define EEPROM_SLAVE_ADDRESS 0x50
//! --------------------------------
//! Signal | I2CA | EEPROM
//! --------------------------------
//! SCL | GPIO105 | SCL
//! SDA | GPIO104 | SDA
//! --------------------------------
//
// Globals
//
struct I2CHandle EEPROM;
struct I2CHandle TempSensor;
struct I2CHandle *currentResponderPtr; // Used in interrupt
uint16_t passCount = 0;
uint16_t failCount = 0;
uint16_t AvailableI2C_slaves[20];
uint16_t TX_MsgBuffer[MAX_BUFFER_SIZE];
uint16_t RX_MsgBuffer[MAX_BUFFER_SIZE];
uint32_t ControlAddr;
uint16_t status=0;
//
// Function Prototypes
//
interrupt void i2cFIFO_isr(void);
interrupt void i2c_isr(void);
void fail(void);
void pass(void);
void initI2CFIFO(void);
void verifyEEPROMRead(void);
void I2C_GPIO_init(void);
void I2Cinit(void);
//
// Main
//
void main(void)
{
//
// Initialize device clock and peripherals
//
Device_init();
//
// Disable pin locks and enable internal pullups.
//
Device_initGPIO();
//
// Initialize I2C pins
//
I2C_GPIO_init();
//
// Initialize PIE and clear PIE registers. Disable CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
I2Cinit();
//
// Interrupts that are used in this example are re-mapped to ISR functions
// found within this file.
//
Interrupt_register(INT_I2CA_FIFO, &i2cFIFO_isr);
Interrupt_enable(INT_I2CA_FIFO);
Interrupt_register(INT_I2CA, &i2c_isr);
Interrupt_enable(INT_I2CA);
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;
//I2Cs connected to I2CA will be found in AvailableI2C_slaves buffer
//after you run I2CBusScan function.
uint16_t *pAvailableI2C_slaves = AvailableI2C_slaves;
status = I2CBusScan(I2CA_BASE, pAvailableI2C_slaves);
uint16_t i;
currentResponderPtr = &EEPROM;
EEPROM.currentHandlePtr = &EEPROM;
EEPROM.SlaveAddr = EEPROM_SLAVE_ADDRESS;
EEPROM.WriteCycleTime_in_us = 10000; //6ms for EEPROM this code was tested
EEPROM.base = I2CA_BASE;
EEPROM.pControlAddr = &ControlAddr;
EEPROM.NumOfAddrBytes = 2;
//Example 1: EEPROM Byte Write
//Write 11 to EEPROM address 0x0
ControlAddr = 0x0; //EEPROM address to write
EEPROM.NumOfDataBytes = 1;
TX_MsgBuffer[0] = 11;
EEPROM.pTX_MsgBuffer = TX_MsgBuffer;
status = I2C_MasterTransmitter(&EEPROM);
//Wait for EEPROM write cycle time
//This delay is not mandatory. User can run their application code instead.
//It is however important to wait for EEPROM write cycle time before you initiate
//another read / write transaction
DEVICE_DELAY_US(EEPROM.WriteCycleTime_in_us);
//Example 2: EEPROM Byte Read
//Make sure 11 is written to EEPROM address 0x0
ControlAddr = 0;
EEPROM.pControlAddr = &ControlAddr;
EEPROM.pRX_MsgBuffer = RX_MsgBuffer;
EEPROM.NumOfDataBytes = 1;
status = I2C_MasterReceiver(&EEPROM);
while(I2C_getStatus(EEPROM.base) & I2C_STS_BUS_BUSY);
verifyEEPROMRead();
//Example 3: EEPROM word (16-bit) write
//EEPROM address 0x1 = 22 & 0x2 = 33
ControlAddr = 1; //EEPROM address to write
EEPROM.NumOfDataBytes = 2;
TX_MsgBuffer[0] = 0x11;
TX_MsgBuffer[1] = 0x22;
EEPROM.pTX_MsgBuffer = TX_MsgBuffer;
status = I2C_MasterTransmitter(&EEPROM);
//Wait for EEPROM write cycle time
//This delay is not mandatory. User can run their application code instead.
//It is however important to wait for EEPROM write cycle time before you initiate
//another read / write transaction
DEVICE_DELAY_US(EEPROM.WriteCycleTime_in_us);
//Example 4: EEPROM word (16-bit) read
//Make sure EEPROM address 1 has 0x11 and 2 has 0x22
ControlAddr = 1;
EEPROM.pControlAddr = &ControlAddr;
EEPROM.pRX_MsgBuffer = RX_MsgBuffer;
EEPROM.NumOfDataBytes = 2;
status = I2C_MasterReceiver(&EEPROM);
verifyEEPROMRead();
//Example 5: EEPROM Page write
//Program address = data pattern from address 64
for(i=0;i<MAX_BUFFER_SIZE;i++)
{
TX_MsgBuffer[i] = i+64;
}
ControlAddr = 64; //EEPROM address to write
EEPROM.NumOfDataBytes = MAX_BUFFER_SIZE;
EEPROM.pTX_MsgBuffer = TX_MsgBuffer;
status = I2C_MasterTransmitter(&EEPROM);
//Wait for EEPROM write cycle time
//This delay is not mandatory. User can run their application code instead.
//It is however important to wait for EEPROM write cycle time before you initiate
//another read / write transaction
DEVICE_DELAY_US(EEPROM.WriteCycleTime_in_us);
//Example 6: EEPROM word Paged read
ControlAddr = 64;
EEPROM.pControlAddr = &ControlAddr;
EEPROM.pRX_MsgBuffer = RX_MsgBuffer;
EEPROM.NumOfDataBytes = MAX_BUFFER_SIZE;
status = I2C_MasterReceiver(&EEPROM);
verifyEEPROMRead();
if(status)
{
fail();
}
else
{
pass();
}
}
//
// pass - Function to be called if data written matches data read
//
void
pass(void)
{
asm(" ESTOP0");
for(;;);
}
//
// fail - Function to be called if data written does NOT match data read
//
void fail(void)
{
asm(" ESTOP0");
for(;;);
}
void verifyEEPROMRead(void)
{
uint16_t i;
while(I2C_getStatus(EEPROM.base) & I2C_STS_BUS_BUSY);
for(i=0;i<EEPROM.NumOfDataBytes;i++)
{
if(RX_MsgBuffer[i] != TX_MsgBuffer[i])
{
//Transmitted data doesn't match received data
//Fail condition. PC shouldn't reach here
ESTOP0;
fail();
}
}
}
interrupt void i2c_isr(void)
{
uint16_t MasterSlave = HWREGH(currentResponderPtr->base + I2C_O_MDR);
handleI2C_ErrorCondition(currentResponderPtr);
if(MasterSlave & I2C_MDR_MST)
{
I2C_enableInterrupt(currentResponderPtr->base, I2C_INT_RXFF);
I2C_clearInterruptStatus(currentResponderPtr->base,(I2C_INT_RXFF));
}
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
}
interrupt void i2cFIFO_isr(void)
{
Write_Read_TX_RX_FIFO(currentResponderPtr);
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
}
void I2C_GPIO_init(void)
{
// I2CA pins (SDAA / SCLA)
GPIO_setDirectionMode(DEVICE_GPIO_PIN_SDAA, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(DEVICE_GPIO_PIN_SDAA, GPIO_PIN_TYPE_PULLUP);
GPIO_setMasterCore(DEVICE_GPIO_PIN_SDAA, GPIO_CORE_CPU1);
GPIO_setQualificationMode(DEVICE_GPIO_PIN_SDAA, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(DEVICE_GPIO_PIN_SCLA, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(DEVICE_GPIO_PIN_SCLA, GPIO_PIN_TYPE_PULLUP);
GPIO_setMasterCore(DEVICE_GPIO_PIN_SCLA, GPIO_CORE_CPU1);
GPIO_setQualificationMode(DEVICE_GPIO_PIN_SCLA, GPIO_QUAL_ASYNC);
GPIO_setPinConfig(DEVICE_GPIO_CFG_SDAA);
GPIO_setPinConfig(DEVICE_GPIO_CFG_SCLA);
}
void I2Cinit(void)
{
//myI2CA initialization
I2C_disableModule(I2CA_BASE);
I2C_initMaster(I2CA_BASE, DEVICE_SYSCLK_FREQ, 100000, I2C_DUTYCYCLE_50);
I2C_setConfig(I2CA_BASE, I2C_MASTER_SEND_MODE);
I2C_setSlaveAddress(I2CA_BASE, 80);
I2C_setOwnSlaveAddress(I2CA_BASE, 96); //I2CA address
I2C_disableLoopback(I2CA_BASE);
I2C_setBitCount(I2CA_BASE, I2C_BITCOUNT_8);
I2C_setDataCount(I2CA_BASE, 2);
I2C_setAddressMode(I2CA_BASE, I2C_ADDR_MODE_7BITS);
I2C_enableFIFO(I2CA_BASE);
I2C_clearInterruptStatus(I2CA_BASE, I2C_INT_ARB_LOST | I2C_INT_NO_ACK);
I2C_setFIFOInterruptLevel(I2CA_BASE, I2C_FIFO_TXEMPTY, I2C_FIFO_RX2);
I2C_enableInterrupt(I2CA_BASE, I2C_INT_ADDR_SLAVE | I2C_INT_ARB_LOST | I2C_INT_NO_ACK | I2C_INT_STOP_CONDITION);
I2C_setEmulationMode(I2CA_BASE, I2C_EMULATION_FREE_RUN);
I2C_enableModule(I2CA_BASE);
}
//
// End of File
//