Update repo
This commit is contained in:
@@ -0,0 +1,67 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="memcfg_ex1_sysconfig_multi"
|
||||
configurations="
|
||||
FLASH,
|
||||
RAM,
|
||||
"
|
||||
device="TMS320F28377D"
|
||||
outputType="system"
|
||||
cgtVersion="20.2.1.LTS"
|
||||
>
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<file path="../system.xml" action="copy" openOnCreation="true"/>
|
||||
<configuration name="FLASH"
|
||||
></configuration>
|
||||
<configuration name="RAM"
|
||||
></configuration>
|
||||
</project>
|
||||
<project
|
||||
name="memcfg_ex1_sysconfig_cpu1"
|
||||
device="TMS320F28377D"
|
||||
cgtVersion="20.2.1.LTS"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json"
|
||||
>
|
||||
<configuration name="FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH --define=CPU1 -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x100" />
|
||||
<configuration name="RAM" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=CPU1 -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x100" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/F2837xD/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/F2837xD/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/F2837xD/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/F2837xD/common/targetConfigs/TMS320F28377D.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/F2837xD/common/source/F2837xD_CodeStartBranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../memcfg_ex1_sysconfig_cpu1.c" targetDirectory="" />
|
||||
<file action="copy" path="../memcfg_ex1_sysconfig_cpu1.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
<project
|
||||
name="memcfg_ex1_sysconfig_cpu2"
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||||
device="TMS320F28377D"
|
||||
cgtVersion="20.2.1.LTS"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json"
|
||||
>
|
||||
<configuration name="FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH --define=CPU2 -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x100" />
|
||||
<configuration name="RAM" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=CPU2 -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x100" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/F2837xD/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/F2837xD/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/F2837xD/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/F2837xD/common/targetConfigs/TMS320F28377D.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/F2837xD/common/source/F2837xD_CodeStartBranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../memcfg_ex1_sysconfig_cpu2.c" targetDirectory="" />
|
||||
<file action="copy" path="../memcfg_ex1_sysconfig_cpu2.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
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||||
@@ -0,0 +1,225 @@
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//#############################################################################
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||||
//
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||||
// FILE: memcfg_ex1_sysconfig_cpu1.c
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//
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// TITLE: SysConfig RAM Management Example
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||||
//
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||||
//! \addtogroup driver_dual_example_list
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||||
//! <h1> LED Blinky Example</h1>
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||||
//!
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||||
//! This example demonstrates how to blink a LED using CPU1 and blink another
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//! LED using CPU2 (led_ex1_blinky_cpu2.c).
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - None.
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - None.
|
||||
//!
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
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||||
#include "device.h"
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||||
#include "inc/hw_ipc.h"
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#include "board.h"
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//
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// Globals
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||||
//
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||||
uint16_t cpu1RArray[256]; // Mapped to GS0 of shared RAM owned by CPU2
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uint16_t cpu1RWArray[256]; // Mapped to GS1 of shared RAM owned by CPU1
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#pragma DATA_SECTION(cpu1RArray,"SHARERAMGS0");
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#pragma DATA_SECTION(cpu1RWArray,"SHARERAMGS1");
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||||
uint16_t error;
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||||
uint16_t multiplier;
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||||
uint16_t isrfuncLoadStart;
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extern uint16_t isrfuncLoadEnd;
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||||
uint16_t isrfuncRunStart;
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uint16_t isrfuncLoadSize;
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||||
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//
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// Function Prototypes
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||||
//
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||||
void initCPUTimer(uint32_t);
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void configCPUTimer(uint32_t, float, float);
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__interrupt void cpuTimer0ISR(void);
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#pragma CODE_SECTION(cpuTimer0ISR, "isrfunc")
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void readDataCPU1(void);
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void writeDataCPU1(void);
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//
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// Main
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//
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void main(void)
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||||
{
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uint16_t ipcFlag10 = 10U;
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//
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// Initialize device clock and peripherals
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//
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Device_init();
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||||
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//
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||||
// Initialize GPIO
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||||
//
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Device_initGPIO();
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//
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// Initialize SysConfig Settings
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||||
//
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Board_init();
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||||
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//
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||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
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//
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Interrupt_initModule();
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||||
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//
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||||
// Initialize the PIE vector table with pointers to the shell Interrupt
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||||
// Service Routines (ISR).
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||||
//
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Interrupt_initVectorTable();
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//
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// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
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//
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EINT;
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ERTM;
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error = 0;
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multiplier = 0;
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||||
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||||
writeDataCPU1();
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HWREG(IPC_BASE + IPC_O_SET) = 1UL << ipcFlag10;
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uint32_t counter = 0;
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//
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// Loop indefinitely
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//
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for(;;)
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{
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//
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// If there is no pending flag
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//
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||||
if( (HWREG(IPC_BASE + IPC_O_FLG) & (1UL << ipcFlag10)) == 0)
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{
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readDataCPU1();
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||||
if(multiplier++ > 255)
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||||
{
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||||
multiplier = 0;
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||||
}
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||||
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||||
//
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||||
// Write an array to a memory location owned by CPU01
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||||
//
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||||
writeDataCPU1();
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||||
|
||||
//
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||||
// Set a flag to notify CPU02 that data is available
|
||||
//
|
||||
HWREG(IPC_BASE + IPC_O_SET) = 1UL << ipcFlag10;
|
||||
}
|
||||
if (counter++ > 2000000)
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||||
{
|
||||
//
|
||||
// Toggle CPU1_LED, defined in sysconfig
|
||||
//
|
||||
GPIO_togglePin(CPU1_LED);
|
||||
counter = 0;
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// writeDataCPU1 - Write a pattern to an array in shared RAM
|
||||
//
|
||||
void writeDataCPU1(void)
|
||||
{
|
||||
uint16_t index;
|
||||
|
||||
//
|
||||
// Use first location to write a multiplier.
|
||||
//
|
||||
cpu1RWArray[0] = multiplier;
|
||||
|
||||
for(index = 1; index < 256; index++)
|
||||
{
|
||||
cpu1RWArray[index] = index;
|
||||
|
||||
//
|
||||
// The following code will attempt to write to a shared RAM assigned
|
||||
// to CPU2 and as a result will cause an access violation.
|
||||
//
|
||||
// cpu1RArray[index] = 1000 + index;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// readDataCPU1 - Read and compare an array from shared RAM
|
||||
//
|
||||
void readDataCPU1(void)
|
||||
{
|
||||
uint16_t index;
|
||||
|
||||
if(cpu1RArray[0] == multiplier)
|
||||
{
|
||||
for(index = 1; index < 256; index++)
|
||||
{
|
||||
if(cpu1RArray[index] != multiplier * cpu1RWArray[index])
|
||||
{
|
||||
error = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
error = 1;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -0,0 +1,68 @@
|
||||
/**
|
||||
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
|
||||
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
|
||||
* @cliArgs --device "F2837xD" --package "F2837xD_337ZWT" --part "F2837xD_337ZWT" --context "CPU1" --product "C2000WARE@4.03.00.00"
|
||||
* @versions {"tool":"1.15.999+71"}
|
||||
*/
|
||||
|
||||
/**
|
||||
* Import the modules used in this configuration.
|
||||
*/
|
||||
const gpio = scripting.addModule("/driverlib/gpio.js", {}, false);
|
||||
const gpio1 = gpio.addInstance();
|
||||
const gpio2 = gpio.addInstance();
|
||||
const ipc = scripting.addModule("/driverlib/ipc.js");
|
||||
const memcfg = scripting.addModule("/driverlib/memcfg.js");
|
||||
const CMD = scripting.addModule("/utilities/cmd_tool/cmd_syscfg/source/CMD");
|
||||
const CMD1 = CMD.addInstance();
|
||||
|
||||
/**
|
||||
* Write custom configuration values to the imported modules.
|
||||
*/
|
||||
gpio1.$name = "CPU1_LED";
|
||||
gpio1.direction = "GPIO_DIR_MODE_OUT";
|
||||
gpio1.gpioPin.$assign = "GPIO34";
|
||||
|
||||
gpio2.$name = "CPU2_LED";
|
||||
gpio2.direction = "GPIO_DIR_MODE_OUT";
|
||||
gpio2.controllerCore = "GPIO_CORE_CPU2";
|
||||
gpio2.gpioPin.$assign = "GPIO31";
|
||||
|
||||
memcfg.config_MEMCFG_SECT_GS0 = "MEMCFG_GSRAMCONTROLLER_CPU2";
|
||||
memcfg.config_MEMCFG_SECT_GS14 = "MEMCFG_GSRAMCONTROLLER_CPU2";
|
||||
|
||||
CMD.activateCMD = true;
|
||||
|
||||
CMD1.$name = "CMD0";
|
||||
CMD1.sectionMemory_text = ["FLASHB","FLASHC","FLASHD","FLASHE"];
|
||||
CMD1.sectionAlignEnable_text = true;
|
||||
CMD1.sectionMemory_ramfunc = ["FLASHD"];
|
||||
CMD1.sectionRunFromDifferentAddr_ramfunc = true;
|
||||
CMD1.sectionRun_ramfunc = ["RAMLS0"];
|
||||
CMD1.sectionAlignEnable_ramfunc = true;
|
||||
CMD1.sectionMemory_ovly = ["FLASHA"];
|
||||
CMD1.sectionAlignEnable_ovly = true;
|
||||
CMD1.sectionMemory_cinit = ["FLASHA"];
|
||||
CMD1.sectionAlignEnable_cinit = true;
|
||||
CMD1.sectionMemory_stack = ["RAMM1"];
|
||||
CMD1.sectionMemory_init_array = ["FLASHB"];
|
||||
CMD1.sectionAlignEnable_init_array = true;
|
||||
CMD1.sectionMemory_bss = ["RAMLS5"];
|
||||
CMD1.sectionMemory_const = ["FLASHF"];
|
||||
CMD1.sectionAlignEnable_const = true;
|
||||
CMD1.sectionMemory_data = ["RAMLS5"];
|
||||
CMD1.sectionMemory_switch = ["FLASHA"];
|
||||
CMD1.sectionAlignEnable_switch = true;
|
||||
CMD1.sectionMemory_sysmem = ["RAMLS5"];
|
||||
CMD1.sectionMemory_binit = ["FLASHA"];
|
||||
CMD1.sectionAlignEnable_binit = true;
|
||||
CMD1.userSection.create(4);
|
||||
CMD1.userSection[0].$name = "isrfunc";
|
||||
CMD1.userSection[0].sectionMemory = ["RAMGS15"];
|
||||
CMD1.userSection[1].$name = "SHARERAMGS0";
|
||||
CMD1.userSection[1].sectionMemory = ["RAMGS0"];
|
||||
CMD1.userSection[2].$name = "SHARERAMGS1";
|
||||
CMD1.userSection[2].sectionMemory = ["RAMGS1"];
|
||||
CMD1.userSection[3].$name = "SHARERAMGS2";
|
||||
CMD1.userSection[3].sectionMemory = ["RAMGS2"];
|
||||
scripting.suppress("RAMGS0 is not configured to be owned by CPU1 in @@@.+?@@@\\. CPU1 will only have read access to this memory\\.", CMD1.userSection[1], "sectionMemory");
|
||||
@@ -0,0 +1,252 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: memcfg_ex1_sysconfig_cpu2.c
|
||||
//
|
||||
// TITLE: SysConfig RAM Management Example
|
||||
//
|
||||
//! \addtogroup driver_dual_example_list
|
||||
//! <h1> LED Blinky Example</h1>
|
||||
//!
|
||||
//! This example demonstrates how to blink a LED using CPU1 and blink another
|
||||
//! LED using CPU2 (led_ex1_blinky_cpu2.c).
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - None.
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - None.
|
||||
//!
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
#include "inc/hw_ipc.h"
|
||||
#include "board.h"
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint16_t cpu2RWArray[256]; // Mapped to GS1 of shared RAM owned by CPU02
|
||||
uint16_t cpu2RArray[256]; // Mapped to GS0 of shared RAM owned by CPU01
|
||||
#pragma DATA_SECTION(cpu2RArray,"SHARERAMGS1");
|
||||
#pragma DATA_SECTION(cpu2RWArray,"SHARERAMGS0");
|
||||
|
||||
uint16_t isrfuncLoadStart;
|
||||
extern uint16_t isrfuncLoadEnd;
|
||||
uint16_t isrfuncRunStart;
|
||||
uint16_t isrfuncLoadSize;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void initCPUTimer(uint32_t);
|
||||
void configCPUTimer(uint32_t, float, float);
|
||||
__interrupt void cpuTimer0ISR(void);
|
||||
#pragma CODE_SECTION(cpuTimer0ISR, "isrfunc")
|
||||
|
||||
void writeDataCPU2(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
uint16_t ipcFlag10 = 10U;
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Initialize SysConfig Settings
|
||||
//
|
||||
Board_init();
|
||||
|
||||
//
|
||||
// Wait until shared RAM is available.
|
||||
//
|
||||
while((HWREGH(MEMCFG_BASE + MEMCFG_O_GSXMSEL) &
|
||||
(MEMCFG_GSXMSEL_MSEL_GS14 | MEMCFG_GSXMSEL_MSEL_GS15)) == 0U)
|
||||
{
|
||||
}
|
||||
|
||||
//
|
||||
// Interrupts that are used in this example are re-mapped to ISR functions
|
||||
// found within this file.
|
||||
//
|
||||
Interrupt_register(INT_TIMER0, &cpuTimer0ISR);
|
||||
|
||||
//
|
||||
// Configure CPU Timer 0 to a 1 second period
|
||||
//
|
||||
initCPUTimer(CPUTIMER0_BASE);
|
||||
configCPUTimer(CPUTIMER0_BASE, DEVICE_SYSCLK_FREQ, 1000000);
|
||||
|
||||
//
|
||||
// Start CPU Timer 0
|
||||
//
|
||||
CPUTimer_startTimer(CPUTIMER0_BASE);
|
||||
|
||||
//
|
||||
// Enable CPU Timer 0 interrupt
|
||||
//
|
||||
Interrupt_enable(INT_TIMER0);
|
||||
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
//
|
||||
// Loop indefinitely
|
||||
//
|
||||
while(1)
|
||||
{
|
||||
if((HWREG(IPC_BASE + IPC_O_STS) & (1UL << ipcFlag10)) == 1)
|
||||
{
|
||||
//
|
||||
// Read cpu2RArray and modify cpu2RWArray
|
||||
//
|
||||
writeDataCPU2();
|
||||
HWREG(IPC_BASE + IPC_O_ACK) = 1UL << ipcFlag10;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// initCPUTimer - This function initializes a CPU Timer to a known state.
|
||||
//
|
||||
void initCPUTimer(uint32_t cpuTimer)
|
||||
{
|
||||
//
|
||||
// Initialize timer period to maximum
|
||||
//
|
||||
CPUTimer_setPeriod(cpuTimer, 0xFFFFFFFF);
|
||||
|
||||
//
|
||||
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT)
|
||||
//
|
||||
CPUTimer_setPreScaler(cpuTimer, 0);
|
||||
|
||||
//
|
||||
// Make sure timer is stopped
|
||||
//
|
||||
CPUTimer_stopTimer(cpuTimer);
|
||||
|
||||
//
|
||||
// Reload all counter registers with period value
|
||||
//
|
||||
CPUTimer_reloadTimerCounter(cpuTimer);
|
||||
}
|
||||
|
||||
//
|
||||
// configCPUTimer - This function initializes the selected timer to the
|
||||
// period specified by the "freq" and "period" parameters. The "freq" is
|
||||
// entered as Hz and the period in microseconds. The timer is held in the
|
||||
// stopped state after configuration.
|
||||
//
|
||||
void configCPUTimer(uint32_t cpuTimer, float freq, float period)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
//
|
||||
// Initialize timer period:
|
||||
//
|
||||
temp = (uint32_t)(freq / 1000000 * period);
|
||||
CPUTimer_setPeriod(cpuTimer, temp);
|
||||
|
||||
//
|
||||
// Set pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||
//
|
||||
CPUTimer_setPreScaler(cpuTimer, 0);
|
||||
|
||||
//
|
||||
// Initializes timer control register. The timer is stopped, reloaded,
|
||||
// free run disabled, and interrupt enabled.
|
||||
//
|
||||
CPUTimer_stopTimer(cpuTimer);
|
||||
CPUTimer_reloadTimerCounter(cpuTimer);
|
||||
CPUTimer_setEmulationMode(cpuTimer,
|
||||
CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT);
|
||||
CPUTimer_enableInterrupt(cpuTimer);
|
||||
}
|
||||
|
||||
//
|
||||
// cpuTimer0ISR - CPU Timer0 ISR
|
||||
//
|
||||
__interrupt void cpuTimer0ISR(void)
|
||||
{
|
||||
GPIO_togglePin(CPU2_LED); // CPU2_LED Defined in Sysconfig
|
||||
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
|
||||
}
|
||||
|
||||
//
|
||||
// writeDataCPU2 - Read data from cpu2RArray written by CPU01 and modify and
|
||||
// write into cpu2RWArray. cpu2RArray[0] is used to hold the
|
||||
// multiplier value.
|
||||
//
|
||||
void writeDataCPU2(void)
|
||||
{
|
||||
uint16_t index;
|
||||
uint16_t multiplier;
|
||||
|
||||
multiplier = cpu2RArray[0];
|
||||
cpu2RWArray[0] = multiplier;
|
||||
|
||||
for(index = 1; index < 256; index ++)
|
||||
{
|
||||
cpu2RWArray[index] = multiplier * cpu2RArray[index];
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
/**
|
||||
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
|
||||
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
|
||||
* @cliArgs --device "F2837xD" --package "F2837xD_337ZWT" --part "F2837xD_337ZWT" --context "CPU2" --product "C2000WARE@4.03.00.00"
|
||||
* @versions {"tool":"1.15.999+71"}
|
||||
*/
|
||||
|
||||
/**
|
||||
* Import the modules used in this configuration.
|
||||
*/
|
||||
const ipc = scripting.addModule("/driverlib/ipc.js");
|
||||
const CMD = scripting.addModule("/utilities/cmd_tool/cmd_syscfg/source/CMD");
|
||||
const CMD1 = CMD.addInstance();
|
||||
|
||||
/**
|
||||
* Write custom configuration values to the imported modules.
|
||||
*/
|
||||
CMD.activateCMD = true;
|
||||
|
||||
CMD1.$name = "CMD0";
|
||||
CMD1.sectionMemory_text = ["FLASHB","FLASHC","FLASHD","FLASHE"];
|
||||
CMD1.sectionAlignEnable_text = true;
|
||||
CMD1.sectionMemory_ramfunc = ["FLASHD"];
|
||||
CMD1.sectionRunFromDifferentAddr_ramfunc = true;
|
||||
CMD1.sectionRun_ramfunc = ["RAMLS0"];
|
||||
CMD1.sectionAlignEnable_ramfunc = true;
|
||||
CMD1.sectionMemory_ovly = ["FLASHA"];
|
||||
CMD1.sectionAlignEnable_ovly = true;
|
||||
CMD1.sectionMemory_cinit = ["FLASHA"];
|
||||
CMD1.sectionAlignEnable_cinit = true;
|
||||
CMD1.sectionMemory_stack = ["RAMM1"];
|
||||
CMD1.sectionMemory_init_array = ["FLASHB"];
|
||||
CMD1.sectionAlignEnable_init_array = true;
|
||||
CMD1.sectionMemory_bss = ["RAMLS5"];
|
||||
CMD1.sectionMemory_const = ["FLASHF"];
|
||||
CMD1.sectionAlignEnable_const = true;
|
||||
CMD1.sectionMemory_data = ["RAMLS5"];
|
||||
CMD1.sectionMemory_switch = ["FLASHA"];
|
||||
CMD1.sectionAlignEnable_switch = true;
|
||||
CMD1.sectionMemory_sysmem = ["RAMLS5"];
|
||||
CMD1.sectionMemory_binit = ["FLASHA"];
|
||||
CMD1.sectionAlignEnable_binit = true;
|
||||
CMD1.userSection.create(4);
|
||||
CMD1.userSection[0].$name = "isrfunc";
|
||||
CMD1.userSection[0].sectionMemory = ["RAMGS14"];
|
||||
CMD1.userSection[1].$name = "SHARERAMGS0";
|
||||
CMD1.userSection[1].sectionMemory = ["RAMGS0"];
|
||||
CMD1.userSection[2].$name = "SHARERAMGS1";
|
||||
CMD1.userSection[2].sectionMemory = ["RAMGS1"];
|
||||
CMD1.userSection[3].$name = "SHARERAMGS2";
|
||||
CMD1.userSection[3].sectionMemory = ["RAMGS2"];
|
||||
scripting.suppress("RAMGS1 is not configured to be owned by CPU2 in @@@.+?@@@\\. CPU2 will only have read access to this memory\\.", CMD1.userSection[2], "sectionMemory");
|
||||
scripting.suppress("RAMGS2 is not configured to be owned by CPU2 in @@@.+?@@@\\. CPU2 will only have read access to this memory\\.", CMD1.userSection[3], "sectionMemory");
|
||||
@@ -0,0 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<system>
|
||||
<project configuration="@match" id="project_0" name="memcfg_ex1_sysconfig_cpu1">
|
||||
</project>
|
||||
<core id="C28xx_CPU1" project="project_0"/>
|
||||
<project configuration="@match" id="project_1" name="memcfg_ex1_sysconfig_cpu2">
|
||||
</project>
|
||||
<core id="C28xx_CPU2" project="project_1"/>
|
||||
<preBuildSteps>
|
||||
</preBuildSteps>
|
||||
<postBuildSteps>
|
||||
</postBuildSteps>
|
||||
|
||||
</system>
|
||||
Reference in New Issue
Block a user