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hangpersonal
2026-08-30 23:04:35 -07:00
parent 749dab5721
commit ce65a0f59a
14950 changed files with 4408250 additions and 1 deletions
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C2000Ware/driverlib/f2837xs/examples/cpu1/emif/2837xS_FLASH_lnk_emif_cpu1.cmd
+199
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@@ -0,0 +1,199 @@
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379S/_, F28377S/F28377S, F28375D/F28375S devices. Remove line on other devices. */
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379S/_, F28377S/F28377S, F28375D/F28375S devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379S/_, F28377S/F28377S, F28375D/F28375S devices. Remove line on other devices. */
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379S/_, F28377S/F28377S, F28375D/F28375S devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379S/_, F28377S/F28377S, F28375D/F28375S devices. Remove line on other devices. */
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB PAGE = 0, ALIGN(4)
.text : > FLASHB PAGE = 0, ALIGN(4)
codestart : > BEGIN PAGE = 0, ALIGN(4)
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
/* Initalized sections go in Flash */
.switch : > FLASHB PAGE = 0, ALIGN(4)
#if defined(__TI_EABI__)
.init_array : > FLASHB, PAGE = 0, ALIGN(4)
.bss : > RAMLS5, PAGE = 1
.bss:output : > RAMLS3, PAGE = 0
.bss:cio : > RAMLS5, PAGE = 1
.data : > RAMLS5, PAGE = 1
.sysmem : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.const : > FLASHF, PAGE = 0, ALIGN(4)
#else
.pinit : > FLASHB, PAGE = 0, ALIGN(4)
.ebss : >> RAMLS5, PAGE = 1
.esysmem : > RAMLS5, PAGE = 1
.cio : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.econst : >> FLASHF PAGE = 0, ALIGN(4)
#endif
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
Filter_RegsFile : > RAMGS0, PAGE = 1
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#else
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
#else
ramfuncs : LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
#endif
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
/* Sections for EMIF ASRAM example */
#if defined(__TI_EABI__)
xintffuncs : LOAD = FLASHD,
RUN = EMIF1_CS2n,
LOAD_START(XintffuncsLoadStart),
LOAD_END(XintffuncsLoadEnd),
RUN_START(XintffuncsRunStart),
PAGE = 0
#else
xintffuncs : LOAD = FLASHD,
RUN = EMIF1_CS2n,
LOAD_START(_XintffuncsLoadStart),
LOAD_END(_XintffuncsLoadEnd),
RUN_START(_XintffuncsRunStart),
PAGE = 0
#endif
/* The following section definition are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/2837xS_RAM_lnk_emif_cpu1.cmd
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MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379S/_, F28377S/F28377S, F28375D/F28375S devices. Remove line on other devices. */
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379S/_, F28377S/F28377S, F28375D/F28375S devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379S/_, F28377S/F28377S, F28375D/F28375S devices. Remove line on other devices. */
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379S/_, F28377S/F28377S, F28375D/F28375S devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379S/_, F28377S/F28377S, F28375D/F28375S devices. Remove line on other devices. */
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0
.TI.ramfunc : > RAMM0 PAGE = 0
.text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
.stack : > RAMM1, PAGE = 1
#if defined(__TI_EABI__)
.bss : > RAMLS5, PAGE = 1
.bss:output : > RAMLS3, PAGE = 0
.init_array : > RAMM0, PAGE = 0
.const : > RAMLS5, PAGE = 1
.data : > RAMLS5, PAGE = 1
.sysmem : > RAMLS5, PAGE = 1
#else
.pinit : > RAMM0, PAGE = 0
.ebss : > RAMLS5, PAGE = 1
.econst : > RAMLS5, PAGE = 1
.esysmem : > RAMLS5, PAGE = 1
#endif
Filter_RegsFile : > RAMGS0, PAGE = 1
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
/* Sections for EMIF ASRAM example */
#if defined(__TI_EABI__)
xintffuncs : LOAD = RAMM0,
RUN = EMIF1_CS2n,
LOAD_START(XintffuncsLoadStart),
LOAD_END(XintffuncsLoadEnd),
RUN_START(XintffuncsRunStart),
PAGE = 0
#else
xintffuncs : LOAD = RAMM0,
RUN = EMIF1_CS2n,
LOAD_START(_XintffuncsLoadStart),
LOAD_END(_XintffuncsLoadEnd),
RUN_START(_XintffuncsRunStart),
PAGE = 0
#endif
/* The following section definition are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/CCS/emif_ex1_16bit_asram.projectspec
+29
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@@ -0,0 +1,29 @@
<projectSpec>
<project
name="emif_ex1_16bit_asram"
device="TMS320F28377S"
cgtVersion="22.6.0.LTS"
products="C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xS"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --float_support=fpu32 --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --float_support=fpu32 --define=CPU1 --define=_FLASH --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_RAM_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_FLASH_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../emif_asram_pin_setup.c" targetDirectory="" />
<file action="copy" path="../emif_ex1_16bit_asram.c" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/CCS/emif_ex2_16bit_asram_codemem.projectspec
+29
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@@ -0,0 +1,29 @@
<projectSpec>
<project
name="emif_ex2_16bit_asram_codemem"
device="TMS320F28377S"
cgtVersion="22.6.0.LTS"
products="C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xS"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --float_support=fpu32 --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --float_support=fpu32 --define=CPU1 --define=_FLASH --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../2837xS_RAM_lnk_emif_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM"/>
<file action="copy" path="../2837xS_FLASH_lnk_emif_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH"/>
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../emif_asram_pin_setup.c" targetDirectory="" />
<file action="copy" path="../emif_ex2_16bit_asram_codemem.c" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/CCS/emif_ex3_16bit_sdram_far.projectspec
+32
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@@ -0,0 +1,32 @@
<projectSpec>
<project
name="emif_ex3_16bit_sdram_far"
device="TMS320F28377S"
cgtVersion="22.6.0.LTS"
products="C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xS"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -ml -mt -v28 --float_support=fpu32 --cla_support=cla1 --vcu_support=vcu2 --tmu_support=tmu0 --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -ml -mt -v28 --float_support=fpu32 --cla_support=cla1 --vcu_support=vcu2 --tmu_support=tmu0 --define=CPU1 --define=_FLASH --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_RAM_lnk_cpu1_far.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM"/>
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_FLASH_lnk_cpu1_far.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH"/>
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../emif_ex3_16bit_sdram_far.c" targetDirectory="" />
<file action="copy" path="../emif_sdram_pin_setup.c" targetDirectory="" />
<file action="copy" path="../fpu_types.h" targetDirectory="" />
<file action="copy" path="../fpu_vector.h" targetDirectory="" />
<file action="copy" path="../memcpy_fast_far.asm" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/CCS/emif_ex4_16bit_sdram_far_lpm.projectspec
+32
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@@ -0,0 +1,32 @@
<projectSpec>
<project
name="emif_ex4_16bit_sdram_far_lpm"
device="TMS320F28377S"
cgtVersion="22.6.0.LTS"
products="C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xS"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --float_support=fpu32 --vcu_support=vcu2 --tmu_support=tmu0 --cla_support=cla1 --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --float_support=fpu32 --vcu_support=vcu2 --tmu_support=tmu0 --cla_support=cla1 --define=CPU1 --define=_FLASH --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_RAM_lnk_cpu1_far.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM"/>
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_FLASH_lnk_cpu1_far.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH"/>
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../emif_ex4_16bit_sdram_far_lpm.c" targetDirectory="" />
<file action="copy" path="../emif_sdram_pin_setup.c" targetDirectory="" />
<file action="copy" path="../fpu_types.h" targetDirectory="" />
<file action="copy" path="../fpu_vector.h" targetDirectory="" />
<file action="copy" path="../memcpy_fast_far.asm" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/CCS/emif_ex5_16bit_sdram_dma.projectspec
+29
View File
@@ -0,0 +1,29 @@
<projectSpec>
<project
name="emif_ex5_16bit_sdram_dma"
device="TMS320F28377S"
cgtVersion="22.6.0.LTS"
products="C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xS"
>
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG -v28 -ml -mt --define=DEBUG --define=CPU1 --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG -v28 -ml -mt --define=DEBUG --define=CPU1 --define=_FLASH --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_RAM_lnk_cpu1_far.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM"/>
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_FLASH_lnk_cpu1_far.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH"/>
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../emif_ex5_16bit_sdram_dma.c" targetDirectory="" />
<file action="copy" path="../emif_sdram_pin_setup.c" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/emif_asram_pin_setup.c
+317
View File
@@ -0,0 +1,317 @@
//#############################################################################
//
// FILE: emif_asram_pin_setup.c
//
// TITLE: Pin setup for EMIF module accessing ASRAM.
//
// This example configures pins for EMIF in ASYNC mode.
//
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include <stdint.h>
#include "device.h"
#include "driverlib.h"
#ifdef CPU1
//
// Function Prototypes
//
void setupEMIF1PinmuxAsync16Bit(void);
void setupEMIF1PinmuxAsync32Bit(void);
void setupEMIF2PinmuxAsync16Bit(void);
#endif
//
// Setup EMIF1 Pinmux Async 16Bit - This function configures pins for 16 bit
// Asynchronous EMIF1.
//
void setupEMIF1PinmuxAsync16Bit(void)
{
uint16_t i;
GPIO_setPinConfig(GPIO_28_EM1CS4N);
GPIO_setPinConfig(GPIO_29_EM1SDCKE);
GPIO_setPinConfig(GPIO_30_EM1CLK);
GPIO_setPinConfig(GPIO_31_EM1WEN);
GPIO_setPinConfig(GPIO_32_EM1CS0N);
GPIO_setPinConfig(GPIO_33_EM1RNW);
GPIO_setPinConfig(GPIO_34_EM1CS2N);
GPIO_setPinConfig(GPIO_35_EM1CS3N);
GPIO_setPinConfig(GPIO_36_EM1WAIT);
GPIO_setPinConfig(GPIO_37_EM1OEN);
//
// Selecting address lines.
//
GPIO_setPinConfig(GPIO_38_EM1A0);
GPIO_setPinConfig(GPIO_39_EM1A1);
GPIO_setPinConfig(GPIO_40_EM1A2);
GPIO_setPinConfig(GPIO_41_EM1A3);
GPIO_setPinConfig(GPIO_44_EM1A4);
GPIO_setPinConfig(GPIO_45_EM1A5);
GPIO_setPinConfig(GPIO_46_EM1A6);
GPIO_setPinConfig(GPIO_47_EM1A7);
GPIO_setPinConfig(GPIO_48_EM1A8);
GPIO_setPinConfig(GPIO_49_EM1A9);
GPIO_setPinConfig(GPIO_50_EM1A10);
GPIO_setPinConfig(GPIO_51_EM1A11);
GPIO_setPinConfig(GPIO_52_EM1A12);
GPIO_setPinConfig(GPIO_86_EM1A13);
GPIO_setPinConfig(GPIO_87_EM1A14);
//
// Selecting data lines.
//
GPIO_setPinConfig(GPIO_63_EM1D21);
GPIO_setPinConfig(GPIO_64_EM1D20);
GPIO_setPinConfig(GPIO_65_EM1D19);
GPIO_setPinConfig(GPIO_66_EM1D18);
GPIO_setPinConfig(GPIO_67_EM1D17);
GPIO_setPinConfig(GPIO_68_EM1D16);
GPIO_setPinConfig(GPIO_69_EM1D15);
GPIO_setPinConfig(GPIO_70_EM1D14);
GPIO_setPinConfig(GPIO_71_EM1D13);
GPIO_setPinConfig(GPIO_72_EM1D12);
GPIO_setPinConfig(GPIO_73_EM1D11);
GPIO_setPinConfig(GPIO_74_EM1D10);
GPIO_setPinConfig(GPIO_75_EM1D9);
GPIO_setPinConfig(GPIO_76_EM1D8);
GPIO_setPinConfig(GPIO_77_EM1D7);
GPIO_setPinConfig(GPIO_78_EM1D6);
GPIO_setPinConfig(GPIO_79_EM1D5);
GPIO_setPinConfig(GPIO_80_EM1D4);
GPIO_setPinConfig(GPIO_81_EM1D3);
GPIO_setPinConfig(GPIO_82_EM1D2);
GPIO_setPinConfig(GPIO_83_EM1D1);
GPIO_setPinConfig(GPIO_85_EM1D0);
//
// Setting DQM and Bank Select lines.
//
GPIO_setPinConfig(GPIO_88_EM1DQM0);
GPIO_setPinConfig(GPIO_89_EM1DQM1);
GPIO_setPinConfig(GPIO_90_EM1DQM2);
GPIO_setPinConfig(GPIO_91_EM1DQM3);
GPIO_setPinConfig(GPIO_92_EM1BA1);
GPIO_setPinConfig(GPIO_93_EM1BA0);
GPIO_setPinConfig(GPIO_94_EM1A21);
//
// Setup async mode and enable pull-ups for Data pins.
//
for(i=69; i<=85;i++)
{
if(i != 84)
{
GPIO_setPadConfig(i, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(i, GPIO_QUAL_ASYNC);
}
}
}
//
// Setup EMIF1 Pinmux Async 32Bit - This function configures pins for 32 bit
// Asynchronous EMIF1.
//
void setupEMIF1PinmuxAsync32Bit(void)
{
uint16_t i;
GPIO_setPinConfig(GPIO_28_EM1CS4N);
GPIO_setPinConfig(GPIO_29_EM1SDCKE);
GPIO_setPinConfig(GPIO_30_EM1CLK);
GPIO_setPinConfig(GPIO_31_EM1WEN);
GPIO_setPinConfig(GPIO_32_EM1CS0N);
GPIO_setPinConfig(GPIO_33_EM1RNW);
GPIO_setPinConfig(GPIO_34_EM1CS2N);
GPIO_setPinConfig(GPIO_35_EM1CS3N);
GPIO_setPinConfig(GPIO_36_EM1WAIT);
GPIO_setPinConfig(GPIO_37_EM1OEN);
//
// Selecting address lines.
//
GPIO_setPinConfig(GPIO_38_EM1A0);
GPIO_setPinConfig(GPIO_39_EM1A1);
GPIO_setPinConfig(GPIO_40_EM1A2);
GPIO_setPinConfig(GPIO_41_EM1A3);
GPIO_setPinConfig(GPIO_44_EM1A4);
GPIO_setPinConfig(GPIO_45_EM1A5);
GPIO_setPinConfig(GPIO_46_EM1A6);
GPIO_setPinConfig(GPIO_47_EM1A7);
GPIO_setPinConfig(GPIO_48_EM1A8);
GPIO_setPinConfig(GPIO_49_EM1A9);
GPIO_setPinConfig(GPIO_50_EM1A10);
GPIO_setPinConfig(GPIO_51_EM1A11);
GPIO_setPinConfig(GPIO_52_EM1A12);
GPIO_setPinConfig(GPIO_86_EM1A13);
GPIO_setPinConfig(GPIO_87_EM1A14);
//
// Selecting data lines.
//
GPIO_setPinConfig(GPIO_53_EM1D31);
GPIO_setPinConfig(GPIO_54_EM1D30);
GPIO_setPinConfig(GPIO_55_EM1D29);
GPIO_setPinConfig(GPIO_56_EM1D28);
GPIO_setPinConfig(GPIO_57_EM1D27);
GPIO_setPinConfig(GPIO_58_EM1D26);
GPIO_setPinConfig(GPIO_59_EM1D25);
GPIO_setPinConfig(GPIO_60_EM1D24);
GPIO_setPinConfig(GPIO_61_EM1D23);
GPIO_setPinConfig(GPIO_62_EM1D22);
GPIO_setPinConfig(GPIO_63_EM1D21);
GPIO_setPinConfig(GPIO_64_EM1D20);
GPIO_setPinConfig(GPIO_65_EM1D19);
GPIO_setPinConfig(GPIO_66_EM1D18);
GPIO_setPinConfig(GPIO_67_EM1D17);
GPIO_setPinConfig(GPIO_68_EM1D16);
GPIO_setPinConfig(GPIO_69_EM1D15);
GPIO_setPinConfig(GPIO_70_EM1D14);
GPIO_setPinConfig(GPIO_71_EM1D13);
GPIO_setPinConfig(GPIO_72_EM1D12);
GPIO_setPinConfig(GPIO_73_EM1D11);
GPIO_setPinConfig(GPIO_74_EM1D10);
GPIO_setPinConfig(GPIO_75_EM1D9);
GPIO_setPinConfig(GPIO_76_EM1D8);
GPIO_setPinConfig(GPIO_77_EM1D7);
GPIO_setPinConfig(GPIO_78_EM1D6);
GPIO_setPinConfig(GPIO_79_EM1D5);
GPIO_setPinConfig(GPIO_80_EM1D4);
GPIO_setPinConfig(GPIO_81_EM1D3);
GPIO_setPinConfig(GPIO_82_EM1D2);
GPIO_setPinConfig(GPIO_83_EM1D1);
GPIO_setPinConfig(GPIO_85_EM1D0);
//
// Setting DQM and Bank Select lines.
//
GPIO_setPinConfig(GPIO_88_EM1DQM0);
GPIO_setPinConfig(GPIO_89_EM1DQM1);
GPIO_setPinConfig(GPIO_90_EM1DQM2);
GPIO_setPinConfig(GPIO_91_EM1DQM3);
GPIO_setPinConfig(GPIO_92_EM1BA1);
GPIO_setPinConfig(GPIO_93_EM1BA0);
GPIO_setPinConfig(GPIO_94_EM1A21);
//
// Setup Async Mode for Data pins.
//
for(i=53; i<=85;i++)
{
if(i != 84)
{
GPIO_setPadConfig(i, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(i, GPIO_QUAL_ASYNC);
}
}
}
//
// Setup EMIF2 Pinmux Async 16Bit - This function configures pins for 16 bit
// Asynchronous EMIF2.
//
void setupEMIF2PinmuxAsync16Bit(void)
{
uint16_t i;
GPIO_setPinConfig(GPIO_96_EM2DQM1);
GPIO_setPinConfig(GPIO_97_EM2DQM0);
GPIO_setPinConfig(GPIO_98_EM2A0);
GPIO_setPinConfig(GPIO_99_EM2A1);
GPIO_setPinConfig(GPIO_100_EM2A2);
GPIO_setPinConfig(GPIO_101_EM2A3);
GPIO_setPinConfig(GPIO_102_EM2A4);
GPIO_setPinConfig(GPIO_103_EM2A5);
GPIO_setPinConfig(GPIO_104_EM2A6);
GPIO_setPinConfig(GPIO_105_EM2A7);
GPIO_setPinConfig(GPIO_106_EM2A8);
GPIO_setPinConfig(GPIO_107_EM2A9);
GPIO_setPinConfig(GPIO_108_EM2A10);
GPIO_setPinConfig(GPIO_109_EM2A11);
GPIO_setPinConfig(GPIO_110_EM2WAIT);
GPIO_setPinConfig(GPIO_111_EM2BA0);
GPIO_setPinConfig(GPIO_112_EM2BA1);
GPIO_setPinConfig(GPIO_113_EM2CAS);
GPIO_setPinConfig(GPIO_114_EM2RAS);
GPIO_setPinConfig(GPIO_115_EM2CS0N);
GPIO_setPinConfig(GPIO_116_EM2CS2N);
GPIO_setPinConfig(GPIO_117_EM2SDCKE);
GPIO_setPinConfig(GPIO_118_EM2CLK);
GPIO_setPinConfig(GPIO_119_EM2RNW);
GPIO_setPinConfig(GPIO_120_EM2WEN);
GPIO_setPinConfig(GPIO_121_EM2OEN);
//
// Selecting Data lines.
//
GPIO_setPinConfig(GPIO_53_EM2D15);
GPIO_setPinConfig(GPIO_54_EM2D14);
GPIO_setPinConfig(GPIO_55_EM2D13);
GPIO_setPinConfig(GPIO_56_EM2D12);
GPIO_setPinConfig(GPIO_57_EM2D11);
GPIO_setPinConfig(GPIO_58_EM2D10);
GPIO_setPinConfig(GPIO_59_EM2D9);
GPIO_setPinConfig(GPIO_60_EM2D8);
GPIO_setPinConfig(GPIO_61_EM2D7);
GPIO_setPinConfig(GPIO_62_EM2D6);
GPIO_setPinConfig(GPIO_63_EM2D5);
GPIO_setPinConfig(GPIO_64_EM2D4);
GPIO_setPinConfig(GPIO_65_EM2D3);
GPIO_setPinConfig(GPIO_66_EM2D2);
GPIO_setPinConfig(GPIO_67_EM2D1);
GPIO_setPinConfig(GPIO_68_EM2D0);
//
// Setup async mode for Data pins.
//
for(i=53; i<=68;i++)
{
GPIO_setPadConfig(i, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(i, GPIO_QUAL_ASYNC);
}
}
//
// End of File
//
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/emif_ex1_16bit_asram.c
+433
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//#############################################################################
//
// FILE: emif_ex1_16bit_asram.c
//
// TITLE: EMIF1 ASYNC module accessing 16bit ASRAM.
//
//! \addtogroup driver_example_list
//! <h1> EMIF1 ASYNC module accessing 16bit ASRAM. </h1>
//!
//! This example configures EMIF1 in 16bit ASYNC mode and uses CS2 as chip
//! enable.
//!
//! \b External \b Connections \n
//! - External ASRAM memory (CY7C1041CV33 -10ZSXA) daughter card
//!
//! \b Watch \b Variables \n
//! - \b testStatusGlobal - Equivalent to \b TEST_PASS if test finished
//! correctly, else the value is set to \b TEST_FAIL
//! - \b errCountGlobal - Error counter
//!
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "device.h"
#include "driverlib.h"
//
// Defines
//
#define TEST_PASS 0xABCDABCD
#define TEST_FAIL 0xDEADDEAD
#define ASRAM_CS2_START_ADDR 0x100000
#define ASRAM_CS2_SIZE 0x8000
//
// Globals
//
uint16_t errCountGlobal = 0;
uint32_t testStatusGlobal;
uint32_t i;
//
// Function Prototypes
//
extern void setupEMIF1PinmuxAsync16Bit(void);
uint16_t readWriteMem(uint32_t startAddr, uint32_t memSize);
uint16_t walkMemData(uint32_t startAddr, uint32_t memSize);
uint16_t walkMemAddr(uint32_t startAddr, uint32_t addrSize);
uint16_t accessMemData(uint32_t startAddr, uint32_t sizeToCheck);
//
// Main
//
void main(void)
{
uint16_t errCountLocal;
EMIF_AsyncTimingParams tparam;
testStatusGlobal = TEST_FAIL;
//
// Initialize device clock and peripherals.
//
Device_init();
//
// Disable all the interrupts.
//
DINT;
//
// Setup GPIO by disabling pin locks and enabling pullups.
//
Device_initGPIO();
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// Configure to run EMIF1 on full Rate. (EMIF1CLK = CPU1SYSCLK)
//
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_1);
//
// Disable Access Protection. (CPU_FETCH/CPU_WR/DMA_WR)
//
EMIF_setAccessProtection(EMIF1CONFIG_BASE, 0x0);
//
// Commit the configuration related to protection. Till this bit remains
// set, contents of EMIF1ACCPROT0 register can't be changed.
//
EMIF_commitAccessConfig(EMIF1CONFIG_BASE);
//
// Lock the configuration so that EMIF1COMMIT register can't be changed
// any more.
//
EMIF_lockAccessConfig(EMIF1CONFIG_BASE);
//
// Configure GPIO pins for EMIF1.
//
setupEMIF1PinmuxAsync16Bit();
//
// Configures Normal Asynchronous Mode of Operation.
//
EMIF_setAsyncMode(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET,
EMIF_ASYNC_NORMAL_MODE);
//
// Disables Extended Wait Mode.
//
EMIF_disableAsyncExtendedWait(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET);
//
// Configure EMIF1 Data Bus Width.
//
EMIF_setAsyncDataBusWidth(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET,
EMIF_ASYNC_DATA_WIDTH_16);
//
// Configure the access timing for CS2 space.
//
tparam.rSetup = 0;
tparam.rStrobe = 3;
tparam.rHold = 0;
tparam.turnArnd = 0;
tparam.wSetup = 0;
tparam.wStrobe = 1;
tparam.wHold = 0;
EMIF_setAsyncTimingParams(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET, &tparam);
//
// Checks basic RD/WR access to CS2 space.
//
errCountLocal = readWriteMem(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE);
errCountGlobal = errCountGlobal + errCountLocal;
//
// Address walk checks. (Tested for Memory with address width of 16bit)
//
errCountLocal = walkMemAddr(ASRAM_CS2_START_ADDR, 16);
errCountGlobal = errCountGlobal + errCountLocal;
//
// Data walk checks.
//
errCountLocal = walkMemData(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE);
errCountGlobal = errCountGlobal + errCountLocal;
//
// Data size checks.
//
errCountLocal = accessMemData(ASRAM_CS2_START_ADDR, 4);
errCountGlobal = errCountGlobal + errCountLocal;
if(errCountGlobal == 0x0)
{
testStatusGlobal = TEST_PASS;
}
while(1);
}
//
// Read Write Memory - This function performs simple read/write word accesses
// to memory.
//
uint16_t readWriteMem(uint32_t startAddr, uint32_t memSize)
{
uint32_t memReadData;
uint32_t memWriteData;
uint32_t *memPtr;
uint32_t i;
memPtr = (uint32_t *)startAddr;
//
// Write data to memory.
//
memWriteData = 0x01234567;
for(i = 0; i < memSize; i++)
{
*memPtr++ = memWriteData;
memWriteData += 0x11111111;
}
//
// Verify data written to memory.
//
memWriteData = 0x01234567;
memPtr = (uint32_t *)startAddr;
for(i = 0; i < memSize; i++)
{
memReadData = *memPtr;
if(memReadData != memWriteData)
{
return(1);
}
memPtr++;
memWriteData += 0x11111111;
}
return(0);
}
//
// Walk Memory Data - This function performs a walking 0 & 1 on data lines
// for SRAM RD & WR.
//
uint16_t walkMemData(uint32_t startAddr, uint32_t memSize)
{
uint32_t sramReadData;
uint32_t sramWriteData;
uint32_t i;
uint32_t k;
uint32_t m;
uint32_t *memPtr;
uint32_t *memPtrIter;
memPtr = (uint32_t *)startAddr;
for(i = 0; i < memSize; i = i + 64)
{
for(m = 0; m < 2; m++)
{
//
// Write loop.
//
memPtrIter = memPtr;
sramWriteData = 0x01;
for(k = 0; k < 32; k++)
{
if(m == 0)
{
*memPtrIter++ = sramWriteData;
}
else
{
*memPtrIter++ = ~sramWriteData;
}
sramWriteData = sramWriteData << 1;
}
//
// Read loop.
//
memPtrIter = memPtr;
sramWriteData = 0x01;
for(k = 0; k < 32; k++)
{
sramReadData = *memPtrIter;
if(m == 1)
{
sramReadData = ~sramReadData;
}
if(sramReadData != sramWriteData)
{
return(1);
}
memPtrIter++;
sramWriteData = sramWriteData << 1;
}
}
memPtr = memPtrIter;
}
return(0);
}
//
// Walk Memory Addresses - This function performs a toggle on each address bit.
//
uint16_t walkMemAddr(uint32_t startAddr, uint32_t addrSize)
{
uint32_t sramReadData;
uint32_t sramWriteData;
uint32_t k;
uint32_t xshift;
uint32_t *memPtr;
uint32_t *memPtrIter;
memPtr = (uint32_t *)startAddr;
//
// Write loop.
//
xshift = 0x00000001;
sramWriteData = 0x00;
for(k = 0; k < addrSize; k++)
{
memPtrIter = (uint32_t *)(startAddr + xshift);
*memPtrIter = sramWriteData++;
xshift = xshift << 1;
}
//
// Read loop.
//
memPtrIter = memPtr;
xshift = 0x00000001;
sramWriteData = 0x00;
for(k = 0; k < addrSize; k++)
{
memPtrIter = (uint32_t *)(startAddr + xshift);
sramReadData = *memPtrIter;
if(sramReadData != sramWriteData)
{
return(1);
}
xshift = xshift << 1;
sramWriteData++;
}
return(0);
}
//
// Access Memory Data - This function performs different data type
// (HALFWORD/WORD) access.
//
uint16_t accessMemData(uint32_t startAddr, uint32_t sizeToCheck)
{
uint16_t memRdShort;
uint32_t memRdLong;
uint16_t memWrShort;
uint32_t memWrLong;
uint32_t i;
uint16_t *memPtrShort;
uint32_t *memPtrLong;
//
// Write short data.
//
memPtrShort = (uint16_t *)startAddr;
memWrShort = 0x0605;
for(i = 0; i < 2; i++)
{
*memPtrShort++ = memWrShort;
memWrShort += 0x0202;
}
//
// Write long data.
//
memPtrLong = (uint32_t *)memPtrShort;
memWrLong = 0x0C0B0A09;
for(i = 0; i < 2; i++)
{
*memPtrLong++ = memWrLong;
memWrLong += 0x04040404;
}
//
// Read short data.
//
memPtrShort = (uint16_t *)startAddr;
memWrShort = 0x0605;
for(i = 0; i < 6; i++)
{
memRdShort = *memPtrShort;
if(memRdShort != memWrShort)
{
return(1);
}
memPtrShort++;
memWrShort += 0x0202;
}
//
// Read long data.
//
memPtrLong = (uint32_t *)startAddr;
memWrLong = 0x08070605;
for(i = 0; i < 3; i++)
{
memRdLong = *memPtrLong;
if(memRdLong != memWrLong)
{
return(1);
}
memPtrLong++;
memWrLong += 0x04040404;
}
return(0);
}
//
// End of File
//
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/emif_ex2_16bit_asram_codemem.c
+287
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@@ -0,0 +1,287 @@
//#############################################################################
//
// FILE: emif_ex2_16bit_asram_codemem.c
//
// TITLE: EMIF1 module accessing 16bit ASRAM as code memory.
//
//! \addtogroup driver_example_list
//! <h1> EMIF1 module accessing 16bit ASRAM as code memory. </h1>
//!
//! This example configures EMIF1 in 16bit ASYNC mode and uses CS2 as chip
//! enable. This example enables use of ASRAM as code memory.
//!
//! \b External \b Connections \n
//! - External ASRAM memory (CY7C1041CV33 -10ZSXA) daughter card
//!
//! \b Watch \b Variables \n
//! - \b testStatusGlobal - Equivalent to \b TEST_PASS if test finished
//! correctly, else the value is set to \b TEST_FAIL
//! - \b errCountGlobal - Error counter
//!
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "device.h"
#include "driverlib.h"
//
// Defines
//
#define TEST_PASS 0xABCDABCD
#define TEST_FAIL 0xDEADDEAD
#define ASRAM_CS2_START_ADDR 0x100000
#define ASRAM_CS2_SIZE 0x8000
//
// This tells the compiler to put methods in code section which influences
// the location in memory where linker will put it.
//
#pragma CODE_SECTION(add,"xintffuncs");
#pragma CODE_SECTION(multiply,"xintffuncs");
//
// Globals
//
extern uint16_t XintffuncsLoadStart;
extern uint16_t XintffuncsLoadEnd;
extern uint16_t XintffuncsRunStart;
uint16_t errCountGlobal = 0;
uint32_t testStatusGlobal;
uint32_t i;
//
// Function Prototypes
//
extern void setupEMIF1PinmuxAsync16Bit(void);
uint16_t add(uint16_t, uint16_t);
uint16_t multiply(uint16_t, uint16_t);
void memCopy(uint16_t *sourceAddr, uint16_t *sourceEndAddr, uint16_t *destAddr);
uint16_t readWriteMem(uint32_t startAddr, uint32_t memSize);
//
// Main
//
void main(void)
{
uint16_t errCountLocal;
EMIF_AsyncTimingParams tparam;
testStatusGlobal = TEST_FAIL;
//
// Initialize device clock and peripherals.
//
Device_init();
//
// Disable all the interrupts.
//
DINT;
//
// Setup GPIO by disabling pin locks and enabling pullups.
//
Device_initGPIO();
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// Configure to run EMIF1 on full Rate. (EMIF1CLK = CPU1SYSCLK)
//
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_1);
//
// Disable Access Protection. (CPU_FETCH/CPU_WR/DMA_WR)
//
EMIF_setAccessProtection(EMIF1CONFIG_BASE, 0x0);
//
// Commit the configuration related to protection. Till this bit remains
// set, contents of EMIF1ACCPROT0 register can't be changed.
//
EMIF_commitAccessConfig(EMIF1CONFIG_BASE);
//
// Lock the configuration so that EMIF1COMMIT register can't be changed
// any more.
//
EMIF_lockAccessConfig(EMIF1CONFIG_BASE);
//
// Configure GPIO pins for EMIF1.
//
setupEMIF1PinmuxAsync16Bit();
//
// Configure Normal Asynchronous Mode of Operation.
//
EMIF_setAsyncMode(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET,
EMIF_ASYNC_NORMAL_MODE);
//
// Disable Extended Wait Mode.
//
EMIF_disableAsyncExtendedWait(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET);
//
// Configure EMIF1 Data Bus Width.
//
EMIF_setAsyncDataBusWidth(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET,
EMIF_ASYNC_DATA_WIDTH_16);
//
// Configure the access timing for CS2 space.
//
tparam.rSetup = 0;
tparam.rStrobe = 3;
tparam.rHold = 0;
tparam.turnArnd = 0;
tparam.wSetup = 0;
tparam.wStrobe = 1;
tparam.wHold = 0;
EMIF_setAsyncTimingParams(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET, &tparam);
//
// Checks basic RD/WR access to CS2 space.
//
errCountLocal = readWriteMem(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE);
errCountGlobal = errCountGlobal + errCountLocal;
if(errCountGlobal == 0x0)
{
testStatusGlobal = TEST_PASS;
//
// Copies methods from load address to run address.
//
memCopy(&XintffuncsLoadStart, &XintffuncsLoadEnd, &XintffuncsRunStart);
//
// These methods are executed from ASRAM. Refer method addresses to
// confirm. The addresses should lie in ASRAM address range.
//
uint16_t sum = add(5, 7);
uint16_t mult = multiply(8, 5);
}
while(1);
}
//
// Add - This function is for reference only. It will be copied to ASRAM
// and is executed from ASRAM.
//
uint16_t add(uint16_t a, uint16_t b)
{
return(a+b);
}
//
// Multiply - This function is for reference only. It will be copied to ASRAM
// and is executed from ASRAM.
//
uint16_t multiply(uint16_t a, uint16_t b)
{
return(a*b);
}
//
// Memory Copy - This function copies source memory data to destination memory.
//
void memCopy(uint16_t *sourceAddr, uint16_t *sourceEndAddr, uint16_t *destAddr)
{
while(sourceAddr < sourceEndAddr)
{
*destAddr++ = *sourceAddr++;
}
return;
}
//
// Read Write Memory - This function performs simple read/write word accesses
// to memory.
//
uint16_t readWriteMem(uint32_t startAddr, uint32_t memSize)
{
uint32_t memReadData;
uint32_t memWriteData;
uint32_t *memPtr;
uint32_t i;
memPtr = (uint32_t *)startAddr;
//
// Write data to memory.
//
memWriteData = 0x01234567;
for(i = 0; i < memSize; i++)
{
*memPtr++ = memWriteData;
memWriteData += 0x11111111;
}
//
// Verify data written to memory.
//
memWriteData = 0x01234567;
memPtr = (uint32_t *)startAddr;
for(i = 0; i < memSize; i++)
{
memReadData = *memPtr;
if(memReadData != memWriteData)
{
return(1);
}
memPtr++;
memWriteData += 0x11111111;
}
return(0);
}
//
// End of File
//
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/emif_ex3_16bit_sdram_far.c
+319
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@@ -0,0 +1,319 @@
//#############################################################################
//
// FILE: emif_ex3_16bit_sdram_far.c
//
// TITLE: EMIF1 module accessing 16bit SDRAM using memcpy_fast_far().
//
//! \addtogroup driver_example_list
//! <h1> EMIF1 module accessing 16bit SDRAM using memcpy_fast_far(). </h1>
//!
//! This example configures EMIF1 in 16bit SYNC mode and uses CS0 as chip
//! enable.It will first write to an array in the SDRAM and then read it
//! back using the FPU function, memcpy_fast_far(), for both operations.
//!
//! The buffer in SDRAM will be placed in the .farbss memory on account
//! of the fact that its assigned the attribute "far" indicating it lies
//! beyond the 22-bit program address space. The compiler will take care
//! to avoid using instructions such as PREAD, which uses the Program
//! Read Bus, or addressing modes restricted to the lower 22-bit space
//! when accessing data with the attribute "far".
//!
//! \note The memory space beyond 22-bits must be treated as data space
//! for load/store operations only. The user is cautioned against using
//! this space for either instructions or working memory.
//!
//! \b External \b Connections \n
//! - External SDR-SDRAM memory (MT48LC32M16A2 -75) daughter card
//!
//! \b Watch \b Variables \n
//! - \b testStatusGlobal - Equivalent to \b TEST_PASS if test finished
//! correctly, else the value is set to \b TEST_FAIL
//! - \b errCountGlobal - Error counter
//!
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "device.h"
#include "driverlib.h"
//
// FPU header file to access memcpy_fast_far().
//
#include "fpu_vector.h"
//
// Defines
//
#define TEST_PASS 0xABCDABCD
#define TEST_FAIL 0xDEADDEAD
#define MEM_BUFFER_SIZE 0x500
//
// Globals
//
uint16_t errCountGlobal = 0;
uint32_t testStatusGlobal;
//
// Buffer in local memory.
//
uint32_t localRAMBuf[MEM_BUFFER_SIZE];
//
// Buffer in far memory.
//
__attribute__((far)) volatile uint32_t extSDRAMBuf[MEM_BUFFER_SIZE];
#pragma DATA_SECTION(localRAMBuf, "ramgs0");
//
// Function Prototypes
//
extern void setupEMIF1PinmuxSync16Bit(void);
void clearDataBuffer(uint32_t memSize);
uint16_t readWriteSyncMemory(uint32_t memSize);
//
// Main
//
void main(void)
{
uint16_t i;
uint16_t errCountLocal;
EMIF_SyncConfig sdConfig;
EMIF_SyncTimingParams tParam;
testStatusGlobal = TEST_FAIL;
//
// Initialize device clock and peripherals.
//
Device_init();
//
// Disable all the interrupts.
//
DINT;
//
// Setup GPIO by disabling pin locks and enabling pullups.
//
Device_initGPIO();
//
// This function initializes the PIE control registers. After globally
// disabling interrupts and enabling the PIE, it clears all of the PIE
// interrupt enable bits and interrupt flags.
//
Interrupt_initModule();
//
// Initializes the PIE vector table by setting all vectors to a default
// handler function.
//
Interrupt_initVectorTable();
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM).
//
EINT;
ERTM;
//
// Configure to run EMIF1 on half Rate. (EMIF1CLK = CPU1SYSCLK/2)
//
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_2);
//
// Disable Access Protection. (CPU_FETCH/CPU_WR/DMA_WR)
//
EMIF_setAccessProtection(EMIF1CONFIG_BASE, 0x0);
//
// Commit the configuration related to protection. Till this bit remains
// set content of EMIF1ACCPROT0 register can't be changed.
//
EMIF_commitAccessConfig(EMIF1CONFIG_BASE);
//
// Lock the configuration so that EMIF1COMMIT register can't be changed
// any more.
//
EMIF_lockAccessConfig(EMIF1CONFIG_BASE);
//
// Configure GPIO pins for EMIF1.
//
setupEMIF1PinmuxSync16Bit();
//
// Configure SDRAM control registers. Needs to be
// programmed based on SDRAM Data-Sheet. For this example:
// T_RFC = 60ns = 0x6; T_RP = 18ns = 0x1;
// T_RCD = 18ns = 0x1; T_WR = 1CLK + 6 ns = 0x1;
// T_RAS = 42ns = 0x4; T_RC = 60ns = 0x6;
// T_RRD = 12ns = 0x1.
//
tParam.tRfc = 0x6U;
tParam.tRp = 0x1U;
tParam.tRcd = 0x1U;
tParam.tWr = 0x1U;
tParam.tRas = 0x4U;
tParam.tRc = 0x6U;
tParam.tRrd = 0x1U;
EMIF_setSyncTimingParams(EMIF1_BASE, &tParam);
//
// Configure Self Refresh exit timing.
// Txsr = 70ns = 0x7.
//
EMIF_setSyncSelfRefreshExitTmng(EMIF1_BASE, 0x7U);
//
// Configure Refresh Rate.
// Tref = 64ms for 8192 ROW, RR = 64000*100(Tfrq)/8192 = 781.25 (0x30E).
//
EMIF_setSyncRefreshRate(EMIF1_BASE, 781);
//
// Configure SDRAM parameters. PAGESIZE=2 (1024 elements per ROW),
// IBANK = 2 (4 BANK), CL = 3, NM = 1 (16bit).
//
sdConfig.casLatency = EMIF_SYNC_CAS_LAT_3;
sdConfig.iBank = EMIF_SYNC_BANK_4;
sdConfig.narrowMode = EMIF_SYNC_NARROW_MODE_TRUE;
sdConfig.pageSize = EMIF_SYNC_COLUMN_WIDTH_10;
EMIF_setSyncMemoryConfig(EMIF1_BASE, &sdConfig);
//
// Adding some delay.
//
for(i = 0; i < 123; i++)
{
}
//
// Clear local and far memory buffers.
//
clearDataBuffer(MEM_BUFFER_SIZE);
//
// Basic read/write check.
//
errCountLocal = readWriteSyncMemory(MEM_BUFFER_SIZE);
errCountGlobal = errCountGlobal + errCountLocal;
if(errCountGlobal == 0x0)
{
testStatusGlobal = TEST_PASS;
}
//
// Checking total memory accesses.
//
uint32_t totAccess = EMIF_getSyncTotalAccesses(EMIF1_BASE);
uint32_t totActAccess = EMIF_getSyncTotalActivateAccesses(EMIF1_BASE);
while(1);
}
//
// Clear Data Buffer - This function clears the memory location of size memSize.
//
void clearDataBuffer(uint32_t memSize)
{
uint32_t i;
uint32_t memWdl = 0x0;
//
// Clear far memory buffer.
//
for(i=0; i < memSize; i++)
{
memcpy_fast_far((extSDRAMBuf + i), &memWdl, 2);
}
//
// Clear local memory buffer.
//
for(i = 0; i < memSize; i++)
{
localRAMBuf[i] = memWdl;
}
}
//
// Read Write Sync Memory - This function writes data into memory & verifies
// the written data.
//
uint16_t readWriteSyncMemory(uint32_t memSize)
{
uint32_t memWdl;
uint32_t i;
//
// Fill far memory buffer with data.
//
memWdl = 0x0;
for(i=0; i < memSize; i++)
{
memcpy_fast_far((extSDRAMBuf + i), &memWdl, 2);
memWdl += 0x00050001;
}
//
// Read far memory buffer into local buffer and verify data.
//
memWdl = 0x0;
for(i=0; i < memSize; i++)
{
memcpy_fast_far((localRAMBuf + i), (extSDRAMBuf + i), 2);
//
// Return error if read data is incorrect.
//
if(localRAMBuf[i] != memWdl)
{
return(1);
}
memWdl += 0x00050001;
}
return(0);
}
//
// End of File
//
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/emif_ex4_16bit_sdram_far_lpm.c
+461
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@@ -0,0 +1,461 @@
//#############################################################################
//
// FILE: emif_ex4_16bit_sdram_far_lpm.c
//
// TITLE: EMIF1 module accessing 16bit SDRAM & puts SDRAM into Self Refresh
// mode before entering Low Power mode.
//
//! \addtogroup driver_example_list
//! <h1> EMIF1 module accessing 16bit SDRAM then puts into Self Refresh
//! mode before entering Low Power Mode. </h1>
//!
//! This example configures EMIF1 in 16bit SYNC mode and uses CS0 as chip
//! enable. This example puts SDRAM into self refresh before entering standby
//! mode. Watchdog timer is configured to trigger WAKEINT interrupt.
//!
//! As soon as the watchdog timer expires, the device should wake up, SDRAM
//! should come out of self refresh mode and GPIO11 can be observed to toggle.
//!
//! \b External \b Connections \n
//! - External SDR-SDRAM memory (MT48LC32M16A2 -75) daughter card
//!
//! \b Watch \b Variables \n
//! - \b testStatusGlobal - Equivalent to \b TEST_PASS if test finished
//! correctly, else the value is set to \b TEST_FAIL
//! - \b errCountGlobal - Error counter
//!
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "device.h"
#include "driverlib.h"
//
// FPU header file to access memcpy_fast_far().
//
#include "fpu_vector.h"
//
// Defines
//
#define TEST_PASS 0xABCDABCD
#define TEST_FAIL 0xDEADDEAD
#define MEM_BUFFER_SIZE 0x500
//
// Globals
//
uint16_t errCountGlobal = 0;
uint32_t testStatusGlobal;
//
// Buffer in local memory.
//
uint32_t localRAMBuf[MEM_BUFFER_SIZE];
//
// Buffer in far memory.
//
__attribute__((far)) volatile uint32_t extSDRAMBuf[MEM_BUFFER_SIZE];
#pragma DATA_SECTION(localRAMBuf, "ramgs0");
//
// Function Prototypes
//
extern void setupEMIF1PinmuxSync16Bit(void);
void clearGlobalDataBuffer(uint32_t memSize);
void clearLocalDataBuffer(uint32_t memSize);
uint16_t readWriteSyncMemory(uint32_t memSize);
uint16_t readSyncMemory(uint32_t memSize);
//
// ISR for WAKEINT.
//
__interrupt void localWakeISR(void);
//
// Main
//
void main(void)
{
uint16_t i;
uint16_t errCountLocal;
EMIF_SyncConfig sdConfig;
EMIF_SyncTimingParams tParam;
testStatusGlobal = TEST_FAIL;
//
// Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks.
//
Device_init();
//
// Initialize GPIO:Disable pin locks and enable pullups.
//
Device_initGPIO();
//
// Configure GPIO11 as output.
//
GPIO_setPinConfig(GPIO_11_GPIO11);
GPIO_setDirectionMode(11, GPIO_DIR_MODE_OUT);
//
// Clear all interrupts.
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR). This will populate the entire table, even if
// the interrupt is not used in this example. This is useful for debug
// purposes.
//
Interrupt_initVectorTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
Interrupt_register(INT_WAKE,localWakeISR);
//
// Set Watchdog to generate Interrupt signal i.e. connect the Watchdog to
// WAKEINT interrupt of the PIE.
//
SysCtl_setWatchdogMode(SYSCTL_WD_MODE_INTERRUPT);
//
// Enable the device to wake from STANDBY mode upon a watchdog interrupt.
//
SysCtl_enableWatchdogStandbyWakeup();
//
// Enables WAKEINT in the PIE: Group 1 interrupt 8 & in CPU.
//
Interrupt_enable(INT_WAKE);
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
//
// EMIF Configurations:
// Configure to run EMIF1 on half Rate. (EMIF1CLK = CPU1SYSCLK/2)
//
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_2);
//
// Disable Access Protection. (CPU_FETCH/CPU_WR/DMA_WR)
//
EMIF_setAccessProtection(EMIF1CONFIG_BASE, 0x0);
//
// Commit the configuration related to protection. Till this bit remains
// set, contents of EMIF1ACCPROT0 register can't be changed.
//
EMIF_commitAccessConfig(EMIF1CONFIG_BASE);
//
// Lock the configuration so that EMIF1COMMIT register can't be changed
// any more.
//
EMIF_lockAccessConfig(EMIF1CONFIG_BASE);
//
// Configure GPIO pins for EMIF1.
//
setupEMIF1PinmuxSync16Bit();
//
// Configure SDRAM control registers. Needs to be programmed
// based on SDRAM Data-Sheet. For this example:
// T_RFC = 60ns = 0x6; T_RP = 18ns = 0x1;
// T_RCD = 18ns = 0x1; T_WR = 1CLK + 6 ns = 0x1;
// T_RAS = 42ns = 0x4; T_RC = 60ns = 0x6;
// T_RRD = 12ns = 0x1.
//
tParam.tRfc = 0x6U;
tParam.tRp = 0x1U;
tParam.tRcd = 0x1U;
tParam.tWr = 0x1U;
tParam.tRas = 0x4U;
tParam.tRc = 0x6U;
tParam.tRrd = 0x1U;
EMIF_setSyncTimingParams(EMIF1_BASE, &tParam);
//
// Configure Self Refresh exit timing.
// Txsr = 70ns = 0x7.
//
EMIF_setSyncSelfRefreshExitTmng(EMIF1_BASE, 0x7U);
//
// Configure Refresh Rate.
// Tref = 64ms for 8192 ROW, RR = 64000*100(Tfrq)/8192 = 781.25 (0x30E).
//
EMIF_setSyncRefreshRate(EMIF1_BASE, 781);
//
// Configure SDRAM parameters. PAGESIZE=2 (1024 elements per ROW),
// IBANK = 2 (4 BANK), CL = 3, NM = 1 (16bit).
//
sdConfig.casLatency = EMIF_SYNC_CAS_LAT_3;
sdConfig.iBank = EMIF_SYNC_BANK_4;
sdConfig.narrowMode = EMIF_SYNC_NARROW_MODE_TRUE;
sdConfig.pageSize = EMIF_SYNC_COLUMN_WIDTH_10;
EMIF_setSyncMemoryConfig(EMIF1_BASE, &sdConfig);
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM).
//
EINT;
ERTM;
//
// Adding some delay.
//
for(i = 0; i < 123; i++)
{
}
//
// Clear local and far memory buffers.
//
clearLocalDataBuffer(MEM_BUFFER_SIZE);
clearGlobalDataBuffer(MEM_BUFFER_SIZE);
//
// Basic read/write check.
//
errCountLocal = readWriteSyncMemory(MEM_BUFFER_SIZE);
errCountGlobal = errCountGlobal + errCountLocal;
if(errCountGlobal == 0x0)
{
testStatusGlobal = TEST_PASS;
}
//
// Enable Self Refresh for SDRAM.
//
EMIF_enableSyncSelfRefresh(EMIF1_BASE);
//
// Enable Watchdog Timer.
//
SysCtl_enableWatchdog();
//
// Reset Watchdog counter.
//
SysCtl_serviceWatchdog();
//
// Enter STANDBY mode.
//
SysCtl_enterStandbyMode();
//
// Disable Watchdog Timer.
//
SysCtl_disableWatchdog();
while(1);
}
//
// Clear Global Data Buffer - This function clears global memory buffers.
//
void clearGlobalDataBuffer(uint32_t memSize)
{
uint32_t i;
uint32_t memWdl = 0x0;
//
// Clear far memory buffer.
//
for(i=0; i < memSize; i++)
{
memcpy_fast_far((extSDRAMBuf + i), &memWdl, 2);
}
}
//
// Clear Local Data Buffer - This function clears the local memory buffer.
//
void clearLocalDataBuffer(uint32_t memSize)
{
uint32_t i;
uint32_t memWdl = 0x0;
//
// Clear local memory buffer.
//
for(i = 0; i < memSize; i++)
{
localRAMBuf[i] = memWdl;
}
}
//
// Read Write Sync Memory - This function writes data into memory & reads the
// written data.
//
uint16_t readWriteSyncMemory(uint32_t memSize)
{
uint32_t memWdl;
uint32_t i;
//
// Fill far memory buffer with data.
//
memWdl = 0x0;
for(i=0; i < memSize; i++)
{
memcpy_fast_far((extSDRAMBuf + i), &memWdl, 2);
memWdl += 0x00050001;
}
//
// Read far memory buffer into local buffer and verify data.
//
memWdl = 0x0;
for(i=0; i < memSize; i++)
{
memcpy_fast_far((localRAMBuf + i), (extSDRAMBuf + i), 2);
//
// Return error if read data is incorrect.
//
if(localRAMBuf[i] != memWdl)
{
return(1);
}
memWdl += 0x00050001;
}
return(0);
}
//
// Read Sync Memory - This function reads the memory data & verify if its
// similar to previously written data.
//
uint16_t readSyncMemory(uint32_t memSize)
{
uint32_t memWdl;
uint32_t i;
//
// Read far memory buffer into local buffer and verify data.
//
memWdl = 0x0;
for(i = 0; i < memSize; i++)
{
memcpy_fast_far((localRAMBuf + i), (extSDRAMBuf + i), 2);
//
// Return error if read data is incorrect.
//
if(localRAMBuf[i] != memWdl)
{
return(1);
}
memWdl += 0x00050001;
}
return(0);
}
//
// Local Wake ISR - ISR for WAKEINT Interrupt.
//
interrupt void localWakeISR(void)
{
uint16_t i;
uint16_t errCountLocal;
testStatusGlobal = TEST_FAIL;
//
// Disable Self Refresh mode in SDRAM.
//
EMIF_disableSyncSelfRefresh(EMIF1_BASE);
//
// Adding some delay.
//
for(i = 0; i < 123; i++)
{
}
//
// Clear local memory buffers.
//
clearLocalDataBuffer(MEM_BUFFER_SIZE);
//
// Verifying contents of memory on exiting
// self refresh mode.
//
errCountLocal = readSyncMemory(MEM_BUFFER_SIZE);
errCountGlobal = errCountGlobal + errCountLocal;
if(errCountGlobal == 0x0)
{
testStatusGlobal = TEST_PASS;
}
//
// GPIO11 is driven high upon exiting STANDBY.
//
GPIO_writePin(11, 0x1);
//
// Acknowledge the interrupt.
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
}
//
// End of File
//
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/emif_ex5_16bit_sdram_dma.c
+412
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@@ -0,0 +1,412 @@
//#############################################################################
//
// FILE: emif_ex5_16bit_sdram_dma.c
//
// TITLE: EMIF1 module accessing 32bit SDRAM using DMA.
//
//! \addtogroup driver_example_list
//! <h1> EMIF1 module accessing 32bit SDRAM using DMA. </h1>
//!
//! This example configures EMIF1 in 16bit SYNC(SDRAM) mode and uses CS0
//! as chip enable. It will first write to an array in the SDRAM and then
//! read it back, using the DMA for both operations.
//!
//! The buffer in SDRAM will be placed in the .farbss memory on account
//! of the fact that its assigned the attribute "far" indicating it lies
//! beyond the 22-bit program address space. The compiler will take care
//! to avoid using instructions such as PREAD, which uses the Program
//! Read Bus, or addressing modes restricted to the lower 22-bit space
//! when accessing data with the attribute "far".
//!
//! \note The memory space beyond 22-bits must be treated as data space
//! for load/store operations only. The user is cautioned against using
//! this space for either instructions or working memory.
//!
//! \b External \b Connections \n
//! - External SDR-SDRAM (Micron MT48LC32M16A2 "P -75 C") daughter card.
//!
//! \b Watch \b Variables \n
//! - \b testStatusGlobal - Equivalent to \b TEST_PASS if test finished
//! correctly, else the value is set to \b TEST_FAIL
//! - \b errCountGlobal - Error counter
//!
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "device.h"
#include "driverlib.h"
//
// Defines
//
#define TEST_PASS 0xABCDABCD
#define TEST_FAIL 0xDEADDEAD
//
// Considering 32-bit word. Total 0x800 memory locations read/written.
//
#define MEM_BUFFER_SIZE 0x400
//
// Globals
//
uint16_t errCountGlobal = 0;
uint32_t testStatusGlobal;
volatile uint32_t initData = 0;
volatile uint32_t *destDMA;
volatile uint32_t *srcDMA;
//
// Buffer in local memory.
//
uint32_t localSrcRAMBuf[MEM_BUFFER_SIZE];
uint32_t localDstRAMBuf[MEM_BUFFER_SIZE];
//
// Buffer in far memory.
//
__attribute__((far)) volatile uint32_t extSDRAMBuf[MEM_BUFFER_SIZE];
#pragma DATA_SECTION(localSrcRAMBuf, "ramgs0");
#pragma DATA_SECTION(localDstRAMBuf, "ramgs1");
//
// Function Prototypes
//
extern void setupEMIF1PinmuxSync16Bit(void);
void clearDestDataBuffer(uint32_t memSize);
void configDMAChannel1(void);
void configDMAChannel2(void);
//
// Main
//
void main(void)
{
uint16_t i;
EMIF_SyncConfig sdConfig;
EMIF_SyncTimingParams tParam;
testStatusGlobal = TEST_FAIL;
//
// Initialize device clock and peripherals.
//
Device_init();
//
// Disable all the interrupts.
//
DINT;
//
// Setup GPIO by disabling pin locks and enabling pullups.
//
Device_initGPIO();
//
// This function initializes the PIE control registers. After globally
// disabling interrupts and enabling the PIE, it clears all of the PIE
// interrupt enable bits and interrupt flags.
//
Interrupt_initModule();
//
// Initializes the PIE vector table by setting all vectors to a default
// handler function.
//
Interrupt_initVectorTable();
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM).
//
EINT;
ERTM;
//
// Configure to run EMIF1 on half Rate (EMIF1CLK = CPU1SYSCLK/2).
//
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_2);
//
// Disable Access Protection (CPU_FETCH/CPU_WR/DMA_WR).
//
EMIF_setAccessProtection(EMIF1CONFIG_BASE, 0x0);
//
// Commit the configuration related to protection. Till this bit remains
// set content of EMIF1ACCPROT0 register can't be changed.
//
EMIF_commitAccessConfig(EMIF1CONFIG_BASE);
//
// Lock the configuration so that EMIF1COMMIT register can't be changed
// any more.
//
EMIF_lockAccessConfig(EMIF1CONFIG_BASE);
//
// Initialize source buffer for DMA transfer.
//
initData = 0x12103456;
for(i = 0; i < MEM_BUFFER_SIZE; i++)
{
initData = initData + 0x11111111;
localSrcRAMBuf[i] = initData;
}
//
// Initialize DMA.
//
DMA_initController();
//
// Configure channel 1 for writing into external memory & channel 2 for
// reading from the external memory.
//
configDMAChannel1();
configDMAChannel2();
//
// Start DMA channels 1 & 2.
//
DMA_startChannel(DMA_CH1_BASE);
DMA_startChannel(DMA_CH2_BASE);
//
// Configure GPIO pins for EMIF1.
//
setupEMIF1PinmuxSync16Bit();
//
// Configure SDRAM control registers. Needs to be
// programmed based on SDRAM Data-Sheet. For this example:
// T_RFC = 60ns = 0x6; T_RP = 18ns = 0x1;
// T_RCD = 18ns = 0x1; T_WR = 1CLK + 6 ns = 0x1;
// T_RAS = 42ns = 0x4; T_RC = 60ns = 0x6;
// T_RRD = 12ns = 0x1.
//
tParam.tRfc = 0x6U;
tParam.tRp = 0x1U;
tParam.tRcd = 0x1U;
tParam.tWr = 0x1U;
tParam.tRas = 0x4U;
tParam.tRc = 0x6U;
tParam.tRrd = 0x1U;
EMIF_setSyncTimingParams(EMIF1_BASE, &tParam);
//
// Configure Self Refresh exit timing.
// Txsr = 70ns = 0x7.
//
EMIF_setSyncSelfRefreshExitTmng(EMIF1_BASE, 0x7U);
//
// Configure Refresh Rate.
// Tref = 64ms for 8192 ROW, RR = 64000*100(Tfrq)/8192 = 781.25 (0x30E).
//
EMIF_setSyncRefreshRate(EMIF1_BASE, 781);
//
// Configure SDRAM parameters. PAGESIZE=2 (1024 elements per ROW),
// IBANK = 2 (4 BANK), CL = 3, NM = 1 (16bit).
//
sdConfig.casLatency = EMIF_SYNC_CAS_LAT_3;
sdConfig.iBank = EMIF_SYNC_BANK_4;
sdConfig.narrowMode = EMIF_SYNC_NARROW_MODE_TRUE;
sdConfig.pageSize = EMIF_SYNC_COLUMN_WIDTH_10;
EMIF_setSyncMemoryConfig(EMIF1_BASE, &sdConfig);
//
// Adding some delay.
//
for(i = 0; i < 123; i++)
{
}
//
// Clear destination data buffers.
//
clearDestDataBuffer(MEM_BUFFER_SIZE);
//
// Write to External Memory(16-bit).
//
DMA_forceTrigger(DMA_CH1_BASE);
EALLOW;
while((HWREGH(DMA_CH1_BASE + DMA_O_CONTROL) &
DMA_CONTROL_TRANSFERSTS) != 0x0U);
EDIS;
//
// Read from External Memory(32-bit).
//
DMA_forceTrigger(DMA_CH2_BASE);
EALLOW;
while((HWREGH(DMA_CH2_BASE + DMA_O_CONTROL) &
DMA_CONTROL_TRANSFERSTS) != 0x0U);
EDIS;
//
// Compare source & destination local buffer data.
//
for(i = 0; i < MEM_BUFFER_SIZE; i++)
{
if(localSrcRAMBuf[i] != localDstRAMBuf[i])
{
errCountGlobal++;
}
}
if(errCountGlobal == 0x0)
{
testStatusGlobal = TEST_PASS;
}
while(1);
}
//
// Clear Dest Data Buffer - This function clears the destination memory
// location of size memSize.
//
void clearDestDataBuffer(uint32_t memSize)
{
uint32_t i;
uint32_t memWdl = 0x0;
//
// Clear far memory buffer.
//
for(i=0; i < memSize; i++)
{
__addr32_write_uint32((uint32_t)(extSDRAMBuf + (i*2)), 0x0);
}
//
// Clear local memory buffer.
//
for(i = 0; i < memSize; i++)
{
localDstRAMBuf[i] = memWdl;
}
}
//
// Configure DMA Channel 1 - This function configures the DMA channel 1 for
// writing to external SDRAM memory.
//
void configDMAChannel1()
{
//
// Configure DMA Channel 1 (16 - bit datasize).
//
destDMA = extSDRAMBuf;
srcDMA = (volatile uint32_t *)localSrcRAMBuf;
DMA_configAddresses(DMA_CH1_BASE,(const void*)destDMA,(const void*)srcDMA);
DMA_configBurst(DMA_CH1_BASE, 32U, 1U, 1U);
DMA_configTransfer(DMA_CH1_BASE, ((MEM_BUFFER_SIZE * 2) / 32), 1, 1);
DMA_configWrap(DMA_CH1_BASE, 0x10000U, 0, 0x10000U, 0);
//
// Configure DMA trigger source as software, enable oneshot, disable
// continuous mode, data size of DMA transfer to 16 bits.
//
DMA_configMode(DMA_CH1_BASE, DMA_TRIGGER_SOFTWARE, (DMA_CFG_ONESHOT_ENABLE
| DMA_CFG_CONTINUOUS_DISABLE | DMA_CFG_SIZE_16BIT));
//
// Enable selected peripheral trigger to start a DMA transfer on DMA
// channel 1.
//
DMA_enableTrigger(DMA_CH1_BASE);
//
// Clear any spurious Peripheral interrupts flags.
//
DMA_clearTriggerFlag(DMA_CH1_BASE);
//
// Clear any spurious sync error flags.
//
DMA_clearErrorFlag(DMA_CH1_BASE);
}
//
// Configure DMA Channel 2-This function configures the DMA channel 2 for
// reading from external SDRAM memory.
//
void configDMAChannel2()
{
//
// Configure DMA channel 2.
//
destDMA = (volatile uint32_t *)localDstRAMBuf;
srcDMA = extSDRAMBuf;
DMA_configAddresses(DMA_CH2_BASE,(const void*)destDMA,(const void*)srcDMA);
DMA_configBurst(DMA_CH2_BASE, 32U, 2U, 2U);
DMA_configTransfer(DMA_CH2_BASE, ((MEM_BUFFER_SIZE * 2) / 32), 2, 2);
DMA_configWrap(DMA_CH2_BASE, 0x10000U, 0, 0x10000U, 0);
//
// Configure DMA trigger source as software, enable oneshot, disable
// continuous mode, data size of DMA transfer to 16 bits.
//
DMA_configMode(DMA_CH2_BASE, DMA_TRIGGER_SOFTWARE, (DMA_CFG_ONESHOT_ENABLE
| DMA_CFG_CONTINUOUS_DISABLE | DMA_CFG_SIZE_32BIT));
//
// Enable selected peripheral trigger to start a DMA transfer on DMA
// channel 2.
//
DMA_enableTrigger(DMA_CH2_BASE);
//
// Clear any spurious Peripheral interrupts flags.
//
DMA_clearTriggerFlag(DMA_CH2_BASE);
//
// Clear any spurious sync error flags.
//
DMA_clearErrorFlag(DMA_CH2_BASE);
}
//
// End of File
//
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/emif_sdram_pin_setup.c
+337
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@@ -0,0 +1,337 @@
//#############################################################################
//
// FILE: emif_sdram_pin_setup.c
//
// TITLE: EMIF module accessing SDRAM.
//
// This example configure pins for EMIF in SYNC mode.
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include <stdint.h>
#include "device.h"
#include "driverlib.h"
#ifdef CPU1
//
// Function Prototypes
//
void setupEMIF1PinmuxSync16Bit(void);
void setupEMIF2PinmuxSync16Bit(void);
void setupEMIF1PinmuxSync32Bit(void);
#endif
//
// Setup EMIF1 Pinmux Sync 16Bit - This function configures pins for 16bit
// Synchronous EMIF1.
//
void setupEMIF1PinmuxSync16Bit(void)
{
uint16_t i;
GPIO_setPinConfig(GPIO_29_EM1SDCKE);
GPIO_setPinConfig(GPIO_30_EM1CLK);
GPIO_setPinConfig(GPIO_31_EM1WEN);
GPIO_setPinConfig(GPIO_32_EM1CS0N);
GPIO_setPinConfig(GPIO_33_EM1RNW);
GPIO_setPinConfig(GPIO_34_EM1CS2N);
GPIO_setPinConfig(GPIO_35_EM1CS3N);
GPIO_setPinConfig(GPIO_36_EM1WAIT);
GPIO_setPinConfig(GPIO_37_EM1OEN);
//
// Selecting address lines.
//
GPIO_setPinConfig(GPIO_38_EM1A0);
GPIO_setPinConfig(GPIO_39_EM1A1);
GPIO_setPinConfig(GPIO_40_EM1A2);
GPIO_setPinConfig(GPIO_41_EM1A3);
GPIO_setPinConfig(GPIO_44_EM1A4);
GPIO_setPinConfig(GPIO_45_EM1A5);
GPIO_setPinConfig(GPIO_46_EM1A6);
GPIO_setPinConfig(GPIO_47_EM1A7);
GPIO_setPinConfig(GPIO_48_EM1A8);
GPIO_setPinConfig(GPIO_49_EM1A9);
GPIO_setPinConfig(GPIO_50_EM1A10);
GPIO_setPinConfig(GPIO_51_EM1A11);
GPIO_setPinConfig(GPIO_52_EM1A12);
//
// Selecting Data Lines.
//
GPIO_setPinConfig(GPIO_69_EM1D15);
GPIO_setPinConfig(GPIO_70_EM1D14);
GPIO_setPinConfig(GPIO_71_EM1D13);
GPIO_setPinConfig(GPIO_72_EM1D12);
GPIO_setPinConfig(GPIO_73_EM1D11);
GPIO_setPinConfig(GPIO_74_EM1D10);
GPIO_setPinConfig(GPIO_75_EM1D9);
GPIO_setPinConfig(GPIO_76_EM1D8);
GPIO_setPinConfig(GPIO_77_EM1D7);
GPIO_setPinConfig(GPIO_78_EM1D6);
GPIO_setPinConfig(GPIO_79_EM1D5);
GPIO_setPinConfig(GPIO_80_EM1D4);
GPIO_setPinConfig(GPIO_81_EM1D3);
GPIO_setPinConfig(GPIO_82_EM1D2);
GPIO_setPinConfig(GPIO_83_EM1D1);
GPIO_setPinConfig(GPIO_85_EM1D0);
//
// Selecting RAS & CAS.
//
GPIO_setPinConfig(GPIO_86_EM1CAS);
GPIO_setPinConfig(GPIO_87_EM1RAS);
//
// Selecting DQM and Bank Select Lines.
//
GPIO_setPinConfig(GPIO_88_EM1DQM0);
GPIO_setPinConfig(GPIO_89_EM1DQM1);
GPIO_setPinConfig(GPIO_90_EM1DQM2);
GPIO_setPinConfig(GPIO_91_EM1DQM3);
GPIO_setPinConfig(GPIO_92_EM1BA1);
GPIO_setPinConfig(GPIO_93_EM1BA0);
//
// Configure Data pins for Async mode.
//
for(i = 69;i <= 85;i++)
{
if(i != 84)
{
GPIO_setPadConfig(i, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(i, GPIO_QUAL_ASYNC);
}
}
for(i = 88; i <= 91; i++)
{
GPIO_setPadConfig(i, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(i, GPIO_QUAL_ASYNC);
}
}
//
// Setup EMIF2 Pinmux Sync 16Bit - This function configures pins for 16bit
// Synchronous EMIF2.
//
void setupEMIF2PinmuxSync16Bit(void)
{
uint16_t i;
//
// Selecting Data lines.
//
GPIO_setPinConfig(GPIO_53_EM2D15);
GPIO_setPinConfig(GPIO_54_EM2D14);
GPIO_setPinConfig(GPIO_55_EM2D13);
GPIO_setPinConfig(GPIO_56_EM2D12);
GPIO_setPinConfig(GPIO_57_EM2D11);
GPIO_setPinConfig(GPIO_58_EM2D10);
GPIO_setPinConfig(GPIO_59_EM2D9);
GPIO_setPinConfig(GPIO_60_EM2D8);
GPIO_setPinConfig(GPIO_61_EM2D7);
GPIO_setPinConfig(GPIO_62_EM2D6);
GPIO_setPinConfig(GPIO_63_EM2D5);
GPIO_setPinConfig(GPIO_64_EM2D4);
GPIO_setPinConfig(GPIO_65_EM2D3);
GPIO_setPinConfig(GPIO_66_EM2D2);
GPIO_setPinConfig(GPIO_67_EM2D1);
GPIO_setPinConfig(GPIO_68_EM2D0);
//
// Selecting DQM lines.
//
GPIO_setPinConfig(GPIO_96_EM2DQM1);
GPIO_setPinConfig(GPIO_97_EM2DQM0);
//
// Selecting Address lines.
//
GPIO_setPinConfig(GPIO_98_EM2A0);
GPIO_setPinConfig(GPIO_99_EM2A1);
GPIO_setPinConfig(GPIO_100_EM2A2);
GPIO_setPinConfig(GPIO_101_EM2A3);
GPIO_setPinConfig(GPIO_102_EM2A4);
GPIO_setPinConfig(GPIO_103_EM2A5);
GPIO_setPinConfig(GPIO_104_EM2A6);
GPIO_setPinConfig(GPIO_105_EM2A7);
GPIO_setPinConfig(GPIO_106_EM2A8);
GPIO_setPinConfig(GPIO_107_EM2A9);
GPIO_setPinConfig(GPIO_108_EM2A10);
GPIO_setPinConfig(GPIO_109_EM2A11);
//
// Selecting extended wait, bank select, CAS, RAS
// chip select, clock enable, read enable, write
// enable & output enable lines.
//
GPIO_setPinConfig(GPIO_110_EM2WAIT);
GPIO_setPinConfig(GPIO_111_EM2BA0);
GPIO_setPinConfig(GPIO_112_EM2BA1);
GPIO_setPinConfig(GPIO_113_EM2CAS);
GPIO_setPinConfig(GPIO_114_EM2RAS);
GPIO_setPinConfig(GPIO_115_EM2CS0N);
GPIO_setPinConfig(GPIO_116_EM2CS2N);
GPIO_setPinConfig(GPIO_117_EM2SDCKE);
GPIO_setPinConfig(GPIO_118_EM2CLK);
GPIO_setPinConfig(GPIO_119_EM2RNW);
GPIO_setPinConfig(GPIO_120_EM2WEN);
GPIO_setPinConfig(GPIO_121_EM2OEN);
//
// Configure Data pins for Async mode.
//
for(i = 53;i <= 68;i++)
{
GPIO_setPadConfig(i, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(i, GPIO_QUAL_ASYNC);
}
}
//
// Setup EMIF1 Pinmux Sync 32Bit - This function configures pins for 32bit
// Synchronous EMIF1.
//
void setupEMIF1PinmuxSync32Bit(void)
{
uint16_t i;
GPIO_setPinConfig(GPIO_28_EM1CS4N);
GPIO_setPinConfig(GPIO_29_EM1SDCKE);
GPIO_setPinConfig(GPIO_30_EM1CLK);
GPIO_setPinConfig(GPIO_31_EM1WEN);
GPIO_setPinConfig(GPIO_32_EM1CS0N);
GPIO_setPinConfig(GPIO_33_EM1RNW);
GPIO_setPinConfig(GPIO_34_EM1CS2N);
GPIO_setPinConfig(GPIO_35_EM1CS3N);
GPIO_setPinConfig(GPIO_36_EM1WAIT);
GPIO_setPinConfig(GPIO_37_EM1OEN);
//
// Selecting address lines.
//
GPIO_setPinConfig(GPIO_38_EM1A0);
GPIO_setPinConfig(GPIO_39_EM1A1);
GPIO_setPinConfig(GPIO_40_EM1A2);
GPIO_setPinConfig(GPIO_41_EM1A3);
GPIO_setPinConfig(GPIO_44_EM1A4);
GPIO_setPinConfig(GPIO_45_EM1A5);
GPIO_setPinConfig(GPIO_46_EM1A6);
GPIO_setPinConfig(GPIO_47_EM1A7);
GPIO_setPinConfig(GPIO_48_EM1A8);
GPIO_setPinConfig(GPIO_49_EM1A9);
GPIO_setPinConfig(GPIO_50_EM1A10);
GPIO_setPinConfig(GPIO_51_EM1A11);
GPIO_setPinConfig(GPIO_52_EM1A12);
//
// Selecting data lines.
//
GPIO_setPinConfig(GPIO_53_EM1D31);
GPIO_setPinConfig(GPIO_54_EM1D30);
GPIO_setPinConfig(GPIO_55_EM1D29);
GPIO_setPinConfig(GPIO_56_EM1D28);
GPIO_setPinConfig(GPIO_57_EM1D27);
GPIO_setPinConfig(GPIO_58_EM1D26);
GPIO_setPinConfig(GPIO_59_EM1D25);
GPIO_setPinConfig(GPIO_60_EM1D24);
GPIO_setPinConfig(GPIO_61_EM1D23);
GPIO_setPinConfig(GPIO_62_EM1D22);
GPIO_setPinConfig(GPIO_63_EM1D21);
GPIO_setPinConfig(GPIO_64_EM1D20);
GPIO_setPinConfig(GPIO_65_EM1D19);
GPIO_setPinConfig(GPIO_66_EM1D18);
GPIO_setPinConfig(GPIO_67_EM1D17);
GPIO_setPinConfig(GPIO_68_EM1D16);
GPIO_setPinConfig(GPIO_69_EM1D15);
GPIO_setPinConfig(GPIO_70_EM1D14);
GPIO_setPinConfig(GPIO_71_EM1D13);
GPIO_setPinConfig(GPIO_72_EM1D12);
GPIO_setPinConfig(GPIO_73_EM1D11);
GPIO_setPinConfig(GPIO_74_EM1D10);
GPIO_setPinConfig(GPIO_75_EM1D9);
GPIO_setPinConfig(GPIO_76_EM1D8);
GPIO_setPinConfig(GPIO_77_EM1D7);
GPIO_setPinConfig(GPIO_78_EM1D6);
GPIO_setPinConfig(GPIO_79_EM1D5);
GPIO_setPinConfig(GPIO_80_EM1D4);
GPIO_setPinConfig(GPIO_81_EM1D3);
GPIO_setPinConfig(GPIO_82_EM1D2);
GPIO_setPinConfig(GPIO_83_EM1D1);
GPIO_setPinConfig(GPIO_85_EM1D0);
//
// Selecting RAS, CAS, DQM & Bank select lines.
//
GPIO_setPinConfig(GPIO_86_EM1CAS);
GPIO_setPinConfig(GPIO_87_EM1RAS);
GPIO_setPinConfig(GPIO_88_EM1DQM0);
GPIO_setPinConfig(GPIO_89_EM1DQM1);
GPIO_setPinConfig(GPIO_90_EM1DQM2);
GPIO_setPinConfig(GPIO_91_EM1DQM3);
GPIO_setPinConfig(GPIO_92_EM1BA1);
GPIO_setPinConfig(GPIO_93_EM1BA0);
GPIO_setPinConfig(GPIO_94_EM1A21);
//
// Configure Data pins for Async mode.
//
for(i = 53;i <= 85;i++)
{
if(i != 84)
{
GPIO_setPadConfig(i, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(i, GPIO_QUAL_ASYNC);
}
}
for(i = 88; i <= 91; i++)
{
GPIO_setPadConfig(i, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(i, GPIO_QUAL_ASYNC);
}
}
//
// End of File
//
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/fpu_types.h
+75
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//###########################################################################
//
// FILE: fpu_types.h
//
// TITLE: Prototypes and Definitions for the C28x FPU Library
//
//###########################################################################
//
//
// $Copyright:
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef _FPU_TYPES_H_
#define _FPU_TYPES_H_
#include <stdint.h>
#include "float.h"
#ifdef __cplusplus
extern "C" {
#endif
//-----------------------------------------------------------------------------
// Type Definitions
//-----------------------------------------------------------------------------
#ifndef FPU_TYPES
#define FPU_TYPES
// Complex Float Data Type
typedef struct {
float dat[2];
} complex_float;
#endif //FPU_TYPES
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of _FPU_TYPES_H_
//===========================================================================
// End of file.
//===========================================================================
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/fpu_vector.h
+467
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@@ -0,0 +1,467 @@
//###########################################################################
//
// FILE: fpu_vector.h
//
// TITLE: Prototypes and Definitions for the C28x FPU Library
//
//###########################################################################
//
// $Release Date: $
// $Copyright:
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef _FPU_VECTOR_H_
#define _FPU_VECTOR_H_
#include "fpu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
//-----------------------------------------------------------------------------
// Definitions and Prototypes
//-----------------------------------------------------------------------------
#ifdef _TMS320C28XX_TMU0__
#define abs_SP_CV abs_SP_CV_TMU0
#define iabs_SP_CV iabs_SP_CV_TMU0
#else
#define abs_SP_CV abs_SP_CV
#define iabs_SP_CV iabs_SP_CV
#endif //_TMS320C28XX_TMU0__
// \brief Absolute Value of a Complex Vector.
//
// This module computes the absolute value of a complex vector. If N is even,
// use abs_SP_CV_2() for better performance.
// \f[y[i]&=& \sqrt(x_{re}[i]^{2} + x_{im}[i]^{2}) \f]
// \param y pointer to the output vector
// \param x pointer to the input vector
// \param N length of the x and y vectors
//
extern void abs_SP_CV(volatile float *y, volatile const complex_float *x, const uint16_t N);
// \brief Absolute Value of an Even Length Complex Vector.
//
// This module computes the absolute value of an even length complex vector.
// \f[ y[i]&=& \sqrt(x_{re}[i]^{2} + x_{im}[i]^{2})\f]
// \param y pointer to the output vector
// \param x pointer to the input vector
// \param N length of the x and y vectors
// \attention N must be even
//
extern void abs_SP_CV_2(volatile float *y, volatile const complex_float *x, const uint16_t N);
// \brief Absolute Value of a Complex Vector (TMU0).
//
// This module computes the absolute value of a complex vector. It uses
// the TMU Type 0 accelerator to speed up the calculation of square roots.
// \f[y[i]&=& \sqrt(x_{re}[i]^{2} + x_{im}[i]^{2}) \f]
// \param y pointer to the output vector
// \param x pointer to the input vector
// \param N length of the x and y vectors
// \attention
// -# This function is optimized for N>=8. It is less cycle efficient
// when N<8. For very small N (e.g., N=1, 2, maybe 3) the user might
// consider using the TMU intrinsics in the compiler instead of this
// function.
//
extern void abs_SP_CV_TMU0(volatile float *y, volatile const complex_float *x, const uint16_t N);
// \brief Addition (Element-Wise) of a Complex Scalar to a Complex Vector.
//
// This module adds a complex scalar element-wise to a complex vector.
// \f[y_{re}[i]&=& x_{re}[i] + c_{re}\f]
// \f[y_{im}[i]&=& x_{im}[i] + c_{im}\f]
// \param y pointer to the complex output vector
// \param x pointer to the complex input vector
// \param c pointer to the complex input scalar
// \param N length of the x and y vectors
//
extern void add_SP_CSxCV(volatile complex_float *y, volatile const complex_float *x, const complex_float c, const uint16_t N);
// \brief Addition of Two Complex Vectors.
//
// This module adds two complex vectors.
// \f[y_{re}[i]&=& w_{re}[i] + x_{re}[i]\f]
// \f[y_{im}[i]&=& w_{im}[i] + x_{im}[i]\f]
// \param y pointer to the complex output vector
// \param w pointer to the first complex input vector
// \param x pointer to the second complex input vector
// \param N length of the w, x and y vectors
//
extern void add_SP_CVxCV(volatile complex_float *y, volatile const complex_float *w, volatile const complex_float *x, const uint16_t N);
// \brief Inverse Absolute Value of a Complex Vector.
//
// This module computes the inverse absolute value of a complex vector.
// \f[y[i]&=& \frac{1}{\sqrt(x_{re}[i]^{2} + x_{im}[i]^{2})}\f]
// \param y pointer to the output vector
// \param x pointer to the input vector
// \param N length of the x and y vectors
// \attention N must be at least 2
//
extern void iabs_SP_CV(volatile float *y, volatile const complex_float *x, const uint16_t N);
// \brief Inverse Absolute Value of an Even Length Complex Vector.
//
// This module calculates the inverse absolute value of an even
// length complex vector.
// \f[y[i]&=& \frac{1}{\sqrt(x_{re}[i]^{2} + x_{im}[i]^{2})}\f]
// \param y pointer to the output vector
// \param x pointer to the input vector
// \param N length of the x and y vectors
// \attention N must be even
//
extern void iabs_SP_CV_2(volatile float *y, volatile const complex_float *x, const uint16_t N);
// \brief Inverse Absolute Value of a Complex Vector (TMU0).
//
// This module computes the inverse absolute value of a complex vector.
// It uses the TMU Type 0 accelerator to speed up the calculation
// of square roots.
// \f[y[i]&=& \frac{1}{\sqrt(x_{re}[i]^{2} + x_{im}[i]^{2})}\f]
// \param y pointer to the output vector
// \param x pointer to the input vector
// \param N length of the x and y vectors
// \attention
// -# This function is optimized for N>=8. It is less cycle efficient
// when N<8. For very small N (e.g., N=1, 2, maybe 3) the user might
// consider using the TMU intrinsics in the compiler instead of this
// function.
//
extern void iabs_SP_CV_TMU0(volatile float *y, volatile const complex_float *x, const uint16_t N);
// \brief Index of Maximum Value of an Even Length Real Array.
//
// \param x pointer to the input vector
// \param N length of the x vector
// \attention
// -# N must be even
// -# If more than one instance of the max value exists in x[], the
// function will return the index of the first occurrence (lowest index
// value)
//
extern uint16_t maxidx_SP_RV_2(volatile float *x, uint16_t N);
// \brief Mean of Real and Imaginary Parts of a Complex Vector.
//
// This module calculates the mean of real and imaginary parts of a
// complex vector.
// \f[y_{re} &=& \frac{\Sigma x_{re}}{N} \f]
// \f[y_{im} &=& \frac{\Sigma x_{im}}{N} \f]
// \param x pointer to the input vector
// \param N length of the x vector
// \attention N must be even and a minimum of 4
//
extern complex_float mean_SP_CV_2(volatile const complex_float *x, const uint16_t N);
// \brief Median of a Real Valued Array of Floats (Preserved Inputs).
//
// This module computes the median of a real valued array of
// floats. The input array is preserved. If input array preservation is not required,
// use median_SP_RV() for better performance. This function calls median_SP_RV() and
// memcpy_fast().
// \param x pointer to the real input vector
// \param N length of the x vector
// \attention
// -# This function simply makes a local copy of the input array, and then
// calls median_SP_CV() using the copy
// -# The length of the copy of the input array is allocated at compile time
// by the constant "K" defined in the code. If the passed parameter N
// is greater than K, memory corruption will result. Be sure to recompile
// the library with an appropriate value \f$K >= N\f$ before executing this code.
// The library uses K = 256 as the default value.
// \return median of the vector x
// \attention The first stage of this function (memory copy) is not interruptible.
// For interruptibility, use median_noreorder_SP_RV instead.
// \attention This function does not support memory above 22-bits address.
// For input data above 22 bits address, use median_noreorder_SP_RV_far instead.
//
extern float median_noreorder_SP_RV(const float *x, uint16_t N);
// \brief Median of a Real Valued Array of Floats (Preserved Inputs).
//
// This module computes the median of a real valued array of
// floats. The input array is preserved. If input array preservation is not required,
// use median_SP_RV() for better performance. This function calls median_SP_RV_far() and
// memcpy_fast_far().
// \param x pointer to the real input vector
// \param N length of the x vector
// \attention
// -# This function simply makes a local copy of the input array, and then
// calls median_SP_CV_far() using the copy
// -# The length of the copy of the input array is allocated at compile time
// by the constant "K" defined in the code. If the passed parameter N
// is greater than K, memory corruption will result. Be sure to recompile
// the library with an appropriate value \f$K >= N\f$ before executing this code.
// The library uses K = 256 as the default value.
// \return median of the vector x
// \attention This function is intended for data above 22 bits address.
// For input data at or below 22 bits address, use median_noreorder_SP_RV instead for possible better performance.
//
extern float median_noreorder_SP_RV_far(volatile const float *x, uint16_t N);
// \brief Median of a real array of floats.
//
// This module computes the median of a real array of floats.
// The Input array is NOT preserved. If input array preservation
// is required, use median_noreorder_SP_RV().
// \param x pointer to the real input vector
// \param N length of the x vector
// \attention
// -# This function is destructive to the input array x in that it
// will be sorted during function execution. If this is not allowable,
// use median_noreorder_SP_CV().
// -# This function should be compiled with -o4, -mf5, and no -g compiler
// options for best performance.
// \return median of the vector x
// \attention The function does not support memory above 22-bits address.
// For input data above 22 bits address, use median_SP_RV_far instead.
//
extern float median_SP_RV(float *x, uint16_t N);
// \brief Median of a real array of floats.
//
// This module computes the median of a real array of floats.
// The Input array is NOT preserved. If input array preservation
// is required, use median_noreorder_SP_RV_far().
// \param x pointer to the real input vector
// \param N length of the x vector
// \attention
// -# This function is destructive to the input array x in that it
// will be sorted during function execution. If this is not allowable,
// use median_noreorder_SP_CV_far().
// -# This function should be compiled with -o4, -mf5, and no -g compiler
// options for best performance.
// \return median of the vector x
// \attention This function is intended for data above 22 bits address.
// For input data at or below 22 bits address, use median_SP_RV instead for possible better performance.
//
extern float median_SP_RV_far(volatile float *x, uint16_t N);
// \brief Optimized Memory Copy.
//
// \param src pointer to the source buffer
// \param dst pointer to the destination buffer
// \param N size (16-bits) of the buffer to be copied
// \attention The function checks for the case of N=0 and just returns if true
// \attention This function is not interruptible. Use memcpy_fast_far instead for interruptibility.
// \attention This function does not support memory above 22 bits address.
// For input data above 22 bits address, use memcpy_fast_far instead.
//
extern void memcpy_fast(void *dst, const void *src, uint16_t N);
// \brief Optimized Memory Copy for far memory (above 22 bits).
//
// \param src pointer to the source buffer
// \param dst pointer to the destination buffer
// \param N size (16-bits) of the buffer to be copied
// \attention The function checks for the case of N=0 and just returns if true
// \attention This function is restricted to C28x devices with the FPU
// \attention This function is intended for data above 22 bits address.
// For input data at or below 22 bits address, use memcpy_fast instead for better performance.
//
extern void memcpy_fast_far(volatile void *dst, volatile const void *src, uint16_t N);
// \brief Optimized Memory Set.
//
// \param dst pointer to the destination buffer
// \param value value to write to all the buffer locations
// \param N size (16-bits) of the buffer to be written
// \attention The function checks for the case of N=0 and just returns if true.
// \attention This function is not interruptible
//
extern void memset_fast(volatile void *dst, int16_t value, uint16_t N);
// \brief Complex Multiply of Two Floating Point Numbers.
//
// This module multiplies two floating point complex values.
// \f[y_{re} &=& w_{re}*x_{re} - w_{im}*x_{im}\f]
// \f[y_{im} &=& w_{re}*x_{im} + w_{im}*x_{re}\f]
// \param w First complex input
// \param x Second complex input
// \return complex product of the first and second complex input
//
extern complex_float mpy_SP_CSxCS(complex_float w, complex_float x);
// \brief Complex Multiply of Two Complex Vectors.
//
// This module performs complex multiplication on two input complex vectors.
// \f[y_{re}[i] &=& w_{re}[i]*x_{re}[i] - w_{im}[i]*x_{im}[i] \f]
// \f[y_{im}[i] &=& w_{re}[i]*x_{im}[i] + w_{im}[i]*x_{re}[i] \f]
// \param y pointer to the complex product of the first and second complex vectors
// \param w pointer to the first complex input vector
// \param x pointer to the second complex input vector
// \param N length of the w, x and y vectors
//
extern void mpy_SP_CVxCV(volatile complex_float *y, volatile const complex_float *w, volatile const complex_float *x, const uint16_t N);
// \brief Multiplication of a Complex Vector and the Complex Conjugate of another Vector.
//
// This module multiplies a complex vector (w) and the complex conjugate of another complex vector (x).
// \f[x^{*}_{re}[i] &=& x_{re}[i]\f]
// \f[x^{*}_{im}[i] &=& - x_{im}[i]\f]
// \f[y_{re}[i] &=& w_{re}[i]*x_{re}[i] - w_{im}[i]*x^{*}_{im}[i]\f]
// \f[y_{im}[i] &=& w_{re}[i]*x^{*}_{im}[i] + w_{im}[i]*x_{re}[i]\f]
// \param y pointer to the complex product of the first and second complex vectors
// \param w pointer to the first complex input vector
// \param x pointer to the second complex input vector
// \param N length of the w, x and y vectors
//
extern void mpy_SP_CVxCVC(volatile complex_float *y, volatile const complex_float *w, volatile const complex_float *x, const uint16_t N);
// \brief Multiplication of a Real scalar and a Real Vector.
//
// This module multiplies a real scalar and a real vector.
// \f[y[i] &=& c*x[i] \f]
// \param y pointer to the product of the scalar and a real vector
// \param x pointer to the real input vector
// \param c scalar multiplier
// \param N length of the x and y vectors
// \attention N must be even and a minimum of 4.
//
extern void mpy_SP_RSxRV_2(volatile float *y, volatile const float *x, const float c, const uint16_t N);
// \brief Multiplication of a Real Scalar, a Real Vector, and another Real Vector.
//
// This module multiplies a real scalar with a real vector and another real vector.
// \f[y[i] &=& c*w[i]*x[i] \f]
// \param y pointer to the product of the scalar and two real vectors
// \param w pointer to the first real input vector
// \param x pointer to the second real input vector
// \param c scalar multiplier
// \param N length of the w, x and y vectors
// \attention N must be even and a minimum of 4.
//
extern void mpy_SP_RSxRVxRV_2(volatile float *y, volatile const float *w, volatile const float *x, const float c, const uint16_t N);
// \brief Multiplication of a Real Vector and a Complex Vector.
//
// This module multiplies a real vector and a complex vector.
// \f[y_{re}[i] &=& x[i]*w_{re}[i] \f]
// \f[y_{im}[i] &=& x[i]*w_{im}[i] \f]
// \param y pointer to the product of the real and complex vectors
// \param w pointer to the complex input vector
// \param x pointer to the real input vector
// \param N length of the w, x and y vectors
// \attention N must be at least 2
//
extern void mpy_SP_RVxCV(volatile complex_float *y, volatile const complex_float *w, volatile const float *x, const uint16_t N);
// \brief Multiplication of a Real Vector and a Real Vector.
//
// This module multiplies two real vectors.
// \f[y[i] &=& w[i]*x[i]\f]
// \param y pointer to the product of two real vectors
// \param w pointer to the first real input vector
// \param x pointer to the second real input vector
// \param N length of the w, x and y vectors
// \attention N must be even and a minimum of 4.
//
extern void mpy_SP_RVxRV_2(volatile float *y, volatile const float *w, volatile const float *x, const uint16_t N);
// \brief Sort an Array of Floats.
//
// This module sorts an array of floats. This function is a partially optimized
// version of qsort.c from the C28x cgtools lib qsort() v6.0.1.
// \param x pointer to the input array
// \param N size of the input array
// \attention Performance is best with -o1, -mf3 compiler options (cgtools v6.0.1)
// \attention This function does not support memory above 22 bits address.
// For input data above 22 bits address, use qsort_SP_RV_far instead.
//
extern void qsort_SP_RV(void *x, uint16_t N);
// \brief Sort an Array of Floats.
//
// This module sorts an array of floats. This function is a partially optimized
// version of qsort.c from the C28x cgtools lib qsort() v6.0.1.
// \param x pointer to the input array
// \param N size of the input array
// \attention Performance is best with -o1, -mf3 compiler options (cgtools v6.0.1)
// \attention This function is intended for data above 22 bits address.
// For input data at or below 22 bits address, use qsort_SP_RV instead for possible better performance.
//
extern void qsort_SP_RV_far(volatile void *x, uint16_t N);
// \brief Rounding (Unbiased) of a Floating Point Scalar.
//
// numerical examples:
// rnd_SP_RS(+4.4) = +4.0 \\
// rnd_SP_RS(-4.4) = -4.0 \\
// rnd_SP_RS(+4.5) = +5.0 \\
// rnd_SP_RS(-4.5) = -5.0 \\
// rnd_SP_RS(+4.6) = +5.0 \\
// rnd_SP_RS(-4.6) = -5.0 \\
// \param x input value
// \return rounded
//
extern float rnd_SP_RS(float x);
// \brief Subtraction of a Complex Scalar from a Complex Vector.
//
// This module subtracts a complex scalar from a complex vector.
// \f[y_{re}[i] &=& x_{re}[i] - c_{re} \f]
// \f[y_{im}[i] &=& x_{im}[i] - c_{im} \f]
// \param y pointer to the difference of a complex scalar from a complex vector
// \param x pointer to the complex input vector
// \param c pointer to the complex input scalar
// \param N length of the x and y vectors
// \attention N must be at least 2
//
extern void sub_SP_CSxCV(volatile complex_float *y,volatile const complex_float *x, const complex_float c, const uint16_t N);
// \brief Subtraction of a Complex Vector and another Complex Vector.
//
// This module subtracts a complex vector from another complex vector.
// \f[y_{re}[i] &=& w_{re}[i] - x_{re}[i] \f]
// \f[y_{im}[i] &=& w_{im}[i] - x_{im}[i] \f]
// \param y pointer to the difference of two complex vectors
// \param w pointer to the first complex input vector
// \param x pointer to the second complex input vector
// \param N length of the w, x and y vectors
// \attention N must be at least 2
//
extern void sub_SP_CVxCV(volatile complex_float *y, volatile const complex_float *w, volatile const complex_float *x, const uint16_t N);
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of _FPU_VECTOR_H_
//===========================================================================
// End of file.
//===========================================================================
C2000Ware/driverlib/f2837xs/examples/cpu1/emif/memcpy_fast_far.asm
+253
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@@ -0,0 +1,253 @@
; =============================================================================
; This software is licensed for use with Texas Instruments C28x
; family DSCs. This license was provided to you prior to installing
; the software. You may review this license by consulting a copy of
; the agreement in the doc directory of this library.
; ------------------------------------------------------------------------
; Copyright (C) 2014-2015 Texas Instruments, Incorporated.
; All Rights Reserved.
; =============================================================================
;
; FILE: memcpy_fast_far.asm
;
; AUTHOR: David M. Alter, Texas Instruments Inc.
;
; HISTORY:
; 10/21/14 - original (D. Alter)
;
; DESCRIPTION: Optimized memory copy, src->dest.
;
; FUNCTION:
; extern void memcpy_fast_far(volatile void* dst, volatile const void* src, Uint16 N);
;
; USAGE: memcpy_fast_far(dst, src, N);
;
; PARAMETERS: volatile void* dst = pointer to destination
; volatile const void* src = pointer to source
; N = number of 16-bit words to copy
;
; RETURNS: none
;
; BENCHMARK: The performance of this function differs depending on the
; address alignment of the src and dst addresses (pointers).
; - If both pointers have the same alignment (even or odd address),
; then 32-bit copies are used for the bulk of the transfers. This
; allows performance to approach 1 cycle/word (16-bit word) plus
; overhead.
; - If the two pointers have different alignments (one even aligned,
; the other odd aligned) then 16-bit transfers must be used. This
; provides performance approaching 2 cycles/word (16-bit word) plus
; overhead.
; The above benchmarks assume that the src and dst are located in
; different internal RAM blocks (so there are no RAM stalls).
;
; NOTES:
; 1) The function checks for the case of N=0 and just returns if true.
; 2) This function is restricted to C28x devices with the FPU.
; 3) This function is intended for data above 22 bits address.
; For input data at or below 22 bits address, use memcpy_fast
; instead for better performance.
; 4) PREAD and PWRITE are used in the function, but this is OK with
; above 22-bit address since the program bus is used for stack
; access (below 22 bits). The data bus is used for the >22-bit
; address access.
;
; =============================================================================
; ###########################################################################
;
; $Release Date: $
; $Copyright:
;// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
;//
;// Redistribution and use in source and binary forms, with or without
;// modification, are permitted provided that the following conditions
;// are met:
;//
;// Redistributions of source code must retain the above copyright
;// notice, this list of conditions and the following disclaimer.
;//
;// Redistributions in binary form must reproduce the above copyright
;// notice, this list of conditions and the following disclaimer in the
;// documentation and/or other materials provided with the
;// distribution.
;//
;// Neither the name of Texas Instruments Incorporated nor the names of
;// its contributors may be used to endorse or promote products derived
;// from this software without specific prior written permission.
;//
;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;// $
; ###########################################################################
.if __TI_EABI__
.asg memcpy_fast_far , _memcpy_fast_far
.endif
.global _memcpy_fast_far
.text
_memcpy_fast_far:
; Need to check 32-bit alignment of src and dst pointers for 32-bit transfers.
; There are found cases:
; Case 1: both pointers aligned
; Case 2: neither pointer aligned
; Case 3: src pointer aligned, dst pointer not aligned
; Case 4: src pointer not aligned, dst pointer aligned
; Test src pointer alignment
TBIT AR5, #0 ;Test if src pointer is aligned
SBF line1a, NTC ;Branch if aligned
; src pointer not aligned. Test dst pointer.
TBIT AR4, #0 ;Test if dst pointer is aligned
SBF line1b, NTC ;Branch if aligned
;--------------
; Case 2 is true - neither pointer aligned
; Copy the first 16-bit word to align both pointers
ADDB AL, #-1 ;Decrement the copy number
BF done3, NC ;Branch if N was zero
MOV AH, *XAR5++ ;Read the src
MOV *XAR4++, AH ;Store to dst
BF line3a, UNC ;Proceed with 32-bit copies
;--------------
line1b:
; Case 4 is true - src pointer not aligned, dst pointer aligned.
BF line2a, UNC ;Proceed with 16-bit copies
;--------------
line1a:
; src pointer aligned. Test dst pointer.
TBIT AR4, #0 ;Test bit 0 of dst pointer
SBF line1c, NTC ;Branch if aligned
;--------------
; Case 3 is true - src pointer aligned, dst pointer not aligned.
; Proceed with 16-bit copies.
;--------------------------------------
line2a:
; 16-bit copies.
; These are used when the src and dst pointers have different alignments
; (i.e., one is aligned, the other is not aligned).
; Copy as many 8x16-bit word blocks as possible.
; 8x16-bit length blocks are used so we can meet minimum size of RPTB.
MOV PL, AL ;Save current copy number
LSR AL, #3 ;Divide by 8
ADDB AL, #-1 ;Repeat "N-1" times
BF line2b, NC ;Branch if N was zero
RPTB line2b, @AL
MOV AH, *XAR5++ ;Read src #1
MOV *XAR4++, AH ;Write dst #1
MOV AH, *XAR5++ ;Read src #2
MOV *XAR4++, AH ;Write dst #2
MOV AH, *XAR5++ ;Read src #3
MOV *XAR4++, AH ;Write dst #3
MOV AH, *XAR5++ ;Read src #4
MOV *XAR4++, AH ;Write dst #4
MOV AH, *XAR5++ ;Read src #5
MOV *XAR4++, AH ;Write dst #5
MOV AH, *XAR5++ ;Read src #6
MOV *XAR4++, AH ;Write dst #6
MOV AH, *XAR5++ ;Read src #7
MOV *XAR4++, AH ;Write dst #7
MOV AH, *XAR5++ ;Read src #8
MOV *XAR4++, AH ;Write dst #8
line2b:
; Do the remaining elements as 16-bit copies. There could be up to 7 of them.
MOV AL, PL ;Restore the saved copy number
AND AL, #0007h ;Isolate 1st 3 bits of the copy number (0 - 15 copies)
MOVL XAR7, #0 ;Zero out XAR7
MOV AR7, SP ;AR7 = SP
ADD SP, AL ;Advance stack pointer beyond copy area
ADDB AL, #-1 ;Repeat "N-1" times
BF done2, NC ;Branch if N was zero
RPT @AL
|| PWRITE *XAR7, *XAR5++ ;Copy src words to the stack
RPT @AL
|| PREAD *XAR4++, *XAR7 ;Copy stack words to the dst
SUB SP, AL ;Restore the stack pointer (part 1)
SUB SP, #1 ;Restore the stack pointer (part 2)
;Finish up
done2:
LRETR ;return
;--------------
line1c:
; Case 1 is true - both pointers aligned.
; Proceed with 32-bit copies.
;--------------------------------------
line3a:
; 32-bit copies.
; Copy as many 8x32-bit word blocks as possible.
; 8x32-bit (16x16-bit) length blocks are used so we can meet minimum size of RPTB.
MOV PL, AL ;Save current copy number
LSR AL, #4 ;Divide by 16
ADDB AL, #-1 ;Repeat "N-1" times
BF line3b, NC ;Branch if N was zero
RPTB line3b, @AL
MOVL ACC, *XAR5++ ;Read src #1
MOVL *XAR4++, ACC ;Write dst #1
MOVL ACC, *XAR5++ ;Read src #2
MOVL *XAR4++, ACC ;Write dst #2
MOVL ACC, *XAR5++ ;Read src #3
MOVL *XAR4++, ACC ;Write dst #3
MOVL ACC, *XAR5++ ;Read src #4
MOVL *XAR4++, ACC ;Write dst #4
MOVL ACC, *XAR5++ ;Read src #5
MOVL *XAR4++, ACC ;Write dst #5
MOVL ACC, *XAR5++ ;Read src #6
MOVL *XAR4++, ACC ;Write dst #6
MOVL ACC, *XAR5++ ;Read src #7
MOVL *XAR4++, ACC ;Write dst #7
MOVL ACC, *XAR5++ ;Read src #8
MOVL *XAR4++, ACC ;Write dst #8
line3b:
; Do the remaining elements as 16-bit copies. There could be up to 15 of them.
MOV AL, PL ;Restore the saved copy number
AND AL, #000Fh ;Isolate 1st 4 bits of the copy number (0 - 15 copies)
MOVL XAR7, #0 ;Zero out XAR7
MOV AR7, SP ;AR7 = SP
ADD SP, AL ;Advance stack pointer beyond copy area
ADDB AL, #-1 ;Repeat "N-1" times
BF done3, NC ;Branch if N was zero
RPT @AL
|| PWRITE *XAR7, *XAR5++ ;Copy src words to the stack
RPT @AL
|| PREAD *XAR4++, *XAR7 ;Copy stack words to the dst
SUB SP, AL ;Restore the stack pointer (part 1)
SUB SP, #1 ;Restore the stack pointer (part 2)
;Finish up
done3:
LRETR ;return
;end of function memcpy_fast_far()
**********************************************************************
.end
;end of file memcpy_fast_far.asm