Update repo
This commit is contained in:
@@ -0,0 +1,29 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="mcbsp_ex1_loopback"
|
||||
device="TMS320F28377S"
|
||||
cgtVersion="22.6.0.LTS"
|
||||
products="C2000WARE"
|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=_FLASH --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
|
||||
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|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_RAM_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_FLASH_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_ex1_loopback.c" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_pin_setup.c" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+29
@@ -0,0 +1,29 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="mcbsp_ex2_loopback_dma"
|
||||
device="TMS320F28377S"
|
||||
cgtVersion="22.6.0.LTS"
|
||||
products="C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xS"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=_FLASH --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_RAM_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_FLASH_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_ex2_loopback_dma.c" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_pin_setup.c" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+29
@@ -0,0 +1,29 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="mcbsp_ex3_loopback_interrupts"
|
||||
device="TMS320F28377S"
|
||||
cgtVersion="22.6.0.LTS"
|
||||
products="C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xS"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=_FLASH --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_RAM_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_FLASH_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_ex3_loopback_interrupts.c" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_pin_setup.c" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+29
@@ -0,0 +1,29 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="mcbsp_ex4_spi_loopback"
|
||||
device="TMS320F28377S"
|
||||
cgtVersion="22.6.0.LTS"
|
||||
products="C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xS"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=_FLASH --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_RAM_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_FLASH_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_ex4_spi_loopback.c" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_pin_setup.c" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+29
@@ -0,0 +1,29 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="mcbsp_ex5_ext_loopback"
|
||||
device="TMS320F28377S"
|
||||
cgtVersion="22.6.0.LTS"
|
||||
products="C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xS"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=_FLASH --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_RAM_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_FLASH_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
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||||
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_ex5_ext_loopback.c" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_pin_setup.c" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+29
@@ -0,0 +1,29 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="mcbsp_ex6_spi_ext_loopback"
|
||||
device="TMS320F28377S"
|
||||
cgtVersion="22.6.0.LTS"
|
||||
products="C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
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||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2837xS"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define RAM" />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=DEBUG --define=_FLASH --define=CPU1 -v28 -ml -mt --define=DEBUG --diag_warning=225 --diag_suppress=10063 --display_error_number" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 " />
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/targetConfigs/TMS320F28377S.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_RAM_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/cmd/2837xS_Generic_FLASH_lnk.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../../../../../../device_support/f2837xs/common/source/F2837xS_CodeStartBranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_ex6_spi_ext_loopback.c" targetDirectory="" />
|
||||
<file action="copy" path="../mcbsp_pin_setup.c" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
@@ -0,0 +1,385 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: mcbsp_ex1_loopback.c
|
||||
//
|
||||
// TITLE: McBSP loopback example.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> McBSP loopback example </h1>
|
||||
//!
|
||||
//! This example demonstrates the McBSP operation using internal loopback.
|
||||
//! This example does not use interrupts. Instead, a polling method is used
|
||||
//! to check the receive data. The incoming data is checked for accuracy.
|
||||
//!
|
||||
//! Three different serial word sizes can be tested. Before compiling
|
||||
//! this project, select the serial word size of 8, 16 or 32 by using
|
||||
//! the \#define statements at the beginning of the code.
|
||||
//!
|
||||
//! This program will execute until terminated by the user.
|
||||
//!
|
||||
//! \b 8-bit \b word \b example: \n
|
||||
//! The sent data looks like this:\n
|
||||
//! 00 01 02 03 04 05 06 07 .... FE FF\n
|
||||
//!
|
||||
//! \b 16-bit \b word \b example: \n
|
||||
//! The sent data looks like this:\n
|
||||
//! 0000 0001 0002 0003 0004 0005 0006 0007 .... FFFE FFFF\n
|
||||
//!
|
||||
//! \b 32-bit \b word \b example: \n
|
||||
//! The sent data looks like this: \n
|
||||
//! FFFF0000 FFFE0001 FFFD0002 .... 0000FFFF \n
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - None
|
||||
//!
|
||||
//! \b Watch \b Variables: \n
|
||||
//! - \b txData1 - Sent data word: 8 or 16-bit or low half of 32-bit
|
||||
//! - \b txData2 - Sent data word: upper half of 32-bit
|
||||
//! - \b rxData1 - Received data word: 8 or 16-bit or low half of 32-bit
|
||||
//! - \b rxData2 - Received data word: upper half of 32-bit
|
||||
//! - \b errCountGlobal - Error counter
|
||||
//!
|
||||
//! \note txData2 and rxData2 are not used for 8-bit or 16-bit word size.
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright:
|
||||
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "device.h"
|
||||
#include "driverlib.h"
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// Define to select clock delay.
|
||||
//
|
||||
#define MCBSP_CYCLE_NOP0(n) __asm(" RPT #(" #n ") || NOP")
|
||||
#define MCBSP_CYCLE_NOP(n) MCBSP_CYCLE_NOP0(n)
|
||||
|
||||
//
|
||||
// Define to select the word-size for McBSP operation to 8, 16 or 32 bit.
|
||||
//
|
||||
//#define WORD_SIZE 8U
|
||||
//#define WORD_SIZE 16U
|
||||
#define WORD_SIZE 32U
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint32_t errCountGlobal = 0;
|
||||
|
||||
//
|
||||
// Variables for transmitting, receiving and testing the data.
|
||||
//
|
||||
uint16_t txData1 = 0x0000;
|
||||
uint16_t txData2 = 0x0000;
|
||||
uint16_t rxData1 = 0x0000;
|
||||
uint16_t rxData2 = 0x0000;
|
||||
uint16_t dataSize;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
extern void setupMcBSPAPinmux(void);
|
||||
void initMcBSPLoopback(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
uint32_t tempData;
|
||||
errCountGlobal = 0x0;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals.
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Disable all the interrupts.
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups.
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize GPIO.
|
||||
//
|
||||
setupMcBSPAPinmux();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
dataSize = WORD_SIZE;
|
||||
|
||||
//
|
||||
// Initialize and release peripheral (McBSP) from reset.
|
||||
//
|
||||
initMcBSPLoopback();
|
||||
|
||||
//
|
||||
// Run a loopback test in 8-bit mode.
|
||||
//
|
||||
if(dataSize == 8)
|
||||
{
|
||||
txData1 = 0x0000;
|
||||
while(1)
|
||||
{
|
||||
//
|
||||
// Write data to be transmitted.
|
||||
//
|
||||
while(!McBSP_isTxReady(MCBSPA_BASE));
|
||||
McBSP_write16bitData(MCBSPA_BASE, txData1);
|
||||
|
||||
//
|
||||
// Check if data is received.
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPA_BASE));
|
||||
rxData1 = McBSP_read16bitData(MCBSPA_BASE);
|
||||
|
||||
if(rxData1 != txData1)
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
txData1++;
|
||||
txData1 = txData1 & 0x00FF;
|
||||
NOP;
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
}
|
||||
else if(dataSize == 16)
|
||||
{
|
||||
txData1 = 0x0000;
|
||||
while(1)
|
||||
{
|
||||
//
|
||||
// Write data to be transmitted.
|
||||
//
|
||||
while(!McBSP_isTxReady(MCBSPA_BASE));
|
||||
McBSP_write16bitData(MCBSPA_BASE, txData1);
|
||||
|
||||
//
|
||||
// Check if data is received.
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPA_BASE));
|
||||
rxData1 = McBSP_read16bitData(MCBSPA_BASE);
|
||||
if(rxData1 != txData1)
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
txData1++;
|
||||
NOP;
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
}
|
||||
else if(dataSize == 32)
|
||||
{
|
||||
txData2 = 0xFFFF;
|
||||
txData1 = 0x0000;
|
||||
while(1)
|
||||
{
|
||||
//
|
||||
// Write data to be transmitted.
|
||||
//
|
||||
tempData = (txData1|(((uint32_t)txData2) << 16U));
|
||||
while(!McBSP_isTxReady(MCBSPA_BASE));
|
||||
McBSP_write32bitData(MCBSPA_BASE, tempData);
|
||||
|
||||
//
|
||||
// Check if data is received.
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPA_BASE));
|
||||
tempData = McBSP_read32bitData(MCBSPA_BASE);
|
||||
rxData1 = tempData & 0xFFFF;
|
||||
rxData2 = tempData >> 16U;
|
||||
if(rxData1 != txData1 || rxData2 != txData2)
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
txData1++;
|
||||
txData2--;
|
||||
NOP;
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Init McBSP Loopback - This function initialises McBSP in digital loopback
|
||||
// mode.
|
||||
//
|
||||
void initMcBSPLoopback()
|
||||
{
|
||||
//
|
||||
// Reset FS generator, sample rate generator, transmitter & receiver.
|
||||
//
|
||||
McBSP_resetFrameSyncLogic(MCBSPA_BASE);
|
||||
McBSP_resetSampleRateGenerator(MCBSPA_BASE);
|
||||
McBSP_resetTransmitter(MCBSPA_BASE);
|
||||
McBSP_resetReceiver(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Set Rx sign-extension and justification mode.
|
||||
//
|
||||
McBSP_setRxSignExtension(MCBSPA_BASE, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);
|
||||
|
||||
//
|
||||
// Enable DLB mode. Comment out for non-DLB mode.
|
||||
//
|
||||
McBSP_enableLoopback(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Set Rx & Tx delay to 1 cycle.
|
||||
//
|
||||
McBSP_setRxDataDelayBits(MCBSPA_BASE, MCBSP_DATA_DELAY_BIT_1);
|
||||
McBSP_setTxDataDelayBits(MCBSPA_BASE, MCBSP_DATA_DELAY_BIT_1);
|
||||
|
||||
//
|
||||
// Set the source for CLKX & FSX as sample rate generator.
|
||||
//
|
||||
McBSP_setTxClockSource(MCBSPA_BASE, MCBSP_INTERNAL_TX_CLOCK_SOURCE);
|
||||
McBSP_setTxFrameSyncSource(MCBSPA_BASE, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE);
|
||||
|
||||
//
|
||||
// Configure McBSP data behaviour.
|
||||
//
|
||||
if(dataSize == 8)
|
||||
{
|
||||
McBSP_setRxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_8, 0);
|
||||
McBSP_setTxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_8, 0);
|
||||
}
|
||||
else if(dataSize == 16)
|
||||
{
|
||||
McBSP_setRxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_16, 0);
|
||||
McBSP_setTxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_16, 0);
|
||||
}
|
||||
else if(dataSize == 32)
|
||||
{
|
||||
McBSP_setRxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_32, 0);
|
||||
McBSP_setTxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_32, 0);
|
||||
}
|
||||
|
||||
//
|
||||
// Set frame-sync pulse period.
|
||||
//
|
||||
McBSP_setFrameSyncPulsePeriod(MCBSPA_BASE, 320);
|
||||
|
||||
//
|
||||
// Set frame-sync pulse width.
|
||||
//
|
||||
McBSP_setFrameSyncPulseWidthDivider(MCBSPA_BASE, 1);
|
||||
|
||||
//
|
||||
// Set the trigger source for internally generated frame-sync pulse.
|
||||
//
|
||||
McBSP_setTxInternalFrameSyncSource(MCBSPA_BASE,
|
||||
MCBSP_TX_INTERNAL_FRAME_SYNC_SRG);
|
||||
|
||||
//
|
||||
// Set LSPCLK as input source for sample rate generator.
|
||||
//
|
||||
McBSP_setTxSRGClockSource(MCBSPA_BASE, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK);
|
||||
|
||||
//
|
||||
// Set Divide down value for CLKG.
|
||||
//
|
||||
McBSP_setSRGDataClockDivider(MCBSPA_BASE, 1);
|
||||
|
||||
//
|
||||
// Set no external clock sync for CLKG.
|
||||
//
|
||||
McBSP_disableSRGSyncFSR(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
|
||||
//
|
||||
// Enable Sample rate generator and wait for atleast 2 CLKG clock cycles.
|
||||
//
|
||||
McBSP_enableSampleRateGenerator(MCBSPA_BASE);
|
||||
McBSP_enableFrameSyncLogic(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 CLKG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/(LSPCLK/(1+CLKGDV_VAL))). In this
|
||||
// example LSPCLK = SYSCLK/4 and CLKGDV_VAL = 1.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(16);
|
||||
|
||||
//
|
||||
// Release Rx, Tx from reset.
|
||||
//
|
||||
McBSP_enableTransmitter(MCBSPA_BASE);
|
||||
McBSP_enableReceiver(MCBSPA_BASE);
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -0,0 +1,722 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: mcbsp_ex2_loopback_dma.c
|
||||
//
|
||||
// TITLE: McBSP loopback with DMA example.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> McBSP loopback with DMA example. </h1>
|
||||
//!
|
||||
//! This example demonstrates the McBSP operation using internal loopback and
|
||||
//! utilizes the DMA to transfer data from one buffer to the McBSP and then
|
||||
//! from McBSP to another buffer.
|
||||
//!
|
||||
//! Initially, txData[] is filled with values from 0x0000- 0x007F. The DMA moves
|
||||
//! the values in txData[] one by one to the DXRx registers of the McBSP. These
|
||||
//! values are transmitted and subsequently received by the McBSP. Then, the
|
||||
//! the DMA moves each data value to rxData[] as it is received by the McBSP.
|
||||
//!
|
||||
//! The sent data buffer looks like this: \n
|
||||
//! 0000 0001 0002 0003 0004 0005 .... 007F \n
|
||||
//!
|
||||
//! Three different serial word sizes can be tested. Before compiling
|
||||
//! this project, select the serial word size of 8, 16 or 32 by using
|
||||
//! the \#define statements at the beginning of the code.
|
||||
//!
|
||||
//! This example uses DMA channel 1 and 2 interrupts. The incoming data is
|
||||
//! checked for accuracy.
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - None
|
||||
//!
|
||||
//! \b Watch \b Variables: \n
|
||||
//! - \b txData - Sent data buffer
|
||||
//! - \b rxData - Received data buffer
|
||||
//! - \b errCountGlobal - Error counter
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright:
|
||||
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "device.h"
|
||||
#include "driverlib.h"
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// Define to select delay in clock cycles.
|
||||
//
|
||||
#define MCBSP_CYCLE_NOP0(n) __asm(" RPT #(" #n ") || NOP")
|
||||
#define MCBSP_CYCLE_NOP(n) MCBSP_CYCLE_NOP0(n)
|
||||
|
||||
//
|
||||
// Define to select the word-size for McBSP operation to 8, 16 or 32 bit.
|
||||
//
|
||||
#define WORD_SIZE 8U
|
||||
//#define WORD_SIZE 16U
|
||||
//#define WORD_SIZE 32U
|
||||
|
||||
#pragma DATA_SECTION(txData, "ramgs0")
|
||||
#pragma DATA_SECTION(rxData, "ramgs1")
|
||||
|
||||
//
|
||||
// Globals
|
||||
uint16_t txData[128];
|
||||
uint16_t rxData[128];
|
||||
uint16_t dataSize;
|
||||
uint16_t errCountGlobal = 0;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
extern void setupMcBSPAPinmux(void);
|
||||
void configDMAChannel1(void);
|
||||
void configDMAChannel2(void);
|
||||
void configDMA32Channel1(void);
|
||||
void configDMA32Channel2(void);
|
||||
void initDMA(void);
|
||||
void initDMA32(void);
|
||||
void initMcBSPLoopback(void);
|
||||
void startDMA(void);
|
||||
|
||||
//
|
||||
// ISR for DMA channel 1 & 2 interrupts.
|
||||
//
|
||||
__interrupt void localDMAINTCH1ISR(void);
|
||||
__interrupt void localDMAINTCH2ISR(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals.
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Disable all the interrupts.
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups.
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize GPIO.
|
||||
//
|
||||
setupMcBSPAPinmux();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Interrupts that are used in this example are re-mapped to
|
||||
// ISR functions found within this file.
|
||||
//
|
||||
Interrupt_register(INT_DMA_CH1, localDMAINTCH1ISR);
|
||||
Interrupt_register(INT_DMA_CH2, localDMAINTCH2ISR);
|
||||
|
||||
//
|
||||
// Configure DMA as secondary master for peripheral frame 2.
|
||||
//
|
||||
SysCtl_selectSecMaster(SYSCTL_SEC_MASTER_DMA, SYSCTL_SEC_MASTER_DMA);
|
||||
|
||||
//
|
||||
// User defined code.
|
||||
//
|
||||
dataSize = WORD_SIZE;
|
||||
|
||||
//
|
||||
// Initialize data buffers.
|
||||
//
|
||||
for(i = 0; i<128; i++)
|
||||
{
|
||||
//
|
||||
// Fill txData with values between 0 and 0x007F.
|
||||
//
|
||||
txData[i] = i;
|
||||
|
||||
//
|
||||
// Initialize rxData to 0xFFFF.
|
||||
//
|
||||
rxData[i] = 0xFFFFU;
|
||||
}
|
||||
|
||||
//
|
||||
// Initialize DMA based on desired word size.
|
||||
//
|
||||
if(dataSize == 32)
|
||||
{
|
||||
//
|
||||
// Initialize DMA for 32-bit transfers.
|
||||
//
|
||||
initDMA32();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Initialize DMA for 16-bit transfers.
|
||||
//
|
||||
initDMA();
|
||||
}
|
||||
|
||||
//
|
||||
// When using DMA, initialize DMA with peripheral interrupts first and then
|
||||
// initialize and release McBSP from reset.
|
||||
//
|
||||
startDMA();
|
||||
initMcBSPLoopback();
|
||||
|
||||
//
|
||||
// Enable interrupts in PIE block.
|
||||
//
|
||||
Interrupt_enable(INT_DMA_CH1);
|
||||
Interrupt_enable(INT_DMA_CH2);
|
||||
|
||||
//
|
||||
// Enable group 7 CPU interrupt.
|
||||
//
|
||||
IER = 0x40;
|
||||
|
||||
//
|
||||
// Enable global interrupts.
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
//
|
||||
// Idle loop.
|
||||
//
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// Configure DMA Channel 1 - This function configures the DMA channel 1 for
|
||||
// writing data to transmit buffer for 8 to 16-bit word size.
|
||||
//
|
||||
void configDMAChannel1()
|
||||
{
|
||||
//
|
||||
// Configure DMA Channel 1 (16 - bit datasize).
|
||||
//
|
||||
DMA_disableInterrupt(DMA_CH1_BASE);
|
||||
|
||||
//
|
||||
// Configure 1 word per burst.
|
||||
//
|
||||
DMA_configBurst(DMA_CH1_BASE, 1U, 0U, 0U);
|
||||
|
||||
//
|
||||
// Configure 127 bursts per transfer.
|
||||
//
|
||||
DMA_configTransfer(DMA_CH1_BASE, 128, 1, 0);
|
||||
|
||||
//
|
||||
// Src start address = buffer & dest start address = MCBSPA DXR
|
||||
//
|
||||
DMA_configAddresses(DMA_CH1_BASE,(const void*)(MCBSPA_BASE + MCBSP_O_DXR1),
|
||||
(const void*)(&txData[0]));
|
||||
|
||||
//
|
||||
// Clear peripheral interrupt event flag.
|
||||
//
|
||||
DMA_clearTriggerFlag(DMA_CH1_BASE);
|
||||
|
||||
//
|
||||
// Clear sync error flag.
|
||||
//
|
||||
DMA_clearErrorFlag(DMA_CH1_BASE);
|
||||
|
||||
//
|
||||
// Configure wrap size to maximum to avoid wrapping.
|
||||
//
|
||||
DMA_configWrap(DMA_CH1_BASE, 0x10000U, 0, 0x10000U, 0);
|
||||
|
||||
//
|
||||
// Enable channel interrupt.
|
||||
//
|
||||
DMA_enableInterrupt(DMA_CH1_BASE);
|
||||
|
||||
//
|
||||
// Interrupt at end of the transfer.
|
||||
//
|
||||
DMA_setInterruptMode(DMA_CH1_BASE, DMA_INT_AT_END);
|
||||
|
||||
//
|
||||
// Enable selected peripheral trigger to start a DMA transfer on DMA
|
||||
// channel 1.
|
||||
//
|
||||
DMA_enableTrigger(DMA_CH1_BASE);
|
||||
|
||||
//
|
||||
// Configure DMA trigger source as McBSPA Tx EVT.
|
||||
//
|
||||
DMA_configMode(DMA_CH1_BASE, DMA_TRIGGER_MCBSPAMXEVT, 0);
|
||||
|
||||
//
|
||||
// Clear any spurious Peripheral interrupts flags.
|
||||
//
|
||||
DMA_clearTriggerFlag(DMA_CH1_BASE);
|
||||
}
|
||||
|
||||
//
|
||||
// Configure DMA Channel 2 - This function configures the DMA channel 2 for
|
||||
// reading from receive buffer for 8 to 16-bit word size.
|
||||
//
|
||||
void configDMAChannel2()
|
||||
{
|
||||
//
|
||||
// Configure DMA Channel 2 (16 - bit datasize).
|
||||
//
|
||||
DMA_disableInterrupt(DMA_CH2_BASE);
|
||||
|
||||
//
|
||||
// Configure 1 word per burst.
|
||||
//
|
||||
DMA_configBurst(DMA_CH2_BASE, 1U, 0U, 0U);
|
||||
|
||||
//
|
||||
// Configure 127 bursts per transfer.
|
||||
//
|
||||
DMA_configTransfer(DMA_CH2_BASE, 128, 0, 1);
|
||||
|
||||
//
|
||||
// Dest start address = buffer & Src start address = MCBSPA DRR
|
||||
//
|
||||
DMA_configAddresses(DMA_CH2_BASE,(const void*)(&rxData[0]),
|
||||
(const void*)(MCBSPA_BASE + MCBSP_O_DRR1));
|
||||
|
||||
//
|
||||
// Clear peripheral interrupt event flag.
|
||||
//
|
||||
DMA_clearTriggerFlag(DMA_CH2_BASE);
|
||||
|
||||
//
|
||||
// Clear sync error flag.
|
||||
//
|
||||
DMA_clearErrorFlag(DMA_CH2_BASE);
|
||||
|
||||
//
|
||||
// Configure wrap size to maximum to avoid wrapping.
|
||||
//
|
||||
DMA_configWrap(DMA_CH2_BASE, 0x10000U, 0, 0x10000U, 0);
|
||||
|
||||
//
|
||||
// Enable channel interrupt.
|
||||
//
|
||||
DMA_enableInterrupt(DMA_CH2_BASE);
|
||||
|
||||
//
|
||||
// Interrupt at end of the transfer.
|
||||
//
|
||||
DMA_setInterruptMode(DMA_CH2_BASE, DMA_INT_AT_END);
|
||||
|
||||
//
|
||||
// Enable selected peripheral trigger to start a DMA transfer on DMA
|
||||
// channel 2.
|
||||
//
|
||||
DMA_enableTrigger(DMA_CH2_BASE);
|
||||
|
||||
//
|
||||
// Configure DMA trigger source as McBSPA Tx EVT.
|
||||
//
|
||||
DMA_configMode(DMA_CH2_BASE, DMA_TRIGGER_MCBSPAMREVT, 0);
|
||||
|
||||
//
|
||||
// Clear any spurious Peripheral interrupts flags.
|
||||
//
|
||||
DMA_clearTriggerFlag(DMA_CH2_BASE);
|
||||
}
|
||||
|
||||
//
|
||||
// Configure DMA 32 Channel 1 - This function configures the DMA channel 1 for
|
||||
// writing to transmit buffer for 32-bit word size.
|
||||
//
|
||||
void configDMA32Channel1()
|
||||
{
|
||||
//
|
||||
// Configure DMA Channel 1
|
||||
//
|
||||
DMA_disableInterrupt(DMA_CH1_BASE);
|
||||
|
||||
//
|
||||
// Configure 2 word per burst. Increment one 16-bit address between words
|
||||
// for src & dest address.
|
||||
//
|
||||
DMA_configBurst(DMA_CH1_BASE, 2U, 1U, 1U);
|
||||
|
||||
//
|
||||
// Configure 63 bursts per transfer. For src move to next word in buffer
|
||||
// after each word in a burst. For dest go back to DXR2.
|
||||
//
|
||||
DMA_configTransfer(DMA_CH1_BASE, 64, 1, 0xFFFF);
|
||||
|
||||
//
|
||||
// Src start address = buffer & dest start address = MCBSPA DXR
|
||||
//
|
||||
DMA_configAddresses(DMA_CH1_BASE,(const void*)(MCBSPA_BASE + MCBSP_O_DXR2),
|
||||
(const void*)(&txData[0]));
|
||||
|
||||
//
|
||||
// Clear peripheral interrupt event flag.
|
||||
//
|
||||
DMA_clearTriggerFlag(DMA_CH1_BASE);
|
||||
|
||||
//
|
||||
// Clear sync error flag.
|
||||
//
|
||||
DMA_clearErrorFlag(DMA_CH1_BASE);
|
||||
|
||||
//
|
||||
// Configure wrap size to maximum to avoid wrapping.
|
||||
//
|
||||
DMA_configWrap(DMA_CH1_BASE, 0x10000U, 0, 0x10000U, 0);
|
||||
|
||||
//
|
||||
// Enable channel interrupt.
|
||||
//
|
||||
DMA_enableInterrupt(DMA_CH1_BASE);
|
||||
|
||||
//
|
||||
// Interrupt at end of the transfer.
|
||||
//
|
||||
DMA_setInterruptMode(DMA_CH1_BASE, DMA_INT_AT_END);
|
||||
|
||||
//
|
||||
// Enable selected peripheral trigger to start a DMA transfer on DMA
|
||||
// channel 1.
|
||||
//
|
||||
DMA_enableTrigger(DMA_CH1_BASE);
|
||||
|
||||
//
|
||||
// Configure DMA trigger source as McBSPA Tx EVT.
|
||||
//
|
||||
DMA_configMode(DMA_CH1_BASE, DMA_TRIGGER_MCBSPAMXEVT, 0);
|
||||
|
||||
//
|
||||
// Clear any spurious Peripheral interrupts flags.
|
||||
//
|
||||
DMA_clearTriggerFlag(DMA_CH1_BASE);
|
||||
}
|
||||
|
||||
//
|
||||
// Configure DMA Channel 2 - This function configures the DMA channel 2 for
|
||||
// reading from receive buffer for 32-bit word-size.
|
||||
//
|
||||
void configDMA32Channel2()
|
||||
{
|
||||
//
|
||||
// Configure DMA Channel 2 (16 - bit datasize).
|
||||
//
|
||||
DMA_disableInterrupt(DMA_CH2_BASE);
|
||||
|
||||
//
|
||||
// Configure 2 word per burst. Increment one 16-bit address between words
|
||||
// for src & dest address.
|
||||
//
|
||||
DMA_configBurst(DMA_CH2_BASE, 2U, 1U, 1U);
|
||||
|
||||
//
|
||||
// Configure 63 bursts per transfer. For src move to next word in buffer
|
||||
// after each word in a burst. For dest go back to DRR2.
|
||||
//
|
||||
DMA_configTransfer(DMA_CH2_BASE, 64, 0xFFFF, 1);
|
||||
|
||||
//
|
||||
// Dest start address = buffer & Src start address = MCBSPA DRR
|
||||
//
|
||||
DMA_configAddresses(DMA_CH2_BASE, (const void*)(&rxData[0]),
|
||||
(const void*)(MCBSPA_BASE + MCBSP_O_DRR2));
|
||||
|
||||
//
|
||||
// Clear peripheral interrupt event flag.
|
||||
//
|
||||
DMA_clearTriggerFlag(DMA_CH2_BASE);
|
||||
|
||||
//
|
||||
// Clear sync error flag.
|
||||
//
|
||||
DMA_clearErrorFlag(DMA_CH2_BASE);
|
||||
|
||||
//
|
||||
// Configure wrap size to maximum to avoid wrapping.
|
||||
//
|
||||
DMA_configWrap(DMA_CH2_BASE, 0x10000U, 0, 0x10000U, 0);
|
||||
|
||||
//
|
||||
// Enable channel interrupt.
|
||||
//
|
||||
DMA_enableInterrupt(DMA_CH2_BASE);
|
||||
|
||||
//
|
||||
// Interrupt at end of the transfer.
|
||||
//
|
||||
DMA_setInterruptMode(DMA_CH2_BASE, DMA_INT_AT_END);
|
||||
|
||||
//
|
||||
// Enable selected peripheral trigger to start a DMA transfer on DMA
|
||||
// channel 1.
|
||||
//
|
||||
DMA_enableTrigger(DMA_CH2_BASE);
|
||||
|
||||
//
|
||||
// Configure DMA trigger source as McBSPA Rx EVT.
|
||||
//
|
||||
DMA_configMode(DMA_CH2_BASE, DMA_TRIGGER_MCBSPAMREVT, 0);
|
||||
|
||||
//
|
||||
// Clear any spurious Peripheral interrupts flags.
|
||||
//
|
||||
DMA_clearTriggerFlag(DMA_CH2_BASE);
|
||||
}
|
||||
|
||||
//
|
||||
// Init DMA - This function initialises the DMA channel 1 & 2 for the 8 or
|
||||
// 16-bit transfer.
|
||||
//
|
||||
void initDMA(void)
|
||||
{
|
||||
DMA_initController();
|
||||
configDMAChannel1();
|
||||
configDMAChannel2();
|
||||
}
|
||||
|
||||
//
|
||||
// Init DMA 32 - This function initialises the DMA channel 1 & 2 for the 32-bit
|
||||
// transfer.
|
||||
//
|
||||
void initDMA32(void)
|
||||
{
|
||||
DMA_initController();
|
||||
configDMA32Channel1();
|
||||
configDMA32Channel2();
|
||||
}
|
||||
|
||||
//
|
||||
// Init McBSP Loopback - This function initialises McBSP peripheral in digital
|
||||
// loopback mode.
|
||||
//
|
||||
void initMcBSPLoopback()
|
||||
{
|
||||
//
|
||||
// Reset FS generator, sample rate generator, transmitter & receiver.
|
||||
//
|
||||
McBSP_resetFrameSyncLogic(MCBSPA_BASE);
|
||||
McBSP_resetSampleRateGenerator(MCBSPA_BASE);
|
||||
McBSP_resetTransmitter(MCBSPA_BASE);
|
||||
McBSP_resetReceiver(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Set Rx sign-extension and justification mode.
|
||||
//
|
||||
McBSP_setRxSignExtension(MCBSPA_BASE, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);
|
||||
|
||||
//
|
||||
// Enable DLB mode. Comment out for non-DLB mode.
|
||||
//
|
||||
McBSP_enableLoopback(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Set Rx & Tx delay to 1 cycle.
|
||||
//
|
||||
McBSP_setRxDataDelayBits(MCBSPA_BASE, MCBSP_DATA_DELAY_BIT_1);
|
||||
McBSP_setTxDataDelayBits(MCBSPA_BASE, MCBSP_DATA_DELAY_BIT_1);
|
||||
|
||||
//
|
||||
// Set CLKX & FSX source as sample rate generator.
|
||||
//
|
||||
McBSP_setTxClockSource(MCBSPA_BASE, MCBSP_INTERNAL_TX_CLOCK_SOURCE);
|
||||
McBSP_setTxFrameSyncSource(MCBSPA_BASE, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE);
|
||||
|
||||
//
|
||||
// Configure McBSP data behaviour.
|
||||
//
|
||||
if(dataSize == 8)
|
||||
{
|
||||
McBSP_setRxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_8, 0);
|
||||
McBSP_setTxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_8, 0);
|
||||
}
|
||||
else if(dataSize == 16)
|
||||
{
|
||||
McBSP_setRxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_16, 0);
|
||||
McBSP_setTxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_16, 0);
|
||||
}
|
||||
else if(dataSize == 32)
|
||||
{
|
||||
McBSP_setRxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_32, 0);
|
||||
McBSP_setTxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_32, 0);
|
||||
}
|
||||
|
||||
//
|
||||
// Set frame-sync pulse period.
|
||||
//
|
||||
McBSP_setFrameSyncPulsePeriod(MCBSPA_BASE, 31);
|
||||
|
||||
//
|
||||
// Set frame-sync pulse width.
|
||||
//
|
||||
McBSP_setFrameSyncPulseWidthDivider(MCBSPA_BASE, 0);
|
||||
|
||||
//
|
||||
// Set the trigger source for internally generated frame-sync pulse.
|
||||
//
|
||||
McBSP_setTxInternalFrameSyncSource(MCBSPA_BASE,
|
||||
MCBSP_TX_INTERNAL_FRAME_SYNC_SRG);
|
||||
|
||||
//
|
||||
// Set LSPCLK as input source for sample rate generator.
|
||||
//
|
||||
McBSP_setTxSRGClockSource(MCBSPA_BASE, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK);
|
||||
|
||||
//
|
||||
// Set Divide down value for CLKG. CLKG frequency = LSPCLK/(CLKGDV+1)
|
||||
//
|
||||
McBSP_setSRGDataClockDivider(MCBSPA_BASE, 0);
|
||||
|
||||
//
|
||||
// Set no external clock sync for CLKG.
|
||||
//
|
||||
McBSP_disableSRGSyncFSR(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
|
||||
//
|
||||
// Enable Sample rate generator and wait for atleast 2 CLKG clock cycles.
|
||||
//
|
||||
McBSP_enableSampleRateGenerator(MCBSPA_BASE);
|
||||
McBSP_enableFrameSyncLogic(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 CLKG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/(LSPCLK/(1+CLKGDV_VAL))). In this
|
||||
// example LSPCLK = SYSCLK/4 and CLKGDV_VAL = 1.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(16);
|
||||
|
||||
//
|
||||
// Release Rx, Tx from reset.
|
||||
//
|
||||
HWREGH(MCBSPA_BASE + MCBSP_O_SPCR2) |= MCBSP_SPCR2_XRST;
|
||||
HWREGH(MCBSPA_BASE + MCBSP_O_SPCR1) |= MCBSP_SPCR1_RRST;
|
||||
}
|
||||
|
||||
//
|
||||
// Start DMA - This function starts DMA channel 1 & 2.
|
||||
//
|
||||
void startDMA(void)
|
||||
{
|
||||
DMA_startChannel(DMA_CH1_BASE);
|
||||
DMA_startChannel(DMA_CH2_BASE);
|
||||
}
|
||||
|
||||
//
|
||||
// Local DMA INT CH1 ISR - ISR for DMA channel 1 interrupt.
|
||||
//
|
||||
__interrupt void localDMAINTCH1ISR(void)
|
||||
{
|
||||
DMA_stopChannel(DMA_CH1_BASE);
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
|
||||
return;
|
||||
}
|
||||
|
||||
//
|
||||
// Local DMA INT CH2 ISR - ISR for DMA channel 2 interrupt.
|
||||
//
|
||||
__interrupt void localDMAINTCH2ISR(void)
|
||||
{
|
||||
uint16_t i;
|
||||
DMA_stopChannel(DMA_CH2_BASE);
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
|
||||
for(i = 0; i < 128; i++)
|
||||
{
|
||||
if(dataSize == 8)
|
||||
{
|
||||
if((rxData[i] & 0x00FF) != (txData[i] & 0x00FF))
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(rxData[i] != txData[i])
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -0,0 +1,323 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: mcbsp_ex3_loopback_interrupts.c
|
||||
//
|
||||
// TITLE: McBSP loopback with interrupts example.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> McBSP loopback with interrupts example </h1>
|
||||
//!
|
||||
//! This example demonstrates the McBSP operation using internal loopback.
|
||||
//! This example uses interrupts. Both Rx and Tx interrupts are enabled.
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - None
|
||||
//!
|
||||
//! \b Watch \b Variables: \n
|
||||
//! - \b txData - Sent data word
|
||||
//! - \b rxData - Received data word
|
||||
//! - \b errCountGlobal - Error counter
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright:
|
||||
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "device.h"
|
||||
#include "driverlib.h"
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// Define to select wait delay.
|
||||
//
|
||||
#define MCBSP_CYCLE_NOP0(n) __asm(" RPT #(" #n ") || NOP")
|
||||
#define MCBSP_CYCLE_NOP(n) MCBSP_CYCLE_NOP0(n)
|
||||
|
||||
//
|
||||
// Define to select the word size for McBSP operation to 8, 16 or 32 bit.
|
||||
//
|
||||
#define WORD_SIZE 8U
|
||||
//#define WORD_SIZE 16U
|
||||
//#define WORD_SIZE 32U
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint32_t errCountGlobal = 0;
|
||||
|
||||
//
|
||||
// Variables for transmitting, receiving and testing the data.
|
||||
//
|
||||
uint16_t txData;
|
||||
uint16_t rxData;
|
||||
uint16_t testData;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
extern void setupMcBSPAPinmux(void);
|
||||
void initMcBSPLoopback(void);
|
||||
|
||||
//
|
||||
// ISR for McBSPA Tx & Rx interrupts.
|
||||
//
|
||||
__interrupt void localMcBSPTxINTAISR(void);
|
||||
__interrupt void localMcBSPRxINTAISR(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
//
|
||||
// Initialize device clock and peripherals.
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Disable all the interrupts.
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups.
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize McBSP pins.
|
||||
//
|
||||
setupMcBSPAPinmux();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Interrupts that are used in this example are re-mapped to
|
||||
// ISR functions found within this file.
|
||||
//
|
||||
Interrupt_register(INT_MCBSPA_RX, localMcBSPRxINTAISR);
|
||||
Interrupt_register(INT_MCBSPA_TX, localMcBSPTxINTAISR);
|
||||
|
||||
//
|
||||
// Initialize and release peripheral (MCBSP) from reset.
|
||||
//
|
||||
initMcBSPLoopback();
|
||||
txData = 0;
|
||||
testData = txData;
|
||||
|
||||
//
|
||||
// Enable McBSP Tx and RX interrupts in PIE block.
|
||||
//
|
||||
Interrupt_enable(INT_MCBSPA_RX);
|
||||
Interrupt_enable(INT_MCBSPA_TX);
|
||||
|
||||
//
|
||||
// Enable group 7 CPU interrupt.
|
||||
//
|
||||
IER = 0x20;
|
||||
|
||||
//
|
||||
// Enable global interrupts.
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
//
|
||||
// Idle loop.
|
||||
//
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// Init McBSP Loopback - This function initialises McBSP peripheral in digital
|
||||
// loopback mode.
|
||||
//
|
||||
void initMcBSPLoopback()
|
||||
{
|
||||
//
|
||||
// Reset FS generator, sample rate generator, transmitter & receiver.
|
||||
//
|
||||
McBSP_resetFrameSyncLogic(MCBSPA_BASE);
|
||||
McBSP_resetSampleRateGenerator(MCBSPA_BASE);
|
||||
McBSP_resetTransmitter(MCBSPA_BASE);
|
||||
McBSP_resetReceiver(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Set Rx sign-extension and justification mode.
|
||||
//
|
||||
McBSP_setRxSignExtension(MCBSPA_BASE, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);
|
||||
|
||||
//
|
||||
// Enable DLB mode. Comment out for non-DLB mode.
|
||||
//
|
||||
McBSP_enableLoopback(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Set Rx & Tx delay to 1 cycle.
|
||||
//
|
||||
McBSP_setRxDataDelayBits(MCBSPA_BASE, MCBSP_DATA_DELAY_BIT_1);
|
||||
McBSP_setTxDataDelayBits(MCBSPA_BASE, MCBSP_DATA_DELAY_BIT_1);
|
||||
|
||||
//
|
||||
// Set CLKX & FSX source as sample rate generator.
|
||||
//
|
||||
McBSP_setTxClockSource(MCBSPA_BASE, MCBSP_INTERNAL_TX_CLOCK_SOURCE);
|
||||
McBSP_setTxFrameSyncSource(MCBSPA_BASE, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE);
|
||||
|
||||
//
|
||||
// Configure McBSP data behaviour.
|
||||
//
|
||||
McBSP_setRxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_8, 0);
|
||||
McBSP_setTxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_8, 0);
|
||||
|
||||
//
|
||||
// Set frame-sync pulse period.
|
||||
//
|
||||
McBSP_setFrameSyncPulsePeriod(MCBSPA_BASE, 320);
|
||||
|
||||
//
|
||||
// Set frame-sync pulse width.
|
||||
//
|
||||
McBSP_setFrameSyncPulseWidthDivider(MCBSPA_BASE, 1);
|
||||
|
||||
//
|
||||
// Set the trigger source for internally generated frame-sync pulse.
|
||||
//
|
||||
McBSP_setTxInternalFrameSyncSource(MCBSPA_BASE,
|
||||
MCBSP_TX_INTERNAL_FRAME_SYNC_SRG);
|
||||
|
||||
//
|
||||
// Set LSPCLK as input source for sample rate generator.
|
||||
//
|
||||
McBSP_setTxSRGClockSource(MCBSPA_BASE, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK);
|
||||
|
||||
//
|
||||
// Set Divide down value for CLKG.
|
||||
//
|
||||
McBSP_setSRGDataClockDivider(MCBSPA_BASE, 15);
|
||||
|
||||
//
|
||||
// Set no external clock sync for CLKG.
|
||||
//
|
||||
McBSP_disableSRGSyncFSR(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Enable Tx and Rx interrupts.
|
||||
//
|
||||
McBSP_enableRxInterrupt(MCBSPA_BASE);
|
||||
McBSP_enableTxInterrupt(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
|
||||
//
|
||||
// Enable Sample rate generator and wait for at least 2 CLKG clock cycles.
|
||||
//
|
||||
McBSP_enableSampleRateGenerator(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 CLKG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/(LSPCLK/(1+CLKGDV_VAL))). In this
|
||||
// example LSPCLK = SYSCLK/4 and CLKGDV_VAL = 1.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(16);
|
||||
|
||||
//
|
||||
// Release Rx, Tx from reset.
|
||||
//
|
||||
McBSP_enableReceiver(MCBSPA_BASE);
|
||||
McBSP_enableTransmitter(MCBSPA_BASE);
|
||||
McBSP_enableFrameSyncLogic(MCBSPA_BASE);
|
||||
}
|
||||
|
||||
//
|
||||
// local McBSP Tx INTA ISR - ISR for McBSPA Tx interrupt.
|
||||
//
|
||||
__interrupt void localMcBSPTxINTAISR(void)
|
||||
{
|
||||
McBSP_write16bitData(MCBSPA_BASE, txData);
|
||||
txData = (txData + 1) & 0x00FF;
|
||||
|
||||
//
|
||||
// Acknowledge the interrupt to receive more interrupts.
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
|
||||
}
|
||||
|
||||
//
|
||||
// local McBSP Rx INTA ISR - ISR for McBSPA Rx interrupt.
|
||||
//
|
||||
__interrupt void localMcBSPRxINTAISR(void)
|
||||
{
|
||||
rxData = McBSP_read16bitData(MCBSPA_BASE);
|
||||
if(rxData != (testData & 0x00FF))
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
testData = (testData + 1) & 0x00FF;
|
||||
|
||||
//
|
||||
// Acknowledge the interrupt to receive more interrupts.
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -0,0 +1,310 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: mcbsp_ex4_spi_loopback.c
|
||||
//
|
||||
// TITLE: McBSP loopback example using SPI mode.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> McBSP loopback example using SPI mode </h1>
|
||||
//!
|
||||
//! This example demonstrates the McBSP operation in SPI mode using internal
|
||||
//! loopback. This example demonstrates SPI master mode transfer of 32-bit word
|
||||
//! size with digital loopback enabled.
|
||||
//!
|
||||
//! \b McBSP \b Signals - \b SPI \b equivalent
|
||||
//! - MCLKX - SPICLK (master)
|
||||
//! - MFSX - SPISTE (master)
|
||||
//! - MDX - SPISIMO
|
||||
//! - MCLKR - SPICLK (slave - not used for this example)
|
||||
//! - MFSR - SPISTE (slave - not used for this example)
|
||||
//! - MDR - SPISOMI (not used for this example)
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - None
|
||||
//!
|
||||
//! \b Watch \b Variables: \n
|
||||
//! - \b txData1 - Sent data word: 8 or 16-bit or low half of 32-bit
|
||||
//! - \b txData2 - Sent data word: upper half of 32-bit
|
||||
//! - \b rxData1 - Received data word: 8 or 16-bit or low half of 32-bit
|
||||
//! - \b rxData2 - Received data word: upper half of 32-bit
|
||||
//! - \b errCountGlobal - Error counter
|
||||
//
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright:
|
||||
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "device.h"
|
||||
#include "driverlib.h"
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// Define to select delay in clock cycles.
|
||||
//
|
||||
#define MCBSP_CYCLE_NOP0(n) __asm(" RPT #(" #n ") || NOP")
|
||||
#define MCBSP_CYCLE_NOP(n) MCBSP_CYCLE_NOP0(n)
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint32_t errCountGlobal = 0;
|
||||
|
||||
//
|
||||
// Variables for transmitting, receiving and testing the data.
|
||||
//
|
||||
uint16_t txData1 = 0x0000;
|
||||
uint16_t txData2 = 0x0000;
|
||||
uint16_t rxData1 = 0x0000;
|
||||
uint16_t rxData2 = 0x0000;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
extern void setupMcBSPAPinmux(void);
|
||||
void initSPImode(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
uint32_t tempData;
|
||||
errCountGlobal = 0x0;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals.
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Disable all the interrupts.
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups.
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize GPIO.
|
||||
//
|
||||
setupMcBSPAPinmux();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Initialize and release peripheral (McBSP) from reset.
|
||||
//
|
||||
initSPImode();
|
||||
txData1 = 0x55aa;
|
||||
txData2 = 0xaa55;
|
||||
|
||||
//
|
||||
// Main loop to transfer 32-bit words through McBSP in SPI mode
|
||||
// periodically.
|
||||
//
|
||||
while(1)
|
||||
{
|
||||
//
|
||||
// Write data to be transmitted.
|
||||
//
|
||||
tempData = (txData1|(((uint32_t)txData2) << 16U));
|
||||
while(!McBSP_isTxReady(MCBSPA_BASE));
|
||||
McBSP_write32bitData(MCBSPA_BASE, tempData);
|
||||
|
||||
//
|
||||
// Check if data is recieved.
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPA_BASE));
|
||||
tempData = McBSP_read32bitData(MCBSPA_BASE);
|
||||
rxData1 = (uint16_t)(tempData & 0xFFFF);
|
||||
rxData2 = (uint16_t)(tempData >> 16U);
|
||||
if(rxData1 != txData1 || rxData2 != txData2)
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
txData1 ^= 0xFFFF;
|
||||
txData2 ^= 0xFFFF;
|
||||
NOP;
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Init SPI Mode - This function initialises McBSP in SPI with digital loopback
|
||||
// mode.
|
||||
//
|
||||
void initSPImode()
|
||||
{
|
||||
//
|
||||
// Reset FS generator, sample rate generator, transmitter, receiver.
|
||||
//
|
||||
McBSP_resetFrameSyncLogic(MCBSPA_BASE);
|
||||
McBSP_resetSampleRateGenerator(MCBSPA_BASE);
|
||||
McBSP_resetTransmitter(MCBSPA_BASE);
|
||||
McBSP_resetReceiver(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Set Rx sign-extension and justification mode.
|
||||
//
|
||||
|
||||
McBSP_setRxSignExtension(MCBSPA_BASE, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);
|
||||
|
||||
//
|
||||
// Enable DLB mode. Comment out for non-DLB mode.
|
||||
//
|
||||
McBSP_enableLoopback(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Enable clock stop mode.
|
||||
//
|
||||
McBSP_setClockStopMode(MCBSPA_BASE, MCBSP_CLOCK_SPI_MODE_NO_DELAY);
|
||||
|
||||
//
|
||||
// Set Rx & Tx delay to 1 cycle.
|
||||
//
|
||||
McBSP_setRxDataDelayBits(MCBSPA_BASE, MCBSP_DATA_DELAY_BIT_1);
|
||||
McBSP_setTxDataDelayBits(MCBSPA_BASE, MCBSP_DATA_DELAY_BIT_1);
|
||||
|
||||
//
|
||||
// Set CLKX & FSX source as sample rate generator.
|
||||
//
|
||||
McBSP_setTxClockSource(MCBSPA_BASE, MCBSP_INTERNAL_TX_CLOCK_SOURCE);
|
||||
McBSP_setRxClockSource(MCBSPA_BASE, MCBSP_INTERNAL_RX_CLOCK_SOURCE);
|
||||
McBSP_setTxFrameSyncSource(MCBSPA_BASE, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE);
|
||||
McBSP_setRxFrameSyncSource(MCBSPA_BASE, MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE);
|
||||
|
||||
//
|
||||
// Set Tx and Rx clock and frame-sync polarity.
|
||||
//
|
||||
McBSP_setTxFrameSyncPolarity(MCBSPA_BASE, MCBSP_TX_FRAME_SYNC_POLARITY_LOW);
|
||||
McBSP_setTxClockPolarity(MCBSPA_BASE, MCBSP_TX_POLARITY_RISING_EDGE);
|
||||
McBSP_setRxClockPolarity(MCBSPA_BASE, MCBSP_RX_POLARITY_FALLING_EDGE);
|
||||
|
||||
//
|
||||
// Initialize McBSP data length.
|
||||
//
|
||||
McBSP_setRxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_32, 0);
|
||||
McBSP_setTxDataSize(MCBSPA_BASE, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_32, 0);
|
||||
|
||||
//
|
||||
// Set frame synchronization pulse period to 1 CLKG cycle.
|
||||
//
|
||||
McBSP_setFrameSyncPulsePeriod(MCBSPA_BASE, 0);
|
||||
|
||||
//
|
||||
// Set frame-sync pulse width to 1 CLKG cycle.
|
||||
//
|
||||
McBSP_setFrameSyncPulseWidthDivider(MCBSPA_BASE, 0);
|
||||
|
||||
//
|
||||
// Set the trigger source for internally generated frame-sync pulse.
|
||||
//
|
||||
McBSP_setTxInternalFrameSyncSource(MCBSPA_BASE,
|
||||
MCBSP_TX_INTERNAL_FRAME_SYNC_DATA);
|
||||
|
||||
//
|
||||
// Set LSPCLK as input source for sample rate generator.
|
||||
//
|
||||
McBSP_setTxSRGClockSource(MCBSPA_BASE, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK);
|
||||
|
||||
//
|
||||
// Set Divide down value for CLKG.
|
||||
//
|
||||
McBSP_setSRGDataClockDivider(MCBSPA_BASE, 16);
|
||||
|
||||
//
|
||||
// Set no external clock sync for CLKG.
|
||||
//
|
||||
McBSP_disableSRGSyncFSR(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
|
||||
//
|
||||
// Enable Sample rate generator and wait for at least 2 CLKG clock cycles.
|
||||
//
|
||||
McBSP_enableSampleRateGenerator(MCBSPA_BASE);
|
||||
McBSP_enableFrameSyncLogic(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 CLKG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/(LSPCLK/(1+CLKGDV_VAL))). In this
|
||||
// example LSPCLK = SYSCLK/4 and CLKGDV_VAL = 1.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(16);
|
||||
|
||||
//
|
||||
// Release Rx, Tx and frame-sync generator from reset.
|
||||
//
|
||||
McBSP_enableTransmitter(MCBSPA_BASE);
|
||||
McBSP_enableReceiver(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -0,0 +1,580 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: mcbsp_ex5_ext_loopback.c
|
||||
//
|
||||
// TITLE: McBSP external loopback example.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> McBSP external loopback example </h1>
|
||||
//!
|
||||
//! This example demonstrates the McBSP operation using external loopback.
|
||||
//! This example does not use interrupts. Instead, a polling method is used
|
||||
//! to check the receive data. The incoming data is checked for accuracy.
|
||||
//!
|
||||
//! Three different serial word sizes can be tested. Before compiling
|
||||
//! this project, select the serial word size of 8, 16 or 32 by using
|
||||
//! the \#define statements at the beginning of the code.
|
||||
//!
|
||||
//! This program will execute until terminated by the user.
|
||||
//!
|
||||
//! \b 8-bit \b word \b example: \n
|
||||
//! The sent data looks like this:\n
|
||||
//! 00 01 02 03 04 05 06 07 .... FE FF\n
|
||||
//!
|
||||
//! \b 16-bit \b word \b example: \n
|
||||
//! The sent data looks like this:\n
|
||||
//! 0000 0001 0002 0003 0004 0005 0006 0007 .... FFFE FFFF\n
|
||||
//!
|
||||
//! \b 32-bit \b word \b example: \n
|
||||
//! The sent data looks like this: \n
|
||||
//! FFFF0000 FFFE0001 FFFD0002 .... 0000FFFF \n
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! \b McBSPA \b Signals - \b McBSPB \b signals
|
||||
//! - MCLKXA - MCLKRB
|
||||
//! - MFSXA - MFSRB
|
||||
//! - MDXA - MDRB
|
||||
//! - MCLKRA - MCLKXB
|
||||
//! - MFSRA - MFSXB
|
||||
//! - MDRA - MDXB
|
||||
//!
|
||||
//! \b Watch \b Variables: \n
|
||||
//! - \b txData1A - Sent data word by McBSPA Transmitter:8 or 16-bit or low
|
||||
//! half of 32-bit
|
||||
//! - \b txData2A - Sent data word by McBSPA Transmitter:upper half of 32-bit
|
||||
//! - \b rxData1A - Received data word by MCBSPA Receiver:8 or 16-bit or lower
|
||||
//! half of 32-bit
|
||||
//! - \b rxData2A - Received data word by McBSPA Receiver:upper half of 32-bit
|
||||
//! - \b txData1B - Sent data word by McBSPB Transmitter:8 or 16-bit or low
|
||||
//! half of 32-bit
|
||||
//! - \b txData2B - Sent data word by McBSPB Transmitter:upper half of 32-bit
|
||||
//! - \b rxData1B - Received data word by McBSPB Receiver:8 or 16-bit or lower
|
||||
//! half of 32-bit
|
||||
//! - \b rxData2B - Received data word by McBSPB Receiver:upper half of 32-bit
|
||||
//! - \b errCountGlobal - Error counter
|
||||
//!
|
||||
//! \note txData2A, rxData2A, txData2B and rxData2B are not used for 8-bit or
|
||||
//! 16-bit word size.
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright:
|
||||
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "device.h"
|
||||
#include "driverlib.h"
|
||||
|
||||
//
|
||||
// Define to select wait delay.
|
||||
//
|
||||
#define MCBSP_CYCLE_NOP0(n) __asm(" RPT #(" #n ") || NOP")
|
||||
#define MCBSP_CYCLE_NOP(n) MCBSP_CYCLE_NOP0(n)
|
||||
|
||||
//
|
||||
// Define to select the word-size for McBSP operation to 8, 16 or 32 bit.
|
||||
//
|
||||
//#define WORD_SIZE 8U
|
||||
//#define WORD_SIZE 16U
|
||||
#define WORD_SIZE 32U
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint32_t errCountGlobal = 0;
|
||||
|
||||
//
|
||||
// Variables for transmitting, receiving and testing the data.
|
||||
//
|
||||
uint16_t txData1A = 0x0000;
|
||||
uint16_t txData2A = 0x0000;
|
||||
|
||||
uint16_t rxData1A = 0x0000;
|
||||
uint16_t rxData2A = 0x0000;
|
||||
|
||||
uint16_t txData1B = 0x0000;
|
||||
uint16_t txData2B = 0x0000;
|
||||
|
||||
uint16_t rxData1B = 0x0000;
|
||||
uint16_t rxData2B = 0x0000;
|
||||
|
||||
uint16_t dataSize;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
extern void setupMcBSPAPinmux(void);
|
||||
extern void setupMcBSPBPinmux(void);
|
||||
void initMcBSPLoopback(void);
|
||||
void initTransmitter(uint32_t base);
|
||||
void initReceiver(uint32_t base);
|
||||
void enableModule(uint32_t base);
|
||||
void resetModule(uint32_t base);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
uint32_t tempData;
|
||||
errCountGlobal = 0x0;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals.
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Disable all the interrupts.
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups.
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize GPIOs for McBSPA and McBSPB.
|
||||
//
|
||||
setupMcBSPAPinmux();
|
||||
setupMcBSPBPinmux();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
dataSize = WORD_SIZE;
|
||||
|
||||
//
|
||||
// Reset McBSPA & McBSPB modules.
|
||||
//
|
||||
resetModule(MCBSPA_BASE);
|
||||
resetModule(MCBSPB_BASE);
|
||||
|
||||
//
|
||||
// Initialize the transmitter & receiver modules in McBSPA & McBSPB.
|
||||
//
|
||||
initTransmitter(MCBSPA_BASE);
|
||||
initReceiver(MCBSPA_BASE);
|
||||
initTransmitter(MCBSPB_BASE);
|
||||
initReceiver(MCBSPB_BASE);
|
||||
|
||||
//
|
||||
// Enable McBSPA & McBSP modules.
|
||||
//
|
||||
enableModule(MCBSPA_BASE);
|
||||
enableModule(MCBSPB_BASE);
|
||||
|
||||
//
|
||||
// Run a loopback test in 8-bit mode.
|
||||
//
|
||||
if(dataSize == 8)
|
||||
{
|
||||
txData1A = 0x0000;
|
||||
while(1)
|
||||
{
|
||||
//
|
||||
// Transmit 8-bit data from McBSPSA Tx.
|
||||
//
|
||||
while(!McBSP_isTxReady(MCBSPA_BASE));
|
||||
McBSP_write16bitData(MCBSPA_BASE, txData1A);
|
||||
|
||||
//
|
||||
// Checks if data is received at McBSPB Rx.
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPB_BASE));
|
||||
rxData1B = McBSP_read16bitData(MCBSPB_BASE);
|
||||
|
||||
txData1B = rxData1B;
|
||||
|
||||
//
|
||||
// Retransmit the received data from McBSPB Tx to McBSPA Rx.
|
||||
//
|
||||
while(!McBSP_isTxReady(MCBSPB_BASE));
|
||||
McBSP_write16bitData(MCBSPB_BASE, txData1B);
|
||||
|
||||
//
|
||||
// Receive data at McBSPA Rx.
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPA_BASE));
|
||||
rxData1A = McBSP_read16bitData(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Check if correct data is received.
|
||||
//
|
||||
if(rxData1A != txData1A)
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
txData1A++;
|
||||
txData1A = txData1A & 0x00FF;
|
||||
NOP;
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
}
|
||||
else if(dataSize == 16)
|
||||
{
|
||||
txData1A = 0x0000;
|
||||
while(1)
|
||||
{
|
||||
//
|
||||
// Transmit 16-bit data from McBSPSA Tx.
|
||||
//
|
||||
while(!McBSP_isTxReady(MCBSPA_BASE));
|
||||
McBSP_write16bitData(MCBSPA_BASE, txData1A);
|
||||
|
||||
//
|
||||
// Checks if data is received at McBSPB Rx.
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPB_BASE));
|
||||
rxData1B = McBSP_read16bitData(MCBSPB_BASE);
|
||||
|
||||
txData1B = rxData1B;
|
||||
|
||||
//
|
||||
// Retransmit the received data from McBSPB Tx to McBSPA Rx.
|
||||
//
|
||||
while(!McBSP_isTxReady(MCBSPB_BASE));
|
||||
McBSP_write16bitData(MCBSPB_BASE, txData1B);
|
||||
|
||||
//
|
||||
// Receive data at McBSPA Rx.
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPA_BASE));
|
||||
rxData1A = McBSP_read16bitData(MCBSPA_BASE);
|
||||
|
||||
//
|
||||
// Check if correct data is received.
|
||||
//
|
||||
if(rxData1A != txData1A)
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
txData1A++;
|
||||
NOP;
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
}
|
||||
else if(dataSize == 32)
|
||||
{
|
||||
txData2A = 0xFFFF;
|
||||
txData1A = 0x0000;
|
||||
while(1)
|
||||
{
|
||||
//
|
||||
// Transmit 32-bit data from McBSPSA Tx.
|
||||
//
|
||||
tempData = (txData1A|(((uint32_t)txData2A) << 16U));
|
||||
while(!McBSP_isTxReady(MCBSPA_BASE));
|
||||
McBSP_write32bitData(MCBSPA_BASE, tempData);
|
||||
|
||||
//
|
||||
// Check if data is received at McBSPB Rx.
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPB_BASE));
|
||||
tempData = McBSP_read32bitData(MCBSPB_BASE);
|
||||
rxData1B = tempData & 0xFFFF;
|
||||
rxData2B = tempData >> 16U;
|
||||
|
||||
//
|
||||
// Retransmit the received data from McBSPB Tx to McBSPA Rx.
|
||||
//
|
||||
txData1B = rxData1B;
|
||||
txData2B = rxData2B;
|
||||
tempData = (txData1B|(((uint32_t)txData2B) << 16U));
|
||||
while(!McBSP_isTxReady(MCBSPB_BASE));
|
||||
McBSP_write32bitData(MCBSPB_BASE, tempData);
|
||||
|
||||
//
|
||||
// Receive data at McBSPA Rx.
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPA_BASE));
|
||||
tempData = McBSP_read32bitData(MCBSPA_BASE);
|
||||
rxData1A = tempData & 0xFFFF;
|
||||
rxData2A = tempData >> 16U;
|
||||
|
||||
//
|
||||
// Check if correct data is received.
|
||||
//
|
||||
if(rxData1A != txData1A || rxData2A != txData2A)
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
txData1A++;
|
||||
txData2A--;
|
||||
NOP;
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Enable Module - This function enables the modules in McBSP.
|
||||
//
|
||||
void enableModule(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Enable Sample rate generator and frame-sync logic and wait for atleast
|
||||
// 2 CLKG clock cycles.
|
||||
//
|
||||
McBSP_enableSampleRateGenerator(base);
|
||||
McBSP_enableFrameSyncLogic(base);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 CLKG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/(LSPCLK/(1+CLKGDV_VAL))). In this
|
||||
// example LSPCLK = SYSCLK/4 and CLKGDV_VAL = 1.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(16);
|
||||
|
||||
//
|
||||
// Release Tx from reset.
|
||||
//
|
||||
McBSP_enableTransmitter(base);
|
||||
McBSP_enableReceiver(base);
|
||||
}
|
||||
|
||||
//
|
||||
// Reset Module - This function disables the modules in McBSP.
|
||||
//
|
||||
void resetModule(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Reset FS generator, sample rate generator, transmitter & receiver.
|
||||
//
|
||||
McBSP_resetFrameSyncLogic(base);
|
||||
McBSP_resetSampleRateGenerator(base);
|
||||
McBSP_resetTransmitter(base);
|
||||
McBSP_resetReceiver(base);
|
||||
}
|
||||
|
||||
//
|
||||
// Init Transmitter - This function initialises McBSP transmitter module.
|
||||
//
|
||||
void initTransmitter(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Right justify word.
|
||||
//
|
||||
McBSP_setRxSignExtension(base, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);
|
||||
|
||||
//
|
||||
// Set Rx & Tx delay to 1 cycle.
|
||||
//
|
||||
McBSP_setTxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1);
|
||||
|
||||
|
||||
//
|
||||
// Configure McBSP data behaviour: phase = 1; frame length = 1 word and
|
||||
// word length = dataSize.
|
||||
//
|
||||
if(dataSize == 8)
|
||||
{
|
||||
McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, MCBSP_BITS_PER_WORD_8,
|
||||
0);
|
||||
}
|
||||
else if(dataSize == 16)
|
||||
{
|
||||
McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, MCBSP_BITS_PER_WORD_16,
|
||||
0);
|
||||
}
|
||||
else if(dataSize == 32)
|
||||
{
|
||||
McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, MCBSP_BITS_PER_WORD_32,
|
||||
0);
|
||||
}
|
||||
|
||||
//
|
||||
// Configure Frame synchronization behaviour.
|
||||
//
|
||||
|
||||
//
|
||||
// Enable transmit frame-sync ignore function.
|
||||
//
|
||||
McBSP_disableTxFrameSyncErrorDetection(base);
|
||||
|
||||
//
|
||||
// Set Tx frame-sync source as internal.
|
||||
//
|
||||
McBSP_setTxFrameSyncSource(base, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE);
|
||||
|
||||
//
|
||||
// Set the trigger source for internally generated frame-sync pulse.
|
||||
//
|
||||
McBSP_setTxInternalFrameSyncSource(base, MCBSP_TX_INTERNAL_FRAME_SYNC_DATA);
|
||||
|
||||
//
|
||||
// Set no external clock sync for CLKG.
|
||||
//
|
||||
McBSP_disableSRGSyncFSR(base);
|
||||
|
||||
//
|
||||
// Set frame-sync pulse period.
|
||||
//
|
||||
McBSP_setFrameSyncPulsePeriod(base, 320);
|
||||
|
||||
//
|
||||
// Set frame-sync pulse width.
|
||||
//
|
||||
McBSP_setFrameSyncPulseWidthDivider(base, 1);
|
||||
|
||||
//
|
||||
// Configure Tx Clock behaviour.
|
||||
//
|
||||
|
||||
//
|
||||
// Set LSPCLK as input source for sample rate generator.
|
||||
//
|
||||
McBSP_setTxSRGClockSource(base, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK);
|
||||
|
||||
//
|
||||
// Set CLKX source as sample rate generator.
|
||||
//
|
||||
McBSP_setTxClockSource(base, MCBSP_INTERNAL_TX_CLOCK_SOURCE);
|
||||
|
||||
//
|
||||
// Set Divide down value for CLKG.
|
||||
//
|
||||
McBSP_setSRGDataClockDivider(base, 1);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
}
|
||||
|
||||
//
|
||||
// Init Receiver - This function initialises the McBSP Receiver module.
|
||||
//
|
||||
void initReceiver(uint32_t base)
|
||||
{
|
||||
//
|
||||
// Configure McBSP data behaviour.
|
||||
//
|
||||
if(dataSize == 8)
|
||||
{
|
||||
McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, MCBSP_BITS_PER_WORD_8,
|
||||
0);
|
||||
}
|
||||
else if(dataSize == 16)
|
||||
{
|
||||
McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, MCBSP_BITS_PER_WORD_16,
|
||||
0);
|
||||
}
|
||||
else if(dataSize == 32)
|
||||
{
|
||||
McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, MCBSP_BITS_PER_WORD_32,
|
||||
0);
|
||||
}
|
||||
|
||||
//
|
||||
// Set Rx data delay to 1 cycle.
|
||||
//
|
||||
McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1);
|
||||
|
||||
//
|
||||
// Set receive sign-extension and justification mode.
|
||||
//
|
||||
McBSP_setRxSignExtension(base, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);
|
||||
|
||||
//
|
||||
// Configure Rx frame-sync behaviour.
|
||||
//
|
||||
|
||||
//
|
||||
// Set Rx frame sync source as external.
|
||||
//
|
||||
McBSP_setRxFrameSyncSource(base, MCBSP_RX_EXTERNAL_FRAME_SYNC_SOURCE);
|
||||
|
||||
//
|
||||
// Disable DLB mode.
|
||||
//
|
||||
McBSP_disableLoopback(base);
|
||||
|
||||
//
|
||||
// Set no external clock sync for CLKG i.e. GSYNC = 0.
|
||||
//
|
||||
McBSP_disableSRGSyncFSR(base);
|
||||
|
||||
//
|
||||
// Configure Rx clock behaviour.
|
||||
//
|
||||
|
||||
//
|
||||
// Set MCLKR pin as source for CLKR.
|
||||
//
|
||||
McBSP_setRxClockSource(base, MCBSP_EXTERNAL_RX_CLOCK_SOURCE);
|
||||
|
||||
//
|
||||
// Set LSPCLK as input source for sample rate generator.
|
||||
//
|
||||
McBSP_setRxSRGClockSource(base, MCBSP_SRG_RX_CLOCK_SOURCE_LSPCLK);
|
||||
|
||||
//
|
||||
// Set Divide down value for CLKG.
|
||||
//
|
||||
McBSP_setSRGDataClockDivider(base, 1);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -0,0 +1,402 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: mcbsp_ex6_spi_ext_loopback.c
|
||||
//
|
||||
// TITLE: McBSP external loopback example using SPI mode.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> McBSP external loopback example using SPI mode </h1>
|
||||
//!
|
||||
//! This example demonstrates the McBSP operation in SPI mode using external
|
||||
//! loopback. This example configures McBSP instances available on the device
|
||||
//! as SPI master and slave and demonstrates transfer of 32-bit word size data
|
||||
//! with external loopback.
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! \b SPI Master(McBSPA) \b SPI Slave(McBSPB) \n
|
||||
//! - MCLKXA(SPICLK) (GPIO22) - MCLKXB(SPICLK) (GPIO26)
|
||||
//! - MFSXA (SPISTE) (GPIO23) - MFSXB (SPISTE) (GPIO27)
|
||||
//! - MDXA (SPISIMO)(GPIO20) - MDRB (SPISIMO)(GPIO25)
|
||||
//! - MDRA (SPISOMI)(GPIO21) - MDXB (SPISOMI)(GPIO24)
|
||||
//!
|
||||
//! \b Watch \b Variables: \n
|
||||
//! - \b txData1 - Sent data word: 8 or 16-bit or low half of 32-bit
|
||||
//! - \b txData2 - Sent data word: upper half of 32-bit
|
||||
//! - \b rxData1 - Received data word: 8 or 16-bit or low half of 32-bit
|
||||
//! - \b rxData2 - Received data word: upper half of 32-bit
|
||||
//! - \b errCountGlobal - Error counter
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright:
|
||||
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "device.h"
|
||||
#include "driverlib.h"
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// Define to select delay in clock cycles.
|
||||
//
|
||||
#define MCBSP_CYCLE_NOP0(n) __asm(" RPT #(" #n ") || NOP")
|
||||
#define MCBSP_CYCLE_NOP(n) MCBSP_CYCLE_NOP0(n)
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint32_t errCountGlobal = 0;
|
||||
|
||||
//
|
||||
// Variables for transmitting, receiving and testing the data.
|
||||
//
|
||||
uint16_t txData1 = 0x0000;
|
||||
uint16_t txData2 = 0x0000;
|
||||
uint16_t rxData1 = 0x0000;
|
||||
uint16_t rxData2 = 0x0000;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
extern void setupMcBSPAPinmux(void);
|
||||
extern void setupMcBSPBPinmux(void);
|
||||
void initSPIMasterMode(uint32_t masterBase);
|
||||
void initSPISlaveMode(uint32_t slaveBase);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
uint32_t tempData;
|
||||
errCountGlobal = 0x0;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals.
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Disable all the interrupts.
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups.
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize GPIO.
|
||||
//
|
||||
setupMcBSPAPinmux();
|
||||
setupMcBSPBPinmux();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Initialize and release McBSPA and McBSPB from reset.
|
||||
//
|
||||
initSPIMasterMode(MCBSPA_BASE);
|
||||
initSPISlaveMode(MCBSPB_BASE);
|
||||
txData1 = 0x55aa;
|
||||
txData2 = 0xaa55;
|
||||
|
||||
//
|
||||
// Main loop to transfer 32-bit words through McBSP in SPI mode
|
||||
// periodically.
|
||||
//
|
||||
while(1)
|
||||
{
|
||||
//
|
||||
// Write data to be transmitted from SPI master
|
||||
//
|
||||
tempData = (txData1|(((uint32_t)txData2) << 16U));
|
||||
while(!McBSP_isTxReady(MCBSPA_BASE));
|
||||
McBSP_write32bitData(MCBSPA_BASE, tempData);
|
||||
|
||||
//
|
||||
// Check if data is received as SPI slave
|
||||
//
|
||||
while(!McBSP_isRxReady(MCBSPB_BASE));
|
||||
tempData = McBSP_read32bitData(MCBSPB_BASE);
|
||||
rxData1 = (uint16_t)(tempData & 0xFFFF);
|
||||
rxData2 = (uint16_t)(tempData >> 16U);
|
||||
if((rxData1 != txData1) || (rxData2 != txData2))
|
||||
{
|
||||
errCountGlobal++;
|
||||
Example_Fail = 1;
|
||||
ESTOP0;
|
||||
}
|
||||
txData1 ^= 0xFFFF;
|
||||
txData2 ^= 0xFFFF;
|
||||
NOP;
|
||||
|
||||
Example_PassCount++;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Init SPI Master Mode - This function initializes McBSP in SPI master mode.
|
||||
//
|
||||
void initSPIMasterMode(uint32_t masterBase)
|
||||
{
|
||||
//
|
||||
// Reset FS generator, sample rate generator, transmitter, receiver.
|
||||
//
|
||||
McBSP_resetFrameSyncLogic(masterBase);
|
||||
McBSP_resetSampleRateGenerator(masterBase);
|
||||
McBSP_resetTransmitter(masterBase);
|
||||
McBSP_resetReceiver(masterBase);
|
||||
|
||||
//
|
||||
// Set Rx sign-extension and justification mode.
|
||||
//
|
||||
McBSP_setRxSignExtension(masterBase, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);
|
||||
|
||||
//
|
||||
// Enable clock stop mode.
|
||||
//
|
||||
McBSP_setClockStopMode(masterBase, MCBSP_CLOCK_SPI_MODE_NO_DELAY);
|
||||
|
||||
//
|
||||
// Set Rx & Tx delay to 1 cycle.
|
||||
//
|
||||
McBSP_setRxDataDelayBits(masterBase, MCBSP_DATA_DELAY_BIT_1);
|
||||
McBSP_setTxDataDelayBits(masterBase, MCBSP_DATA_DELAY_BIT_1);
|
||||
|
||||
//
|
||||
// Set CLKX & FSX source as sample rate generator.
|
||||
//
|
||||
McBSP_setTxClockSource(masterBase, MCBSP_INTERNAL_TX_CLOCK_SOURCE);
|
||||
McBSP_setRxClockSource(masterBase, MCBSP_INTERNAL_RX_CLOCK_SOURCE);
|
||||
McBSP_setTxFrameSyncSource(masterBase, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE);
|
||||
McBSP_setRxFrameSyncSource(masterBase, MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE);
|
||||
|
||||
//
|
||||
// Set Tx and Rx clock and frame-sync polarity.
|
||||
//
|
||||
McBSP_setTxFrameSyncPolarity(masterBase, MCBSP_TX_FRAME_SYNC_POLARITY_LOW);
|
||||
McBSP_setTxClockPolarity(masterBase, MCBSP_TX_POLARITY_RISING_EDGE);
|
||||
McBSP_setRxClockPolarity(masterBase, MCBSP_RX_POLARITY_FALLING_EDGE);
|
||||
|
||||
//
|
||||
// Initialize McBSP data length.
|
||||
//
|
||||
McBSP_setRxDataSize(masterBase, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_32, 0);
|
||||
McBSP_setTxDataSize(masterBase, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_32, 0);
|
||||
|
||||
//
|
||||
// Set frame synchronization pulse period to 1 CLKG cycle.
|
||||
//
|
||||
McBSP_setFrameSyncPulsePeriod(masterBase, 0);
|
||||
|
||||
//
|
||||
// Set frame-sync pulse width to 1 CLKG cycle.
|
||||
//
|
||||
McBSP_setFrameSyncPulseWidthDivider(masterBase, 0);
|
||||
|
||||
//
|
||||
// Set the trigger source for internally generated frame-sync pulse.
|
||||
//
|
||||
McBSP_setTxInternalFrameSyncSource(masterBase,
|
||||
MCBSP_TX_INTERNAL_FRAME_SYNC_DATA);
|
||||
|
||||
//
|
||||
// Set LSPCLK as input source for sample rate generator.
|
||||
//
|
||||
McBSP_setTxSRGClockSource(masterBase, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK);
|
||||
|
||||
//
|
||||
// Set Divide down value for CLKG.
|
||||
//
|
||||
McBSP_setSRGDataClockDivider(masterBase, 16);
|
||||
|
||||
//
|
||||
// Set no external clock sync for CLKG.
|
||||
//
|
||||
McBSP_disableSRGSyncFSR(masterBase);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
|
||||
//
|
||||
// Enable Sample rate generator and wait for at least 2 CLKG clock cycles.
|
||||
//
|
||||
McBSP_enableSampleRateGenerator(masterBase);
|
||||
McBSP_enableFrameSyncLogic(masterBase);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 CLKG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/(LSPCLK/(1+CLKGDV_VAL))). In this
|
||||
// example LSPCLK = SYSCLK/4 and CLKGDV_VAL = 1.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(16);
|
||||
|
||||
//
|
||||
// Release Rx, Tx and frame-sync generator from reset.
|
||||
//
|
||||
McBSP_enableTransmitter(masterBase);
|
||||
McBSP_enableReceiver(masterBase);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Init SPI Slave Mode - This function initializes McBSP in SPI slave mode.
|
||||
//
|
||||
void initSPISlaveMode(uint32_t slaveBase)
|
||||
{
|
||||
//
|
||||
// Reset FS generator, sample rate generator, transmitter, receiver.
|
||||
//
|
||||
McBSP_resetFrameSyncLogic(slaveBase);
|
||||
McBSP_resetSampleRateGenerator(slaveBase);
|
||||
McBSP_resetTransmitter(slaveBase);
|
||||
McBSP_resetReceiver(slaveBase);
|
||||
|
||||
//
|
||||
// Set Rx sign-extension and justification mode.
|
||||
//
|
||||
McBSP_setRxSignExtension(slaveBase, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);
|
||||
|
||||
//
|
||||
// Enable clock stop mode.
|
||||
//
|
||||
McBSP_setClockStopMode(slaveBase, MCBSP_CLOCK_SPI_MODE_NO_DELAY);
|
||||
|
||||
//
|
||||
// Set Rx & Tx delay to 0.
|
||||
//
|
||||
McBSP_setRxDataDelayBits(slaveBase, MCBSP_DATA_DELAY_BIT_0);
|
||||
McBSP_setTxDataDelayBits(slaveBase, MCBSP_DATA_DELAY_BIT_0);
|
||||
|
||||
//
|
||||
// Set CLKX & FSX as inputs
|
||||
//
|
||||
McBSP_setTxClockSource(slaveBase, MCBSP_EXTERNAL_TX_CLOCK_SOURCE);
|
||||
McBSP_setTxFrameSyncSource(slaveBase, MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE);
|
||||
|
||||
//
|
||||
// Set Tx and Rx clock and frame-sync polarity.
|
||||
//
|
||||
McBSP_setTxFrameSyncPolarity(slaveBase, MCBSP_TX_FRAME_SYNC_POLARITY_LOW);
|
||||
McBSP_setTxClockPolarity(slaveBase, MCBSP_TX_POLARITY_RISING_EDGE);
|
||||
McBSP_setRxClockPolarity(slaveBase, MCBSP_RX_POLARITY_FALLING_EDGE);
|
||||
|
||||
//
|
||||
// Initialize McBSP data length.
|
||||
//
|
||||
McBSP_setRxDataSize(slaveBase, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_32, 0);
|
||||
McBSP_setTxDataSize(slaveBase, MCBSP_PHASE_ONE_FRAME,
|
||||
MCBSP_BITS_PER_WORD_32, 0);
|
||||
|
||||
//
|
||||
// Set LSPCLK as input source for sample rate generator.
|
||||
//
|
||||
McBSP_setTxSRGClockSource(slaveBase, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK);
|
||||
|
||||
//
|
||||
// Set Divide down value for CLKG.
|
||||
//
|
||||
McBSP_setSRGDataClockDivider(slaveBase, 1);
|
||||
|
||||
//
|
||||
// Set no external clock sync for CLKG.
|
||||
//
|
||||
McBSP_disableSRGSyncFSR(slaveBase);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
|
||||
//
|
||||
// Enable Sample rate generator and wait for at least 2 CLKG clock cycles.
|
||||
//
|
||||
McBSP_enableSampleRateGenerator(slaveBase);
|
||||
McBSP_enableFrameSyncLogic(slaveBase);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 CLKG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/(LSPCLK/(1+CLKGDV_VAL))). In this
|
||||
// example LSPCLK = SYSCLK/4 and CLKGDV_VAL = 1.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(16);
|
||||
|
||||
//
|
||||
// Release Rx, Tx and frame-sync generator from reset.
|
||||
//
|
||||
McBSP_enableTransmitter(slaveBase);
|
||||
McBSP_enableReceiver(slaveBase);
|
||||
|
||||
//
|
||||
// Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
|
||||
// Total cycles required = 2*(SYSCLK/LSPCLK). In this example
|
||||
// LSPCLK = SYSCLK/4.
|
||||
//
|
||||
MCBSP_CYCLE_NOP(8);
|
||||
}
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -0,0 +1,194 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: mcbsp_pin_setup.c
|
||||
//
|
||||
// TITLE: Pin Setup for McBSP module.
|
||||
//
|
||||
// This file contains functions to configures pins for McBSPA and McBSPB.
|
||||
//
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright:
|
||||
// Copyright (C) 2014-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include <stdint.h>
|
||||
#include "device.h"
|
||||
#include "driverlib.h"
|
||||
|
||||
#ifdef CPU1
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void setupMcBSPAPinmux(void);
|
||||
void setupMcBSPBPinmux(void);
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// Setup McBSPA Pinmux - This function configures pins for McBSPA instance.
|
||||
//
|
||||
void setupMcBSPAPinmux(void)
|
||||
{
|
||||
//
|
||||
// This specifies which of the possible GPIO pins will be McBSPA functional
|
||||
// pins. Comment out unwanted connections. Set qualification for selected
|
||||
// input pins to asynchronous only. This will select asynchronous (no
|
||||
// qualification) for the selected pins.
|
||||
//
|
||||
|
||||
//
|
||||
// MDXA pin - GPIO20 or GPIO84
|
||||
//
|
||||
GPIO_setPinConfig(GPIO_20_MDXA);
|
||||
GPIO_setQualificationMode(20, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_84_MDXA);
|
||||
//GPIO_setQualificationMode(84, GPIO_QUAL_ASYNC);
|
||||
|
||||
//
|
||||
// MDRA pin - GPIO21 or GPIO85
|
||||
//
|
||||
GPIO_setPinConfig(GPIO_21_MDRA);
|
||||
GPIO_setQualificationMode(21, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_85_MDRA);
|
||||
//GPIO_setQualificationMode(85, GPIO_QUAL_ASYNC);
|
||||
|
||||
//
|
||||
// MCLKXA - GPIO22 or GPIO86
|
||||
//
|
||||
GPIO_setPinConfig(GPIO_22_MCLKXA);
|
||||
GPIO_setQualificationMode(22, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_86_MCLKXA);
|
||||
//GPIO_setQualificationMode(86, GPIO_QUAL_ASYNC);
|
||||
|
||||
//
|
||||
// MCLKRA - GPIO7 or GPIO58
|
||||
//
|
||||
GPIO_setPinConfig(GPIO_7_MCLKRA);
|
||||
GPIO_setQualificationMode(7, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_58_MCLKRA);
|
||||
//GPIO_setQualificationMode(58, GPIO_QUAL_ASYNC);
|
||||
|
||||
//
|
||||
// MFSXA - GPIO23 or GPIO87
|
||||
//
|
||||
GPIO_setPinConfig(GPIO_23_MFSXA);
|
||||
GPIO_setQualificationMode(23, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_87_MFSXA);
|
||||
//GPIO_setQualificationMode(87, GPIO_QUAL_ASYNC);
|
||||
|
||||
//
|
||||
// MFSRA - GPIO5 or GPIO59
|
||||
//
|
||||
GPIO_setPinConfig(GPIO_5_MFSRA);
|
||||
GPIO_setQualificationMode(5, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_59_MFSRA);
|
||||
//GPIO_setQualificationMode(59, GPIO_QUAL_ASYNC);
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
// Setup McBSPB Pinmux - This function configures pins for McBSPB instance.
|
||||
//
|
||||
void setupMcBSPBPinmux(void)
|
||||
{
|
||||
//
|
||||
// This specifies which of the possible GPIO pins will be McBSPB functional
|
||||
// pins. Comment out unwanted connections. Set qualification for selected
|
||||
// input pins to asynchronous only. This will select asynchronous (no
|
||||
// qualification) for the selected pins.
|
||||
//
|
||||
|
||||
//
|
||||
// MDXB pin - GPIO24 or GPIO84
|
||||
//
|
||||
GPIO_setPinConfig(GPIO_24_MDXB);
|
||||
GPIO_setQualificationMode(24, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_84_MDXB);
|
||||
//GPIO_setQualificationMode(84, GPIO_QUAL_ASYNC);
|
||||
|
||||
//
|
||||
// MDRB pin - GPIO13 or GPIO25 or GPIO85
|
||||
//
|
||||
//GPIO_setPinConfig(GPIO_13_MDRB);
|
||||
//GPIO_setQualificationMode(13, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_25_MDRB);
|
||||
GPIO_setQualificationMode(25, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_85_MDRA);
|
||||
//GPIO_setQualificationMode(85, GPIO_QUAL_ASYNC);
|
||||
|
||||
//
|
||||
// MCLKXB - GPIO14 or GPIO26 or GPIO86
|
||||
//
|
||||
//GPIO_setPinConfig(GPIO_14_MCLKXB);
|
||||
//GPIO_setQualificationMode(14, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_26_MCLKXB);
|
||||
GPIO_setQualificationMode(26, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_86_MCLKXA);
|
||||
//GPIO_setQualificationMode(86, GPIO_QUAL_ASYNC);
|
||||
|
||||
//
|
||||
// MCLKRB - GPIO3 or GPIO60
|
||||
//
|
||||
GPIO_setPinConfig(GPIO_3_MCLKRB);
|
||||
GPIO_setQualificationMode(3, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_60_MCLKRB);
|
||||
//GPIO_setQualificationMode(60, GPIO_QUAL_ASYNC);
|
||||
|
||||
//
|
||||
// MFSXB - GPIO15 or GPIO27 or GPIO87
|
||||
//
|
||||
//GPIO_setPinConfig(GPIO_15_MFSXB);
|
||||
//GPIO_setQualificationMode(15, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_27_MFSXB);
|
||||
GPIO_setQualificationMode(27, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_87_MFSXA);
|
||||
//GPIO_setQualificationMode(87, GPIO_QUAL_ASYNC);
|
||||
|
||||
//
|
||||
// MFSRB - GPIO1 or GPIO61
|
||||
//
|
||||
GPIO_setPinConfig(GPIO_1_MFSRB);
|
||||
GPIO_setQualificationMode(1, GPIO_QUAL_ASYNC);
|
||||
//GPIO_setPinConfig(GPIO_61_MFSRB);
|
||||
//GPIO_setQualificationMode(61, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
Reference in New Issue
Block a user