Update repo
This commit is contained in:
@@ -0,0 +1,40 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="bgcrc_ex1_cpuinterrupt"
|
||||
device="TMS320F28388D"
|
||||
cgtVersion="22.6.1.LTS"
|
||||
products="sysconfig;C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
|
||||
postBuildStep="
|
||||
echo "========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) ============="
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js" "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/" "${BuildDirectory}/syscfg" "${BuildDirectory}/syscfg/clb.dot"
|
||||
;if ${GENERATE_DIAGRAM} == 1 mkdir "${BuildDirectory}/diagrams"
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js" "${C2000WARE_ROOT}" "${BuildDirectory}/diagrams" "${BuildDirectory}/syscfg"
|
||||
"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
|
||||
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
|
||||
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
|
||||
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../bgcrc_ex1_cpuinterrupt.c" targetDirectory="" />
|
||||
<file action="copy" path="../bgcrc_ex1_cpuinterrupt.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="bgcrc_ex2_cpubgcrc_basic"
|
||||
device="TMS320F28388D"
|
||||
cgtVersion="22.6.1.LTS"
|
||||
products="sysconfig;C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
|
||||
postBuildStep="
|
||||
echo "========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) ============="
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js" "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/" "${BuildDirectory}/syscfg" "${BuildDirectory}/syscfg/clb.dot"
|
||||
;if ${GENERATE_DIAGRAM} == 1 mkdir "${BuildDirectory}/diagrams"
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js" "${C2000WARE_ROOT}" "${BuildDirectory}/diagrams" "${BuildDirectory}/syscfg"
|
||||
"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
|
||||
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
|
||||
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
|
||||
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../bgcrc_ex2_cpubgcrc_basic.c" targetDirectory="" />
|
||||
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="bgcrc_ex3_clabgcrc_crcmode"
|
||||
device="TMS320F28388D"
|
||||
cgtVersion="22.6.1.LTS"
|
||||
products="sysconfig;C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
|
||||
postBuildStep="
|
||||
echo "========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) ============="
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js" "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/" "${BuildDirectory}/syscfg" "${BuildDirectory}/syscfg/clb.dot"
|
||||
;if ${GENERATE_DIAGRAM} == 1 mkdir "${BuildDirectory}/diagrams"
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js" "${C2000WARE_ROOT}" "${BuildDirectory}/diagrams" "${BuildDirectory}/syscfg"
|
||||
"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
|
||||
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
|
||||
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
|
||||
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../bgcrc_ex3_clabgcrc_crcmode.c" targetDirectory="" />
|
||||
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="bgcrc_ex4_clabgcrc_scrubmode"
|
||||
device="TMS320F28388D"
|
||||
cgtVersion="22.6.1.LTS"
|
||||
products="sysconfig;C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
|
||||
postBuildStep="
|
||||
echo "========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) ============="
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js" "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/" "${BuildDirectory}/syscfg" "${BuildDirectory}/syscfg/clb.dot"
|
||||
;if ${GENERATE_DIAGRAM} == 1 mkdir "${BuildDirectory}/diagrams"
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js" "${C2000WARE_ROOT}" "${BuildDirectory}/diagrams" "${BuildDirectory}/syscfg"
|
||||
"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
|
||||
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
|
||||
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
|
||||
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../bgcrc_ex4_clabgcrc_scrubmode.c" targetDirectory="" />
|
||||
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
@@ -0,0 +1,185 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: bgcrc_ex1_cpuinterrupt.c
|
||||
//
|
||||
// TITLE: Background CRC computation with interrupt.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> BGCRC CPU Interrupt Example </h1>
|
||||
//!
|
||||
//! This example demonstrates how to configure and trigger BGCRC from the CPU.
|
||||
//! BGCRC module is configured for 1 KB of GS0 RAM which is programmed with a
|
||||
//! known data. The pre-computed CRC value is used as the golden CRC value.
|
||||
//! Interrupt is generated once the computation is done and checks if no error
|
||||
//! flags are raised
|
||||
//! Calculation uses the 32-bit polynomial 0x04C11DB7 and seed value 0x00000000.
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - None.
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - pass - This should be 1.
|
||||
//! - runStatus - BGCRC running status. This will be BGCRC_ACTIVE if the module
|
||||
//! is running, BGCRC_IDLE if the module is idle
|
||||
//!
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
#include "board.h"
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
bool pass = false;
|
||||
|
||||
volatile uint32_t currentAddress = 0x0000;
|
||||
volatile bool runStatus = false;
|
||||
|
||||
#pragma DATA_SECTION(test_data_gs0, "ramgs0")
|
||||
#pragma DATA_ALIGN(test_data_gs0, 0x80)
|
||||
uint32_t test_data_gs0[myBGCRC0_BLOCKSIZE/4];
|
||||
const void *td_gs0 = test_data_gs0;
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
__interrupt void bgcrcISR(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Initialize GPIO and configure the GPIO pin as a push-pull output
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Disable global interrupts.
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
//
|
||||
// Fill RAMGS0 with known data
|
||||
//
|
||||
for(i = 0; i < (myBGCRC0_BLOCKSIZE/4); i++)
|
||||
{
|
||||
test_data_gs0[i] = 0x1000 + i;
|
||||
}
|
||||
//
|
||||
// Set runStatus to true
|
||||
//
|
||||
runStatus = true;
|
||||
|
||||
//initialize sysconfig options
|
||||
//
|
||||
Board_init();
|
||||
|
||||
//
|
||||
// Loop Forever
|
||||
//
|
||||
while(1)
|
||||
{
|
||||
//
|
||||
// Check the run status and current address of the CRC calculation.
|
||||
//
|
||||
runStatus = BGCRC_getRunStatus(myBGCRC0_BASE);
|
||||
currentAddress = BGCRC_getCurrentAddress(myBGCRC0_BASE);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// bgcrcISR - DONE interrupt from BGCRC.
|
||||
//
|
||||
__interrupt void
|
||||
bgcrcISR(void)
|
||||
{
|
||||
//
|
||||
// Check the status of the CRC calculation and set the global pass
|
||||
// variable. Check if no error flags are set.
|
||||
//
|
||||
if(BGCRC_getInterruptStatus(myBGCRC0_BASE) == (BGCRC_GLOBAL_INT | BGCRC_TEST_DONE))
|
||||
{
|
||||
pass = true;
|
||||
}
|
||||
|
||||
//
|
||||
// Clear the BGCRC interrupt flags.
|
||||
//
|
||||
BGCRC_clearInterruptStatus(myBGCRC0_BASE, (BGCRC_GLOBAL_INT | BGCRC_TEST_DONE | BGCRC_ALL_ERROR_FLAGS));
|
||||
|
||||
//
|
||||
// Acknowledge the PIE interrupt.
|
||||
//
|
||||
|
||||
Interrupt_clearACKGroup(INT_myBGCRC0_INTERRUPT_ACK_GROUP);
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -0,0 +1,29 @@
|
||||
/**
|
||||
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
|
||||
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
|
||||
* @cliArgs --device "F28002x" --package "80QFP" --part "F28002x_80QFP" --product "C2000WARE@4.00.00.00"
|
||||
* @versions {"tool":"1.11.0+2225"}
|
||||
*/
|
||||
|
||||
/**
|
||||
* Import the modules used in this configuration.
|
||||
*/
|
||||
const bgcrc = scripting.addModule("/driverlib/bgcrc.js", {}, false);
|
||||
const bgcrc1 = bgcrc.addInstance();
|
||||
|
||||
/**
|
||||
* Write custom configuration values to the imported modules.
|
||||
*/
|
||||
bgcrc1.$name = "myBGCRC0";
|
||||
bgcrc1.goldVal = "0x8474ca32";
|
||||
bgcrc1.seedVal = "0";
|
||||
bgcrc1.intFlags = ["BGCRC_TEST_DONE"];
|
||||
bgcrc1.emuCtl = "BGCRC_EMUCTRL_FREE";
|
||||
bgcrc1.nmiMode = "BGCRC_NMI_DISABLE";
|
||||
bgcrc1.blockSize = "1024";
|
||||
bgcrc1.registerInterrupts = true;
|
||||
bgcrc1.startBGCRC = true;
|
||||
bgcrc1.startAddrInputMode = "VARIABLE";
|
||||
bgcrc1.startAddrVariable = "td_gs0";
|
||||
bgcrc1.bgcrcInt.enableInterrupt = true;
|
||||
bgcrc1.bgcrcInt.interruptHandler = "bgcrcISR";
|
||||
@@ -0,0 +1,471 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: bgcrc_ex2_basic_cpubgcrc.c
|
||||
//
|
||||
// TITLE: Background CRC computation with interrupt.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> BGCRC Example with Watchdog and Lock</h1>
|
||||
//!
|
||||
//! This example demonstrates how to configure and trigger BGCRC from the CPU.
|
||||
//! It also showcases how to configure the CRC watchdog and lock the
|
||||
//! registers after configuring the module. The watchdog is used as a diagnostic
|
||||
//! to check memory test completion within the expected time window. An error
|
||||
//! signal is generated if the test does not complete in the specified time
|
||||
//! window.
|
||||
//!
|
||||
//! The module is configured for 1kB of GS0 RAM which is programmed with
|
||||
//! random data. The golden CRC value for comparison is computed using software
|
||||
//! method. Interrupt is generated once the computation is done and checks if no
|
||||
//! error flags are raised. The NMI is enabled and is triggered if an error is
|
||||
//! detected.
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - None.
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - pass
|
||||
//! - bgcrcDone
|
||||
//!
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
#include <stdlib.h>
|
||||
#include <time.h>
|
||||
|
||||
//
|
||||
// Defines and globals
|
||||
//
|
||||
#define DATA_SIZE 256 // Total size = 256 * 4 = 1kB
|
||||
#define CRC_FAIL 0 // Set this as 1 to make the CRC check fail
|
||||
|
||||
uint32_t POLYNOMIAL = (uint32_t)0x04C11DB7;
|
||||
uint32_t crc32;
|
||||
uint32_t seed;
|
||||
uint32_t byteSwappedData;
|
||||
|
||||
volatile bool bgcrcDone = false;
|
||||
volatile bool bgcrcError = false;
|
||||
volatile uint32_t BgcrcNmiStatus = 0;
|
||||
volatile uint32_t intStatus =0;
|
||||
volatile bool Bgcrc_fail = false;
|
||||
volatile bool Bgcrc_uncorr_err = false;
|
||||
volatile bool Bgcrc_corr_err = false;
|
||||
volatile bool Bgcrc_Wd_underflow = false;
|
||||
volatile bool Bgcrc_Wd_overflow = false;
|
||||
volatile bool error_status_pin_diagnostic_failed = false;
|
||||
|
||||
bool pass = false;
|
||||
|
||||
#pragma DATA_SECTION(data,"ramgs0")
|
||||
#pragma DATA_ALIGN(data, 0x80)
|
||||
volatile uint32_t data[DATA_SIZE] = {0};
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void dataInit(void);
|
||||
void bgcrcInit(void);
|
||||
void delay(uint32_t i);
|
||||
__interrupt void CPUbgcrcIsr(void);
|
||||
__interrupt void NMIbgcrcIsr(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
//
|
||||
// Initialize device clock and peripherals
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Initialize GPIO and configure the GPIO pin as a push-pull output
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Disable global interrupts.
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
//
|
||||
// Map the ISRs of the BGCRC interrupt and NMI.
|
||||
//
|
||||
Interrupt_register(INT_CPUCRC, CPUbgcrcIsr);
|
||||
Interrupt_register(INT_NMI, NMIbgcrcIsr);
|
||||
|
||||
//
|
||||
// Enable the BGCRC interrupt
|
||||
//
|
||||
Interrupt_enable(INT_CPUCRC);
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP12);
|
||||
|
||||
//
|
||||
// Enable NMI
|
||||
//
|
||||
Interrupt_enable(INT_NMI);
|
||||
SysCtl_enableNMIGlobalInterrupt();
|
||||
SysCtl_setNMIWatchdogPeriod(0xFFFFU);
|
||||
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
//
|
||||
// Initialize the data with random numbers
|
||||
//
|
||||
dataInit();
|
||||
|
||||
//
|
||||
// Initialize the BGCRC module
|
||||
//
|
||||
bgcrcInit();
|
||||
|
||||
delay(2000); // Expecting the BGCRC completion in this time
|
||||
|
||||
if(error_status_pin_diagnostic_failed == true )
|
||||
{
|
||||
//
|
||||
// Something is wrong with the error status pin
|
||||
// Need to reset the system
|
||||
//
|
||||
}
|
||||
|
||||
if((bgcrcDone == true) && (bgcrcError == false))
|
||||
{
|
||||
if((intStatus == BGCRC_TEST_DONE))
|
||||
{
|
||||
pass = true;
|
||||
}
|
||||
}
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// Fill the buffer with random data and compute CRC using SW method
|
||||
//
|
||||
void dataInit()
|
||||
{
|
||||
uint32_t tseed;
|
||||
uint32_t i,j;
|
||||
|
||||
//
|
||||
// Initialize the random number generator
|
||||
//
|
||||
tseed = time(NULL);
|
||||
srand(tseed);
|
||||
srand(rand());
|
||||
|
||||
seed = rand();
|
||||
seed = (uint32_t)(seed <<16) | rand(); // Initialize with seed
|
||||
crc32 = seed;
|
||||
|
||||
//
|
||||
// Initialize the Data_Buffer with 32 bit random data
|
||||
//
|
||||
for(i = 0; i < DATA_SIZE; i++)
|
||||
{
|
||||
data[i] = rand();
|
||||
data[i] = (data[i] << 16) | rand();
|
||||
}
|
||||
|
||||
//
|
||||
// Compute the Software CRC for validation
|
||||
//
|
||||
for(i = 0; i < DATA_SIZE; i++)
|
||||
{
|
||||
byteSwappedData = (((data[i] & (uint32_t)0x000000FFU) << 24) |
|
||||
((data[i] & (uint32_t)0x0000FF00U) << 8) |
|
||||
((data[i] & (uint32_t)0x00FF0000U) >> 8) |
|
||||
((data[i] & (uint32_t)0xFF000000U) >> 24)
|
||||
);
|
||||
|
||||
crc32 = byteSwappedData ^ crc32;
|
||||
|
||||
for(j = 0; j < 32; j++)
|
||||
{
|
||||
if(crc32 & (uint32_t)0x80000000U)
|
||||
{
|
||||
crc32 = ( (crc32 << 1) ^ POLYNOMIAL);
|
||||
}
|
||||
else
|
||||
{
|
||||
crc32 = (crc32 << 1);
|
||||
}
|
||||
crc32 = crc32 & (uint32_t)0xFFFFFFFFU;
|
||||
}
|
||||
}
|
||||
|
||||
#if CRC_FAIL == 1 // To make the BGCRC to fail
|
||||
crc32 = 0xdeadbeef; //This is to test the error NMIs and Pins
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// Init routine for BGCRC module
|
||||
//
|
||||
void bgcrcInit()
|
||||
{
|
||||
//
|
||||
// Unlock the BGCRC configuration in case it is locked CFG-1
|
||||
//
|
||||
BGCRC_unlockRegister(BGCRC_CPU_BASE, BGCRC_REG_CTRL1 |
|
||||
BGCRC_REG_WD_CFG |
|
||||
BGCRC_REG_INTEN |
|
||||
BGCRC_REG_SEED);
|
||||
|
||||
//
|
||||
// Unlock the BGCRC configuration in case it is locked CFG-2
|
||||
//
|
||||
BGCRC_unlockRegister(BGCRC_CPU_BASE, BGCRC_REG_EN |
|
||||
BGCRC_REG_CTRL2 |
|
||||
BGCRC_REG_START_ADDR |
|
||||
BGCRC_REG_GOLDEN |
|
||||
BGCRC_REG_WD_MIN |
|
||||
BGCRC_REG_WD_MAX);
|
||||
//
|
||||
// Enable NMI and set the emulation mode as soft.
|
||||
// The CRC module and the watchdog stops immediately on debug suspend
|
||||
//
|
||||
BGCRC_setConfig(BGCRC_CPU_BASE, BGCRC_NMI_ENABLE, BGCRC_EMUCTRL_SOFT);
|
||||
|
||||
//
|
||||
// Configure the CRC Watchdog
|
||||
// Watchdog window - Min : DATA_SIZE, Max : DATA_SIZE + 1
|
||||
//
|
||||
BGCRC_enableWatchdog(BGCRC_CPU_BASE);
|
||||
BGCRC_setWatchdogWindow(BGCRC_CPU_BASE, DATA_SIZE, DATA_SIZE + 1);
|
||||
|
||||
//
|
||||
// Configure the region
|
||||
//
|
||||
BGCRC_setRegion(BGCRC_CPU_BASE, (uint32_t)data,
|
||||
BGCRC_SIZE_KBYTES(1), BGCRC_CRC_MODE);
|
||||
|
||||
//
|
||||
// Set the seed value same as used in SW computation
|
||||
//
|
||||
BGCRC_setSeedValue(BGCRC_CPU_BASE, seed);
|
||||
|
||||
//
|
||||
// Initialize the golden value with previously computed CRC using software
|
||||
//
|
||||
BGCRC_setGoldenCRCValue(BGCRC_CPU_BASE, crc32);
|
||||
|
||||
//
|
||||
// Enable interrupts
|
||||
// No need to enable the NMIs as all the NMIs are enabled by default
|
||||
//
|
||||
BGCRC_enableInterrupt(BGCRC_CPU_BASE, BGCRC_TEST_DONE |
|
||||
BGCRC_CRC_FAIL |
|
||||
BGCRC_UNCORR_ERR |
|
||||
BGCRC_CORR_ERR |
|
||||
BGCRC_WD_UNDERFLOW |
|
||||
BGCRC_WD_OVERFLOW);
|
||||
|
||||
//
|
||||
// Lock Register configuration for CFG1
|
||||
//
|
||||
BGCRC_lockRegister(BGCRC_CPU_BASE, BGCRC_REG_CTRL1 |
|
||||
BGCRC_REG_WD_CFG |
|
||||
BGCRC_REG_INTEN |
|
||||
BGCRC_REG_SEED);
|
||||
|
||||
|
||||
//
|
||||
// Commit Register Lock for CFG1
|
||||
//
|
||||
BGCRC_commitRegisterLock(BGCRC_CPU_BASE, BGCRC_REG_CTRL1 |
|
||||
BGCRC_REG_WD_CFG |
|
||||
BGCRC_REG_INTEN |
|
||||
BGCRC_REG_SEED);
|
||||
|
||||
BGCRC_start(BGCRC_CPU_BASE);
|
||||
|
||||
//
|
||||
// Lock Register configuration for CFG2
|
||||
//
|
||||
BGCRC_lockRegister(BGCRC_CPU_BASE, BGCRC_REG_EN |
|
||||
BGCRC_REG_CTRL2 |
|
||||
BGCRC_REG_START_ADDR |
|
||||
BGCRC_REG_GOLDEN |
|
||||
BGCRC_REG_WD_MIN |
|
||||
BGCRC_REG_WD_MAX);
|
||||
}
|
||||
|
||||
//
|
||||
// CPUbgcrcIsr - DONE interrupt from BGCRC.
|
||||
//
|
||||
__interrupt void CPUbgcrcIsr(void)
|
||||
{
|
||||
bgcrcDone = true;
|
||||
|
||||
//
|
||||
// Read the interrupt status
|
||||
//
|
||||
intStatus= BGCRC_getInterruptStatus(BGCRC_CPU_BASE);
|
||||
intStatus &= ~BGCRC_GLOBAL_INT;
|
||||
|
||||
//
|
||||
// Clear interrupt status
|
||||
//
|
||||
BGCRC_clearInterruptStatus(BGCRC_CPU_BASE, BGCRC_GLOBAL_INT |
|
||||
BGCRC_TEST_DONE |
|
||||
BGCRC_ALL_ERROR_FLAGS);
|
||||
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP12);
|
||||
}
|
||||
|
||||
//
|
||||
// NMIbgcrcIsr - NMI ISR
|
||||
//
|
||||
__interrupt void NMIbgcrcIsr(void)
|
||||
{
|
||||
uint32_t timeout = 20;
|
||||
BgcrcNmiStatus = BGCRC_getNMIStatus(BGCRC_CPU_BASE);
|
||||
|
||||
//
|
||||
// Safety diagnostic check
|
||||
//
|
||||
if(!SysCtl_isErrorTriggered())
|
||||
{
|
||||
//
|
||||
// If due to some fault the ERROR STS couldn't be triggered, force
|
||||
// the error status pin so that external host get to know the error
|
||||
//
|
||||
while((SysCtl_getErrorPinStatus() == 0) && (timeout > 0))
|
||||
{
|
||||
SysCtl_forceError();
|
||||
timeout--;
|
||||
}
|
||||
|
||||
if (timeout == 0)
|
||||
{
|
||||
//
|
||||
// Something is wrong with the error status pin
|
||||
//
|
||||
error_status_pin_diagnostic_failed = true;
|
||||
}
|
||||
}
|
||||
|
||||
if((BgcrcNmiStatus & BGCRC_CRC_FAIL) == BGCRC_CRC_FAIL)
|
||||
{
|
||||
//
|
||||
// CRC Fail NMI
|
||||
//
|
||||
Bgcrc_fail = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CPU_BASE, BGCRC_CRC_FAIL);
|
||||
}
|
||||
|
||||
if( (BgcrcNmiStatus&BGCRC_UNCORR_ERR) == BGCRC_UNCORR_ERR )
|
||||
{
|
||||
//
|
||||
// Uncorrectable Error NMI
|
||||
//
|
||||
Bgcrc_uncorr_err = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CPU_BASE, BGCRC_UNCORR_ERR);
|
||||
}
|
||||
|
||||
if(BgcrcNmiStatus&BGCRC_CORR_ERR == BGCRC_CORR_ERR)
|
||||
{
|
||||
//
|
||||
// Correctable Error NMI
|
||||
//
|
||||
Bgcrc_corr_err = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CPU_BASE, BGCRC_CORR_ERR);
|
||||
}
|
||||
|
||||
if(BgcrcNmiStatus&BGCRC_WD_UNDERFLOW == BGCRC_WD_UNDERFLOW)
|
||||
{
|
||||
//
|
||||
// Watchdog Underflow Error NMI
|
||||
//
|
||||
Bgcrc_Wd_underflow = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CPU_BASE, BGCRC_WD_UNDERFLOW);
|
||||
}
|
||||
|
||||
if(BgcrcNmiStatus&BGCRC_WD_OVERFLOW == BGCRC_WD_OVERFLOW)
|
||||
{
|
||||
//
|
||||
// Watchdog Overflow Error NMI
|
||||
//
|
||||
Bgcrc_Wd_overflow = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CPU_BASE, BGCRC_WD_OVERFLOW);
|
||||
}
|
||||
|
||||
SysCtl_clearAllNMIFlags();
|
||||
bgcrcError = true;
|
||||
}
|
||||
|
||||
//
|
||||
// Delay function
|
||||
//
|
||||
void delay(uint32_t i)
|
||||
{
|
||||
uint32_t j =i;
|
||||
while(j > 0)
|
||||
{
|
||||
j--;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -0,0 +1,456 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: bgcrc_ex2_basic_cpubgcrc.c
|
||||
//
|
||||
// TITLE: Background CRC computation with interrupt.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> CLA-BGCRC Example in CRC mode </h1>
|
||||
//!
|
||||
//! This example demonstrates how to configure and trigger CLABGCRC from the CPU.
|
||||
//! It also showcases how to configure the CRC watchdog and lock the registers
|
||||
//! after configuring the module. The watchdog is used as a diagnostic to check
|
||||
//! memory test completion within the expected time window. An error signal is
|
||||
//! generated if the test does not complete in the specified time window.
|
||||
//!
|
||||
//! The module is configured for 1kB of CLA ROM memory. The golden CRC value
|
||||
//! for comparison is computed using software method. Interrupt is generated
|
||||
//! once the computation is done and checks if no error flags are raised. The
|
||||
//! NMI is enabled and is triggered if an error is detected.
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - None.
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - pass
|
||||
//! - bgcrcDone
|
||||
//!
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
#include <stdlib.h>
|
||||
#include <time.h>
|
||||
|
||||
//
|
||||
// Defines and globals
|
||||
//
|
||||
#define DATA_SIZE 256 // Total size = 256 * 4 = 1kB
|
||||
#define CLA_ROM_ADDR 0x1001080 // CPU view
|
||||
#define CLA_ROM_ADDR_BGCRC_VIEW 0xF080 // BGCRC_CLA view
|
||||
|
||||
uint32_t POLYNOMIAL = (uint32_t)0x04C11DB7;
|
||||
uint32_t crc32;
|
||||
uint32_t seed;
|
||||
uint32_t byteSwappedData;
|
||||
|
||||
volatile bool bgcrcDone = false;
|
||||
volatile bool bgcrcError = false;
|
||||
volatile uint32_t BgcrcNmiStatus = 0;
|
||||
volatile uint32_t intStatus =0;
|
||||
volatile bool Bgcrc_fail = false;
|
||||
volatile bool Bgcrc_uncorr_err = false;
|
||||
volatile bool Bgcrc_corr_err = false;
|
||||
volatile bool Bgcrc_Wd_underflow = false;
|
||||
volatile bool Bgcrc_Wd_overflow = false;
|
||||
volatile bool error_status_pin_diagnostic_failed = false;
|
||||
|
||||
bool pass = false;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void computeCRC_software(void);
|
||||
void bgcrcInit(void);
|
||||
void delay(uint32_t i);
|
||||
__interrupt void CLAbgcrcIsr(void);
|
||||
__interrupt void NMIbgcrcIsr(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
//
|
||||
// Initialize device clock and peripherals
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Initialize GPIO and configure the GPIO pin as a push-pull output
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Disable global interrupts.
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
//
|
||||
// Map the ISRs of the BGCRC interrupt and NMI.
|
||||
//
|
||||
Interrupt_register(INT_CLA1CRC, CLAbgcrcIsr);
|
||||
Interrupt_register(INT_NMI, NMIbgcrcIsr);
|
||||
|
||||
//
|
||||
// Enable the CRC interrupt in the PIE
|
||||
//
|
||||
Interrupt_enable(INT_CLA1CRC);
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP12);
|
||||
|
||||
//
|
||||
// Enable NMI
|
||||
//
|
||||
Interrupt_enable(INT_NMI);
|
||||
SysCtl_clearAllNMIFlags();
|
||||
SysCtl_enableNMIGlobalInterrupt();
|
||||
SysCtl_setNMIWatchdogPeriod(0xFFFFU);
|
||||
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
//
|
||||
// Initialize the data with random numbers
|
||||
//
|
||||
computeCRC_software();
|
||||
|
||||
//
|
||||
// Initialize the BGCRC module
|
||||
//
|
||||
bgcrcInit();
|
||||
|
||||
delay(2000); // Expecting the BGCRC completion in this time
|
||||
|
||||
if(error_status_pin_diagnostic_failed == true )
|
||||
{
|
||||
//
|
||||
// Something is wrong with the error status pin
|
||||
// Need to reset the system
|
||||
//
|
||||
}
|
||||
|
||||
if((bgcrcDone == true) && (bgcrcError == false))
|
||||
{
|
||||
if((intStatus == BGCRC_TEST_DONE))
|
||||
{
|
||||
pass = true;
|
||||
}
|
||||
}
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// SW method for computing CRC of CLA ROM memory data
|
||||
//
|
||||
void computeCRC_software()
|
||||
{
|
||||
uint32_t tseed;
|
||||
uint32_t i,j;
|
||||
|
||||
//
|
||||
// Initialize the random number generator
|
||||
//
|
||||
tseed = time(NULL);
|
||||
srand(tseed);
|
||||
srand(rand());
|
||||
|
||||
seed = rand();
|
||||
seed = (uint32_t)(seed << 16) | rand(); // Initialize with seed
|
||||
crc32 = seed;
|
||||
|
||||
//
|
||||
// Compute the Software CRC for validation
|
||||
//
|
||||
uint32_t current_data;
|
||||
for(i = 0; i < DATA_SIZE; i++)
|
||||
{
|
||||
current_data = HWREG(CLA_ROM_ADDR + 2 * i);
|
||||
|
||||
byteSwappedData = (((current_data & (uint32_t)0x000000FFU) << 24) |
|
||||
((current_data & (uint32_t)0x0000FF00U) << 8) |
|
||||
((current_data & (uint32_t)0x00FF0000U) >> 8) |
|
||||
((current_data & (uint32_t)0xFF000000U) >> 24)
|
||||
);
|
||||
|
||||
crc32 = byteSwappedData ^ crc32;
|
||||
|
||||
for(j = 0; j < 32; j++)
|
||||
{
|
||||
if(crc32 & (uint32_t)0x80000000U)
|
||||
{
|
||||
crc32 = ((crc32 << 1) ^ POLYNOMIAL);
|
||||
}
|
||||
else
|
||||
{
|
||||
crc32 = (crc32 << 1);
|
||||
}
|
||||
crc32 = crc32 & (uint32_t)0xFFFFFFFFU;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Init routine for BGCRC module
|
||||
//
|
||||
void bgcrcInit()
|
||||
{
|
||||
//
|
||||
// Unlock the BGCRC configuration in case it is locked CFG-1
|
||||
//
|
||||
BGCRC_unlockRegister(BGCRC_CLA1_BASE, BGCRC_REG_CTRL1 |
|
||||
BGCRC_REG_WD_CFG |
|
||||
BGCRC_REG_INTEN |
|
||||
BGCRC_REG_SEED);
|
||||
|
||||
//
|
||||
// Unlock the BGCRC configuration in case it is locked CFG-2
|
||||
//
|
||||
BGCRC_unlockRegister(BGCRC_CLA1_BASE, BGCRC_REG_EN |
|
||||
BGCRC_REG_CTRL2 |
|
||||
BGCRC_REG_START_ADDR |
|
||||
BGCRC_REG_GOLDEN |
|
||||
BGCRC_REG_WD_MIN |
|
||||
BGCRC_REG_WD_MAX);
|
||||
//
|
||||
// Enable NMI and set the emulation mode as soft.
|
||||
// The CRC module and the watchdog stops immediately on debug suspend
|
||||
//
|
||||
BGCRC_setConfig(BGCRC_CLA1_BASE, BGCRC_NMI_ENABLE, BGCRC_EMUCTRL_SOFT);
|
||||
|
||||
//
|
||||
// Configure the CRC Watchdog
|
||||
// Watchdog window - Min : DATA_SIZE, Max : DATA_SIZE + 100
|
||||
//
|
||||
BGCRC_enableWatchdog(BGCRC_CLA1_BASE);
|
||||
BGCRC_setWatchdogWindow(BGCRC_CLA1_BASE, DATA_SIZE, DATA_SIZE + 100);
|
||||
|
||||
//
|
||||
// Configure the region
|
||||
//
|
||||
BGCRC_setRegion(BGCRC_CLA1_BASE, CLA_ROM_ADDR_BGCRC_VIEW,
|
||||
BGCRC_SIZE_KBYTES(1), BGCRC_CRC_MODE);
|
||||
|
||||
//
|
||||
// Set the seed value same as used in SW computation
|
||||
//
|
||||
BGCRC_setSeedValue(BGCRC_CLA1_BASE, seed);
|
||||
|
||||
//
|
||||
// Initialize the golden value with previously computed CRC using software
|
||||
//
|
||||
BGCRC_setGoldenCRCValue(BGCRC_CLA1_BASE, crc32);
|
||||
|
||||
//
|
||||
// Enable interrupts
|
||||
//
|
||||
BGCRC_enableInterrupt(BGCRC_CLA1_BASE, BGCRC_TEST_DONE |
|
||||
BGCRC_CRC_FAIL |
|
||||
BGCRC_UNCORR_ERR |
|
||||
BGCRC_CORR_ERR |
|
||||
BGCRC_WD_UNDERFLOW |
|
||||
BGCRC_WD_OVERFLOW);
|
||||
|
||||
//
|
||||
// Lock Register configuration for CFG1
|
||||
//
|
||||
BGCRC_lockRegister(BGCRC_CLA1_BASE, BGCRC_REG_CTRL1 |
|
||||
BGCRC_REG_WD_CFG |
|
||||
BGCRC_REG_INTEN |
|
||||
BGCRC_REG_SEED);
|
||||
|
||||
|
||||
//
|
||||
// Commit Register Lock for CFG1
|
||||
//
|
||||
BGCRC_commitRegisterLock(BGCRC_CLA1_BASE, BGCRC_REG_CTRL1 |
|
||||
BGCRC_REG_WD_CFG |
|
||||
BGCRC_REG_INTEN |
|
||||
BGCRC_REG_SEED);
|
||||
|
||||
BGCRC_start(BGCRC_CLA1_BASE);
|
||||
|
||||
//
|
||||
// Lock Register configuration for CFG2
|
||||
//
|
||||
BGCRC_lockRegister(BGCRC_CLA1_BASE, BGCRC_REG_EN |
|
||||
BGCRC_REG_CTRL2 |
|
||||
BGCRC_REG_START_ADDR |
|
||||
BGCRC_REG_GOLDEN |
|
||||
BGCRC_REG_WD_MIN |
|
||||
BGCRC_REG_WD_MAX);
|
||||
}
|
||||
|
||||
//
|
||||
// CLAbgcrcIsr - DONE interrupt from BGCRC.
|
||||
//
|
||||
__interrupt void CLAbgcrcIsr(void)
|
||||
{
|
||||
bgcrcDone = true;
|
||||
|
||||
//
|
||||
// Read the interrupt status
|
||||
//
|
||||
intStatus= BGCRC_getInterruptStatus(BGCRC_CLA1_BASE);
|
||||
intStatus &= ~BGCRC_GLOBAL_INT;
|
||||
|
||||
//
|
||||
// Clear interrupt status
|
||||
//
|
||||
BGCRC_clearInterruptStatus(BGCRC_CLA1_BASE, BGCRC_GLOBAL_INT |
|
||||
BGCRC_TEST_DONE |
|
||||
BGCRC_ALL_ERROR_FLAGS);
|
||||
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP12);
|
||||
}
|
||||
|
||||
//
|
||||
// NMIbgcrcIsr - NMI ISR
|
||||
//
|
||||
__interrupt void NMIbgcrcIsr(void)
|
||||
{
|
||||
uint32_t timeout = 20;
|
||||
BgcrcNmiStatus = BGCRC_getNMIStatus(BGCRC_CLA1_BASE);
|
||||
|
||||
//
|
||||
// Safety diagnostic check
|
||||
//
|
||||
if(!SysCtl_isErrorTriggered())
|
||||
{
|
||||
//
|
||||
// If due to some fault the ERROR STS couldn't be triggered, force
|
||||
// the error status pin so that external host get to know the error
|
||||
//
|
||||
while((SysCtl_getErrorPinStatus() == 0) && (timeout > 0))
|
||||
{
|
||||
SysCtl_forceError();
|
||||
timeout--;
|
||||
}
|
||||
|
||||
if (timeout == 0)
|
||||
{
|
||||
//
|
||||
// Something is wrong with the error status pin
|
||||
//
|
||||
error_status_pin_diagnostic_failed = true;
|
||||
}
|
||||
}
|
||||
|
||||
if((BgcrcNmiStatus & BGCRC_CRC_FAIL) == BGCRC_CRC_FAIL)
|
||||
{
|
||||
//
|
||||
// CRC Fail NMI
|
||||
//
|
||||
Bgcrc_fail = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CLA1_BASE, BGCRC_CRC_FAIL);
|
||||
}
|
||||
|
||||
if((BgcrcNmiStatus & BGCRC_UNCORR_ERR) == BGCRC_UNCORR_ERR )
|
||||
{
|
||||
//
|
||||
// Uncorrectable Error NMI
|
||||
//
|
||||
Bgcrc_uncorr_err = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CLA1_BASE, BGCRC_UNCORR_ERR);
|
||||
}
|
||||
|
||||
if((BgcrcNmiStatus & BGCRC_CORR_ERR) == BGCRC_CORR_ERR)
|
||||
{
|
||||
//
|
||||
// Correctable Error NMI
|
||||
//
|
||||
Bgcrc_corr_err = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CLA1_BASE, BGCRC_CORR_ERR);
|
||||
}
|
||||
|
||||
if((BgcrcNmiStatus & BGCRC_WD_UNDERFLOW) == BGCRC_WD_UNDERFLOW)
|
||||
{
|
||||
//
|
||||
// Watchdog Underflow Error NMI
|
||||
//
|
||||
Bgcrc_Wd_underflow = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CLA1_BASE, BGCRC_WD_UNDERFLOW);
|
||||
}
|
||||
|
||||
if((BgcrcNmiStatus & BGCRC_WD_OVERFLOW) == BGCRC_WD_OVERFLOW)
|
||||
{
|
||||
//
|
||||
// Watchdog Overflow Error NMI
|
||||
//
|
||||
Bgcrc_Wd_overflow = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CLA1_BASE, BGCRC_WD_OVERFLOW);
|
||||
}
|
||||
|
||||
SysCtl_clearAllNMIFlags();
|
||||
bgcrcError = true;
|
||||
}
|
||||
|
||||
//
|
||||
// Delay function
|
||||
//
|
||||
void delay(uint32_t i)
|
||||
{
|
||||
uint32_t j =i;
|
||||
while(j > 0)
|
||||
{
|
||||
j--;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -0,0 +1,384 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: bgcrc_ex3_basic_clabgcrc.c
|
||||
//
|
||||
// TITLE: Background CRC computation with interrupt.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> CLA-BGCRC Example in Scrub Mode </h1>
|
||||
//!
|
||||
//! This example demonstrates how to configure and trigger CLA-BGCRC in Scrub
|
||||
//! mode. In Scrub mode, CRC of data is not compared with the golden CRC. Error
|
||||
//! check is done using the ECC/Parity logic.
|
||||
//! It also showcases how to configure the CRC watchdog and lock the
|
||||
//! registers after configuring the module. The watchdog is used as a diagnostic
|
||||
//! to check memory test completion within the expected time window. An error
|
||||
//! signal is generated if the test does not complete in the specified time
|
||||
//! window.
|
||||
//!
|
||||
//! The module is configured for 256 bytes of CLA ROM memory. Interrupt is
|
||||
//! generated once the computation is done and checks if no error flags are
|
||||
//! raised. The NMI is enabled and is triggered if an error is detected.
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - None.
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - pass
|
||||
//! - bgcrcDone
|
||||
//!
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
|
||||
//
|
||||
// Defines and globals
|
||||
//
|
||||
#define DATA_SIZE 64 // 256 Bytes
|
||||
#define CLA_ROM_ADDR 0x1001080 // CPU view
|
||||
#define CLA_ROM_ADDR_BGCRC_VIEW 0xF080 // BGCRC_CLA view
|
||||
|
||||
volatile bool bgcrcDone = false;
|
||||
volatile bool bgcrcError = false;
|
||||
volatile uint32_t BgcrcNmiStatus = 0;
|
||||
volatile uint32_t intStatus =0;
|
||||
volatile bool Bgcrc_fail = false;
|
||||
volatile bool Bgcrc_uncorr_err = false;
|
||||
volatile bool Bgcrc_corr_err = false;
|
||||
volatile bool Bgcrc_Wd_underflow = false;
|
||||
volatile bool Bgcrc_Wd_overflow = false;
|
||||
volatile bool error_status_pin_diagnostic_failed = false;
|
||||
|
||||
bool pass = false;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void bgcrcInit(void);
|
||||
void delay(uint32_t i);
|
||||
__interrupt void CLAbgcrcIsr(void);
|
||||
__interrupt void NMIbgcrcIsr(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
//
|
||||
// Initialize device clock and peripherals
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Initialize GPIO and configure the GPIO pin as a push-pull output
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Disable global interrupts.
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
//
|
||||
// Map the ISRs of the BGCRC interrupt and NMI.
|
||||
//
|
||||
Interrupt_register(INT_CLA1CRC, CLAbgcrcIsr);
|
||||
Interrupt_register(INT_NMI, NMIbgcrcIsr);
|
||||
|
||||
//
|
||||
// Enable the CRC interrupt in the PIE
|
||||
//
|
||||
Interrupt_enable(INT_CLA1CRC);
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP12);
|
||||
//
|
||||
// Enable NMI
|
||||
//
|
||||
Interrupt_enable(INT_NMI);
|
||||
SysCtl_enableNMIGlobalInterrupt();
|
||||
SysCtl_setNMIWatchdogPeriod(0xFFFFU);
|
||||
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
//
|
||||
// Initialize the BGCRC module
|
||||
//
|
||||
bgcrcInit();
|
||||
|
||||
delay(2000); // Expecting the BGCRC completion in this time
|
||||
|
||||
if(error_status_pin_diagnostic_failed == true )
|
||||
{
|
||||
//
|
||||
// Something is wrong with the error status pin
|
||||
// Need to reset the system
|
||||
//
|
||||
}
|
||||
|
||||
if((bgcrcDone == true) && (bgcrcError == false))
|
||||
{
|
||||
if((intStatus == BGCRC_TEST_DONE))
|
||||
{
|
||||
pass = true;
|
||||
}
|
||||
}
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// Init routine for BGCRC module
|
||||
//
|
||||
void bgcrcInit()
|
||||
{
|
||||
//
|
||||
// Unlock the BGCRC configuration in case it is locked CFG-1
|
||||
//
|
||||
BGCRC_unlockRegister(BGCRC_CLA1_BASE, BGCRC_REG_CTRL1 |
|
||||
BGCRC_REG_WD_CFG |
|
||||
BGCRC_REG_INTEN |
|
||||
BGCRC_REG_SEED);
|
||||
|
||||
//
|
||||
// Unlock the BGCRC configuration in case it is locked CFG-2
|
||||
//
|
||||
BGCRC_unlockRegister(BGCRC_CLA1_BASE, BGCRC_REG_EN |
|
||||
BGCRC_REG_CTRL2 |
|
||||
BGCRC_REG_START_ADDR |
|
||||
BGCRC_REG_GOLDEN |
|
||||
BGCRC_REG_WD_MIN |
|
||||
BGCRC_REG_WD_MAX);
|
||||
//
|
||||
// Disable NMI and set the emulation mode as soft.
|
||||
// The CRC module and the watchdog stops immediately on debug suspend
|
||||
//
|
||||
BGCRC_setConfig(BGCRC_CLA1_BASE, BGCRC_NMI_ENABLE, BGCRC_EMUCTRL_SOFT);
|
||||
|
||||
//
|
||||
// Configure the CRC Watchdog
|
||||
// Watchdog window - Min : DATA_SIZE - 10, Max : DATA_SIZE + 100
|
||||
//
|
||||
BGCRC_enableWatchdog(BGCRC_CLA1_BASE);
|
||||
BGCRC_setWatchdogWindow(BGCRC_CLA1_BASE, DATA_SIZE - 10, DATA_SIZE + 100);
|
||||
|
||||
//
|
||||
// Configure the region.
|
||||
// Configure the module in Scrub mode. CRC of data is not compared with the
|
||||
// golden CRC. Error check is done using the ECC/Parity logic.
|
||||
//
|
||||
BGCRC_setRegion(BGCRC_CLA1_BASE, CLA_ROM_ADDR_BGCRC_VIEW,
|
||||
BGCRC_SIZE_BYTES_256, BGCRC_SCRUB_MODE);
|
||||
|
||||
|
||||
//
|
||||
// Enable interrupts
|
||||
//
|
||||
BGCRC_enableInterrupt(BGCRC_CLA1_BASE, BGCRC_TEST_DONE |
|
||||
BGCRC_CRC_FAIL |
|
||||
BGCRC_UNCORR_ERR |
|
||||
BGCRC_CORR_ERR |
|
||||
BGCRC_WD_UNDERFLOW |
|
||||
BGCRC_WD_OVERFLOW);
|
||||
|
||||
//
|
||||
// Lock Register configuration for CFG1
|
||||
//
|
||||
BGCRC_lockRegister(BGCRC_CLA1_BASE, BGCRC_REG_CTRL1 |
|
||||
BGCRC_REG_WD_CFG |
|
||||
BGCRC_REG_INTEN |
|
||||
BGCRC_REG_SEED);
|
||||
|
||||
|
||||
//
|
||||
// Commit Register Lock for CFG1
|
||||
//
|
||||
BGCRC_commitRegisterLock(BGCRC_CLA1_BASE, BGCRC_REG_CTRL1 |
|
||||
BGCRC_REG_WD_CFG |
|
||||
BGCRC_REG_INTEN |
|
||||
BGCRC_REG_SEED);
|
||||
|
||||
BGCRC_start(BGCRC_CLA1_BASE);
|
||||
|
||||
//
|
||||
// Lock Register configuration for CFG2
|
||||
//
|
||||
BGCRC_lockRegister(BGCRC_CLA1_BASE, BGCRC_REG_EN |
|
||||
BGCRC_REG_CTRL2 |
|
||||
BGCRC_REG_START_ADDR |
|
||||
BGCRC_REG_GOLDEN |
|
||||
BGCRC_REG_WD_MIN |
|
||||
BGCRC_REG_WD_MAX);
|
||||
}
|
||||
|
||||
//
|
||||
// CLAbgcrcIsr - DONE interrupt from BGCRC.
|
||||
//
|
||||
__interrupt void CLAbgcrcIsr (void)
|
||||
{
|
||||
bgcrcDone = true;
|
||||
|
||||
//
|
||||
// Read the interrupt status
|
||||
//
|
||||
intStatus= BGCRC_getInterruptStatus(BGCRC_CLA1_BASE);
|
||||
intStatus &= ~BGCRC_GLOBAL_INT;
|
||||
|
||||
//
|
||||
// Clear interrupt status
|
||||
//
|
||||
BGCRC_clearInterruptStatus(BGCRC_CLA1_BASE, BGCRC_TEST_DONE |
|
||||
BGCRC_ALL_ERROR_FLAGS);
|
||||
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP12);
|
||||
}
|
||||
|
||||
//
|
||||
// NMIbgcrcIsr - NMI ISR
|
||||
//
|
||||
__interrupt void NMIbgcrcIsr(void)
|
||||
{
|
||||
uint32_t timeout = 20;
|
||||
BgcrcNmiStatus = BGCRC_getNMIStatus(BGCRC_CLA1_BASE);
|
||||
|
||||
//
|
||||
// Safety diagnostic check
|
||||
//
|
||||
if(!SysCtl_isErrorTriggered())
|
||||
{
|
||||
//
|
||||
// If due to some fault the ERROR STS couldn't be triggered, force
|
||||
// the error status pin so that external host get to know the error
|
||||
//
|
||||
while((SysCtl_getErrorPinStatus() == 0) && (timeout > 0))
|
||||
{
|
||||
SysCtl_forceError();
|
||||
timeout--;
|
||||
}
|
||||
|
||||
if (timeout == 0)
|
||||
{
|
||||
//
|
||||
// Something is wrong with the error status pin
|
||||
//
|
||||
error_status_pin_diagnostic_failed = true;
|
||||
}
|
||||
}
|
||||
|
||||
if((BgcrcNmiStatus & BGCRC_CRC_FAIL) == BGCRC_CRC_FAIL)
|
||||
{
|
||||
//
|
||||
// CRC Fail NMI
|
||||
//
|
||||
Bgcrc_fail = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CLA1_BASE, BGCRC_CRC_FAIL);
|
||||
}
|
||||
|
||||
if( (BgcrcNmiStatus & BGCRC_UNCORR_ERR) == BGCRC_UNCORR_ERR )
|
||||
{
|
||||
//
|
||||
// Uncorrectable Error NMI
|
||||
//
|
||||
Bgcrc_uncorr_err = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CLA1_BASE, BGCRC_UNCORR_ERR);
|
||||
}
|
||||
|
||||
if((BgcrcNmiStatus & BGCRC_CORR_ERR) == BGCRC_CORR_ERR)
|
||||
{
|
||||
//
|
||||
// Correctable Error NMI
|
||||
//
|
||||
Bgcrc_corr_err = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CLA1_BASE, BGCRC_CORR_ERR);
|
||||
}
|
||||
|
||||
if((BgcrcNmiStatus & BGCRC_WD_UNDERFLOW) == BGCRC_WD_UNDERFLOW)
|
||||
{
|
||||
//
|
||||
// Watchdog Underflow Error NMI
|
||||
//
|
||||
Bgcrc_Wd_underflow = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CLA1_BASE, BGCRC_WD_UNDERFLOW);
|
||||
}
|
||||
|
||||
if((BgcrcNmiStatus & BGCRC_WD_OVERFLOW) == BGCRC_WD_OVERFLOW)
|
||||
{
|
||||
//
|
||||
// Watchdog Overflow Error NMI
|
||||
//
|
||||
Bgcrc_Wd_overflow = true;
|
||||
BGCRC_clearNMIStatus(BGCRC_CLA1_BASE, BGCRC_WD_OVERFLOW);
|
||||
}
|
||||
|
||||
SysCtl_clearAllNMIFlags();
|
||||
bgcrcError = true;
|
||||
}
|
||||
|
||||
//
|
||||
// Delay function
|
||||
//
|
||||
void delay(uint32_t i)
|
||||
{
|
||||
uint32_t j =i;
|
||||
while(j > 0)
|
||||
{
|
||||
j--;
|
||||
}
|
||||
}
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
Reference in New Issue
Block a user