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hangpersonal
2026-08-30 23:04:35 -07:00
parent 749dab5721
commit ce65a0f59a
14950 changed files with 4408250 additions and 1 deletions
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C2000Ware/driverlib/f2838x/examples/c28x/interrupt/CCS/interrupt_ex1_external.projectspec
+40
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@@ -0,0 +1,40 @@
<projectSpec>
<project
name="interrupt_ex1_external"
device="TMS320F28388D"
cgtVersion="22.6.1.LTS"
products="sysconfig;C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
postBuildStep="
echo &quot;========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) =============&quot;
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} &quot;${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js&quot; &quot;${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/&quot; &quot;${BuildDirectory}/syscfg&quot; &quot;${BuildDirectory}/syscfg/clb.dot&quot;
;if ${GENERATE_DIAGRAM} == 1 mkdir &quot;${BuildDirectory}/diagrams&quot;
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} &quot;${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js&quot; &quot;${C2000WARE_ROOT}&quot; &quot;${BuildDirectory}/diagrams&quot; &quot;${BuildDirectory}/syscfg&quot;
"
>
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../interrupt_ex1_external.c" targetDirectory="" />
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2838x/examples/c28x/interrupt/CCS/interrupt_ex2_with_i2c_sci_spi_loopback.projectspec
+40
View File
@@ -0,0 +1,40 @@
<projectSpec>
<project
name="interrupt_ex2_with_i2c_sci_spi_loopback"
device="TMS320F28388D"
cgtVersion="22.6.1.LTS"
products="sysconfig;C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
postBuildStep="
echo &quot;========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) =============&quot;
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} &quot;${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js&quot; &quot;${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/&quot; &quot;${BuildDirectory}/syscfg&quot; &quot;${BuildDirectory}/syscfg/clb.dot&quot;
;if ${GENERATE_DIAGRAM} == 1 mkdir &quot;${BuildDirectory}/diagrams&quot;
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} &quot;${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js&quot; &quot;${C2000WARE_ROOT}&quot; &quot;${BuildDirectory}/diagrams&quot; &quot;${BuildDirectory}/syscfg&quot;
"
>
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../interrupt_ex2_with_i2c_sci_spi_loopback.c" targetDirectory="" />
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2838x/examples/c28x/interrupt/CCS/interrupt_ex3_sw_prioritization.projectspec
+42
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@@ -0,0 +1,42 @@
<projectSpec>
<project
name="interrupt_ex3_sw_prioritization"
device="TMS320F28388D"
cgtVersion="22.6.1.LTS"
products="sysconfig;C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
postBuildStep="
echo &quot;========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) =============&quot;
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} &quot;${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js&quot; &quot;${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/&quot; &quot;${BuildDirectory}/syscfg&quot; &quot;${BuildDirectory}/syscfg/clb.dot&quot;
;if ${GENERATE_DIAGRAM} == 1 mkdir &quot;${BuildDirectory}/diagrams&quot;
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} &quot;${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js&quot; &quot;${C2000WARE_ROOT}&quot; &quot;${BuildDirectory}/diagrams&quot; &quot;${BuildDirectory}/syscfg&quot;
"
>
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=0 -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_COMMON_INCLUDE} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=0 -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -I${C2000WARE_COMMON_INCLUDE} -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
<pathVariable name="C2000WARE_COMMON_INCLUDE" path="../../../../../../device_support/f2838x/common/include/" scope="project" />
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../interrupt_ex3_sw_prioritization.c" targetDirectory="" />
<file action="copy" path="../sw_prioritized_isr_levels.h" targetDirectory="" />
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2838x/examples/c28x/interrupt/CCS/interrupt_ex4_epwm_realtime_interrupt.projectspec
+41
View File
@@ -0,0 +1,41 @@
<projectSpec>
<project
name="interrupt_ex4_epwm_realtime_interrupt"
device="TMS320F28388D"
cgtVersion="22.6.1.LTS"
products="sysconfig;C2000WARE"
outputFormat="ELF"
launchWizard="False"
linkerCommandFile=""
enableSysConfigTool="true"
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
postBuildStep="
echo &quot;========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) =============&quot;
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} &quot;${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js&quot; &quot;${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/&quot; &quot;${BuildDirectory}/syscfg&quot; &quot;${BuildDirectory}/syscfg/clb.dot&quot;
;if ${GENERATE_DIAGRAM} == 1 mkdir &quot;${BuildDirectory}/diagrams&quot;
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} &quot;${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js&quot; &quot;${C2000WARE_ROOT}&quot; &quot;${BuildDirectory}/diagrams&quot; &quot;${BuildDirectory}/syscfg&quot;
"
>
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_dbgier.asm" targetDirectory="" />
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
<file action="copy" path="../interrupt_ex4_epwm_realtime_interrupt.c" targetDirectory="" />
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
</project>
</projectSpec>
C2000Ware/driverlib/f2838x/examples/c28x/interrupt/interrupt_ex1_external.c
+317
View File
@@ -0,0 +1,317 @@
//###########################################################################
//
// FILE: interrupt_ex1_external.c
//
// TITLE: External Interrupt test program.
//
//! \addtogroup driver_example_list
//! <h1>External Interrupts (ExternalInterrupt)</h1>
//!
//! This program sets up GPIO0 as XINT1 and GPIO1 as XINT2. Two other
//! GPIO signals are used to trigger the interrupt (GPIO10 triggers
//! XINT1 and GPIO11 triggers XINT2). The user is required to
//! externally connect these signals for the program to work
//! properly.
//!
//! XINT1 input is synced to SYSCLKOUT.
//!
//! XINT2 has a long qualification - 6 samples at 510*SYSCLKOUT each.
//!
//! GPIO16 will go high outside of the interrupts and low within the
//! interrupts. This signal can be monitored on a scope.
//!
//! Each interrupt is fired in sequence - XINT1 first and then XINT2
//!
//! \b External \b Connections \n
//! - Connect GPIO10 to GPIO0. GPIO0 will be assigned to XINT1
//! - Connect GPIO11 to GPIO1. GPIO1 will be assigned to XINT2
//!
//! Monitor GPIO16 with an oscilloscope. GPIO16 will be high outside of the
//! ISRs and low within each ISR.
//!
//! \b Watch \b Variables \n
//! - xint1Count for the number of times through XINT1 interrupt
//! - xint2Count for the number of times through XINT2 interrupt
//! - loopCount for the number of times through the idle loop
//!
//
//###########################################################################
//
//
//
// C2000Ware v5.04.00.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "device.h"
#include "driverlib.h"
//
// Defines
//
// Qualification period at 6 samples in microseconds
#define DELAY (6.0 * 510.0 * 1000000.0 * (1.0 / DEVICE_SYSCLK_FREQ))
//
// Globals
//
volatile uint32_t xint1Count;
volatile uint32_t xint2Count;
volatile uint32_t loopCount;
//
// Function Prototypes
//
interrupt void xint1ISR(void);
interrupt void xint2ISR(void);
//
// Main
//
void main(void)
{
uint32_t tempX1Count;
uint32_t tempX2Count;
//
// Initialize device clock and peripherals
//
Device_init();
//
// Disable pin locks and enable internal pullups
//
//Device_initGPIO(); // Skipped for this example
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR)
//
Interrupt_initVectorTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
Interrupt_register(INT_XINT1, &xint1ISR);
Interrupt_register(INT_XINT2, &xint2ISR);
//
// User specific code, enable interrupts:
//
// Clear the counters
//
xint1Count = 0; // Count XINT1 interrupts
xint2Count = 0; // Count XINT2 interrupts
loopCount = 0; // Count times through idle loop
//
// Enable XINT1 and XINT2 in the PIE: Group 1 interrupt 4 & 5
// Enable INT1 which is connected to WAKEINT:
//
Interrupt_enable(INT_XINT1);
Interrupt_enable(INT_XINT2);
//
// Enable Global Interrupt (INTM) and real time interrupt (DBGM)
//
EINT;
ERTM;
//
// GPIO10 & GPIO11 are outputs, start GPIO10 high and GPIO11 low
//
//
// Load the output latch
//
GPIO_writePin(10, 1);
GPIO_setDirectionMode(10, GPIO_DIR_MODE_OUT); // output
//
// Load the output latch
//
GPIO_writePin(11, 0);
GPIO_setDirectionMode(11, GPIO_DIR_MODE_OUT); // output
//
// GPIO0 and GPIO1 are configured as inputs
//
GPIO_setDirectionMode(0, GPIO_DIR_MODE_IN); // input
//
// XINT1 Synch to SYSCLKOUT only
//
GPIO_setQualificationMode(0, GPIO_QUAL_SYNC);
GPIO_setDirectionMode(1, GPIO_DIR_MODE_IN); // input
//
// XINT2 Qual using 6 samples
//
GPIO_setQualificationMode(1, GPIO_QUAL_6SAMPLE);
//
// Set qualification period for GPIO0 to GPIO7
// Each sampling window is 510*SYSCLKOUT
//
GPIO_setQualificationPeriod(3, 510);
//
// GPIO0 is mapped to XINT1, GPIO1 is mapped to XINT2
//
GPIO_setInterruptPin(0, GPIO_INT_XINT1);
GPIO_setInterruptPin(1, GPIO_INT_XINT2);
//
// Configure falling edge trigger for XINT1
//
GPIO_setInterruptType(GPIO_INT_XINT1, GPIO_INT_TYPE_FALLING_EDGE);
//
// Configure rising edge trigger for XINT2
//
GPIO_setInterruptType(GPIO_INT_XINT2, GPIO_INT_TYPE_RISING_EDGE);
//
// Enable XINT1 and XINT2
//
GPIO_enableInterrupt(GPIO_INT_XINT1); // Enable XINT1
GPIO_enableInterrupt(GPIO_INT_XINT2); // Enable XINT2
//
// GPIO16 will go low inside each interrupt. Monitor this on a scope
//
GPIO_setDirectionMode(16, GPIO_DIR_MODE_OUT); // output
//
// IDLE loop:
//
for(;;)
{
tempX1Count = xint1Count;
tempX2Count = xint2Count;
//
// Set GPIO16
//
GPIO_writePin(16, 1);
//
// Lower GPIO10, trigger XINT1
//
GPIO_clearPortPins(GPIO_PORT_A, GPIO_GPADIR_GPIO10);
while(xint1Count == tempX1Count) {}
//
// Set GPIO16
//
GPIO_writePin(16, 1);
//
// Wait for Qual period
//
DEVICE_DELAY_US(DELAY);
//
// Raise GPIO11, trigger XINT2
//
GPIO_writePin(11, 1);
while(xint2Count == tempX2Count) {}
//
// Check that the counts were incremented properly and get ready
// to start over.
//
if((xint1Count == tempX1Count + 1) && (xint2Count == tempX2Count + 1))
{
loopCount++;
//
// Raise GPIO10
//
GPIO_writePin(10, 1);
//
// Lower GPIO11
//
GPIO_writePin(11, 0);
}
else
{
ESTOP0;
}
}
}
//
// xint1ISR - External Interrupt 1 ISR
//
interrupt void xint1ISR(void)
{
GPIO_writePin(16, 0); // GPIO16 is lowered
xint1Count++;
//
// Acknowledge this interrupt to get more from group 1
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
}
//
// xint2ISR - External Interrupt 2 ISR
//
interrupt void xint2ISR(void)
{
GPIO_writePin(16, 0); // GPIO16 is lowered
xint2Count++;
//
// Acknowledge this interrupt to get more from group 1
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
}
//
// End of file
//
C2000Ware/driverlib/f2838x/examples/c28x/interrupt/interrupt_ex2_with_i2c_sci_spi_loopback.c
+570
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@@ -0,0 +1,570 @@
//#############################################################################
//
// FILE: interrupt_ex2_with_i2c_sci_spi_loopback.c
//
// TITLE: Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
//
//! \addtogroup driver_example_list
//! <h1>Multiple interrupt handling of I2C, SCI & SPI Digital Loopback</h1>
//!
//! This program is used to demonstrate how to handle multiple interrupts
//! when using multiple communication peripherals like I2C, SCI & SPI
//! Digital Loopback all in a single example. The data transfers would
//! be done with FIFO Interrupts.
//!
//! It uses the internal loopback test mode of these modules. Both
//! the TX and RX FIFOs and their interrupts are used.
//! Other than boot mode pin configuration, no other hardware configuration
//! is required.
//!
//! A stream of data is sent and then compared to the received stream.
//! The sent data looks like this for I2C and SCI: \n
//! 0000 0001 \n
//! 0001 0002 \n
//! 0002 0003 \n
//! .... \n
//! 00FE 00FF \n
//! 00FF 0000 \n
//! etc.. \n
//!
//! The sent data looks like this for SPI: \n
//! 0000 0001 \n
//! 0001 0002 \n
//! 0002 0003 \n
//! .... \n
//! FFFE FFFF \n
//! FFFF 0000 \n
//! etc.. \n
//!
//! This pattern is repeated forever.
//!
//! \b External \b Connections \n
//! - None
//!
//! \b Watch \b Variables \n
//! - \b sDatai2cA - Data to send through I2C
//! - \b rDatai2cA - Received I2C data
//! - \b rDataPoint - Used to keep track of the last position in the receive
//! I2C stream for error checking
//!
//! - \b sDataspiA - Data to send through SPI
//! - \b rDataspiA - Received SPI data
//! - \b rDataPointspiA - Used to keep track of the last position in the receive
//! SPI stream for error checking
//!
//! - \b sDatasciA - SCI Data being sent
//! - \b rDatasciA - SCI Data received
//! - \b rDataPointA - Keep track of where we are in the SCI data stream.
//! This is used to check the incoming data
//!
//
//#############################################################################
//
//
//
// C2000Ware v5.04.00.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
//
// Defines
//
#define TARGET_ADDRESS 0x3C
//
// Globals
//
//
// I2C data Globals
//
uint16_t sDatai2cA[2]; // Send I2CA data buffer
uint16_t rDatai2cA[2]; // Receive I2CA data buffer
uint16_t rDataPoint = 0; // To keep track of where we are in the
// data stream to check received I2C data
//
// SCI data Globals
//
uint16_t sDatasciA[2]; // Send SCI-A data buffer
uint16_t rDatasciA[2]; // Receive SCI-A data buffer
uint16_t rDataPointA = 0; // Used for checking the received SCI data
//
// SPI data Globals
//
uint16_t sDataspiA[2]; // Send SPI data buffer
uint16_t rDataspiA[2]; // Receive SPI data buffer
uint16_t rDataPointspiA = 0; // To keep track of where we are in the
// data stream to check received SPI data
//
// Function Prototypes
//
void initI2CFIFO(void);
__interrupt void i2cFIFOISR(void);
__interrupt void sciaTXFIFOISR(void);
__interrupt void sciaRXFIFOISR(void);
void initSCIAFIFO(void);
void initSPIFIFO(void);
__interrupt void spiTxFIFOISR(void);
__interrupt void spiRxFIFOISR(void);
//
// Main
//
void main(void)
{
uint16_t i;
//
// Initialize device clock and peripherals
//
Device_init();
//
// Disable pin locks and enable internal pullups.
//
Device_initGPIO();
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// Interrupts that are used in this example are re-mapped to ISR functions
// found within this file.
//
Interrupt_register(INT_I2CA_FIFO, &i2cFIFOISR);
Interrupt_register(INT_SCIA_RX, &sciaRXFIFOISR);
Interrupt_register(INT_SCIA_TX, &sciaTXFIFOISR);
Interrupt_register(INT_SPIA_TX, &spiTxFIFOISR);
Interrupt_register(INT_SPIA_RX, &spiRxFIFOISR);
//
// Set I2C use, initializing it for FIFO mode
//
initI2CFIFO();
//
// Set SCI use, initializing it for FIFO mode
//
initSCIAFIFO();
//
// Set up SPI, initializing it for FIFO mode
//
initSPIFIFO();
//
// Initialize the I2C data buffers
//
for(i = 0; i < 2; i++)
{
sDatai2cA[i] = i;
rDatai2cA[i]= 0;
}
//
// Init the SCI send data. After each transmission this data
// will be updated for the next transmission
//
for(i = 0; i < 2; i++)
{
sDatasciA[i] = i;
}
//
// Initialize the SPI data buffers
//
for(i = 0; i < 2; i++)
{
sDataspiA[i] = i;
rDataspiA[i]= 0;
}
//
// Enable interrupts required for this example
//
Interrupt_enable(INT_I2CA_FIFO);
Interrupt_enable(INT_SCIA_RX);
Interrupt_enable(INT_SCIA_TX);
Interrupt_enable(INT_SPIA_TX);
Interrupt_enable(INT_SPIA_RX);
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;
//
// Loop forever. Suspend or place breakpoints to observe the buffers.
//
while(1)
{
// A FIFO interrupt will be generated for each Tx and Rx based
// on the Interrupt levels configured for each of the modules.
}
}
//
// Function to configure I2C A in FIFO mode.
//
void initI2CFIFO()
{
//
// Must put I2C into reset before configuring it
//
I2C_disableModule(I2CA_BASE);
//
// I2C configuration. Use a 400kHz I2CCLK with a 50% duty cycle.
//
I2C_initController(I2CA_BASE, DEVICE_SYSCLK_FREQ, 400000, I2C_DUTYCYCLE_50);
I2C_setConfig(I2CA_BASE, I2C_CONTROLLER_SEND_MODE);
I2C_setDataCount(I2CA_BASE, 2);
I2C_setBitCount(I2CA_BASE, I2C_BITCOUNT_8);
//
// Configure for internal loopback mode
//
I2C_setTargetAddress(I2CA_BASE, TARGET_ADDRESS);
I2C_setOwnAddress(I2CA_BASE, TARGET_ADDRESS);
I2C_enableLoopback(I2CA_BASE);
I2C_setEmulationMode(I2CA_BASE, I2C_EMULATION_STOP_SCL_LOW);
//
// FIFO and interrupt configuration
//
I2C_enableFIFO(I2CA_BASE);
I2C_clearInterruptStatus(I2CA_BASE, I2C_INT_RXFF | I2C_INT_TXFF);
//
// Transmit FIFO interrupt levels are set to generate an interrupt
// when the 16 byte TX fifo contains 2 or lesser bytes of data.
// Receive FIFO interrupt levels are set to generate an interrupt
// when the 16 byte RX fifo contains 2 or greater bytes of data.
//
I2C_setFIFOInterruptLevel(I2CA_BASE, I2C_FIFO_TX2, I2C_FIFO_RX2);
I2C_enableInterrupt(I2CA_BASE, I2C_INT_RXFF | I2C_INT_TXFF);
//
// Configuration complete. Enable the module.
//
I2C_enableModule(I2CA_BASE);
}
//
// I2C A Transmit & Receive FIFO ISR.
// The ISR will handle pushing/pulling data to/from the TX and
// RX FIFOs resp.
//
__interrupt void i2cFIFOISR(void)
{
uint16_t i;
//
// If receive FIFO interrupt flag is set, read data
//
if((I2C_getInterruptStatus(I2CA_BASE) & I2C_INT_RXFF) != 0)
{
for(i = 0; i < 2; i++)
{
rDatai2cA[i] = I2C_getData(I2CA_BASE);
}
//
// Check received data
//
for(i = 0; i < 2; i++)
{
if(rDatai2cA[i] != ((rDataPoint + i) & 0xFF))
{
//
// Something went wrong. rDatai2cA doesn't contain expected data.
//
ESTOP0;
}
}
rDataPoint = (rDataPoint + 1) & 0xFF;
//
// Clear interrupt flag
//
I2C_clearInterruptStatus(I2CA_BASE, I2C_INT_RXFF);
}
//
// If transmit FIFO interrupt flag is set, put data in the buffer
//
else if((I2C_getInterruptStatus(I2CA_BASE) & I2C_INT_TXFF) != 0)
{
for(i = 0; i < 2; i++)
{
I2C_putData(I2CA_BASE, sDatai2cA[i]);
}
//
// Send the start condition
//
I2C_sendStartCondition(I2CA_BASE);
//
// Increment data for next cycle
//
for(i = 0; i < 2; i++)
{
sDatai2cA[i] = (sDatai2cA[i] + 1) & 0xFF;
}
//
// Clear interrupt flag
//
I2C_clearInterruptStatus(I2CA_BASE, I2C_INT_TXFF);
}
//
// Issue ACK
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
}
//
// sciaTXFIFOISR - SCIA Transmit FIFO ISR
//
__interrupt void sciaTXFIFOISR(void)
{
uint16_t i;
SCI_writeCharArray(SCIA_BASE, sDatasciA, 2);
//
// Increment send data for next cycle
//
for(i = 0; i < 2; i++)
{
sDatasciA[i] = (sDatasciA[i] + 1) & 0x00FF;
}
SCI_clearInterruptStatus(SCIA_BASE, SCI_INT_TXFF);
//
// Issue PIE ACK
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP9);
}
//
// sciaRXFIFOISR - SCIA Receive FIFO ISR
//
__interrupt void sciaRXFIFOISR(void)
{
uint16_t i;
SCI_readCharArray(SCIA_BASE, rDatasciA, 2);
//
// Check received data
//
for(i = 0; i < 2; i++)
{
if(rDatasciA[i] != ((rDataPointA + i) & 0x00FF))
{
//
// Something went wrong. rDatasciA doesn't contain expected data.
//
ESTOP0;
}
}
rDataPointA = (rDataPointA + 1) & 0x00FF;
SCI_clearOverflowStatus(SCIA_BASE);
SCI_clearInterruptStatus(SCIA_BASE, SCI_INT_RXFF);
//
// Issue PIE ack
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP9);
}
//
// initSCIAFIFO - Configure SCIA FIFO
//
void initSCIAFIFO()
{
//
// 8 char bits, 1 stop bit, no parity. Baud rate is 9600.
//
SCI_setConfig(SCIA_BASE, DEVICE_LSPCLK_FREQ, 9600, (SCI_CONFIG_WLEN_8 |
SCI_CONFIG_STOP_ONE |
SCI_CONFIG_PAR_NONE));
SCI_enableModule(SCIA_BASE);
SCI_enableLoopback(SCIA_BASE);
SCI_resetChannels(SCIA_BASE);
SCI_enableFIFO(SCIA_BASE);
//
// RX and TX FIFO Interrupts Enabled
//
SCI_enableInterrupt(SCIA_BASE, (SCI_INT_RXFF | SCI_INT_TXFF));
SCI_disableInterrupt(SCIA_BASE, SCI_INT_RXERR);
//
// The transmit FIFO generates an interrupt when FIFO status
// bits are less than or equal to 2 out of 16 words
// The receive FIFO generates an interrupt when FIFO status
// bits are greater than equal to 2 out of 16 words
//
SCI_setFIFOInterruptLevel(SCIA_BASE, SCI_FIFO_TX2, SCI_FIFO_RX2);
SCI_performSoftwareReset(SCIA_BASE);
SCI_resetTxFIFO(SCIA_BASE);
SCI_resetRxFIFO(SCIA_BASE);
}
//
// Function to configure SPI A in FIFO mode.
//
void initSPIFIFO()
{
//
// Must put SPI into reset before configuring it
//
SPI_disableModule(SPIA_BASE);
//
// SPI configuration. Use a 500kHz SPICLK and 16-bit word size.
//
SPI_setConfig(SPIA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0,
SPI_MODE_CONTROLLER, 500000, 16);
SPI_enableLoopback(SPIA_BASE);
SPI_setEmulationMode(SPIA_BASE, SPI_EMULATION_STOP_AFTER_TRANSMIT);
//
// FIFO and interrupt configuration
//
SPI_enableFIFO(SPIA_BASE);
SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
SPI_setFIFOInterruptLevel(SPIA_BASE, SPI_FIFO_TX2, SPI_FIFO_RX2);
SPI_enableInterrupt(SPIA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
//
// Configuration complete. Enable the module.
//
SPI_enableModule(SPIA_BASE);
}
//
// SPI A Transmit FIFO ISR
//
__interrupt void spiTxFIFOISR(void)
{
uint16_t i;
//
// Send data
//
for(i = 0; i < 2; i++)
{
SPI_writeDataNonBlocking(SPIA_BASE, sDataspiA[i]);
}
//
// Increment data for next cycle
//
for(i = 0; i < 2; i++)
{
sDataspiA[i] = sDataspiA[i] + 1;
}
//
// Clear interrupt flag and issue ACK
//
SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_TXFF);
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
}
//
// SPI A Receive FIFO ISR
//
__interrupt void spiRxFIFOISR(void)
{
uint16_t i;
//
// Read data
//
for(i = 0; i < 2; i++)
{
rDataspiA[i] = SPI_readDataNonBlocking(SPIA_BASE);
}
//
// Check received data
//
for(i = 0; i < 2; i++)
{
if(rDataspiA[i] != (rDataPointspiA + i))
{
// Something went wrong. rDataspiA doesn't contain expected data.
ESTOP0;
}
}
rDataPointspiA++;
//
// Clear interrupt flag and issue ACK
//
SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_RXFF);
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
}
//
// End of File
//
C2000Ware/driverlib/f2838x/examples/c28x/interrupt/interrupt_ex3_sw_prioritization.c
+422
View File
@@ -0,0 +1,422 @@
//#############################################################################
//
// FILE: interrupt_ex3_sw_prioritization.c
//
// TITLE: CPU Timer Interrupt Software Prioritization
//
//! \addtogroup driver_example_list
//! <h1> CPU Timer Interrupt Software Prioritization </h1>
//!
//! This examples demonstrates the software prioritization of interrupts
//! through CPU Timer Interrupts. Software prioritization of interrupts is
//! achieved by enabling interrupt nesting.
//!
//! In this device, hardware priorities for CPU Timer 0, 1 and 2 are set
//! as timer 0 being highest priority and timer 2 being lowest priority.
//! This example configures CPU Timer0, 1, and 2 priority in software with
//! timer 2 priority being highest and timer 0 being lowest in software and
//! prints a trace for the order of execution.
//!
//! For most applications, the hardware prioritizing of the interrupts is
//! sufficient. For applications that need custom prioritizing, this example
//! illustrates how this can be done through software.User specific priorities
//! can be configured in sw_prioritized_isr_level.h header file.
//!
//! To enable interrupt nesting, following sequence needs to followed in ISRs.
//! <b>Step 1:</b> Set the global priority:
//! Modify the IER register to allow CPU interrupts with a higher user
//! priority to be serviced.
//! Note: at this time IER has already been saved on the stack.
//! <b>Step 2:</b> Set the group priority: (optional)
//! Modify the appropriate PIEIERx register to allow group interrupts with a
//! higher user set priority to be serviced. Do NOT clear PIEIER register bits
//! from another group other than that being serviced by this ISR. Doing so
//! can cause erroneous interrupts to occur.
//! <b>Step 3:</b> Enable interrupts: There are three steps to do this:
//! a. Clear the PIEACK bits
//! b. Wait at least one cycle
//! c. Clear the INTM bit.
//! <b>Step 4:</b> Run the main part of the ISR
//! <b>Step 5:</b> Set INTM to disable interrupts.
//! <b>Step 6:</b> Restore PIEIERx (optional depending on step 2)
//! <b>Step 7:</b> Return from ISR
//!
//! Refer to below link on more details on Interrupt nesting in C28x devices:
//! <C2000Ware>\docs\c28x_interrupt_nesting\html\index.html
//!
//! \b External \b Connections \n
//! - None
//!
//! \b Watch \b Variables \n
//! - traceISR - shows the order in which ISRs are executed.
//!
//
//#############################################################################
//
//
//
// C2000Ware v5.04.00.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
#include "sw_prioritized_isr_levels.h"
//
// Defines
//
#define TRACE_SIZE 51U
//
// Globals
//
uint16_t cpuTimer0IntCount;
uint16_t cpuTimer1IntCount;
uint16_t cpuTimer2IntCount;
//
// This array will be used as a trace to check the
// order that the interrupts were serviced
//
uint16_t traceISR[TRACE_SIZE];
//
// Index to update an element in the trace buffer
//
uint16_t traceISRIndex = 0;
//
// Function Prototypes
//
__interrupt void cpuTimer0ISR(void);
__interrupt void cpuTimer1ISR(void);
__interrupt void cpuTimer2ISR(void);
void initCPUTimers(void);
void configCPUTimer(uint32_t, float, float);
//
// Main
//
void main(void)
{
uint32_t i;
//
// Initializes device clock and peripherals
//
Device_init();
//
// Configures the GPIO pin as a push-pull output
//
Device_initGPIO();
//
// Initializes PIE and clears PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initializes the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// ISRs for each CPU Timer interrupt
//
Interrupt_register(INT_TIMER0, &cpuTimer0ISR);
Interrupt_register(INT_TIMER1, &cpuTimer1ISR);
Interrupt_register(INT_TIMER2, &cpuTimer2ISR);
//
// Reset the ISR trace
//
for(i = 0; i < TRACE_SIZE; i++)
{
traceISR[i] = 0;
}
//
// Initializes the Device Peripheral. For this example, only initialize the
// Cpu Timers.
//
initCPUTimers();
//
// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
// 1 second Period (in uSeconds)
//
configCPUTimer(CPUTIMER0_BASE, DEVICE_SYSCLK_FREQ, 1000000);
configCPUTimer(CPUTIMER1_BASE, DEVICE_SYSCLK_FREQ, 1000000);
configCPUTimer(CPUTIMER2_BASE, DEVICE_SYSCLK_FREQ, 1000000);
//
// To ensure precise timing, use write-only instructions to write to the
// entire register. Therefore, if any of the configuration bits are changed
// in configCPUTimer and initCPUTimers, the below settings must also
// be updated.
//
CPUTimer_enableInterrupt(CPUTIMER0_BASE);
CPUTimer_enableInterrupt(CPUTIMER1_BASE);
CPUTimer_enableInterrupt(CPUTIMER2_BASE);
//
// Enables CPU int1, int13, and int14 which are connected to CPU-Timer 0,
// CPU-Timer 1, and CPU-Timer 2 respectively.
// Enable TINT0 in the PIE: Group 1 interrupt 7
//
Interrupt_enable(INT_TIMER0);
Interrupt_enable(INT_TIMER1);
Interrupt_enable(INT_TIMER2);
//
// Starts CPU-Timer 0, CPU-Timer 1, and CPU-Timer 2.
//
CPUTimer_startTimer(CPUTIMER0_BASE);
CPUTimer_startTimer(CPUTIMER1_BASE);
CPUTimer_startTimer(CPUTIMER2_BASE);
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;
//
// IDLE loop. Just sit and loop forever (optional)
//
while(1)
{
}
}
//
// initCPUTimers - This function initializes all three CPU timers
// to a known state.
//
void
initCPUTimers(void)
{
//
// Initialize timer period to maximum
//
CPUTimer_setPeriod(CPUTIMER0_BASE, 0xFFFFFFFF);
CPUTimer_setPeriod(CPUTIMER1_BASE, 0xFFFFFFFF);
CPUTimer_setPeriod(CPUTIMER2_BASE, 0xFFFFFFFF);
//
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT)
//
CPUTimer_setPreScaler(CPUTIMER0_BASE, 0);
CPUTimer_setPreScaler(CPUTIMER1_BASE, 0);
CPUTimer_setPreScaler(CPUTIMER2_BASE, 0);
//
// Make sure timer is stopped
//
CPUTimer_stopTimer(CPUTIMER0_BASE);
CPUTimer_stopTimer(CPUTIMER1_BASE);
CPUTimer_stopTimer(CPUTIMER2_BASE);
//
// Reload all counter register with period value
//
CPUTimer_reloadTimerCounter(CPUTIMER0_BASE);
CPUTimer_reloadTimerCounter(CPUTIMER1_BASE);
CPUTimer_reloadTimerCounter(CPUTIMER2_BASE);
//
// Reset interrupt counter
//
cpuTimer0IntCount = 0;
cpuTimer1IntCount = 0;
cpuTimer2IntCount = 0;
}
//
// configCPUTimer - This function initializes the selected timer to the
// period specified by the "freq" and "period" parameters. The "freq" is
// entered as Hz and the period in uSeconds. The timer is held in the stopped
// state after configuration.
//
void
configCPUTimer(uint32_t cpuTimer, float freq, float period)
{
uint32_t temp;
//
// Initialize timer period:
//
temp = (uint32_t)(freq / 1000000 * period);
CPUTimer_setPeriod(cpuTimer, temp - 1);
//
// Set pre-scale counter to divide by 1 (SYSCLKOUT):
//
CPUTimer_setPreScaler(cpuTimer, 0);
//
// Initializes timer control register. The timer is stopped, reloaded,
// free run disabled, and interrupt enabled.
// Additionally, the free and soft bits are set
//
CPUTimer_stopTimer(cpuTimer);
CPUTimer_reloadTimerCounter(cpuTimer);
CPUTimer_setEmulationMode(cpuTimer,
CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT);
CPUTimer_enableInterrupt(cpuTimer);
//
// Resets interrupt counters for the three cpuTimers
//
if (cpuTimer == CPUTIMER0_BASE)
{
cpuTimer0IntCount = 0;
}
else if(cpuTimer == CPUTIMER1_BASE)
{
cpuTimer1IntCount = 0;
}
else if(cpuTimer == CPUTIMER2_BASE)
{
cpuTimer2IntCount = 0;
}
}
//
// cpuTimer0ISR - Counter for CpuTimer0
//
__interrupt void
cpuTimer0ISR(void)
{
//
// Save IER register on stack
//
volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);
//
// Set the global and group priority to allow CPU interrupts
// with higher priority
//
IER |= M_INT1;
IER &= MINT1;
HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_7;
//
// Enable Interrupts
//
Interrupt_clearACKGroup(0xFFFFU);
__asm(" NOP");
EINT;
//
// Insert ISR code here
//
cpuTimer0IntCount++;
//
// Disable interrupts and restore registers saved:
//
DINT;
HWREGH(PIECTRL_BASE + PIE_O_IER1) = tempPIEIER;
//
// Add ISR to Trace
//
traceISR[traceISRIndex % TRACE_SIZE] = 0x0017;
traceISRIndex++;
}
//
// cpuTimer1ISR - Counter for CpuTimer1
//
__interrupt void
cpuTimer1ISR(void)
{
//
// Set the global priority to allow CPU interrupts with higher priority
//
IER &= MINT13;
EINT;
//
// Insert ISR code here
//
cpuTimer1IntCount++;
//
// Disable Interrupts
//
DINT;
//
// Add ISR to Trace
//
traceISR[traceISRIndex % TRACE_SIZE] = 0x00D0;
traceISRIndex++;
}
//
// cpuTimer2ISR - Counter for CpuTimer2
//
__interrupt void
cpuTimer2ISR(void)
{
IER &= MINT14; // Set "global" priority
EINT;
//
// Insert ISR code here
//
cpuTimer2IntCount++;
//
// Disable interrupts
//
DINT;
//
// Add ISR to Trace
//
traceISR[traceISRIndex % TRACE_SIZE] = 0x00E0;
traceISRIndex++;
}
//
// End of File
//
C2000Ware/driverlib/f2838x/examples/c28x/interrupt/interrupt_ex4_epwm_realtime_interrupt.c
+275
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//#############################################################################
//
// FILE: interrupt_ex4_epwm_realtime_interrupt.c
//
// TITLE: EPWM Real-Time Interrupt
//
//! \addtogroup driver_example_list
//! <h1> EPWM Real-Time Interrupt </h1>
//!
//! This example configures the ePWM1 Timer and increments a counter each time
//! the ISR is executed. ePWM interrupt can be configured as time critical
//! to demonstrate real-time mode functionality and real-time interrupt
//! capability.
//!
//! The example uses 2 LEDs - LED1 is toggled in the main loop and LED2 is
//! toggled in the EPWM Timer Interrupt. FREE_SOFT bits and DBGIER.INT3 bit
//! must be set to enable ePWM1 interrupt to be time critical and operational
//! in real time mode after halt command
//!
//! How to run the example?
//! - Add the watch variables as mentioned below and enable Continuous Refresh.
//! - Enable real-time mode (Run->Advanced->Enable Silicon Real-time Mode)
//! - Initially, the DBGIER register is set to 0 and the EPWM emulation mode
//! is set to EPWM_EMULATION_STOP_AFTER_NEXT_TB (FREE_SOFT = 0)
//! - When the application is running, you will find both LEDs toggling and
//! the watch variables EPwm1TimerIntCount, EPwm1Regs.TBCTR getting updated.
//! - When the application is halted, both LEDs stop toggling and the watch
//! variables remain constant. EPWM counter is stopped on debugger halt.
//! - To enable EPWM counter run during debugger halt, set emulation mode as
//! EPWM_EMULATION_FREE_RUN (FREE_SOFT = 2). You will find EPwm1Regs.TBCTR
//! is running, but EPwm1TimerIntCount remains constant. This means,
//! the EPWM counter is running, but the ISRs are not getting serviced.
//! - To enable real-time interrupts, set DBGIER.INT3 = 1 (EPWM1 interrupt is
//! part of PIE Group 3). You will find that the EPwm1TimerIntCount is
//! incrementing and the LED starts toggling. The EPWM ISR is getting
//! serviced even during a debugger halt.
//!
//! For more details, watch this video :
//! [C2000 Real-Time
//! Features](https://training.ti.com/c2000-real-time-features)
//!
//! \b External \b Connections \n
//! - None
//!
//! \b Watch \b Variables \n
//! - EPwm1TimerIntCount - EPWM1 ISR counter
//! - EPwm1Regs.TBCTR.TBCTR - EPWM1 Time Base counter
//! - EPwm1Regs.TBCTL.FREE_SOFT - Set this to 2 to enable free run
//! - DBGIER.INT3 - Set to 1 to enable real time interrupt
//!
//
//#############################################################################
//
//
//
// C2000Ware v5.04.00.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
#include "driverlib.h"
#include "device.h"
//
// Defines
//
#define EPWM1_TIMER_TBPRD 0x2000
//
// Globals
//
uint32_t EPwm1TimerIntCount;
uint16_t LEDcount;
//
// Function Prototypes
//
extern void SetDBGIER(uint16_t dbgier); // Defined in <device>_dbgier.asm file
void initEPWM(void);
__interrupt void epwm1ISR(void);
//
// Main
//
void main(void)
{
//
// Initializes device clock and peripherals
//
Device_init();
//
// Configures the GPIO pin as a push-pull output
//
Device_initGPIO();
GPIO_setPadConfig(DEVICE_GPIO_PIN_LED1, GPIO_PIN_TYPE_STD);
GPIO_setDirectionMode(DEVICE_GPIO_PIN_LED1, GPIO_DIR_MODE_OUT);
GPIO_setPadConfig(DEVICE_GPIO_PIN_LED2, GPIO_PIN_TYPE_STD);
GPIO_setDirectionMode(DEVICE_GPIO_PIN_LED2, GPIO_DIR_MODE_OUT);
//
// Initializes PIE and clears PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initializes the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
Interrupt_register(INT_EPWM1, &epwm1ISR);
//
// Initialize EPWM1
//
initEPWM();
//
// Initialize counters
//
EPwm1TimerIntCount = 0;
LEDcount = 0;
//
// Enable EPWM1 Interrupt
//
Interrupt_enable(INT_EPWM1);
//
// Initially disable time-critical interrupts.
// The parameter to SetDBGIER() can be Ored value of INTERRUPT_CPU_INTx.
// Eg : SetDBGIER(INTERRUPT_CPU_INT3);
//
SetDBGIER(0x0000); // PIE groups time-critical designation
//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;
//
// Loop forever
//
while(1)
{
//
// Toggle LED1
//
GPIO_togglePin(DEVICE_GPIO_PIN_LED1);
//
// 200ms delay
//
DEVICE_DELAY_US(200000);
}
}
void initEPWM()
{
//
// Disable sync
//
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
//
// Initially disable Free/Soft Bits
//
EPWM_setEmulationMode(EPWM1_BASE, EPWM_EMULATION_STOP_AFTER_NEXT_TB);
//
// Setup TBCLK
//
EPWM_setTimeBasePeriod(EPWM1_BASE, EPWM1_TIMER_TBPRD);
EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP);
EPWM_setTimeBaseCounter(EPWM1_BASE, 0U);
//
// CompareA event at half of period
//
EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A,
EPWM1_TIMER_TBPRD/2);
//
// Action Qualifiers : Set on CMPA, Clear on PRD
//
EPWM_setActionQualifierAction(EPWM1_BASE,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(EPWM1_BASE,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
//
// Configure interrupt on event CTR=ZERO
//
EPWM_setInterruptSource(EPWM1_BASE, EPWM_INT_TBCTR_ZERO);
EPWM_enableInterrupt(EPWM1_BASE);
EPWM_setInterruptEventCount(EPWM1_BASE, 1);
//
// Enable sync and clock to PWM
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
}
__interrupt void
epwm1ISR(void)
{
EPwm1TimerIntCount++;
LEDcount++;
//
// Toggle LED2 when the count reaches 500
//
if (LEDcount == 500)
{
GPIO_togglePin(DEVICE_GPIO_PIN_LED2);
LEDcount=0;
}
//
// Clear INT flag for this timer
//
EPWM_clearEventTriggerInterruptFlag(EPWM1_BASE);
//
// Acknowledge this interrupt to receive more interrupts from group 3
//
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP3);
}
//
// End of File
//
C2000Ware/driverlib/f2838x/examples/c28x/interrupt/sw_prioritized_isr_levels.h
+368
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//###########################################################################
//
// FILE: sw_prioritized_isr_levels.h
//
// TITLE: Software Prioritized Interrupt Service Routine Level
// definitions.
//
//#############################################################################
//
//
//
// C2000Ware v5.04.00.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#ifndef SW_PRIORITZIED_ISR_LEVELS_H
#define SW_PRIORITZIED_ISR_LEVELS_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Mask for interrupt groups
//
#define M_INT1 0x0001 // INT1 Mask
#define M_INT2 0x0002 // INT2 Mask
#define M_INT3 0x0004 // INT3 Mask
#define M_INT4 0x0008 // INT4 Mask
#define M_INT5 0x0010 // INT5 Mask
#define M_INT6 0x0020 // INT6 Mask
#define M_INT7 0x0040 // INT7 Mask
#define M_INT8 0x0080 // INT8 Mask
#define M_INT9 0x0100 // INT9 Mask
#define M_INT10 0x0200 // INT10 Mask
#define M_INT11 0x0400 // INT11 Mask
#define M_INT12 0x0800 // INT12 Mask
#define M_INT13 0x1000 // INT13 Mask
#define M_INT14 0x2000 // INT14 Mask
#define M_DLOG 0x4000 // DLOGINT Mask
#define M_RTOS 0x8000 // RTOSINT Mask
//
// Interrupt Enable Register Allocation:
// Interrupts can be enabled/disabled using the CPU interrupt enable register
// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12).
//
//
// Set "Global" Interrupt Priority Level (IER register):
//
// The user must set the appropriate priority level for each of the CPU
// interrupts. This is termed as the "global" priority. The priority level
// must be a number between 1 (highest) to 16 (lowest). A value of 0 must
// be entered for reserved interrupts or interrupts that are not used.
//
// Note: The priority levels below are used to calculate the IER register
// interrupt masks MINT1 to MINT16.
//
// Note: The priority levels shown here may not make sense in a
// real application. This is for demonstration purposes only!!!
//
// The user should change these to values that make sense for
// their application.
//
// 0 = not used
// 1 = highest priority
// ...
// 16 = lowest priority
//
#define INT1PL 16 // Global Priority for Group1 Interrupts
#define INT2PL 0 // Global Priority for Group2 Interrupts
#define INT3PL 0 // Global Priority for Group3 Interrupts
#define INT4PL 0 // Global Priority for Group4 Interrupts
#define INT5PL 0 // Global Priority for Group5 Interrupts
#define INT6PL 0 // Global Priority for Group6 Interrupts
#define INT7PL 0 // Global Priority for Group7 Interrupts
#define INT8PL 0 // Global Priority for Group8 Interrupts
#define INT9PL 0 // Global Priority for Group9 Interrupts
#define INT10PL 0 // Global Priority for Group10 Interrupts
#define INT11PL 0 // Global Priority for Group11 Interrupts
#define INT12PL 0 // Global Priority for Group12 Interrupts
#define INT13PL 7 // Global Priority for INT13 (TINT1)
#define INT14PL 1 // Global Priority for INT14 (TINT2)
#define INT15PL 0 // Global Priority for DATALOG
#define INT16PL 0 // Global Priority for RTOSINT
//
// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers):
//
// The user must set the appropriate priority level for each of the PIE
// interrupts. This is termed as the "group" priority. The priority level
// must be a number between 1 (highest) to 16 (lowest). A value of 0 must
// be entered for reserved interrupts or interrupts that are not used.
//
// Note: The priority levels below are used to calculate the following
// PIEIER register interrupt masks:
// MG1_1 to MG1_16
// MG2_1 to MG2_16
// MG3_1 to MG3_16
// MG4_1 to MG4_16
// MG5_1 to MG5_16
// MG6_1 to MG6_16
// MG7_1 to MG7_16
// MG8_1 to MG8_16
// MG9_1 to MG9_16
// MG10_1 to MG10_16
// MG11_1 to MG11_16
// MG12_1 to MG12_16
//
// Note: The priority levels shown here may not make sense in a
// real application. This is for demonstration purposes only!!!
//
// The user should change these to values that make sense for
// their application.
//
// 0 = not used
// 1 = highest priority
// ...
// 16 = lowest priority
//
#define G1_1PL 0 // ADCA1_INT
#define G1_2PL 0 // ADCB1_INT
#define G1_3PL 0 // ADCC1_INT
#define G1_4PL 0 // XINT1_INT
#define G1_5PL 0 // XINT2_INT
#define G1_6PL 0 // ADCD1_INT
#define G1_7PL 4 // TIMER0_INT
#define G1_8PL 0 // WAKE_INT
#define G1_9PL 0 // I2CA_HIGH_INT
#define G1_10PL 0 // SYS_ERROR_INT
#define G1_11PL 0 // ECATSYNC0_INT
#define G1_12PL 0 // ECAT_INT
#define G1_13PL 0 // IPC0_INT
#define G1_14PL 0 // IPC1_INT
#define G1_15PL 0 // IPC2_INT
#define G1_16PL 0 // IPC3_INT
#define G2_1PL 0 // EPWM1_TZ_INT
#define G2_2PL 0 // EPWM2_TZ_INT
#define G2_3PL 0 // EPWM3_TZ_INT
#define G2_4PL 0 // EPWM4_TZ_INT
#define G2_5PL 0 // EPWM5_TZ_INT
#define G2_6PL 0 // EPWM6_TZ_INT
#define G2_7PL 0 // EPWM7_TZ_INT
#define G2_8PL 0 // EPWM8_TZ_INT
#define G2_9PL 0 // EPWM9_TZ_INT
#define G2_10PL 0 // EPWM10_TZ_INT
#define G2_11PL 0 // EPWM11_TZ_INT
#define G2_12PL 0 // EPWM12_TZ_INT
#define G2_13PL 0 // EPWM13_TZ_INT
#define G2_14PL 0 // EPWM14_TZ_INT
#define G2_15PL 0 // EPWM15_TZ_INT
#define G2_16PL 0 // EPWM16_TZ_INT
#define G3_1PL 0 // EPWM1_INT
#define G3_2PL 0 // EPWM2_INT
#define G3_3PL 0 // EPWM3_INT
#define G3_4PL 0 // EPWM4_INT
#define G3_5PL 0 // EPWM5_INT
#define G3_6PL 0 // EPWM6_INT
#define G3_7PL 0 // EPWM7_INT
#define G3_8PL 0 // EPWM8_INT
#define G3_9PL 0 // EPWM9_INT
#define G3_10PL 0 // EPWM10_INT
#define G3_11PL 0 // EPWM11_INT
#define G3_12PL 0 // EPWM12_INT
#define G3_13PL 0 // EPWM13_INT
#define G3_14PL 0 // EPWM14_INT
#define G3_15PL 0 // EPWM15_INT
#define G3_16PL 0 // EPWM16_INT
#define G4_1PL 0 // ECAP1_INT
#define G4_2PL 0 // ECAP2_INT
#define G4_3PL 0 // ECAP3_INT
#define G4_4PL 0 // ECAP4_INT
#define G4_5PL 0 // ECAP5_INT
#define G4_6PL 0 // ECAP6_INT
#define G4_7PL 0 // ECAP7_INT
#define G4_8PL 0 // Reserved
#define G4_9PL 0 // FSITXA1_INT
#define G4_10PL 0 // FSITXA2_INT
#define G4_11PL 0 // FSITXB1_INT
#define G4_12PL 0 // FSITXB2_INT
#define G4_13PL 0 // FSIRXA1_INT
#define G4_14PL 0 // FSIRXA2_INT
#define G4_15PL 0 // FSIRXB1_INT
#define G4_16PL 0 // FSIRXB2_INT
#define G5_1PL 0 // EQEP1_INT
#define G5_2PL 0 // EQEP2_INT
#define G5_3PL 0 // EQEP3_INT
#define G5_4PL 0 // Reserved
#define G5_5PL 0 // CLB1_INT
#define G5_6PL 0 // CLB2_INT
#define G5_7PL 0 // CLB3_INT
#define G5_8PL 0 // CLB4_INT
#define G5_9PL 0 // SD1_INT
#define G5_10PL 0 // SD2_INT
#define G5_11PL 0 // ECATRST_INT
#define G5_12PL 0 // ECATSYNC1_INT
#define G5_13PL 0 // SDFM1DR1_INT
#define G5_14PL 0 // SDFM1DR2_INT
#define G5_15PL 0 // SDFM1DR3_INT
#define G5_16PL 0 // SDFM1DR4_INT
#define G6_1PL 0 // SPIA_RX_INT
#define G6_2PL 0 // SPIA_TX_INT
#define G6_3PL 0 // SPIB_RX_INT
#define G6_4PL 0 // SPIB_TX_INT
#define G6_5PL 0 // MCBSPA_RX_INT
#define G6_6PL 0 // MCBSPA_TX_INT
#define G6_7PL 0 // MCBSPB_RX_INT
#define G6_8PL 0 // MCBSPB_TX_INT
#define G6_9PL 0 // SPIC_RX_INT
#define G6_10PL 0 // SPIC_TX_INT
#define G6_11PL 0 // SPID_RX_INT
#define G6_12PL 0 // SPID_TX_INT
#define G6_13PL 0 // SDFM2DR1_INT
#define G6_14PL 0 // SDFM2DR2_INT
#define G6_15PL 0 // SDFM2DR3_INT
#define G6_16PL 0 // SDFM2DR4_INT
#define G7_1PL 0 // DMA_CH1_INT
#define G7_2PL 0 // DMA_CH2_INT
#define G7_3PL 0 // DMA_CH3_INT
#define G7_4PL 0 // DMA_CH4_INT
#define G7_5PL 0 // DMA_CH5_INT
#define G7_6PL 0 // DMA_CH6_INT
#define G7_7PL 0 // Reserved
#define G7_8PL 0 // Reserved
#define G7_9PL 0 // FSIRXC1_INT
#define G7_10PL 0 // FSIRXC2_INT
#define G7_11PL 0 // FSIRXD1_INT
#define G7_12PL 0 // FSIRXD2_INT
#define G7_13PL 0 // FSIRXE1_INT
#define G7_14PL 0 // FSIRXE2_INT
#define G7_15PL 0 // FSIRXF1_INT
#define G7_16PL 0 // FSIRXF2_INT
#define G8_1PL 0 // I2CA_INT
#define G8_2PL 0 // I2CA_FIFO_INT
#define G8_3PL 0 // I2CB_INT
#define G8_4PL 0 // I2CB_FIFO_INT
#define G8_5PL 0 // SCIC_RX_INT
#define G8_6PL 0 // SCIC_TX_INT
#define G8_7PL 0 // SCID_RX_INT
#define G8_8PL 0 // SCID_TX_INT
#define G8_9PL 0 // FSIRXG1_INT
#define G8_10PL 0 // FSIRXG2_INT
#define G8_11PL 0 // FSIRXH1_INT
#define G8_12PL 0 // FSIRXH2_INT
#define G8_13PL 0 // Reserved
#define G8_14PL 0 // Reserved
#define G8_15PL 0 // Reserved
#define G8_16PL 0 // Reserved
#define G9_1PL 0 // SCIA_RX_INT
#define G9_2PL 0 // SCIA_TX_INT
#define G9_3PL 0 // SCIB_RX_INT
#define G9_4PL 0 // SCIB_TX_INT
#define G9_5PL 0 // CANA0_INT
#define G9_6PL 0 // CANA1_INT
#define G9_7PL 0 // CANB0_INT
#define G9_8PL 0 // CANB1_INT
#define G9_9PL 0 // MCAN0_INT
#define G9_10PL 0 // MCAN1_INT
#define G9_11PL 0 // Reserved
#define G9_12PL 0 // Reserved
#define G9_13PL 0 // PMBUSA_INT
#define G9_14PL 0 // CM_STATUS_INT
#define G9_15PL 0 // USBA_INT
#define G9_16PL 0 // Reserved
#define G10_1PL 0 // ADCA_EVT_INT
#define G10_2PL 0 // ADCA2_INT
#define G10_3PL 0 // ADCA3_INT
#define G10_4PL 0 // ADCA4_INT
#define G10_5PL 0 // ADCB_EVT_INT
#define G10_6PL 0 // ADCB2_INT
#define G10_7PL 0 // ADCB3_INT
#define G10_8PL 0 // ADCB4_INT
#define G10_9PL 0 // ADCC_EVT_INT
#define G10_10PL 0 // ADCC2_INT
#define G10_11PL 0 // ADCC3_INT
#define G10_12PL 0 // ADCC4_INT
#define G10_13PL 0 // ADCD_EVT_INT
#define G10_14PL 0 // ADCD2_INT
#define G10_15PL 0 // ADCD3_INT
#define G10_16PL 0 // ADCD4_INT
#define G11_1PL 0 // CLA1_1_INT
#define G11_2PL 0 // CLA1_2_INT
#define G11_3PL 0 // CLA1_3_INT
#define G11_4PL 0 // CLA1_4_INT
#define G11_5PL 0 // CLA1_5_INT
#define G11_6PL 0 // CLA1_6_INT
#define G11_7PL 0 // CLA1_7_INT
#define G11_8PL 0 // CLA1_8_INT
#define G11_9PL 0 // CMTOCPUXIPC0_INT
#define G11_10PL 0 // CMTOCPUXIPC1_INT
#define G11_11PL 0 // CMTOCPUXIPC2_INT
#define G11_12PL 0 // CMTOCPUXIPC3_INT
#define G11_13PL 0 // CMTOCPUXIPC4_INT
#define G11_14PL 0 // CMTOCPUXIPC5_INT
#define G11_15PL 0 // CMTOCPUXIPC6_INT
#define G11_16PL 0 // CMTOCPUXIPC7_INT
#define G12_1PL 0 // XINT3_INT
#define G12_2PL 0 // XINT4_INT
#define G12_3PL 0 // XINT5_INT
#define G12_4PL 0 // Reserved
#define G12_5PL 0 // FMC_INT
#define G12_6PL 0 // Reserved
#define G12_7PL 0 // FPU_OVERFLOW_ISR
#define G12_8PL 0 // FPU_UNDERFLOW_ISR
#define G12_9PL 0 // Reserved
#define G12_10PL 0 // ECAP6_2_INT
#define G12_11PL 0 // ECAP7_2_INT
#define G12_12PL 0 // Reserved
#define G12_13PL 0 // CPUCRC_INT
#define G12_14PL 0 // CLA1CRC_INT
#define G12_15PL 0 // CLA_OVERFLOW_INT
#define G12_16PL 0 // CLA_UNDERFLOW_INT
//
// Include the header file with software interrupt prioritization logic
//
#include "sw_interrupt_prioritization_logic.h"
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // eof
//
// End of file
//