Update repo
This commit is contained in:
+41
@@ -0,0 +1,41 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="sdfm_ex1_filter_sync_cpuread"
|
||||
device="TMS320F28388D"
|
||||
cgtVersion="22.6.1.LTS"
|
||||
products="sysconfig;C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
|
||||
postBuildStep="
|
||||
echo "========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) ============="
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js" "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/" "${BuildDirectory}/syscfg" "${BuildDirectory}/syscfg/clb.dot"
|
||||
;if ${GENERATE_DIAGRAM} == 1 mkdir "${BuildDirectory}/diagrams"
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js" "${C2000WARE_ROOT}" "${BuildDirectory}/diagrams" "${BuildDirectory}/syscfg"
|
||||
"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
|
||||
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
|
||||
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
|
||||
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../sdfm_ex1_filter_sync_cpuread.c" targetDirectory="" />
|
||||
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
|
||||
+48
@@ -0,0 +1,48 @@
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||||
<projectSpec>
|
||||
<project
|
||||
name="sdfm_ex2_filter_sync_claread"
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||||
device="TMS320F28388D"
|
||||
cgtVersion="22.6.1.LTS"
|
||||
products="sysconfig;C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
|
||||
postBuildStep="
|
||||
echo "========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) ============="
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js" "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/" "${BuildDirectory}/syscfg" "${BuildDirectory}/syscfg/clb.dot"
|
||||
;if ${GENERATE_DIAGRAM} == 1 mkdir "${BuildDirectory}/diagrams"
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js" "${C2000WARE_ROOT}" "${BuildDirectory}/diagrams" "${BuildDirectory}/syscfg"
|
||||
"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_COMMON_INCLUDE} -I${C2000WARE_HEADERS_INCLUDE} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -I${C2000WARE_COMMON_INCLUDE} -I${C2000WARE_HEADERS_INCLUDE} -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
|
||||
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
|
||||
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
|
||||
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
|
||||
|
||||
<pathVariable name="C2000WARE_COMMON_INCLUDE" path="../../../../../../device_support/f2838x/common/include/" scope="project" />
|
||||
<pathVariable name="C2000WARE_HEADERS_INCLUDE" path="../../../../../../device_support/f2838x/headers/include/" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
|
||||
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/headers/cmd/f2838x_headers_nonBIOS_cpu1.cmd" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/headers/source/f2838x_globalvariabledefs.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_SDFM_CLA_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_SDFM_CLA_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../sdfm_ex2_filter_sync_claread_cla.cla" targetDirectory="" />
|
||||
<file action="copy" path="../sdfm_ex2_filter_sync_claread.c" targetDirectory="" />
|
||||
<file action="copy" path="../sdfm_claread.h" targetDirectory="" />
|
||||
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="sdfm_ex3_filter_sync_dmaread"
|
||||
device="TMS320F28388D"
|
||||
cgtVersion="22.6.1.LTS"
|
||||
products="sysconfig;C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
|
||||
postBuildStep="
|
||||
echo "========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) ============="
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js" "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/" "${BuildDirectory}/syscfg" "${BuildDirectory}/syscfg/clb.dot"
|
||||
;if ${GENERATE_DIAGRAM} == 1 mkdir "${BuildDirectory}/diagrams"
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js" "${C2000WARE_ROOT}" "${BuildDirectory}/diagrams" "${BuildDirectory}/syscfg"
|
||||
"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
|
||||
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
|
||||
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
|
||||
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../sdfm_ex3_filter_sync_dmaread.c" targetDirectory="" />
|
||||
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="sdfm_ex4_pwm_sync_cpuread"
|
||||
device="TMS320F28388D"
|
||||
cgtVersion="22.6.1.LTS"
|
||||
products="sysconfig;C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
|
||||
postBuildStep="
|
||||
echo "========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) ============="
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js" "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/" "${BuildDirectory}/syscfg" "${BuildDirectory}/syscfg/clb.dot"
|
||||
;if ${GENERATE_DIAGRAM} == 1 mkdir "${BuildDirectory}/diagrams"
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js" "${C2000WARE_ROOT}" "${BuildDirectory}/diagrams" "${BuildDirectory}/syscfg"
|
||||
"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
|
||||
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
|
||||
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
|
||||
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../sdfm_ex4_pwm_sync_cpuread.c" targetDirectory="" />
|
||||
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="sdfm_ex5_type1_filter_fifo_cpuread"
|
||||
device="TMS320F28388D"
|
||||
cgtVersion="22.6.1.LTS"
|
||||
products="sysconfig;C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
|
||||
postBuildStep="
|
||||
echo "========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) ============="
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js" "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/" "${BuildDirectory}/syscfg" "${BuildDirectory}/syscfg/clb.dot"
|
||||
;if ${GENERATE_DIAGRAM} == 1 mkdir "${BuildDirectory}/diagrams"
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js" "${C2000WARE_ROOT}" "${BuildDirectory}/diagrams" "${BuildDirectory}/syscfg"
|
||||
"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
|
||||
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
|
||||
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
|
||||
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../sdfm_ex5_type1_filter_fifo_cpuread.c" targetDirectory="" />
|
||||
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
<projectSpec>
|
||||
<project
|
||||
name="sdfm_ex6_FIFO_freeze_claread"
|
||||
device="TMS320F28388D"
|
||||
cgtVersion="22.6.1.LTS"
|
||||
products="sysconfig;C2000WARE"
|
||||
outputFormat="ELF"
|
||||
launchWizard="False"
|
||||
linkerCommandFile=""
|
||||
enableSysConfigTool="true"
|
||||
sysConfigBuildOptions="--product ${C2000WARE_ROOT}/.metadata/sdk.json --device F2838x --package 337bga --part F2838x_337bga"
|
||||
postBuildStep="
|
||||
echo "========= Build of the CLB simulation has moved to the CLB Tool. Click the '?' icon by the _Generate CLB Simulation File_ enable for more details (located in the Global Parameters of the Tile Design SysConfig module) ============="
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/dot_file_libraries/clbDotUtility.js" "${C2000WARE_ROOT}/utilities/clb_tool/clb_syscfg/" "${BuildDirectory}/syscfg" "${BuildDirectory}/syscfg/clb.dot"
|
||||
;if ${GENERATE_DIAGRAM} == 1 mkdir "${BuildDirectory}/diagrams"
|
||||
;if ${GENERATE_DIAGRAM} == 1 ${NODE_TOOL} "${C2000WARE_ROOT}/driverlib/.meta/generate_diagrams.js" "${C2000WARE_ROOT}" "${BuildDirectory}/diagrams" "${BuildDirectory}/syscfg"
|
||||
"
|
||||
>
|
||||
<configuration name="CPU1_RAM" compilerBuildOptions= "--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} -I${C2000WARE_COMMON_INCLUDE} -I${C2000WARE_HEADERS_INCLUDE} -v28 -ml -mt --cla_support=cla2 --define=RAM --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=RAM -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
<configuration name="CPU1_FLASH" compilerBuildOptions="--opt_level=off -I${C2000WARE_ROOT} -I${PROJECT_ROOT}/device -I${C2000WARE_DLIB_ROOT} --define=_FLASH -I${C2000WARE_COMMON_INCLUDE} -I${C2000WARE_HEADERS_INCLUDE} -v28 -ml -mt --cla_support=cla2 --float_support=fpu64 --tmu_support=tmu0 --define=DEBUG --define=CPU1 --gen_func_subsections=on --diag_warning=225 --diag_suppress=10063" linkerBuildOptions="--entry_point code_start --stack_size=0x3F8 --heap_size=0x200 --define=_FLASH -i${C2000WARE_ROOT} -i${PROJECT_BUILD_DIR}/syscfg -lc2000ware_libraries.cmd.genlibs " />
|
||||
|
||||
<pathVariable name="C2000WARE_DLIB_ROOT" path="../../../../../../driverlib/f2838x/driverlib/" scope="project" />
|
||||
<pathVariable name="C2000WARE_ROOT" path="../../../../../../" scope="project" />
|
||||
<pathVariable name="CLB_SYSCFG_ROOT" path="../../../../../../utilities/clb_tool/clb_syscfg/" scope="project" />
|
||||
<pathVariable name="SYSTEMC_INSTALL" path="../../../../../../utilities/clb_tool/clb_syscfg/systemc-2.3.3" scope="project" />
|
||||
<pathVariable name="CLB_SIM_COMPILER" path="C:/TDM-GCC-64/bin" scope="project" />
|
||||
<buildVariable name="GENERATE_DIAGRAM" value="0" scope="project" />
|
||||
|
||||
<pathVariable name="C2000WARE_COMMON_INCLUDE" path="../../../../../../device_support/f2838x/common/include/" scope="project" />
|
||||
<pathVariable name="C2000WARE_HEADERS_INCLUDE" path="../../../../../../device_support/f2838x/headers/include/" scope="project" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/driverlib.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/include/device.h" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/device.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/targetConfigs/TMS320F28388D.ccxml" targetDirectory="targetConfigs" />
|
||||
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/headers/cmd/f2838x_headers_nonBIOS_cpu1.cmd" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/headers/source/f2838x_globalvariabledefs.c" targetDirectory="device" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_RAM_SDFM_CLA_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_RAM" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/cmd/2838x_FLASH_SDFM_CLA_lnk_cpu1.cmd" targetDirectory="" applicableConfigurations="CPU1_FLASH" />
|
||||
<file action="copy" path="../../../../../../device_support/f2838x/common/source/f2838x_codestartbranch.asm" targetDirectory="device" />
|
||||
<file action="link" path="../../../../../../driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib" targetDirectory="" />
|
||||
<file action="copy" path="../../../../../../driverlib/f2838x/driverlib/" targetDirectory="device" excludeFromBuild="True" />
|
||||
<file action="copy" path="../sdfm_ex6_FIFO_freeze_claread_cla.cla" targetDirectory="" />
|
||||
<file action="copy" path="../sdfm_ex6_FIFO_freeze_claread.c" targetDirectory="" />
|
||||
<file action="copy" path="../sdfm_claread.h" targetDirectory="" />
|
||||
<file action="copy" path="../../empty_projects/c2000.syscfg" targetDirectory="" />
|
||||
</project>
|
||||
</projectSpec>
|
||||
@@ -0,0 +1,111 @@
|
||||
#ifndef _CLA_SDFM_FILTER_SYNCH_SHARED_H_
|
||||
#define _CLA_SDFM_FILTER_SYNCH_SHARED_H_
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: sdfm_ex2_filter_sync_claread_shared.h
|
||||
//
|
||||
// TITLE: SDFM filter sync CLA
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define MAX_SAMPLES 1024
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
extern int16_t filter1Result[MAX_SAMPLES];
|
||||
extern int16_t filter2Result[MAX_SAMPLES];
|
||||
extern int16_t filter3Result[MAX_SAMPLES];
|
||||
extern int16_t filter4Result[MAX_SAMPLES];
|
||||
|
||||
//
|
||||
// The following are symbols defined in the CLA code
|
||||
// Including them in the shared header file makes them
|
||||
// .global and the main CPU can make use of them.
|
||||
//
|
||||
//
|
||||
|
||||
//
|
||||
// CLA C Tasks
|
||||
//
|
||||
__interrupt void Cla1Task1();
|
||||
__interrupt void Cla1Task2();
|
||||
__interrupt void Cla1Task3();
|
||||
__interrupt void Cla1Task4();
|
||||
__interrupt void Cla1Task5();
|
||||
__interrupt void Cla1Task6();
|
||||
__interrupt void Cla1Task7();
|
||||
__interrupt void Cla1Task8();
|
||||
|
||||
__interrupt void cla1Isr1();
|
||||
__interrupt void cla1Isr2();
|
||||
__interrupt void cla1Isr3();
|
||||
__interrupt void cla1Isr4();
|
||||
__interrupt void cla1Isr5();
|
||||
__interrupt void cla1Isr6();
|
||||
__interrupt void cla1Isr7();
|
||||
__interrupt void cla1Isr8();
|
||||
|
||||
//
|
||||
// Linker command variables
|
||||
//
|
||||
extern uint32_t Cla1funcsLoadEnd;
|
||||
extern uint32_t Cla1funcsLoadStart;
|
||||
extern uint32_t Cla1funcsRunStart;
|
||||
extern uint32_t Cla1funcsLoadSize;
|
||||
extern uint32_t Cla1ConstLoadStart;
|
||||
extern uint32_t Cla1ConstLoadEnd;
|
||||
extern uint32_t Cla1ConstRunStart;
|
||||
extern uint32_t Cla1ConstLoadSize;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif // extern "C"
|
||||
|
||||
#endif //end of _CLA_SDFM_FILTER_SYNCH_SHARED_H_ definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -0,0 +1,586 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: sdfm_ex1_filter_sync_cpuread.c
|
||||
//
|
||||
// TITLE: SDFM Filter sync CPU Example.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> SDFM Filter Sync CPU</h1>
|
||||
//!
|
||||
//! In this example, SDFM filter data is read by CPU in SDFM ISR routine. The
|
||||
//! SDFM configuration is shown below:
|
||||
//! - SDFM used in this example - SDFM1
|
||||
//! - Input control mode selected - MODE0
|
||||
//! - Comparator settings
|
||||
//! - Sinc3 filter selected
|
||||
//! - OSR = 32
|
||||
//! - HLT = 0x7FFF (Higher threshold setting)
|
||||
//! - LLT = 0x0000(Lower threshold setting)
|
||||
//! - Data filter settings
|
||||
//! - All the 4 filter modules enabled
|
||||
//! - Sinc3 filter selected
|
||||
//! - OSR = 128
|
||||
//! - All the 4 filters are synchronized by using MFE
|
||||
//! (Master Filter enable bit)
|
||||
//! - Filter output represented in 16 bit format
|
||||
//! - In order to convert 25 bit Data filter
|
||||
//! into 16 bit format user needs to right shift by 7 bits for
|
||||
//! Sinc3 filter with OSR = 128
|
||||
//! - Interrupt module settings for SDFM filter
|
||||
//! - All the 4 higher threshold comparator interrupts disabled
|
||||
//! - All the 4 lower threshold comparator interrupts disabled
|
||||
//! - All the 4 modulator failure interrupts disabled
|
||||
//! - All the 4 filter will generate interrupt when a new filter data
|
||||
//! is available.
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO16-GPIO31
|
||||
//! - SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO48-GPIO63
|
||||
//! - SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO122-GPIO137
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - \b filter1Result - Output of filter 1
|
||||
//! - \b filter2Result - Output of filter 2
|
||||
//! - \b filter3Result - Output of filter 3
|
||||
//! - \b filter4Result - Output of filter 4
|
||||
//!
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
//
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
#include <stdio.h>
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define MAX_SAMPLES 1024
|
||||
#define SDFM_PIN_MUX_OPTION1 1
|
||||
#define SDFM_PIN_MUX_OPTION2 2
|
||||
#define SDFM_PIN_MUX_OPTION3 3
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint16_t peripheralNumber;
|
||||
int16_t filter1Result[MAX_SAMPLES];
|
||||
int16_t filter2Result[MAX_SAMPLES];
|
||||
int16_t filter3Result[MAX_SAMPLES];
|
||||
int16_t filter4Result[MAX_SAMPLES];
|
||||
#pragma DATA_SECTION(filter1Result, "Filter1_RegsFile");
|
||||
#pragma DATA_SECTION(filter2Result, "Filter2_RegsFile");
|
||||
#pragma DATA_SECTION(filter3Result, "Filter3_RegsFile");
|
||||
#pragma DATA_SECTION(filter4Result, "Filter4_RegsFile");
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define SDFM_FILTER_ENABLE 0x2U
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void configureSDFMPins(uint16_t);
|
||||
void done(void);
|
||||
__interrupt void sdfm1ISR(void);
|
||||
__interrupt void sdfm2ISR(void);
|
||||
void setPinConfig1(void);
|
||||
void setPinConfig2(void);
|
||||
void setPinConfig3(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
uint16_t pinMuxOption;
|
||||
uint16_t hlt, llt;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Interrupts that are used in this example are re-mapped to
|
||||
// ISR functions found within this file.
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
|
||||
Interrupt_register(INT_SDFM1, sdfm1ISR);
|
||||
Interrupt_register(INT_SDFM2, sdfm2ISR);
|
||||
|
||||
//
|
||||
// Enable SDFM1 amd SDFM2 interrupts
|
||||
//
|
||||
Interrupt_enable(INT_SDFM1);
|
||||
Interrupt_enable(INT_SDFM2);
|
||||
|
||||
//
|
||||
// Configure SDFM type to 0 and see if data ack generated SDINT.
|
||||
//
|
||||
SysCtl_configureType(SYSCTL_SDFMTYPE, 0, 1);
|
||||
|
||||
#ifdef CPU1
|
||||
pinMuxOption = SDFM_PIN_MUX_OPTION1;
|
||||
|
||||
//
|
||||
// Configure GPIO pins as SDFM pins
|
||||
//
|
||||
configureSDFMPins(pinMuxOption);
|
||||
#endif
|
||||
|
||||
//
|
||||
// Input Control Unit
|
||||
//
|
||||
// Configure Input Control Unit: Modulator Clock rate = Modulator data rate
|
||||
//
|
||||
SDFM_setupModulatorClock(SDFM1_BASE, SDFM_FILTER_1,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(SDFM1_BASE, SDFM_FILTER_2,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(SDFM1_BASE, SDFM_FILTER_3,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(SDFM1_BASE, SDFM_FILTER_4,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
//
|
||||
// Comparator Unit - over and under value threshold settings
|
||||
//
|
||||
hlt = 0x7FFF;
|
||||
llt = 0x0000;
|
||||
|
||||
//
|
||||
// Configure Comparator Unit's comparator filter type and comparator's
|
||||
// OSR value, higher threshold, lower threshold
|
||||
//
|
||||
SDFM_configComparator(SDFM1_BASE,
|
||||
(SDFM_FILTER_1 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(SDFM1_BASE,
|
||||
(SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(SDFM1_BASE,
|
||||
(SDFM_FILTER_3 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(SDFM1_BASE,
|
||||
(SDFM_FILTER_4 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
|
||||
//
|
||||
// Data Filter Unit
|
||||
//
|
||||
// Configure Data Filter Unit - filter type, OSR value and
|
||||
// enable / disable data filter
|
||||
//
|
||||
SDFM_configDataFilter(SDFM1_BASE, (SDFM_FILTER_1 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(128)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x0007)));
|
||||
|
||||
SDFM_configDataFilter(SDFM1_BASE, (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(128)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x0007)));
|
||||
|
||||
SDFM_configDataFilter(SDFM1_BASE, (SDFM_FILTER_3 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(128)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x0007)));
|
||||
|
||||
SDFM_configDataFilter(SDFM1_BASE, (SDFM_FILTER_4 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(128)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x0007)));
|
||||
|
||||
//
|
||||
// Enable Master filter bit: Unless this bit is set none of the filter modules
|
||||
// can be enabled. All the filter modules are synchronized when master filter
|
||||
// bit is enabled after individual filter modules are enabled.
|
||||
//
|
||||
SDFM_enableMainFilter(SDFM1_BASE);
|
||||
|
||||
//
|
||||
// PWM11.CMPC, PWM11.CMPD, PWM12.CMPC and PWM12.CMPD signals cannot synchronize
|
||||
// the filters. This option is not being used in this example.
|
||||
//
|
||||
SDFM_disableExternalReset(SDFM1_BASE, SDFM_FILTER_1);
|
||||
SDFM_disableExternalReset(SDFM1_BASE, SDFM_FILTER_2);
|
||||
SDFM_disableExternalReset(SDFM1_BASE, SDFM_FILTER_3);
|
||||
SDFM_disableExternalReset(SDFM1_BASE, SDFM_FILTER_4);
|
||||
|
||||
//
|
||||
// Enable interrupts
|
||||
//
|
||||
// Following SDFM interrupts can be enabled / disabled using this function.
|
||||
// Enable / disable comparator high threshold
|
||||
// Enable / disable comparator low threshold
|
||||
// Enable / disable modulator clock failure
|
||||
// Enable / disable data filter acknowledge
|
||||
//
|
||||
SDFM_enableInterrupt(SDFM1_BASE, SDFM_FILTER_1,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(SDFM1_BASE, SDFM_FILTER_2,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(SDFM1_BASE, SDFM_FILTER_3,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(SDFM1_BASE, SDFM_FILTER_4,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(SDFM1_BASE, SDFM_FILTER_1,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(SDFM1_BASE, SDFM_FILTER_2,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(SDFM1_BASE, SDFM_FILTER_3,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(SDFM1_BASE, SDFM_FILTER_4,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
//
|
||||
// Enable master interrupt so that any of the filter interrupts can trigger
|
||||
// by SDFM interrupt to CPU
|
||||
//
|
||||
SDFM_enableMainInterrupt(SDFM1_BASE);
|
||||
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
//
|
||||
// Wait for an interrupt
|
||||
//
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// sdfm1ISR - SDFM 1 ISR
|
||||
//
|
||||
__interrupt void sdfm1ISR(void)
|
||||
{
|
||||
volatile uint32_t sdfmReadFlagRegister = 0;
|
||||
static uint16_t loopCounter1 = 0;
|
||||
|
||||
SDFM_setOutputDataFormat(SDFM1_BASE, SDFM_FILTER_1,
|
||||
SDFM_DATA_FORMAT_16_BIT);
|
||||
|
||||
SDFM_setOutputDataFormat(SDFM1_BASE, SDFM_FILTER_2,
|
||||
SDFM_DATA_FORMAT_16_BIT);
|
||||
|
||||
SDFM_setOutputDataFormat(SDFM1_BASE, SDFM_FILTER_3,
|
||||
SDFM_DATA_FORMAT_16_BIT);
|
||||
|
||||
SDFM_setOutputDataFormat(SDFM1_BASE, SDFM_FILTER_4,
|
||||
SDFM_DATA_FORMAT_16_BIT);
|
||||
|
||||
//
|
||||
// Read SDFM flag register (SDIFLG)
|
||||
//
|
||||
sdfmReadFlagRegister = HWREG(SDFM1_BASE + SDFM_O_SDIFLG);
|
||||
|
||||
if(loopCounter1 < MAX_SAMPLES)
|
||||
{
|
||||
//
|
||||
// Read each SDFM filter output and store it in respective filter
|
||||
// result array
|
||||
//
|
||||
filter1Result[loopCounter1] =
|
||||
(int16_t)(SDFM_getFilterData(SDFM1_BASE, SDFM_FILTER_1) >> 16U);
|
||||
|
||||
filter2Result[loopCounter1] =
|
||||
(int16_t)(SDFM_getFilterData(SDFM1_BASE, SDFM_FILTER_2) >> 16U);
|
||||
|
||||
filter3Result[loopCounter1] =
|
||||
(int16_t)(SDFM_getFilterData(SDFM1_BASE, SDFM_FILTER_3) >> 16U);
|
||||
|
||||
filter4Result[loopCounter1++] =
|
||||
(int16_t)(SDFM_getFilterData(SDFM1_BASE, SDFM_FILTER_4) >> 16U);
|
||||
|
||||
//
|
||||
// Clear SDFM flag register (SDIFLG)
|
||||
//
|
||||
SDFM_clearInterruptFlag(SDFM1_BASE, SDFM_MAIN_INTERRUPT_FLAG |
|
||||
0xFFFF);
|
||||
|
||||
//
|
||||
// Read SDFM flag register (SDIFLG)
|
||||
//
|
||||
sdfmReadFlagRegister = HWREG(SDFM1_BASE + SDFM_O_SDIFLG);
|
||||
}
|
||||
else
|
||||
{
|
||||
ESTOP0;
|
||||
done();
|
||||
}
|
||||
|
||||
//
|
||||
// Acknowledge this __interrupt to receive more __interrupts from group 5
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
|
||||
}
|
||||
|
||||
//
|
||||
// sdfm2ISR - SDFM 2 ISR
|
||||
//
|
||||
__interrupt void sdfm2ISR(void)
|
||||
{
|
||||
uint32_t sdfmReadFlagRegister = 0;
|
||||
static uint16_t loopCounter1 = 0;
|
||||
|
||||
SDFM_setOutputDataFormat(SDFM2_BASE, SDFM_FILTER_1,
|
||||
SDFM_DATA_FORMAT_16_BIT);
|
||||
|
||||
SDFM_setOutputDataFormat(SDFM2_BASE, SDFM_FILTER_2,
|
||||
SDFM_DATA_FORMAT_16_BIT);
|
||||
|
||||
SDFM_setOutputDataFormat(SDFM2_BASE, SDFM_FILTER_3,
|
||||
SDFM_DATA_FORMAT_16_BIT);
|
||||
|
||||
SDFM_setOutputDataFormat(SDFM2_BASE, SDFM_FILTER_4,
|
||||
SDFM_DATA_FORMAT_16_BIT);
|
||||
|
||||
//
|
||||
// Read SDFM flag register (SDIFLG)
|
||||
//
|
||||
sdfmReadFlagRegister = HWREG(SDFM2_BASE + SDFM_O_SDIFLG);
|
||||
|
||||
if(loopCounter1 < MAX_SAMPLES)
|
||||
{
|
||||
//
|
||||
// Read each SDFM filter output and store it in respective filter
|
||||
// result array
|
||||
//
|
||||
filter1Result[loopCounter1] =
|
||||
(int16_t)SDFM_getFilterData(SDFM2_BASE, SDFM_FILTER_1);
|
||||
|
||||
filter2Result[loopCounter1] =
|
||||
(int16_t)SDFM_getFilterData(SDFM2_BASE, SDFM_FILTER_2);
|
||||
|
||||
filter3Result[loopCounter1] =
|
||||
(int16_t)SDFM_getFilterData(SDFM2_BASE, SDFM_FILTER_3);
|
||||
|
||||
filter4Result[loopCounter1++] =
|
||||
(int16_t)SDFM_getFilterData(SDFM2_BASE, SDFM_FILTER_4);
|
||||
|
||||
//
|
||||
// Clear SDFM flag register
|
||||
//
|
||||
SDFM_clearInterruptFlag(SDFM2_BASE,
|
||||
(SDFM_MAIN_INTERRUPT_FLAG | 0xFFFF));
|
||||
|
||||
sdfmReadFlagRegister = HWREG(SDFM2_BASE + SDFM_O_SDIFLG);
|
||||
|
||||
if(sdfmReadFlagRegister != 0x0)
|
||||
{
|
||||
ESTOP0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ESTOP0;
|
||||
done();
|
||||
}
|
||||
|
||||
//
|
||||
// Acknowledge this __interrupt to receive more __interrupts from group 5
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
|
||||
}
|
||||
|
||||
//
|
||||
// configureSDFMPins - Configure SDFM GPIOs
|
||||
//
|
||||
void configureSDFMPins(uint16_t sdfmPinOption)
|
||||
{
|
||||
uint16_t pin;
|
||||
|
||||
switch (sdfmPinOption)
|
||||
{
|
||||
case SDFM_PIN_MUX_OPTION1:
|
||||
for(pin = 16; pin <= 31; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig1();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION2:
|
||||
for(pin = 48; pin <= 63; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig2();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION3:
|
||||
for(pin = 122; pin <= 137; pin++)
|
||||
{
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig3();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// done - Function to halt debugger and stop application
|
||||
//
|
||||
void done(void)
|
||||
{
|
||||
asm(" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig1 - sets the pin configuration for pins 16-21
|
||||
//
|
||||
void setPinConfig1()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_16_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_17_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_18_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_19_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_20_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_21_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_22_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_23_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_24_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_25_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_26_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_27_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_28_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_29_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_30_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_31_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig2 - sets the pin configuration for
|
||||
// pins 48-63
|
||||
//
|
||||
void setPinConfig2()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_48_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_49_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_50_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_51_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_52_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_53_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_54_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_55_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_56_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_57_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_58_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_59_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_60_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_61_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_62_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_63_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig3 - sets the pin configuration for pins 122-137
|
||||
//
|
||||
void setPinConfig3()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_122_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_123_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_124_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_125_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_126_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_127_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_128_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_129_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_130_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_131_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_132_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_133_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_134_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_135_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_136_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_137_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -0,0 +1,665 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: sdfm_ex2_filter_sync_claread.c
|
||||
//
|
||||
// TITLE: SDFM Filter sync CLA Example.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> SDFM Filter Sync CLA</h1>
|
||||
//!
|
||||
//! In this example, SDFM filter data is read by CLA in Cla1Task1. The
|
||||
//! SDFM configuration is shown below:
|
||||
//! - SDFM1 used in this example.For using SDFM2, few modifications
|
||||
//! would be needed in the example.
|
||||
//! - MODE0 Input control mode selected
|
||||
//! - Comparator settings
|
||||
//! - Sinc3 filter selected
|
||||
//! - OSR = 32
|
||||
//! - hlt = 0x7FFF (Higher threshold setting)
|
||||
//! - llt = 0x0000(Lower threshold setting)
|
||||
//! - Data filter settings
|
||||
//! - All the 4 filter modules enabled
|
||||
//! - Sinc3 filter selected
|
||||
//! - OSR = 256
|
||||
//! - All the 4 filters are synchronized by using MFE
|
||||
//! (Master Filter enable bit)
|
||||
//! - Filter output represented in 16 bit format
|
||||
//! - In order to convert 25 bit Data filter
|
||||
//! into 16 bit format user needs to right shift by 10 bits for
|
||||
//! Sinc3 filter with OSR = 256
|
||||
//! - Interrupt module settings for SDFM filter
|
||||
//! - All the 4 higher threshold comparator interrupts disabled
|
||||
//! - All the 4 lower threshold comparator interrupts disabled
|
||||
//! - All the 4 modulator failure interrupts disabled
|
||||
//! - All the 4 filter will generate interrupt when a new filter data
|
||||
//! is available
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO16-GPIO31
|
||||
//! - SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO48-GPIO63
|
||||
//! - SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO122-GPIO137
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - \b filter1Result - Output of filter 1
|
||||
//! - \b filter2Result - Output of filter 2
|
||||
//! - \b filter3Result - Output of filter 3
|
||||
//! - \b filter4Result - Output of filter 4
|
||||
//!
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
#include <stdio.h>
|
||||
#include "sdfm_claread.h"
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define SDFM_PIN_MUX_OPTION1 1
|
||||
#define SDFM_PIN_MUX_OPTION2 2
|
||||
#define SDFM_PIN_MUX_OPTION3 3
|
||||
#define WAITSTEP asm(" RPT #255 || NOP")
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint32_t sdfmInstance;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void configureSDFMPins(uint16_t);
|
||||
void setPinConfig1(void);
|
||||
void setPinConfig2(void);
|
||||
void setPinConfig3(void);
|
||||
void initCLAMemoryMap(void);
|
||||
void initCPU1CLA(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
int main(void)
|
||||
{
|
||||
uint16_t pinMuxOption;
|
||||
uint16_t hlt, llt;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Configure SDFM type to 0 and see if data ack generated SDINT.
|
||||
//
|
||||
SysCtl_configureType(SYSCTL_SDFMTYPE, 0, 1);
|
||||
|
||||
#ifdef CPU1
|
||||
pinMuxOption = SDFM_PIN_MUX_OPTION1;
|
||||
|
||||
//
|
||||
// Configure GPIO pins as SDFM pins
|
||||
//
|
||||
configureSDFMPins(pinMuxOption);
|
||||
#endif
|
||||
|
||||
//
|
||||
// Configure the CLA memory spaces
|
||||
//
|
||||
initCLAMemoryMap();
|
||||
|
||||
//
|
||||
// Configure the CLA task vectors & end-of task interrupts
|
||||
//
|
||||
initCPU1CLA();
|
||||
|
||||
//
|
||||
// Force task 8
|
||||
//
|
||||
CLA_forceTasks(CLA1_BASE,CLA_TASKFLAG_8);
|
||||
WAITSTEP;
|
||||
|
||||
//
|
||||
// Trigger Source for TASK1 of CLA1 = SDFM1
|
||||
//
|
||||
CLA_setTriggerSource(CLA_TASK_1, CLA_TRIGGER_SDFM1INT);
|
||||
|
||||
//
|
||||
// Trigger Source for TASK2 of CLA1 = SDFM2
|
||||
//
|
||||
CLA_setTriggerSource(CLA_TASK_2, CLA_TRIGGER_SDFM2INT);
|
||||
|
||||
//
|
||||
// Configure SDFM1
|
||||
//
|
||||
sdfmInstance = SDFM1_BASE;
|
||||
|
||||
//
|
||||
// Input Control Module
|
||||
//
|
||||
// Configure Input Control Mode: Modulator Clock rate = Modulator data rate
|
||||
//
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_1,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_2,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_3,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_4,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
//
|
||||
// Comparator Module
|
||||
//
|
||||
hlt = 0x7FFF; //Over value threshold settings
|
||||
llt = 0x0000; //Under value threshold settings
|
||||
|
||||
//
|
||||
// Configure Comparator module's comparator filter type and comparator's OSR
|
||||
// value, higher threshold, lower threshold
|
||||
//
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_1 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_3 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_4 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
|
||||
//
|
||||
// Data filter Module
|
||||
//
|
||||
// Configure Data filter modules filter type, OSR value and
|
||||
// enable / disable data filter
|
||||
//
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_1 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_3 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_4 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
//
|
||||
// Enable Master filter bit: Unless this bit is set none of the filter
|
||||
// modules can be enabled. All the filter modules are synchronized when
|
||||
// master filter bit is enabled after individual filter modules are enabled.
|
||||
//
|
||||
SDFM_enableMainFilter(sdfmInstance);
|
||||
|
||||
//
|
||||
// PWM11.CMPC, PWM11.CMPD, PWM12.CMPC and PWM12.CMPD signals can synchronize
|
||||
// the filters. This option is not being used in this example.
|
||||
//
|
||||
SDFM_disableExternalReset(sdfmInstance, SDFM_FILTER_1);
|
||||
SDFM_disableExternalReset(sdfmInstance, SDFM_FILTER_2);
|
||||
SDFM_disableExternalReset(sdfmInstance, SDFM_FILTER_3);
|
||||
SDFM_disableExternalReset(sdfmInstance, SDFM_FILTER_4);
|
||||
|
||||
//
|
||||
// Enable interrupts
|
||||
//
|
||||
// Following SDFM interrupts can be enabled / disabled using this function.
|
||||
// Enable / disable comparator high threshold
|
||||
// Enable / disable comparator low threshold
|
||||
// Enable / disable modulator clock failure
|
||||
// Enable / disable filter acknowledge
|
||||
//
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_1,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_2,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_3,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_4,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_1,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_2,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_3,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_4,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
//
|
||||
// Enable master interrupt so that any of the filter interrupts can
|
||||
// trigger by SDFM interrupt to CPU
|
||||
//
|
||||
SDFM_enableMainInterrupt(sdfmInstance);
|
||||
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// configureSDFMPins - Configure SDFM GPIOs
|
||||
//
|
||||
void configureSDFMPins(uint16_t sdfmPinOption)
|
||||
{
|
||||
uint16_t pin;
|
||||
|
||||
switch (sdfmPinOption)
|
||||
{
|
||||
case SDFM_PIN_MUX_OPTION1:
|
||||
for(pin = 16; pin <= 31; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig1();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION2:
|
||||
for(pin = 48; pin <= 63; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig2();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION3:
|
||||
for(pin = 122; pin <= 137; pin++)
|
||||
{
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig3();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig1 - sets the pin configuration for pins 16-21
|
||||
//
|
||||
void setPinConfig1()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_16_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_17_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_18_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_19_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_20_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_21_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_22_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_23_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_24_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_25_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_26_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_27_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_28_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_29_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_30_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_31_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig2 - sets the pin configuration for
|
||||
// pins 48-63
|
||||
//
|
||||
void setPinConfig2()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_48_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_49_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_50_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_51_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_52_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_53_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_54_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_55_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_56_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_57_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_58_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_59_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_60_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_61_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_62_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_63_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig3 - sets the pin configuration for pins 122-137
|
||||
//
|
||||
void setPinConfig3()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_122_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_123_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_124_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_125_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_126_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_127_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_128_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_129_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_130_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_131_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_132_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_133_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_134_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_135_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_136_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_137_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// initCLAMemoryMap - Initialize Memory map
|
||||
//
|
||||
void initCLAMemoryMap(void)
|
||||
{
|
||||
//
|
||||
// Initialize and wait for CPUToCLA1MsgRAM
|
||||
//
|
||||
MemCfg_initSections(MEMCFG_SECT_MSGCLA1TOCPU);
|
||||
while(MemCfg_getInitStatus(MEMCFG_SECT_MSGCLA1TOCPU) != true);
|
||||
|
||||
//
|
||||
// Copy the program and constants from FLASH to RAM before configuring
|
||||
// the CLA
|
||||
//
|
||||
#if defined(_FLASH)
|
||||
memcpy((uint32_t *)&Cla1funcsRunStart, (uint32_t *)&Cla1funcsLoadStart,
|
||||
(uint32_t)&Cla1funcsLoadSize );
|
||||
memcpy((uint32_t *)&Cla1ConstRunStart, (uint32_t *)&Cla1ConstLoadStart,
|
||||
(uint32_t)&Cla1ConstLoadSize );
|
||||
#endif //defined(_FLASH)
|
||||
|
||||
//
|
||||
// Select LS0 and LS1 RAM to be data RAM for the CLA and LS5 to be
|
||||
// programming space for the CLA as per linker cmd file used in this
|
||||
// example. This configuration should be updated as per the linker cmd file
|
||||
// used in the application.
|
||||
//
|
||||
MemCfg_setCLAMemType(MEMCFG_SECT_LS5, MEMCFG_CLA_MEM_PROGRAM);
|
||||
MemCfg_setCLAMemType(MEMCFG_SECT_LS0, MEMCFG_CLA_MEM_DATA);
|
||||
MemCfg_setCLAMemType(MEMCFG_SECT_LS1, MEMCFG_CLA_MEM_DATA);
|
||||
MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS5, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
|
||||
MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS0, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
|
||||
MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS1, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
|
||||
|
||||
|
||||
//
|
||||
// Initialize and wait for CPUToCLA1MsgRAM
|
||||
//
|
||||
MemCfg_initSections(MEMCFG_SECT_MSGCPUTOCLA1);
|
||||
while(MemCfg_getInitStatus(MEMCFG_SECT_MSGCPUTOCLA1) != true);
|
||||
|
||||
//
|
||||
// Filter1 and Filter2 data memory is mapped to LS6 RAM in linker cmd file
|
||||
// used in this example. This configuration should be updated as per the
|
||||
// linker cmd file used in the application.
|
||||
//
|
||||
MemCfg_setCLAMemType(MEMCFG_SECT_LS6, MEMCFG_CLA_MEM_DATA);
|
||||
MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS6, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
|
||||
|
||||
//
|
||||
// Filter3 and Filter4 data memory is mapped to LS7 RAM in linker cmd file
|
||||
// used in this example. This configuration should be updated as per the
|
||||
// linker cmd file used in the application.
|
||||
//
|
||||
MemCfg_setCLAMemType(MEMCFG_SECT_LS7, MEMCFG_CLA_MEM_DATA);
|
||||
MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS7, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
|
||||
}
|
||||
|
||||
//
|
||||
// initCPU1CLA - Initialize CLA1 task vectors and end of task interrupts
|
||||
//
|
||||
void initCPU1CLA(void)
|
||||
{
|
||||
//
|
||||
// Compute all CLA task vectors
|
||||
// Beyond Type-1 CLAs the MVECT registers accept full 16-bit task addresses
|
||||
// as opposed to offsets used on older Type-0 CLAs
|
||||
//
|
||||
#pragma diag_suppress=770
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_1,(uint16_t)&Cla1Task1);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_2,(uint16_t)&Cla1Task2);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_3,(uint16_t)&Cla1Task3);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_4,(uint16_t)&Cla1Task4);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_5,(uint16_t)&Cla1Task5);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_6,(uint16_t)&Cla1Task6);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_7,(uint16_t)&Cla1Task7);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_8,(uint16_t)&Cla1Task8);
|
||||
#pragma diag_warning=770
|
||||
|
||||
//
|
||||
// Enable IACK instruction to start a task on CLA in software
|
||||
// for all 8 CLA tasks
|
||||
//
|
||||
asm(" RPT #3 || NOP");
|
||||
CLA_enableIACK(CLA1_BASE);
|
||||
CLA_enableTasks(CLA1_BASE, CLA_TASKFLAG_ALL);
|
||||
|
||||
//
|
||||
// Configure the vectors for the end-of-task interrupt for all
|
||||
// 8 tasks
|
||||
//
|
||||
Interrupt_register(INT_CLA1_1, &cla1Isr1);
|
||||
Interrupt_register(INT_CLA1_2, &cla1Isr2);
|
||||
Interrupt_register(INT_CLA1_3, &cla1Isr3);
|
||||
Interrupt_register(INT_CLA1_4, &cla1Isr4);
|
||||
Interrupt_register(INT_CLA1_5, &cla1Isr5);
|
||||
Interrupt_register(INT_CLA1_6, &cla1Isr6);
|
||||
Interrupt_register(INT_CLA1_7, &cla1Isr7);
|
||||
Interrupt_register(INT_CLA1_8, &cla1Isr8);
|
||||
|
||||
//
|
||||
// Enable CLA interrupts at the group and subgroup levels
|
||||
//
|
||||
Interrupt_enable(INT_CLA1_1);
|
||||
Interrupt_enable(INT_CLA1_2);
|
||||
Interrupt_enable(INT_CLA1_3);
|
||||
Interrupt_enable(INT_CLA1_4);
|
||||
Interrupt_enable(INT_CLA1_5);
|
||||
Interrupt_enable(INT_CLA1_6);
|
||||
Interrupt_enable(INT_CLA1_7);
|
||||
Interrupt_enable(INT_CLA1_8);
|
||||
|
||||
EINT; // Enable Global interrupt INTM
|
||||
ERTM; // Enable Global realtime interrupt DBGM
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 1
|
||||
//
|
||||
interrupt void cla1Isr1 ()
|
||||
{
|
||||
//
|
||||
// Acknowledge the end-of-task interrupt for task 1
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11);
|
||||
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 2
|
||||
//
|
||||
interrupt void cla1Isr2 ()
|
||||
{
|
||||
//
|
||||
// Acknowledge the end-of-task interrupt for task 2
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11);
|
||||
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 3
|
||||
//
|
||||
interrupt void cla1Isr3 ()
|
||||
{
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 4
|
||||
//
|
||||
interrupt void cla1Isr4 ()
|
||||
{
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 5
|
||||
//
|
||||
interrupt void cla1Isr5 ()
|
||||
{
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 6
|
||||
//
|
||||
interrupt void cla1Isr6 ()
|
||||
{
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 7
|
||||
//
|
||||
interrupt void cla1Isr7 ()
|
||||
{
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 8
|
||||
//
|
||||
interrupt void cla1Isr8 ()
|
||||
{
|
||||
//
|
||||
// Acknowledge the end-of-task interrupt for task 8
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11);
|
||||
|
||||
// //
|
||||
// // Uncomment to halt debugger and stop here
|
||||
// //
|
||||
// asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -0,0 +1,206 @@
|
||||
//#############################################################################
|
||||
// \file sdfm_ex2_filter_sync_claread_cla.cla
|
||||
//
|
||||
// \brief SDFM filter sync
|
||||
// \author
|
||||
// \date
|
||||
//
|
||||
//
|
||||
// Group: C2000
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include <stdint.h>
|
||||
#include "f2838x_device.h"
|
||||
#include "f2838x_sdfm_drivers.h"
|
||||
#include "sdfm_claread.h"
|
||||
|
||||
//
|
||||
// Whether MDEBUGSTOP needs to be compiled or not
|
||||
//
|
||||
#define CLA_DEBUG 1
|
||||
#define PIEACK_GROUP5 0x0010
|
||||
|
||||
#pragma DATA_SECTION(filter1Result,"Filter1_RegsFile");
|
||||
#pragma DATA_SECTION(filter2Result,"Filter2_RegsFile");
|
||||
#pragma DATA_SECTION(filter3Result,"Filter3_RegsFile");
|
||||
#pragma DATA_SECTION(filter4Result,"Filter4_RegsFile");
|
||||
|
||||
int16_t filter1Result[MAX_SAMPLES];
|
||||
int16_t filter2Result[MAX_SAMPLES];
|
||||
int16_t filter3Result[MAX_SAMPLES];
|
||||
int16_t filter4Result[MAX_SAMPLES];
|
||||
|
||||
int16_t loopCounter1;
|
||||
int16_t loopCounter2;
|
||||
|
||||
//
|
||||
// Task 1
|
||||
//
|
||||
__interrupt void Cla1Task1 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
uint32_t sdfmReadFlagRegister;
|
||||
|
||||
//
|
||||
// Read SDIFLG of SDFM1
|
||||
//
|
||||
sdfmReadFlagRegister = Sdfm1Regs.SDIFLG.all;
|
||||
|
||||
//
|
||||
// Reset the loop counter
|
||||
//
|
||||
if(loopCounter1 >= MAX_SAMPLES)
|
||||
{
|
||||
loopCounter1 = 0;
|
||||
}
|
||||
|
||||
filter1Result[loopCounter1] = SDFM1_READ_FILTER1_DATA_16BIT;
|
||||
filter2Result[loopCounter1] = SDFM1_READ_FILTER2_DATA_16BIT;
|
||||
filter3Result[loopCounter1] = SDFM1_READ_FILTER3_DATA_16BIT;
|
||||
filter4Result[loopCounter1++] = SDFM1_READ_FILTER4_DATA_16BIT;
|
||||
|
||||
//
|
||||
// Clear SDFM1.SDIFLG register
|
||||
//
|
||||
Sdfm1Regs.SDIFLGCLR.all = sdfmReadFlagRegister;
|
||||
}
|
||||
|
||||
//
|
||||
// Task 2
|
||||
//
|
||||
__interrupt void Cla1Task2 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
uint32_t sdfmReadFlagRegister;
|
||||
|
||||
//
|
||||
// Read SDIFLG of SDFM2
|
||||
//
|
||||
sdfmReadFlagRegister = Sdfm2Regs.SDIFLG.all;
|
||||
|
||||
//
|
||||
// Reset the loop counter
|
||||
//
|
||||
if(loopCounter2 >= MAX_SAMPLES)
|
||||
{
|
||||
loopCounter2 = 0;
|
||||
}
|
||||
|
||||
filter1Result[loopCounter2] = SDFM2_READ_FILTER1_DATA_16BIT;
|
||||
filter2Result[loopCounter2] = SDFM2_READ_FILTER2_DATA_16BIT;
|
||||
filter3Result[loopCounter2] = SDFM2_READ_FILTER3_DATA_16BIT;
|
||||
filter4Result[loopCounter2++] = SDFM2_READ_FILTER4_DATA_16BIT;
|
||||
|
||||
//
|
||||
// Clear SDFM2.SDIFLG register
|
||||
//
|
||||
Sdfm2Regs.SDIFLGCLR.all = sdfmReadFlagRegister;
|
||||
}
|
||||
|
||||
//
|
||||
// Task 3
|
||||
//
|
||||
__interrupt void Cla1Task3 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// Task 4
|
||||
//
|
||||
__interrupt void Cla1Task4 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// Task 5
|
||||
//
|
||||
__interrupt void Cla1Task5 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
// Task 6
|
||||
//
|
||||
__interrupt void Cla1Task6 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// Task 7
|
||||
//
|
||||
__interrupt void Cla1Task7 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// Task 8
|
||||
//
|
||||
__interrupt void Cla1Task8 ( void )
|
||||
{
|
||||
loopCounter1 = 0;
|
||||
loopCounter2 = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -0,0 +1,622 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: sdfm_ex3_filter_sync_dmaread.c
|
||||
//
|
||||
// TITLE: SDFM Filter Sync DMA Example.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> SDFM Filter Sync DMA </h1>
|
||||
//!
|
||||
//! In this example, SDFM filter data is read by DMA. The
|
||||
//! SDFM configuration is shown below:
|
||||
//! - SDFM1 used in this example. For using SDFM2, few modifications
|
||||
//! would be needed in the example.
|
||||
//! - MODE0 Input control mode selected
|
||||
//! - Comparator settings
|
||||
//! - Sinc3 filter selected
|
||||
//! - OSR = 32
|
||||
//! - hlt = 0x7FFF (Higher threshold setting)
|
||||
//! - llt = 0x0000(Lower threshold setting)
|
||||
//! - Data filter settings
|
||||
//! - All the 4 filter modules enabled
|
||||
//! - Sinc3 filter selected
|
||||
//! - OSR = 256
|
||||
//! - All the 4 filters are synchronized by using MFE
|
||||
//! (Master Filter enable bit)
|
||||
//! - Filter output represented in 16 bit format
|
||||
//! - In order to convert 25 bit Data filter
|
||||
//! into 16 bit format user needs to right shift by 10 bits for
|
||||
//! Sinc3 filter with OSR = 256
|
||||
//! - Interrupt module settings for SDFM filter
|
||||
//! - All the 4 higher threshold comparator interrupts disabled
|
||||
//! - All the 4 lower threshold comparator interrupts disabled
|
||||
//! - All the 4 modulator failure interrupts disabled
|
||||
//! - All the 4 filter will generate interrupt when a new filter
|
||||
//! data is available
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO16-GPIO31
|
||||
//! - SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO48-GPIO63
|
||||
//! - SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO122-GPIO137
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - \b filter1Result - Output of filter 1
|
||||
//! - \b filter2Result - Output of filter 2
|
||||
//! - \b filter3Result - Output of filter 3
|
||||
//! - \b filter4Result - Output of filter 4
|
||||
//!
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
//
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
#include <stdio.h>
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define MAX_SAMPLES 1024
|
||||
#define SDFM_PIN_MUX_OPTION1 1
|
||||
#define SDFM_PIN_MUX_OPTION2 2
|
||||
#define SDFM_PIN_MUX_OPTION3 3
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint32_t sdfmInstance;
|
||||
int16_t filter1Result[MAX_SAMPLES];
|
||||
int16_t filter2Result[MAX_SAMPLES];
|
||||
int16_t filter3Result[MAX_SAMPLES];
|
||||
int16_t filter4Result[MAX_SAMPLES];
|
||||
#pragma DATA_SECTION(filter1Result, "Filter1_RegsFile");
|
||||
#pragma DATA_SECTION(filter2Result, "Filter2_RegsFile");
|
||||
#pragma DATA_SECTION(filter3Result, "Filter3_RegsFile");
|
||||
#pragma DATA_SECTION(filter4Result, "Filter4_RegsFile");
|
||||
|
||||
// Pointers for DMA source & destination addresses
|
||||
int16_t *dma1SrcAddr, *dma1DestAddr;
|
||||
int16_t *dma2SrcAddr, *dma2DestAddr;
|
||||
int16_t *dma3SrcAddr, *dma3DestAddr;
|
||||
int16_t *dma4SrcAddr, *dma4DestAddr;
|
||||
|
||||
// Variable to update DMA transfer status
|
||||
volatile uint16_t dmaDone = 0;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
__interrupt void dmaCh1ISR(void);
|
||||
__interrupt void dmaCh2ISR(void);
|
||||
__interrupt void dmaCh3ISR(void);
|
||||
__interrupt void dmaCh4ISR(void);
|
||||
void initializeDMA(void);
|
||||
void configureDMAChannels(void);
|
||||
void configureSDFMPins(uint16_t sdfmPinOption);
|
||||
void setPinConfig1(void);
|
||||
void setPinConfig2(void);
|
||||
void setPinConfig3(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
uint16_t pinMuxOption;
|
||||
uint16_t hlt, llt;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Interrupts that are used in this example are re-mapped to
|
||||
// ISR functions found within this file.
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
|
||||
Interrupt_register(INT_DMA_CH1, dmaCh1ISR);
|
||||
Interrupt_register(INT_DMA_CH2, dmaCh2ISR);
|
||||
Interrupt_register(INT_DMA_CH3, dmaCh3ISR);
|
||||
Interrupt_register(INT_DMA_CH4, dmaCh4ISR);
|
||||
|
||||
//
|
||||
// Enable DMA INTn in the PIE: Group 7 __interrupt 1-6
|
||||
//
|
||||
Interrupt_enable(INT_DMA_CH1);
|
||||
Interrupt_enable(INT_DMA_CH2);
|
||||
Interrupt_enable(INT_DMA_CH3);
|
||||
Interrupt_enable(INT_DMA_CH4);
|
||||
|
||||
//
|
||||
// Configure DMA for the transfer
|
||||
//
|
||||
initializeDMA();
|
||||
configureDMAChannels();
|
||||
|
||||
//
|
||||
// Configure SDFM type to 0 and see if data ack generated SDINT.
|
||||
//
|
||||
SysCtl_configureType(SYSCTL_SDFMTYPE, 0, 1);
|
||||
|
||||
#ifdef CPU1
|
||||
pinMuxOption = SDFM_PIN_MUX_OPTION1;
|
||||
|
||||
//
|
||||
// Configure GPIO pins as SDFM pins
|
||||
//
|
||||
configureSDFMPins(pinMuxOption);
|
||||
#endif
|
||||
|
||||
sdfmInstance = SDFM1_BASE;
|
||||
|
||||
//
|
||||
// Input Control Unit
|
||||
//
|
||||
// Configure Input Control Unit: Modulator Clock rate = Modulator data rate
|
||||
//
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_1,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_2,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_3,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_4,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
//
|
||||
// Comparator Module
|
||||
//
|
||||
hlt = 0x7FFF; // Over value threshold settings
|
||||
llt = 0x0000; // Under value threshold settings
|
||||
|
||||
//
|
||||
// Configure Comparator module's comparator filter type and comparator's OSR
|
||||
// value, higher threshold, lower threshold
|
||||
//
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_1 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_3 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_4 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
|
||||
//
|
||||
// Data filter Module
|
||||
//
|
||||
// Configure Data filter modules filter type, OSR value and
|
||||
// enable / disable data filter
|
||||
//
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_1 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_3 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_4 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
//
|
||||
// Enable Master filter bit: Unless this bit is set none of the filter
|
||||
// modules can be enabled. All the filter modules are synchronized when
|
||||
// master filter bit is enabled after individual filter modules are enabled.
|
||||
//
|
||||
SDFM_enableMainFilter(sdfmInstance);
|
||||
|
||||
//
|
||||
// PWM11.CMPC, PWM11.CMPD signals can synchronize SDFM1 filters and
|
||||
// PWM12.CMPC and PWM12.CMPD signals can synchronize SDFM2 filters. This
|
||||
// option is not being used in this example for SDFM1.
|
||||
//
|
||||
SDFM_disableExternalReset(sdfmInstance, SDFM_FILTER_1);
|
||||
SDFM_disableExternalReset(sdfmInstance, SDFM_FILTER_2);
|
||||
SDFM_disableExternalReset(sdfmInstance, SDFM_FILTER_3);
|
||||
SDFM_disableExternalReset(sdfmInstance, SDFM_FILTER_4);
|
||||
|
||||
//
|
||||
// Enable interrupts
|
||||
//
|
||||
// Following SDFM interrupts can be enabled / disabled using this function.
|
||||
// Enable / disable comparator high threshold
|
||||
// Enable / disable comparator low threshold
|
||||
// Enable / disable modulator clock failure
|
||||
// Enable / disable filter acknowledge
|
||||
//
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_1,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_2,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_3,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_4,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_1,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_2,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_3,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_4,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
//
|
||||
// Enable master interrupt so that any of the filter interrupts can trigger
|
||||
// by SDFM interrupt to CPU
|
||||
//
|
||||
SDFM_enableMainInterrupt(sdfmInstance);
|
||||
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// configureSDFMPins - Configure SDFM GPIOs
|
||||
//
|
||||
void configureSDFMPins(uint16_t sdfmPinOption)
|
||||
{
|
||||
uint16_t pin;
|
||||
|
||||
switch (sdfmPinOption)
|
||||
{
|
||||
case SDFM_PIN_MUX_OPTION1:
|
||||
for(pin = 16; pin <= 31; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig1();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION2:
|
||||
for(pin = 48; pin <= 63; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig2();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION3:
|
||||
for(pin = 122; pin <= 137; pin++)
|
||||
{
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig3();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig1 - sets the pin configuration for pins 16-21
|
||||
//
|
||||
void setPinConfig1()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_16_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_17_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_18_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_19_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_20_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_21_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_22_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_23_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_24_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_25_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_26_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_27_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_28_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_29_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_30_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_31_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig2 - sets the pin configuration for
|
||||
// pins 48-63
|
||||
//
|
||||
void setPinConfig2()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_48_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_49_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_50_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_51_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_52_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_53_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_54_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_55_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_56_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_57_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_58_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_59_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_60_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_61_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_62_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_63_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig3 - sets the pin configuration for pins 122-137
|
||||
//
|
||||
void setPinConfig3()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_122_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_123_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_124_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_125_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_126_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_127_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_128_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_129_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_130_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_131_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_132_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_133_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_134_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_135_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_136_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_137_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// dmaCh1ISR - DMA Channel 1 ISR
|
||||
//
|
||||
__interrupt void dmaCh1ISR(void)
|
||||
{
|
||||
dmaDone |= 0x0001;
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
|
||||
ESTOP0;
|
||||
}
|
||||
|
||||
//
|
||||
// dmaCh2ISR - DMA Channel 2 ISR
|
||||
//
|
||||
__interrupt void dmaCh2ISR(void)
|
||||
{
|
||||
dmaDone |= 0x0002;
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
|
||||
ESTOP0;
|
||||
}
|
||||
|
||||
//
|
||||
// dmaCh3ISR - DMA Channel 3 ISR
|
||||
//
|
||||
__interrupt void dmaCh3ISR(void)
|
||||
{
|
||||
dmaDone |= 0x0004;
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
|
||||
ESTOP0;
|
||||
}
|
||||
|
||||
//
|
||||
// dmaCh4ISR - DMA Channel 4 ISR
|
||||
//
|
||||
__interrupt void dmaCh4ISR(void)
|
||||
{
|
||||
dmaDone |= 0x0008;
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP7);
|
||||
ESTOP0;
|
||||
}
|
||||
|
||||
//
|
||||
// initializeDMA - Initialize DMA through hard reset
|
||||
//
|
||||
void initializeDMA(void)
|
||||
{
|
||||
//
|
||||
// Perform a hard reset on DMA
|
||||
//
|
||||
DMA_initController();
|
||||
|
||||
//
|
||||
// Allow DMA to run free on emulation suspend
|
||||
//
|
||||
DMA_setEmulationMode(DMA_EMULATION_FREE_RUN);
|
||||
}
|
||||
|
||||
//
|
||||
// configureDMAChannels - Configure DMA channels 1,2,3, and 4
|
||||
//
|
||||
void configureDMAChannels(void)
|
||||
{
|
||||
//
|
||||
// Initialize the DMA channel addresses
|
||||
//
|
||||
dma1SrcAddr = (int16_t *)(0x5E17);
|
||||
dma1DestAddr = &filter1Result[0];
|
||||
dma2SrcAddr = (int16_t *)(0x5E27);
|
||||
dma2DestAddr = &filter2Result[0];
|
||||
dma3SrcAddr = (int16_t *)(0x5E37);
|
||||
dma3DestAddr = &filter3Result[0];
|
||||
dma4SrcAddr = (int16_t *)(0x5E47);
|
||||
dma4DestAddr = &filter4Result[0];
|
||||
|
||||
DMA_configAddresses(DMA_CH1_BASE, dma1DestAddr, dma1SrcAddr);
|
||||
DMA_configAddresses(DMA_CH2_BASE, dma2DestAddr, dma2SrcAddr);
|
||||
DMA_configAddresses(DMA_CH3_BASE, dma3DestAddr, dma3SrcAddr);
|
||||
DMA_configAddresses(DMA_CH4_BASE, dma4DestAddr, dma4SrcAddr);
|
||||
|
||||
//
|
||||
// Set up to use 16-bit data size
|
||||
// Pointers are based on 16-bit words
|
||||
// Increment by 1 (16 16-bit words)
|
||||
//
|
||||
|
||||
//
|
||||
// BURST size = 1 | Source step size = 0 | Dest step size += 1
|
||||
//
|
||||
DMA_configBurst(DMA_CH1_BASE, 1, 0, 1);
|
||||
DMA_configBurst(DMA_CH2_BASE, 1, 0, 1);
|
||||
DMA_configBurst(DMA_CH3_BASE, 1, 0, 1);
|
||||
DMA_configBurst(DMA_CH4_BASE, 1, 0, 1);
|
||||
|
||||
//
|
||||
// Transfer size = 0x400 | Source step size = 0 | Dest step size += 1
|
||||
//
|
||||
DMA_configTransfer(DMA_CH1_BASE, 0x400, 0, 1);
|
||||
DMA_configTransfer(DMA_CH2_BASE, 0x400, 0, 1);
|
||||
DMA_configTransfer(DMA_CH3_BASE, 0x400, 0, 1);
|
||||
DMA_configTransfer(DMA_CH4_BASE, 0x400, 0, 1);
|
||||
|
||||
//
|
||||
// Configure wrap for DMA channels 1-4
|
||||
//
|
||||
DMA_configWrap(DMA_CH1_BASE, 0xFFFF, 0, 0xFFFF, 0);
|
||||
DMA_configWrap(DMA_CH2_BASE, 0xFFFF, 0, 0xFFFF, 0);
|
||||
DMA_configWrap(DMA_CH3_BASE, 0xFFFF, 0, 0xFFFF, 0);
|
||||
DMA_configWrap(DMA_CH4_BASE, 0xFFFF, 0, 0xFFFF, 0);
|
||||
|
||||
//
|
||||
// Configure mode for DMA channels 1-4
|
||||
//
|
||||
|
||||
// DMA channel 1
|
||||
DMA_configMode(DMA_CH1_BASE, DMA_TRIGGER_SDFM1FLT1,
|
||||
(DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_DISABLE |
|
||||
DMA_CFG_SIZE_16BIT));
|
||||
|
||||
DMA_enableTrigger(DMA_CH1_BASE);
|
||||
DMA_disableOverrunInterrupt(DMA_CH1_BASE);
|
||||
DMA_setInterruptMode(DMA_CH1_BASE, DMA_INT_AT_END);
|
||||
DMA_enableInterrupt(DMA_CH1_BASE);
|
||||
|
||||
// DMA channel 2
|
||||
DMA_configMode(DMA_CH2_BASE, DMA_TRIGGER_SDFM1FLT1,
|
||||
(DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_DISABLE |
|
||||
DMA_CFG_SIZE_16BIT));
|
||||
|
||||
DMA_enableTrigger(DMA_CH2_BASE);
|
||||
DMA_disableOverrunInterrupt(DMA_CH2_BASE);
|
||||
DMA_setInterruptMode(DMA_CH2_BASE, DMA_INT_AT_END);
|
||||
DMA_enableInterrupt(DMA_CH2_BASE);
|
||||
|
||||
// DMA channel 3
|
||||
DMA_configMode(DMA_CH3_BASE, DMA_TRIGGER_SDFM1FLT1,
|
||||
(DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_DISABLE |
|
||||
DMA_CFG_SIZE_16BIT));
|
||||
|
||||
DMA_enableTrigger(DMA_CH3_BASE);
|
||||
DMA_disableOverrunInterrupt(DMA_CH3_BASE);
|
||||
DMA_setInterruptMode(DMA_CH3_BASE, DMA_INT_AT_END);
|
||||
DMA_enableInterrupt(DMA_CH3_BASE);
|
||||
|
||||
// DMA channel 4
|
||||
DMA_configMode(DMA_CH4_BASE, DMA_TRIGGER_SDFM1FLT1,
|
||||
(DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_DISABLE |
|
||||
DMA_CFG_SIZE_16BIT));
|
||||
|
||||
DMA_enableTrigger(DMA_CH4_BASE);
|
||||
DMA_disableOverrunInterrupt(DMA_CH4_BASE);
|
||||
DMA_setInterruptMode(DMA_CH4_BASE, DMA_INT_AT_END);
|
||||
DMA_enableInterrupt(DMA_CH4_BASE);
|
||||
|
||||
//
|
||||
// Start DMA channels
|
||||
//
|
||||
DMA_startChannel(DMA_CH1_BASE);
|
||||
DMA_startChannel(DMA_CH2_BASE);
|
||||
DMA_startChannel(DMA_CH3_BASE);
|
||||
DMA_startChannel(DMA_CH4_BASE);
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -0,0 +1,622 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: sdfm_ex4_pwm_sync_cpuread.c
|
||||
//
|
||||
// TITLE: SDFM PWM Sync Example
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> SDFM PWM Sync </h1>
|
||||
//!
|
||||
//! In this example, SDFM filter data is read by CPU in SDFM ISR routine. The
|
||||
//! SDFM configuration is shown below:
|
||||
//! - SDFM1 is used in this example. For using SDFM2, few modifications
|
||||
//! would be needed in the example.
|
||||
//! - MODE0 Input control mode selected
|
||||
//! - Comparator settings
|
||||
//! - Sinc3 filter selected
|
||||
//! - OSR = 32
|
||||
//! - hlt = 0x7FFF (Higher threshold setting)
|
||||
//! - llt = 0x0000(Lower threshold setting)
|
||||
//! - Data filter settings
|
||||
//! - All the 4 filter modules enabled
|
||||
//! - Sinc3 filter selected
|
||||
//! - OSR = 256
|
||||
//! - All the 4 filters are synchronized by using PWM
|
||||
//! (Master Filter enable bit)
|
||||
//! - Filter output represented in 16 bit format
|
||||
//! - In order to convert 25 bit Data filter
|
||||
//! into 16 bit format user needs to right shift by 10 bits for
|
||||
//! Sinc3 filter with OSR = 256
|
||||
//! - Interrupt module settings for SDFM filter
|
||||
//! - All the 4 higher threshold comparator interrupts disabled
|
||||
//! - All the 4 lower threshold comparator interrupts disabled
|
||||
//! - All the 4 modulator failure interrupts disabled
|
||||
//! - All the 4 filter will generate interrupt when a new filter data
|
||||
//! is available
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO16-GPIO31
|
||||
//! - SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO48-GPIO63
|
||||
//! - SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO122-GPIO137
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - \b filter1Result - Output of filter 1
|
||||
//! - \b filter2Result - Output of filter 2
|
||||
//! - \b filter3Result - Output of filter 3
|
||||
//! - \b filter4Result - Output of filter 4
|
||||
//!
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
//
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
#include <stdio.h>
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define MAX_SAMPLES 1024
|
||||
#define SDFM_PIN_MUX_OPTION1 1
|
||||
#define SDFM_PIN_MUX_OPTION2 2
|
||||
#define SDFM_PIN_MUX_OPTION3 3
|
||||
#define EPWM_TIMER_TBPRD 65535 // ePWM Period register
|
||||
#define SDFM_INT_MASK 0x8000F000U
|
||||
|
||||
//
|
||||
// Macro to read the SDFM filter data in 16-bit format
|
||||
//
|
||||
#define READ_16BIT_FILTER_DATA(base, offset) \
|
||||
(*((volatile int16_t *)(base + offset + 1)))
|
||||
|
||||
#define READ_32BIT_FILTER_DATA(base, offset) \
|
||||
(*((volatile int32_t *)(base + offset)))
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint32_t sdfmInstance;
|
||||
uint32_t pwmInstance = EPWM11_BASE; // ePWM 11 for synchronizing SDFM1 filters
|
||||
int16_t filter1Result[MAX_SAMPLES];
|
||||
int16_t filter2Result[MAX_SAMPLES];
|
||||
int16_t filter3Result[MAX_SAMPLES];
|
||||
int16_t filter4Result[MAX_SAMPLES];
|
||||
#pragma DATA_SECTION(filter1Result, "Filter1_RegsFile");
|
||||
#pragma DATA_SECTION(filter2Result, "Filter2_RegsFile");
|
||||
#pragma DATA_SECTION(filter3Result, "Filter3_RegsFile");
|
||||
#pragma DATA_SECTION(filter4Result, "Filter4_RegsFile");
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void configureSDFMPins(uint16_t sdfmPinOption);
|
||||
void setPinConfig1(void);
|
||||
void setPinConfig2(void);
|
||||
void setPinConfig3(void);
|
||||
void initEPWM(uint32_t epwmInstance);
|
||||
__interrupt void sdfm1ISR(void);
|
||||
__interrupt void sdfm2ISR(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
uint16_t pinMuxOption;
|
||||
uint16_t hlt, llt;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Interrupts that are used in this example are re-mapped to
|
||||
// ISR functions found within this file.
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
|
||||
Interrupt_register(INT_SDFM1, sdfm1ISR);
|
||||
Interrupt_register(INT_SDFM2, sdfm2ISR);
|
||||
|
||||
//
|
||||
// Enable SDFM1 amd SDFM2 interrupts
|
||||
//
|
||||
Interrupt_enable(INT_SDFM1);
|
||||
Interrupt_enable(INT_SDFM2);
|
||||
|
||||
//
|
||||
// Configure SDFM type to 0 and see if data ack generated SDINT.
|
||||
//
|
||||
SysCtl_configureType(SYSCTL_SDFMTYPE, 0, 1);
|
||||
|
||||
#ifdef CPU1
|
||||
pinMuxOption = SDFM_PIN_MUX_OPTION1;
|
||||
|
||||
//
|
||||
// Configure GPIO pins as SDFM pins
|
||||
//
|
||||
configureSDFMPins(pinMuxOption);
|
||||
#endif
|
||||
|
||||
//
|
||||
// Select SDFM1
|
||||
//
|
||||
sdfmInstance = SDFM1_BASE;
|
||||
|
||||
//
|
||||
// Input Control Module:
|
||||
// Configure Modulator Clock rate = Modulator data rate
|
||||
//
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_1,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_2,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_3,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_4,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
//
|
||||
// Comparator Module
|
||||
//
|
||||
hlt = 0x7FFF; //Over value threshold settings
|
||||
llt = 0x0000; //Under value threshold settings
|
||||
|
||||
//
|
||||
// Configure Comparator module's comparator filter type and comparator's OSR
|
||||
// value, higher threshold, lower threshold
|
||||
//
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_1 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_3 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_4 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_GET_LOW_THRESHOLD(llt) | SDFM_GET_HIGH_THRESHOLD(hlt)), 0);
|
||||
|
||||
//
|
||||
// Data filter Module
|
||||
//
|
||||
// Configure Data filter modules filter type, OSR value and
|
||||
// enable / disable data filter
|
||||
//
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_1 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_3 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_4 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
//
|
||||
// Enable Master filter bit: Unless this bit is set none of the filter modules
|
||||
// can be enabled. All the filter modules are synchronized when master filter
|
||||
// bit is enabled after individual filter modules are enabled.
|
||||
//
|
||||
SDFM_enableMainFilter(sdfmInstance);
|
||||
|
||||
|
||||
//
|
||||
// PWM11.CMPC, PWM11.CMPD signals can synchronize SDFM1 filters and
|
||||
// PWM12.CMPC and PWM12.CMPD signals can synchronize SDFM2 filters. This
|
||||
// option is being used in this example for SDFM1.
|
||||
//
|
||||
SDFM_enableExternalReset(sdfmInstance, SDFM_FILTER_1);
|
||||
SDFM_enableExternalReset(sdfmInstance, SDFM_FILTER_2);
|
||||
SDFM_enableExternalReset(sdfmInstance, SDFM_FILTER_3);
|
||||
SDFM_enableExternalReset(sdfmInstance, SDFM_FILTER_4);
|
||||
|
||||
//
|
||||
// Init EPWMs
|
||||
//
|
||||
initEPWM(pwmInstance);
|
||||
|
||||
//
|
||||
// Enable interrupts
|
||||
//
|
||||
// Following SDFM interrupts can be enabled / disabled using this function.
|
||||
// Enable / disable comparator high threshold
|
||||
// Enable / disable comparator low threshold
|
||||
// Enable / disable modulator clock failure
|
||||
// Enable / disable filter acknowledge
|
||||
//
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_1,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_2,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_3,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_4,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_1,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_2,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_3,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
SDFM_disableInterrupt(sdfmInstance, SDFM_FILTER_4,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
while((HWREGH(pwmInstance + EPWM_O_TBCTR)) < 550);
|
||||
|
||||
//
|
||||
// Enable master interrupt so that any of the filter interrupts can trigger
|
||||
// by SDFM interrupt to CPU
|
||||
//
|
||||
SDFM_enableMainInterrupt(sdfmInstance);
|
||||
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// sdfm1ISR - SDFM 1 ISR
|
||||
//
|
||||
__interrupt void sdfm1ISR(void)
|
||||
{
|
||||
static uint16_t loopCounter1 = 0;
|
||||
|
||||
//
|
||||
// Wait for result from all the filters (SDIFLG)
|
||||
//
|
||||
while(HWREG(SDFM1_BASE + SDFM_O_SDIFLG) & SDFM_INT_MASK != SDFM_INT_MASK);
|
||||
|
||||
//
|
||||
// Reset the loop counter
|
||||
//
|
||||
if(loopCounter1 >= MAX_SAMPLES)
|
||||
{
|
||||
loopCounter1 = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// Read each SDFM filter output and store it in respective filter
|
||||
// result array
|
||||
//
|
||||
filter1Result[loopCounter1] =
|
||||
READ_16BIT_FILTER_DATA(SDFM1_BASE, SDFM_O_SDDATA1);
|
||||
filter2Result[loopCounter1] =
|
||||
READ_16BIT_FILTER_DATA(SDFM1_BASE, SDFM_O_SDDATA2);
|
||||
filter3Result[loopCounter1] =
|
||||
READ_16BIT_FILTER_DATA(SDFM1_BASE, SDFM_O_SDDATA3);
|
||||
filter4Result[loopCounter1++] =
|
||||
READ_16BIT_FILTER_DATA(SDFM1_BASE, SDFM_O_SDDATA4);
|
||||
|
||||
//
|
||||
// Clear SDFM flag register
|
||||
//
|
||||
SDFM_clearInterruptFlag(SDFM1_BASE, SDFM_INT_MASK);
|
||||
|
||||
//
|
||||
// Acknowledge this __interrupt to receive more __interrupts from group 5
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
|
||||
}
|
||||
|
||||
//
|
||||
// sdfm2ISR - SDFM 2 ISR
|
||||
//
|
||||
__interrupt void sdfm2ISR(void)
|
||||
{
|
||||
static uint16_t loopCounter2 = 0;
|
||||
|
||||
//
|
||||
// Wait for result from all the filters (SDIFLG)
|
||||
//
|
||||
while(HWREG(SDFM2_BASE + SDFM_O_SDIFLG) & SDFM_INT_MASK != SDFM_INT_MASK);
|
||||
|
||||
//
|
||||
// Reset the loop counter
|
||||
//
|
||||
if(loopCounter2 >= MAX_SAMPLES)
|
||||
{
|
||||
loopCounter2 = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// Read each SDFM filter output and store it in respective filter
|
||||
// result array
|
||||
//
|
||||
filter1Result[loopCounter2] =
|
||||
READ_16BIT_FILTER_DATA(SDFM2_BASE, SDFM_O_SDDATA1);
|
||||
filter2Result[loopCounter2] =
|
||||
READ_16BIT_FILTER_DATA(SDFM2_BASE, SDFM_O_SDDATA1);
|
||||
filter3Result[loopCounter2] =
|
||||
READ_16BIT_FILTER_DATA(SDFM2_BASE, SDFM_O_SDDATA1);
|
||||
filter4Result[loopCounter2++] =
|
||||
READ_16BIT_FILTER_DATA(SDFM2_BASE, SDFM_O_SDDATA1);
|
||||
|
||||
//
|
||||
// Clear SDFM flag register
|
||||
//
|
||||
SDFM_clearInterruptFlag(SDFM2_BASE, SDFM_INT_MASK);
|
||||
|
||||
//
|
||||
// Acknowledge this __interrupt to receive more __interrupts from group 5
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
|
||||
}
|
||||
|
||||
//
|
||||
// configureSDFMPins - Configure SDFM GPIOs
|
||||
//
|
||||
void configureSDFMPins(uint16_t sdfmPinOption)
|
||||
{
|
||||
uint16_t pin;
|
||||
|
||||
switch (sdfmPinOption)
|
||||
{
|
||||
case SDFM_PIN_MUX_OPTION1:
|
||||
for(pin = 16; pin <= 31; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig1();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION2:
|
||||
for(pin = 48; pin <= 63; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig2();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION3:
|
||||
for(pin = 122; pin <= 137; pin++)
|
||||
{
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig3();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// done - Function to halt debugger and stop application
|
||||
//
|
||||
void done(void)
|
||||
{
|
||||
asm(" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig1 - sets the pin configuration for pins 16-21
|
||||
//
|
||||
void setPinConfig1()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_16_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_17_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_18_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_19_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_20_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_21_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_22_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_23_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_24_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_25_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_26_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_27_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_28_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_29_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_30_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_31_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig2 - sets the pin configuration for
|
||||
// pins 48-63
|
||||
//
|
||||
void setPinConfig2()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_48_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_49_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_50_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_51_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_52_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_53_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_54_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_55_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_56_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_57_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_58_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_59_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_60_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_61_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_62_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_63_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig3 - sets the pin configuration for pins 122-137
|
||||
//
|
||||
void setPinConfig3()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_122_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_123_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_124_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_125_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_126_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_127_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_128_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_129_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_130_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_131_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_132_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_133_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_134_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_135_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_136_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_137_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// initEPWM - Initialize specified EPWM settings
|
||||
//
|
||||
void initEPWM(uint32_t epwmInstance)
|
||||
{
|
||||
uint16_t compCVal,compDVal;
|
||||
|
||||
compCVal = 200;
|
||||
compDVal = 200;
|
||||
|
||||
#ifdef CPU1
|
||||
GPIO_setDirectionMode(4, GPIO_DIR_MODE_OUT);
|
||||
GPIO_setPinConfig(GPIO_4_GPIO4);
|
||||
#endif
|
||||
|
||||
//
|
||||
// Disable sync(Freeze clock to PWM as well)
|
||||
//
|
||||
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
|
||||
|
||||
//
|
||||
// Setup TBCLK: Configure timer period = 801 TBCLKs, phase = 0 &
|
||||
// clear counter
|
||||
//
|
||||
EPWM_setTimeBasePeriod(epwmInstance, EPWM_TIMER_TBPRD);
|
||||
EPWM_setPhaseShift(epwmInstance, 0U);
|
||||
EPWM_setTimeBaseCounter(epwmInstance, 0U);
|
||||
|
||||
//
|
||||
// Set CMPA, CMPB, CMPC & CMPD values
|
||||
//
|
||||
EPWM_setCounterCompareValue(epwmInstance, EPWM_COUNTER_COMPARE_C, compCVal);
|
||||
EPWM_setCounterCompareValue(epwmInstance, EPWM_COUNTER_COMPARE_D, compDVal);
|
||||
EPWM_setCounterCompareValue(epwmInstance, EPWM_COUNTER_COMPARE_A, compCVal);
|
||||
EPWM_setCounterCompareValue(epwmInstance, EPWM_COUNTER_COMPARE_B, compDVal);
|
||||
|
||||
//
|
||||
// Setup counter mode
|
||||
//
|
||||
EPWM_setTimeBaseCounterMode(epwmInstance, EPWM_COUNTER_MODE_UP);
|
||||
EPWM_setClockPrescaler(epwmInstance,
|
||||
EPWM_CLOCK_DIVIDER_1,
|
||||
EPWM_HSCLOCK_DIVIDER_1);
|
||||
|
||||
//
|
||||
// Set actions:
|
||||
// Toggle PWMxA on event A, up-count
|
||||
// Toggle PWMxB on event A, up-count
|
||||
//
|
||||
EPWM_setActionQualifierAction(EPWM1_BASE,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_TOGGLE,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
|
||||
EPWM_setActionQualifierAction(EPWM1_BASE,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_TOGGLE,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
|
||||
|
||||
//
|
||||
// Enable sync and clock to PWM
|
||||
//
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -0,0 +1,454 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: sdfm_ex5_type1_filter_fifo_cpuread.c
|
||||
//
|
||||
// TITLE: SDFM Type 1 Filter FIFO Example.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> SDFM Type 1 Filter FIFO </h1>
|
||||
//!
|
||||
//! This example configures SDFM1 filter in type 1 to demonstrate data read
|
||||
//! through CPU in FIFO & non-FIFO mode. Data filter is configured in mode 0
|
||||
//! to select SINC3 filter with OSR of 256. Filter output is configured
|
||||
//! for 16-bit format and data shift of 10 is used.
|
||||
//!
|
||||
//! This example demonstrates the FIFO usage if enabled. FIFO length is set
|
||||
//! at 16 and data ready interrupt is configured to be triggered when FIFO is
|
||||
//! full. In this example, SDFM filter data is read by CPU in SDFM Data Ready
|
||||
//! ISR routine.
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams(SD1-D1, SD1-C1) to
|
||||
//! (GPIO16, GPIO17)
|
||||
//! - SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams(SD1-D1, SD1-C1) to
|
||||
//! (GPIO48, GPIO49)
|
||||
//! - SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams(SD1-D1, SD1-C1) to
|
||||
//! (GPIO122, GPIO123)
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - \b filter1Result - Output of filter 1
|
||||
//!
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
//
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
#include <stdio.h>
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define MAX_SAMPLES 1024
|
||||
#define FIFO_INT_NUM 16U
|
||||
#define SDFM_FILTER_ENABLE 0x2U
|
||||
|
||||
//
|
||||
// Macro to enable FIFO mode. Make it zero to disable
|
||||
// FIFO mode.
|
||||
//
|
||||
#define ENABLE_FIFO 1
|
||||
|
||||
//
|
||||
// Macro for pin-mux options
|
||||
//
|
||||
#define SDFM_PIN_MUX_OPTION1 1
|
||||
#define SDFM_PIN_MUX_OPTION2 2
|
||||
#define SDFM_PIN_MUX_OPTION3 3
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
int16_t filter1Result[MAX_SAMPLES];
|
||||
#pragma DATA_SECTION(filter1Result, "Filter1_RegsFile");
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void configureSDFMPins(uint16_t);
|
||||
void setPinConfig1(void);
|
||||
void setPinConfig2(void);
|
||||
void setPinConfig3(void);
|
||||
void done(void);
|
||||
|
||||
//
|
||||
// ISRs
|
||||
//
|
||||
__interrupt void sdfmFIFO1ISR(void);
|
||||
__interrupt void sdfm1ErrorISR(void);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
void main(void)
|
||||
{
|
||||
uint16_t pinMuxOption;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Interrupts that are used in this example are re-mapped to
|
||||
// ISR functions found within this file.
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
|
||||
Interrupt_register(INT_SDFM1DR1, sdfmFIFO1ISR);
|
||||
Interrupt_register(INT_SDFM1, sdfm1ErrorISR);
|
||||
|
||||
//
|
||||
// Enable SDFM1 interrupts(Data Ready & Error interrupts)
|
||||
//
|
||||
Interrupt_enableGlobal();
|
||||
Interrupt_enable(INT_SDFM1DR1);
|
||||
Interrupt_enable(INT_SDFM1);
|
||||
|
||||
//
|
||||
// Configure SDFM type to 1.
|
||||
//
|
||||
SysCtl_configureType(SYSCTL_SDFMTYPE, 1, 1);
|
||||
|
||||
#ifdef CPU1
|
||||
pinMuxOption = SDFM_PIN_MUX_OPTION1;
|
||||
|
||||
//
|
||||
// Configure GPIO pins as SDFM pins
|
||||
//
|
||||
configureSDFMPins(pinMuxOption);
|
||||
#endif
|
||||
|
||||
//
|
||||
// Input Control Unit
|
||||
//
|
||||
// Configure Input Control Unit: Modulator Clock rate = Modulator data rate
|
||||
//
|
||||
SDFM_setupModulatorClock(SDFM1_BASE, SDFM_FILTER_1,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
//
|
||||
// Data Filter Unit
|
||||
//
|
||||
|
||||
// Configure Data Filter Unit - filter type, OSR value and
|
||||
// enable / disable data filter
|
||||
//
|
||||
SDFM_configDataFilter(SDFM1_BASE, (SDFM_FILTER_1 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
#if (ENABLE_FIFO)
|
||||
//
|
||||
// Set data ready interrupt source as fifo interrupt
|
||||
//
|
||||
SDFM_setDataReadyInterruptSource(SDFM1_BASE, SDFM_FILTER_1,
|
||||
SDFM_DATA_READY_SOURCE_FIFO);
|
||||
|
||||
//
|
||||
// Enable FIFO and set the FIFO interrupt level
|
||||
//
|
||||
SDFM_enableFIFOBuffer(SDFM1_BASE, SDFM_FILTER_1);
|
||||
|
||||
SDFM_setFIFOInterruptLevel(SDFM1_BASE, SDFM_FILTER_1, FIFO_INT_NUM);
|
||||
|
||||
SDFM_enableInterrupt(SDFM1_BASE, SDFM_FILTER_1,
|
||||
(SDFM_FIFO_INTERRUPT | SDFM_FIFO_OVERFLOW_INTERRUPT));
|
||||
#else
|
||||
//
|
||||
// Set data ready interrupt source as fifo interrupt
|
||||
//
|
||||
SDFM_setDataReadyInterruptSource(SDFM1_BASE, SDFM_FILTER_1,
|
||||
SDFM_DATA_READY_SOURCE_DIRECT);
|
||||
|
||||
SDFM_enableInterrupt(SDFM1_BASE, SDFM_FILTER_1,
|
||||
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT);
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// Enable Master filter bit: Unless this bit is set none of the filter
|
||||
// modules can be enabled. All the filter modules are synchronized when
|
||||
// master filter bit is enabled after individual filter modules are enabled.
|
||||
//
|
||||
SDFM_enableMainFilter(SDFM1_BASE);
|
||||
|
||||
//
|
||||
// PWM11.CMPC, PWM11.CMPD, PWM12.CMPC and PWM12.CMPD signals cannot
|
||||
// synchronize the filters. This option is not being used in this example.
|
||||
//
|
||||
SDFM_disableExternalReset(SDFM1_BASE, SDFM_FILTER_1);
|
||||
|
||||
//
|
||||
// Enable modulator failure interrupt, disable threshold interrupts
|
||||
//
|
||||
SDFM_enableInterrupt(SDFM1_BASE, SDFM_FILTER_1,
|
||||
SDFM_MODULATOR_FAILURE_INTERRUPT);
|
||||
|
||||
SDFM_disableInterrupt(SDFM1_BASE, SDFM_FILTER_1,
|
||||
(SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
|
||||
SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
|
||||
|
||||
//
|
||||
// Enable master interrupt so that any of the filter interrupts can trigger
|
||||
// by SDFM interrupt to CPU
|
||||
//
|
||||
SDFM_enableMainInterrupt(SDFM1_BASE);
|
||||
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
//
|
||||
// Wait for an interrupt
|
||||
//
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// sdfm1ErrorISR - SDFM1 Error ISR
|
||||
//
|
||||
__interrupt void sdfm1ErrorISR(void)
|
||||
{
|
||||
//
|
||||
// Clear SDFM flag register (SDIFLG)
|
||||
//
|
||||
SDFM_clearInterruptFlag(SDFM1_BASE, SDFM_MAIN_INTERRUPT_FLAG |
|
||||
0xFFFF);
|
||||
|
||||
//
|
||||
// Acknowledge this interrupt to receive more interrupts from group 5
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// sdfmFIFO1ISR - SDFM FIFO1 ISR
|
||||
//
|
||||
__interrupt void sdfmFIFO1ISR(void)
|
||||
{
|
||||
uint16_t i;
|
||||
static uint16_t loopCounter1 = 0;
|
||||
|
||||
SDFM_setOutputDataFormat(SDFM1_BASE, SDFM_FILTER_1,
|
||||
SDFM_DATA_FORMAT_16_BIT);
|
||||
|
||||
//
|
||||
// Read SDFM flag register (SDIFLG)
|
||||
//
|
||||
if(loopCounter1 >= MAX_SAMPLES)
|
||||
{
|
||||
ESTOP0;
|
||||
}
|
||||
else if(SDFM_getFIFOISRStatus(SDFM1_BASE, SDFM_FILTER_1) == 0x1U)
|
||||
{
|
||||
for(i = 0; i < FIFO_INT_NUM; i++)
|
||||
{
|
||||
filter1Result[loopCounter1++] =
|
||||
(int16_t)(SDFM_getFIFOData(SDFM1_BASE,
|
||||
SDFM_FILTER_1) >> 16U);
|
||||
}
|
||||
|
||||
}
|
||||
else if(SDFM_getNewFilterDataStatus(SDFM1_BASE, SDFM_FILTER_1) == 0x1U)
|
||||
{
|
||||
filter1Result[loopCounter1++] =
|
||||
(int16_t)(SDFM_getFilterData(SDFM1_BASE, SDFM_FILTER_1) >> 16U);
|
||||
}
|
||||
|
||||
//
|
||||
// Clear SDFM flag register (SDIFLG)
|
||||
//
|
||||
SDFM_clearInterruptFlag(SDFM1_BASE, SDFM_MAIN_INTERRUPT_FLAG |
|
||||
SDFM_FILTER_1_FIFO_INTERRUPT_FLAG |
|
||||
SDFM_FILTER_1_NEW_DATA_FLAG |
|
||||
SDFM_FILTER_1_FIFO_OVERFLOW_FLAG);
|
||||
|
||||
//
|
||||
// Acknowledge this interrupt to receive more interrupts from group 5
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);
|
||||
}
|
||||
|
||||
//
|
||||
// configureSDFMPins - Configure SDFM GPIOs
|
||||
//
|
||||
void configureSDFMPins(uint16_t sdfmPinOption)
|
||||
{
|
||||
uint16_t pin;
|
||||
|
||||
switch (sdfmPinOption)
|
||||
{
|
||||
case SDFM_PIN_MUX_OPTION1:
|
||||
for(pin = 16; pin <= 31; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig1();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION2:
|
||||
for(pin = 48; pin <= 63; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig2();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION3:
|
||||
for(pin = 122; pin <= 137; pin++)
|
||||
{
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig3();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// done - Function to halt debugger and stop application
|
||||
//
|
||||
void done(void)
|
||||
{
|
||||
asm(" ESTOP0");
|
||||
for(;;);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig1 - sets the pin configuration for pins 16-21
|
||||
//
|
||||
void setPinConfig1()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_16_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_17_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_18_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_19_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_20_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_21_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_22_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_23_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_24_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_25_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_26_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_27_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_28_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_29_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_30_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_31_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig2 - sets the pin configuration for
|
||||
// pins 48-63
|
||||
//
|
||||
void setPinConfig2()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_48_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_49_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_50_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_51_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_52_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_53_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_54_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_55_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_56_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_57_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_58_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_59_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_60_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_61_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_62_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_63_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig3 - sets the pin configuration for pins 122-137
|
||||
//
|
||||
void setPinConfig3()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_122_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_123_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_124_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_125_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_126_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_127_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_128_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_129_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_130_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_131_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_132_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_133_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_134_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_135_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_136_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_137_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -0,0 +1,911 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: sdfm_ex6_FIFO_freeze_claread.c
|
||||
//
|
||||
// TITLE: SDFM Filter sync with FIFO Freeze CLA Example.
|
||||
//
|
||||
//! \addtogroup driver_example_list
|
||||
//! <h1> SDFM Filter Sync CLA</h1>
|
||||
//!
|
||||
//! In this example, SDFM FIFO will not be filled until a SDSYNC event.
|
||||
//! On a SDSYNC event, SDFM data filter output will start filling FIFO
|
||||
//! and stop filling after programmable number 'N' of FIFO is filled.
|
||||
//!
|
||||
//! SDy-C1 (Filter1 channel clock) is internally configured to connected
|
||||
//! SDy-C2 / SDy-C3 / SDy-C4
|
||||
//! SDFM configuration is shown below:
|
||||
//! - SDFM1 used in this example.For using SDFM2, few modifications
|
||||
//! would be needed in the example.
|
||||
//! - MODE0 Input control mode selected
|
||||
//! - Comparator settings
|
||||
//! - Sinc3 filter selected
|
||||
//! - OSR = 32
|
||||
//! - hlt = 0x7FFF (Higher threshold setting)
|
||||
//! - llt = 0x0000(Lower threshold setting)
|
||||
//! - Data filter settings
|
||||
//! - All the 4 filter modules enabled
|
||||
//! - Sinc3 filter selected
|
||||
//! - OSR = 256
|
||||
//! - All the 4 filters are synchronized by using MFE
|
||||
//! (Master Filter enable bit)
|
||||
//! - Filter output represented in 16 bit format
|
||||
//! - In order to convert 25 bit Data filter
|
||||
//! into 16 bit format user needs to right shift by 10 bits for
|
||||
//! Sinc3 filter with OSR = 256
|
||||
//! - Interrupt module settings for SDFM filter
|
||||
//! - All the 4 higher threshold comparator interrupts disabled
|
||||
//! - All the 4 lower threshold comparator interrupts disabled
|
||||
//! - All the 4 modulator failure interrupts disabled
|
||||
//! - All the 4 filter will generate interrupt when a new filter data
|
||||
//! is available
|
||||
//!
|
||||
//! \b External \b Connections \n
|
||||
//! - SDFM_PIN_MUX_OPTION1 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO16-GPIO31
|
||||
//! - SDFM_PIN_MUX_OPTION2 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO48-GPIO63
|
||||
//! - SDFM_PIN_MUX_OPTION3 Connect Sigma-Delta streams to
|
||||
//! (SDx-D1, SDx-C1 to SDx-D4,SDx-C4) on GPIO122-GPIO137
|
||||
//!
|
||||
//! \b Watch \b Variables \n
|
||||
//! - \b filter1Result - Output of filter 1
|
||||
//! - \b filter2Result - Output of filter 2
|
||||
//! - \b filter3Result - Output of filter 3
|
||||
//! - \b filter4Result - Output of filter 4
|
||||
//!
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
#include "device.h"
|
||||
#include <stdio.h>
|
||||
#include "sdfm_claread.h"
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define SDFM_PIN_MUX_OPTION1 1
|
||||
#define SDFM_PIN_MUX_OPTION2 2
|
||||
#define SDFM_PIN_MUX_OPTION3 3
|
||||
#define WAITSTEP asm(" RPT #255 || NOP")
|
||||
|
||||
#define OSCLK_INPUT_CLOCK_MHz 20
|
||||
#define EPWM_TIMER_TBPRD 65535
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint32_t sdfmInstance;
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void configurePWMPins(void);
|
||||
void configureSDFMPins(uint16_t);
|
||||
void setPinConfig1(void);
|
||||
void setPinConfig2(void);
|
||||
void setPinConfig3(void);
|
||||
void initCLAMemoryMap(void);
|
||||
void initCPU1CLA(void);
|
||||
|
||||
|
||||
void generateSD_clock_MHz(float,uint16_t);
|
||||
void initEPWM(uint32_t,EPWM_CounterCompareModule);
|
||||
|
||||
//
|
||||
// Main
|
||||
//
|
||||
int main(void)
|
||||
{
|
||||
uint16_t pinMuxOption;
|
||||
uint16_t hlt, llt;
|
||||
|
||||
//
|
||||
// Initialize device clock and peripherals
|
||||
//
|
||||
Device_init();
|
||||
|
||||
//
|
||||
// Setup GPIO by disabling pin locks and enabling pullups
|
||||
//
|
||||
Device_initGPIO();
|
||||
|
||||
//
|
||||
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
|
||||
//
|
||||
Interrupt_initModule();
|
||||
|
||||
//
|
||||
// Initialize the PIE vector table with pointers to the shell Interrupt
|
||||
// Service Routines (ISR).
|
||||
//
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
//
|
||||
// Configure SDFM type to 0 and see if data ack generated SDINT.
|
||||
//
|
||||
SysCtl_configureType(SYSCTL_SDFMTYPE, 0, 1);
|
||||
|
||||
#ifdef CPU1
|
||||
pinMuxOption = SDFM_PIN_MUX_OPTION1;
|
||||
|
||||
//
|
||||
// Configure GPIO pins as SDFM pins
|
||||
//
|
||||
configureSDFMPins(pinMuxOption);
|
||||
|
||||
// This PWM signal can be used to generate clock for SD-modulator
|
||||
// Configure GPIO0 pins as PWM pin
|
||||
//
|
||||
configurePWMPins();
|
||||
|
||||
#endif
|
||||
|
||||
float SD_Modulator_freq_in_MHz = 20;
|
||||
|
||||
//
|
||||
// PWM1A is configured to generated SD-modulator input clock
|
||||
//
|
||||
generateSD_clock_MHz(SD_Modulator_freq_in_MHz, OSCLK_INPUT_CLOCK_MHz);
|
||||
|
||||
//
|
||||
// PWM11A is configured to generated SDSYNC signal to SDFM
|
||||
//
|
||||
initEPWM(EPWM11_BASE, EPWM_COUNTER_COMPARE_A);
|
||||
|
||||
//
|
||||
// Configure the CLA memory spaces
|
||||
//
|
||||
initCLAMemoryMap();
|
||||
|
||||
//
|
||||
// Configure the CLA task vectors & end-of task interrupts
|
||||
//
|
||||
initCPU1CLA();
|
||||
|
||||
//
|
||||
// Force task 8
|
||||
//
|
||||
CLA_forceTasks(CLA1_BASE,CLA_TASKFLAG_8);
|
||||
WAITSTEP;
|
||||
|
||||
//
|
||||
// Trigger Source for TASK1 of CLA1 = SDFM1
|
||||
//
|
||||
CLA_setTriggerSource(CLA_TASK_1, CLA_TRIGGER_SDFM1DRINT1);
|
||||
|
||||
//
|
||||
// Trigger Source for TASK2 of CLA1 = SDFM2
|
||||
//
|
||||
CLA_setTriggerSource(CLA_TASK_2, CLA_TRIGGER_SDFM2DRINT1);
|
||||
|
||||
//
|
||||
// Configure SDFM1
|
||||
//
|
||||
sdfmInstance = SDFM1_BASE;
|
||||
|
||||
//
|
||||
// Use FILTER (SD-C1) for FILTER2, FILTER3, FILTER4
|
||||
//
|
||||
SDFM_selectClockSource(sdfmInstance, SDFM_FILTER_1, SDFM_CLK_SOURCE_CHANNEL_CLK);
|
||||
SDFM_selectClockSource(sdfmInstance, SDFM_FILTER_2, SDFM_CLK_SOURCE_SD1_CLK);
|
||||
SDFM_selectClockSource(sdfmInstance, SDFM_FILTER_3, SDFM_CLK_SOURCE_SD1_CLK);
|
||||
SDFM_selectClockSource(sdfmInstance, SDFM_FILTER_4, SDFM_CLK_SOURCE_SD1_CLK);
|
||||
|
||||
//
|
||||
// Use Synchronizer on both SD-Cx and SD-Dx channels
|
||||
//
|
||||
SDFM_enableSynchronizer(sdfmInstance, SDFM_FILTER_1, SDFM_CLOCK_SYNCHRONIZER |
|
||||
SDFM_DATA_SYNCHRONIZER);
|
||||
SDFM_enableSynchronizer(sdfmInstance, SDFM_FILTER_2, SDFM_CLOCK_SYNCHRONIZER |
|
||||
SDFM_DATA_SYNCHRONIZER);
|
||||
SDFM_enableSynchronizer(sdfmInstance, SDFM_FILTER_3, SDFM_CLOCK_SYNCHRONIZER |
|
||||
SDFM_DATA_SYNCHRONIZER);
|
||||
SDFM_enableSynchronizer(sdfmInstance, SDFM_FILTER_4, SDFM_CLOCK_SYNCHRONIZER |
|
||||
SDFM_DATA_SYNCHRONIZER);
|
||||
|
||||
//
|
||||
// Input Control Module
|
||||
//
|
||||
// Configure Input Control Mode: Modulator Clock rate = Modulator data rate
|
||||
//
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_1,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_2,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_3,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
SDFM_setupModulatorClock(sdfmInstance, SDFM_FILTER_4,
|
||||
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
|
||||
|
||||
//
|
||||
// Comparator Module
|
||||
//
|
||||
hlt = 0x7FFF; //Over value threshold settings
|
||||
llt = 0x0000; //Under value threshold settings
|
||||
|
||||
//
|
||||
// Configure Comparator module's comparator filter type and comparator's OSR
|
||||
// value, higher threshold, lower threshold
|
||||
//
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_1 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_THRESHOLD(hlt,llt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_THRESHOLD(hlt,llt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_3 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_THRESHOLD(hlt,llt)), 0);
|
||||
SDFM_configComparator(sdfmInstance,
|
||||
(SDFM_FILTER_4 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
|
||||
(SDFM_THRESHOLD(hlt,llt)), 0);
|
||||
|
||||
//
|
||||
// Data filter Module
|
||||
//
|
||||
// Configure Data filter modules filter type, OSR value and
|
||||
// enable / disable data filter
|
||||
//
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_1 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_3 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
SDFM_configDataFilter(sdfmInstance, (SDFM_FILTER_4 | SDFM_FILTER_SINC_3 |
|
||||
SDFM_SET_OSR(256)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE |
|
||||
SDFM_SHIFT_VALUE(0x000A)));
|
||||
|
||||
|
||||
//
|
||||
// Enable SDFM FIFO for all filters
|
||||
//
|
||||
SDFM_enableFIFOBuffer(sdfmInstance, SDFM_FILTER_1);
|
||||
SDFM_enableFIFOBuffer(sdfmInstance, SDFM_FILTER_2);
|
||||
SDFM_enableFIFOBuffer(sdfmInstance, SDFM_FILTER_3);
|
||||
SDFM_enableFIFOBuffer(sdfmInstance, SDFM_FILTER_4);
|
||||
|
||||
//
|
||||
// Set SDFFIL = 5 for all filters
|
||||
//
|
||||
SDFM_setFIFOInterruptLevel(sdfmInstance, SDFM_FILTER_1, 5);
|
||||
SDFM_setFIFOInterruptLevel(sdfmInstance, SDFM_FILTER_2, 5);
|
||||
SDFM_setFIFOInterruptLevel(sdfmInstance, SDFM_FILTER_3, 5);
|
||||
SDFM_setFIFOInterruptLevel(sdfmInstance, SDFM_FILTER_4, 5);
|
||||
|
||||
//
|
||||
// Enable FIFO data ready interrupt for SDFM
|
||||
//
|
||||
SDFM_setDataReadyInterruptSource(sdfmInstance, SDFM_FILTER_1, SDFM_DATA_READY_SOURCE_FIFO);
|
||||
SDFM_setDataReadyInterruptSource(sdfmInstance, SDFM_FILTER_2, SDFM_DATA_READY_SOURCE_FIFO);
|
||||
SDFM_setDataReadyInterruptSource(sdfmInstance, SDFM_FILTER_3, SDFM_DATA_READY_SOURCE_FIFO);
|
||||
SDFM_setDataReadyInterruptSource(sdfmInstance, SDFM_FILTER_4, SDFM_DATA_READY_SOURCE_FIFO);
|
||||
|
||||
|
||||
//
|
||||
// Enable SDFM Wait for Sync feature
|
||||
//
|
||||
SDFM_enableWaitForSync(sdfmInstance, SDFM_FILTER_1);
|
||||
SDFM_enableWaitForSync(sdfmInstance, SDFM_FILTER_2);
|
||||
SDFM_enableWaitForSync(sdfmInstance, SDFM_FILTER_3);
|
||||
SDFM_enableWaitForSync(sdfmInstance, SDFM_FILTER_4);
|
||||
|
||||
//
|
||||
// Enable Master filter bit: Unless this bit is set none of the filter
|
||||
// modules can be enabled. All the filter modules are synchronized when
|
||||
// master filter bit is enabled after individual filter modules are enabled.
|
||||
//
|
||||
SDFM_enableMainFilter(sdfmInstance);
|
||||
|
||||
//
|
||||
// PWM11.CMPC, PWM11.CMPD, PWM12.CMPC and PWM12.CMPD signals can synchronize
|
||||
// the filters. This option is not being used in this example.
|
||||
//
|
||||
SDFM_enableExternalReset(sdfmInstance, SDFM_FILTER_1);
|
||||
SDFM_enableExternalReset(sdfmInstance, SDFM_FILTER_2);
|
||||
SDFM_enableExternalReset(sdfmInstance, SDFM_FILTER_3);
|
||||
SDFM_enableExternalReset(sdfmInstance, SDFM_FILTER_4);
|
||||
|
||||
//
|
||||
// Use PWM11.SOCA to provide SDSYNC pulse to SDFM
|
||||
//
|
||||
SDFM_setPWMSyncSource(sdfmInstance, SDFM_FILTER_1, SDFM_SYNC_PWM11_SOCA);
|
||||
SDFM_setPWMSyncSource(sdfmInstance, SDFM_FILTER_2, SDFM_SYNC_PWM11_SOCA);
|
||||
SDFM_setPWMSyncSource(sdfmInstance, SDFM_FILTER_3, SDFM_SYNC_PWM11_SOCA);
|
||||
SDFM_setPWMSyncSource(sdfmInstance, SDFM_FILTER_4, SDFM_SYNC_PWM11_SOCA);
|
||||
|
||||
|
||||
//
|
||||
// Enable interrupts
|
||||
//
|
||||
// Following SDFM interrupts can be enabled / disabled using this function.
|
||||
// Enable / disable comparator high threshold
|
||||
// Enable / disable comparator low threshold
|
||||
// Enable / disable modulator clock failure
|
||||
// Enable / disable filter acknowledge
|
||||
//
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_1,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_FIFO_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_2,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_FIFO_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_3,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_FIFO_INTERRUPT));
|
||||
|
||||
SDFM_enableInterrupt(sdfmInstance, SDFM_FILTER_4,
|
||||
(SDFM_MODULATOR_FAILURE_INTERRUPT |
|
||||
SDFM_FIFO_INTERRUPT));
|
||||
|
||||
//
|
||||
// Enable master interrupt so that any of the filter interrupts can
|
||||
// trigger by SDFM interrupt to CPU
|
||||
//
|
||||
SDFM_enableMainInterrupt(sdfmInstance);
|
||||
|
||||
//
|
||||
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
|
||||
//
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
//
|
||||
// configureSDFMPins - Configure SDFM GPIOs
|
||||
//
|
||||
void configureSDFMPins(uint16_t sdfmPinOption)
|
||||
{
|
||||
uint16_t pin;
|
||||
|
||||
switch (sdfmPinOption)
|
||||
{
|
||||
case SDFM_PIN_MUX_OPTION1:
|
||||
for(pin = 16; pin <= 31; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_PULLUP);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig1();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION2:
|
||||
for(pin = 48; pin <= 63; pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig2();
|
||||
break;
|
||||
|
||||
case SDFM_PIN_MUX_OPTION3:
|
||||
for(pin = 122; pin <= 137; pin++)
|
||||
{
|
||||
GPIO_setControllerCore(pin, GPIO_CORE_CPU1);
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setPadConfig(pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
}
|
||||
setPinConfig3();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig1 - sets the pin configuration for pins 16-21
|
||||
//
|
||||
void setPinConfig1()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_16_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_17_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_18_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_19_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_20_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_21_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_22_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_23_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_24_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_25_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_26_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_27_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_28_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_29_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_30_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_31_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig2 - sets the pin configuration for
|
||||
// pins 48-63
|
||||
//
|
||||
void setPinConfig2()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_48_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_49_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_50_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_51_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_52_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_53_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_54_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_55_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_56_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_57_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_58_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_59_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_60_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_61_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_62_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_63_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// setPinConfig3 - sets the pin configuration for pins 122-137
|
||||
//
|
||||
void setPinConfig3()
|
||||
{
|
||||
GPIO_setPinConfig(GPIO_122_SD1_D1);
|
||||
GPIO_setPinConfig(GPIO_123_SD1_C1);
|
||||
GPIO_setPinConfig(GPIO_124_SD1_D2);
|
||||
GPIO_setPinConfig(GPIO_125_SD1_C2);
|
||||
GPIO_setPinConfig(GPIO_126_SD1_D3);
|
||||
GPIO_setPinConfig(GPIO_127_SD1_C3);
|
||||
GPIO_setPinConfig(GPIO_128_SD1_D4);
|
||||
GPIO_setPinConfig(GPIO_129_SD1_C4);
|
||||
GPIO_setPinConfig(GPIO_130_SD2_D1);
|
||||
GPIO_setPinConfig(GPIO_131_SD2_C1);
|
||||
GPIO_setPinConfig(GPIO_132_SD2_D2);
|
||||
GPIO_setPinConfig(GPIO_133_SD2_C2);
|
||||
GPIO_setPinConfig(GPIO_134_SD2_D3);
|
||||
GPIO_setPinConfig(GPIO_135_SD2_C3);
|
||||
GPIO_setPinConfig(GPIO_136_SD2_D4);
|
||||
GPIO_setPinConfig(GPIO_137_SD2_C4);
|
||||
}
|
||||
|
||||
//
|
||||
// initCLAMemoryMap - Initialize Memory map
|
||||
//
|
||||
void initCLAMemoryMap(void)
|
||||
{
|
||||
//
|
||||
// Initialize and wait for CPUToCLA1MsgRAM
|
||||
//
|
||||
MemCfg_initSections(MEMCFG_SECT_MSGCLA1TOCPU);
|
||||
while(MemCfg_getInitStatus(MEMCFG_SECT_MSGCLA1TOCPU) != true);
|
||||
|
||||
//
|
||||
// Copy the program and constants from FLASH to RAM before configuring
|
||||
// the CLA
|
||||
//
|
||||
#if defined(_FLASH)
|
||||
memcpy((uint32_t *)&Cla1funcsRunStart, (uint32_t *)&Cla1funcsLoadStart,
|
||||
(uint32_t)&Cla1funcsLoadSize );
|
||||
memcpy((uint32_t *)&Cla1ConstRunStart, (uint32_t *)&Cla1ConstLoadStart,
|
||||
(uint32_t)&Cla1ConstLoadSize );
|
||||
#endif //defined(_FLASH)
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Select LS0 and LS1 RAM to be data RAM for the CLA and LS5 to be
|
||||
// programming space for the CLA as per linker cmd file used in this
|
||||
// example. This configuration should be updated as per the linker cmd file
|
||||
// used in the application.
|
||||
//
|
||||
MemCfg_setCLAMemType(MEMCFG_SECT_LS5, MEMCFG_CLA_MEM_PROGRAM);
|
||||
MemCfg_setCLAMemType(MEMCFG_SECT_LS0, MEMCFG_CLA_MEM_DATA);
|
||||
MemCfg_setCLAMemType(MEMCFG_SECT_LS1, MEMCFG_CLA_MEM_DATA);
|
||||
MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS5, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
|
||||
MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS0, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
|
||||
MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS1, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
|
||||
|
||||
|
||||
//
|
||||
// Initialize and wait for CPUToCLA1MsgRAM
|
||||
//
|
||||
MemCfg_initSections(MEMCFG_SECT_MSGCPUTOCLA1);
|
||||
while(MemCfg_getInitStatus(MEMCFG_SECT_MSGCPUTOCLA1) != true);
|
||||
|
||||
//
|
||||
// Filter1 and Filter2 data memory is mapped to LS6 RAM in linker cmd file
|
||||
// used in this example. This configuration should be updated as per the
|
||||
// linker cmd file used in the application.
|
||||
//
|
||||
MemCfg_setCLAMemType(MEMCFG_SECT_LS6, MEMCFG_CLA_MEM_DATA);
|
||||
MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS6, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
|
||||
|
||||
//
|
||||
// Filter3 and Filter4 data memory is mapped to LS7 RAM in linker cmd file
|
||||
// used in this example. This configuration should be updated as per the
|
||||
// linker cmd file used in the application.
|
||||
//
|
||||
MemCfg_setCLAMemType(MEMCFG_SECT_LS7, MEMCFG_CLA_MEM_DATA);
|
||||
MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS7, MEMCFG_LSRAMCONTROLLER_CPU_CLA1);
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
// initCPU1CLA - Initialize CLA1 task vectors and end of task interrupts
|
||||
//
|
||||
void initCPU1CLA(void)
|
||||
{
|
||||
//
|
||||
// Compute all CLA task vectors
|
||||
// Beyond Type-1 CLAs the MVECT registers accept full 16-bit task addresses
|
||||
// as opposed to offsets used on older Type-0 CLAs
|
||||
//
|
||||
#pragma diag_suppress=770
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_1,(uint16_t)&Cla1Task1);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_2,(uint16_t)&Cla1Task2);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_3,(uint16_t)&Cla1Task3);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_4,(uint16_t)&Cla1Task4);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_5,(uint16_t)&Cla1Task5);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_6,(uint16_t)&Cla1Task6);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_7,(uint16_t)&Cla1Task7);
|
||||
CLA_mapTaskVector(CLA1_BASE,CLA_MVECT_8,(uint16_t)&Cla1Task8);
|
||||
#pragma diag_warning=770
|
||||
|
||||
//
|
||||
// Enable IACK instruction to start a task on CLA in software
|
||||
// for all 8 CLA tasks
|
||||
//
|
||||
asm(" RPT #3 || NOP");
|
||||
CLA_enableIACK(CLA1_BASE);
|
||||
CLA_enableTasks(CLA1_BASE, CLA_TASKFLAG_ALL);
|
||||
|
||||
//
|
||||
// Configure the vectors for the end-of-task interrupt for all
|
||||
// 8 tasks
|
||||
//
|
||||
Interrupt_register(INT_CLA1_1, &cla1Isr1);
|
||||
Interrupt_register(INT_CLA1_2, &cla1Isr2);
|
||||
Interrupt_register(INT_CLA1_3, &cla1Isr3);
|
||||
Interrupt_register(INT_CLA1_4, &cla1Isr4);
|
||||
Interrupt_register(INT_CLA1_5, &cla1Isr5);
|
||||
Interrupt_register(INT_CLA1_6, &cla1Isr6);
|
||||
Interrupt_register(INT_CLA1_7, &cla1Isr7);
|
||||
Interrupt_register(INT_CLA1_8, &cla1Isr8);
|
||||
|
||||
//
|
||||
// Enable CLA interrupts at the group and subgroup levels
|
||||
//
|
||||
Interrupt_enable(INT_CLA1_1);
|
||||
Interrupt_enable(INT_CLA1_2);
|
||||
Interrupt_enable(INT_CLA1_3);
|
||||
Interrupt_enable(INT_CLA1_4);
|
||||
Interrupt_enable(INT_CLA1_5);
|
||||
Interrupt_enable(INT_CLA1_6);
|
||||
Interrupt_enable(INT_CLA1_7);
|
||||
Interrupt_enable(INT_CLA1_8);
|
||||
|
||||
EINT; // Enable Global interrupt INTM
|
||||
ERTM; // Enable Global realtime interrupt DBGM
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 1
|
||||
//
|
||||
interrupt void cla1Isr1 ()
|
||||
{
|
||||
//
|
||||
// Acknowledge the end-of-task interrupt for task 1
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11);
|
||||
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 2
|
||||
//
|
||||
interrupt void cla1Isr2 ()
|
||||
{
|
||||
//
|
||||
// Acknowledge the end-of-task interrupt for task 2
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11);
|
||||
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 3
|
||||
//
|
||||
interrupt void cla1Isr3 ()
|
||||
{
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 4
|
||||
//
|
||||
interrupt void cla1Isr4 ()
|
||||
{
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 5
|
||||
//
|
||||
interrupt void cla1Isr5 ()
|
||||
{
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 6
|
||||
//
|
||||
interrupt void cla1Isr6 ()
|
||||
{
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 7
|
||||
//
|
||||
interrupt void cla1Isr7 ()
|
||||
{
|
||||
//
|
||||
// Halt debugger and stop here
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// cla1Isr1 - CLA1 ISR 8
|
||||
//
|
||||
interrupt void cla1Isr8 ()
|
||||
{
|
||||
//
|
||||
// Acknowledge the end-of-task interrupt for task 8
|
||||
//
|
||||
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11);
|
||||
|
||||
// //
|
||||
// // Uncomment to halt debugger and stop here
|
||||
// //
|
||||
// asm(" ESTOP0");
|
||||
}
|
||||
|
||||
|
||||
void configurePWMPins(void)
|
||||
{
|
||||
//EPWM1 GPIO
|
||||
GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setPinConfig(GPIO_0_EPWM1A);
|
||||
|
||||
//EPWM11 GPIO: This can be enabled to check freq of PWM cycle
|
||||
GPIO_setPadConfig(20, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setPinConfig(GPIO_20_EPWM11A);
|
||||
}
|
||||
|
||||
//
|
||||
// generateSD_clock_MHz - Configure ePWM1
|
||||
//
|
||||
void generateSD_clock_MHz(float sdclk_MHz, uint16_t oscclkInMHz)
|
||||
{
|
||||
ASSERT(oscclkInMHz <= 20);
|
||||
|
||||
uint32_t sysclk_in_MHz = SysCtl_getClock(oscclkInMHz);
|
||||
uint16_t period = (uint16_t)(sysclk_in_MHz / sdclk_MHz)-1;
|
||||
|
||||
//
|
||||
// Set-up PWMCLK = SYSCLK
|
||||
//
|
||||
SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_1);
|
||||
|
||||
//
|
||||
// Set-up TBCLK
|
||||
//
|
||||
EPWM_setTimeBasePeriod(EPWM1_BASE, period);
|
||||
EPWM_setPhaseShift(EPWM1_BASE, 0U);
|
||||
EPWM_setTimeBaseCounter(EPWM1_BASE, 0U);
|
||||
|
||||
//
|
||||
// Set Compare values
|
||||
//
|
||||
EPWM_setCounterCompareValue(EPWM1_BASE,
|
||||
EPWM_COUNTER_COMPARE_A,
|
||||
(period)>>1);
|
||||
//
|
||||
// Set up counter mode
|
||||
//
|
||||
EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP);
|
||||
EPWM_disablePhaseShiftLoad(EPWM1_BASE);
|
||||
EPWM_setClockPrescaler(EPWM1_BASE,
|
||||
EPWM_CLOCK_DIVIDER_1,
|
||||
EPWM_HSCLOCK_DIVIDER_1);
|
||||
|
||||
//
|
||||
// Set up shadowing
|
||||
//
|
||||
EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE,
|
||||
EPWM_COUNTER_COMPARE_A,
|
||||
EPWM_COMP_LOAD_ON_CNTR_ZERO);
|
||||
EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE,
|
||||
EPWM_COUNTER_COMPARE_B,
|
||||
EPWM_COMP_LOAD_ON_CNTR_ZERO);
|
||||
|
||||
//
|
||||
// Set actions
|
||||
//
|
||||
EPWM_setActionQualifierAction(EPWM1_BASE,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_HIGH,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
|
||||
|
||||
EPWM_setActionQualifierAction(EPWM1_BASE,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_LOW,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
|
||||
|
||||
EPWM_setEmulationMode(EPWM1_BASE, EPWM_EMULATION_FREE_RUN);
|
||||
}
|
||||
|
||||
//
|
||||
// initEPWM - Initialize specified EPWM settings
|
||||
//
|
||||
void initEPWM(uint32_t epwmInstance, EPWM_CounterCompareModule compModule)
|
||||
{
|
||||
uint16_t compCVal,compDVal;
|
||||
|
||||
compCVal = 200;
|
||||
compDVal = 200;
|
||||
|
||||
#ifdef CPU1
|
||||
GPIO_setDirectionMode(4, GPIO_DIR_MODE_OUT);
|
||||
GPIO_setPinConfig(GPIO_4_GPIO4);
|
||||
#endif
|
||||
|
||||
//
|
||||
// Disable sync(Freeze clock to PWM as well)
|
||||
//
|
||||
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
|
||||
|
||||
//
|
||||
// Setup TBCLK: Configure timer period = 801 TBCLKs, phase = 0 &
|
||||
// clear counter
|
||||
//
|
||||
EPWM_setTimeBasePeriod(epwmInstance, EPWM_TIMER_TBPRD);
|
||||
EPWM_setPhaseShift(epwmInstance, 0U);
|
||||
EPWM_setTimeBaseCounter(epwmInstance, 0U);
|
||||
|
||||
//
|
||||
// Set CMPA, CMPB, CMPC & CMPD values
|
||||
//
|
||||
EPWM_setCounterCompareValue(epwmInstance, EPWM_COUNTER_COMPARE_C, compCVal);
|
||||
EPWM_setCounterCompareValue(epwmInstance, EPWM_COUNTER_COMPARE_D, compDVal);
|
||||
EPWM_setCounterCompareValue(epwmInstance, EPWM_COUNTER_COMPARE_A, compCVal);
|
||||
EPWM_setCounterCompareValue(epwmInstance, EPWM_COUNTER_COMPARE_B, compDVal);
|
||||
|
||||
//
|
||||
// Setup counter mode
|
||||
//
|
||||
EPWM_setTimeBaseCounterMode(epwmInstance, EPWM_COUNTER_MODE_UP);
|
||||
EPWM_setClockPrescaler(epwmInstance,
|
||||
EPWM_CLOCK_DIVIDER_1,
|
||||
EPWM_HSCLOCK_DIVIDER_1);
|
||||
|
||||
//
|
||||
// Set actions:
|
||||
// Toggle PWMxA on event A, up-count
|
||||
// Toggle PWMxB on event A, up-count
|
||||
//
|
||||
EPWM_setActionQualifierAction(epwmInstance,
|
||||
EPWM_AQ_OUTPUT_A,
|
||||
EPWM_AQ_OUTPUT_TOGGLE,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
|
||||
EPWM_setActionQualifierAction(epwmInstance,
|
||||
EPWM_AQ_OUTPUT_B,
|
||||
EPWM_AQ_OUTPUT_TOGGLE,
|
||||
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
|
||||
|
||||
if(compModule == EPWM_COUNTER_COMPARE_A)
|
||||
{
|
||||
EPWM_enableADCTrigger(epwmInstance,EPWM_SOC_A);
|
||||
EPWM_setADCTriggerSource(epwmInstance,EPWM_SOC_A,EPWM_SOC_TBCTR_U_CMPA);
|
||||
EPWM_setADCTriggerEventPrescale(epwmInstance, EPWM_SOC_A, 1); //1st event
|
||||
|
||||
EPWM_setInterruptSource(epwmInstance, EPWM_INT_TBCTR_U_CMPA);
|
||||
EPWM_enableInterrupt(epwmInstance);
|
||||
EPWM_setInterruptEventCount(epwmInstance, 1);
|
||||
|
||||
}
|
||||
if(compModule == EPWM_COUNTER_COMPARE_B)
|
||||
{
|
||||
EPWM_enableADCTrigger(epwmInstance,EPWM_SOC_B);
|
||||
EPWM_setADCTriggerSource(epwmInstance,EPWM_SOC_B,EPWM_SOC_TBCTR_U_CMPA);
|
||||
EPWM_setADCTriggerEventPrescale(epwmInstance, EPWM_SOC_B, 1); //1st event
|
||||
|
||||
EPWM_setInterruptSource(epwmInstance, EPWM_INT_TBCTR_U_CMPB);
|
||||
}
|
||||
|
||||
//
|
||||
// Enable sync and clock to PWM
|
||||
//
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
|
||||
|
||||
//
|
||||
// Emulation free run
|
||||
//
|
||||
EPWM_setEmulationMode(epwmInstance, EPWM_EMULATION_FREE_RUN);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -0,0 +1,217 @@
|
||||
//#############################################################################
|
||||
// \file sdfm_ex6_filter_sync_claread_cla.cla
|
||||
//
|
||||
// \brief SDFM filter sync
|
||||
// \author
|
||||
// \date
|
||||
//
|
||||
//
|
||||
// Group: C2000
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
//
|
||||
// C2000Ware v5.04.00.00
|
||||
//
|
||||
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include <stdint.h>
|
||||
#include "f2838x_device.h"
|
||||
#include "f2838x_sdfm_drivers.h"
|
||||
#include "sdfm_claread.h"
|
||||
|
||||
//
|
||||
// Whether MDEBUGSTOP needs to be compiled or not
|
||||
//
|
||||
#define CLA_DEBUG 1
|
||||
#define PIEACK_GROUP5 0x0010
|
||||
|
||||
#pragma DATA_SECTION(filter1Result,"Filter1_RegsFile");
|
||||
#pragma DATA_SECTION(filter2Result,"Filter2_RegsFile");
|
||||
#pragma DATA_SECTION(filter3Result,"Filter3_RegsFile");
|
||||
#pragma DATA_SECTION(filter4Result,"Filter4_RegsFile");
|
||||
|
||||
int16_t filter1Result[MAX_SAMPLES];
|
||||
int16_t filter2Result[MAX_SAMPLES];
|
||||
int16_t filter3Result[MAX_SAMPLES];
|
||||
int16_t filter4Result[MAX_SAMPLES];
|
||||
|
||||
int16_t loopCounter1;
|
||||
int16_t loopCounter2;
|
||||
|
||||
//
|
||||
// Task 1
|
||||
//
|
||||
__interrupt void Cla1Task1 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
uint32_t sdfmReadFlagRegister;
|
||||
uint16_t i=0;
|
||||
|
||||
//
|
||||
// Read SDIFLG of SDFM1
|
||||
//
|
||||
sdfmReadFlagRegister = Sdfm1Regs.SDIFLG.all;
|
||||
|
||||
//
|
||||
// Reset the loop counter
|
||||
//
|
||||
if(loopCounter1 >= MAX_SAMPLES)
|
||||
{
|
||||
loopCounter1 = 0;
|
||||
}
|
||||
|
||||
uint16_t fifolevel = Sdfm1Regs.SDFIFOCTL1.bit.SDFFST;
|
||||
|
||||
for(i=0;i<fifolevel;i++)
|
||||
{
|
||||
filter1Result[loopCounter1] = Sdfm1Regs.SDDATFIFO1.all >> 16;
|
||||
filter2Result[loopCounter1] = Sdfm1Regs.SDDATFIFO2.all >> 16;
|
||||
filter3Result[loopCounter1] = Sdfm1Regs.SDDATFIFO3.all >> 16;
|
||||
filter4Result[loopCounter1++] = Sdfm1Regs.SDDATFIFO4.all >> 16;
|
||||
}
|
||||
|
||||
//
|
||||
// Clear SDFM1.SDIFLG register
|
||||
//
|
||||
Sdfm1Regs.SDIFLGCLR.all = sdfmReadFlagRegister;
|
||||
}
|
||||
|
||||
//
|
||||
// Task 2
|
||||
//
|
||||
__interrupt void Cla1Task2 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
uint32_t sdfmReadFlagRegister;
|
||||
uint16_t i=0;
|
||||
|
||||
//
|
||||
// Read SDIFLG of SDFM2
|
||||
//
|
||||
sdfmReadFlagRegister = Sdfm2Regs.SDIFLG.all;
|
||||
|
||||
//
|
||||
// Reset the loop counter
|
||||
//
|
||||
if(loopCounter1 >= MAX_SAMPLES)
|
||||
{
|
||||
loopCounter1 = 0;
|
||||
}
|
||||
|
||||
uint16_t fifolevel = Sdfm2Regs.SDFIFOCTL1.bit.SDFFST;
|
||||
|
||||
for(i=0;i<fifolevel;i++)
|
||||
{
|
||||
filter1Result[loopCounter1] = Sdfm2Regs.SDDATFIFO1.all >> 16;
|
||||
filter2Result[loopCounter1] = Sdfm2Regs.SDDATFIFO2.all >> 16;
|
||||
filter3Result[loopCounter1] = Sdfm2Regs.SDDATFIFO3.all >> 16;
|
||||
filter4Result[loopCounter1++] = Sdfm2Regs.SDDATFIFO4.all >> 16;
|
||||
}
|
||||
|
||||
//
|
||||
// Clear SDFM1.SDIFLG register
|
||||
//
|
||||
Sdfm2Regs.SDIFLGCLR.all = sdfmReadFlagRegister;
|
||||
}
|
||||
|
||||
//
|
||||
// Task 3
|
||||
//
|
||||
__interrupt void Cla1Task3 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// Task 4
|
||||
//
|
||||
__interrupt void Cla1Task4 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// Task 5
|
||||
//
|
||||
__interrupt void Cla1Task5 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
// Task 6
|
||||
//
|
||||
__interrupt void Cla1Task6 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// Task 7
|
||||
//
|
||||
__interrupt void Cla1Task7 ( void )
|
||||
{
|
||||
#if (CLA_DEBUG==1)
|
||||
__mdebugstop();
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// Task 8
|
||||
//
|
||||
__interrupt void Cla1Task8 ( void )
|
||||
{
|
||||
loopCounter1 = 0;
|
||||
loopCounter2 = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
Reference in New Issue
Block a user