Update repo
This commit is contained in:
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<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/>
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<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>
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<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
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</cproject>
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@@ -0,0 +1,136 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>c28x_vcrc_library</name>
|
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<comment></comment>
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<key>?name?</key>
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<value></value>
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<dictionary>
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<key>org.eclipse.cdt.make.core.append_environment</key>
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<value>true</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
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<value>all</value>
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<dictionary>
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<key>org.eclipse.cdt.make.core.buildArguments</key>
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<value>-k</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.buildCommand</key>
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<value>${CCS_UTILS_DIR}/bin/gmake</value>
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</dictionary>
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<dictionary>
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||||
<key>org.eclipse.cdt.make.core.buildLocation</key>
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<value>${BuildDirectory}</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
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<value>clean</value>
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<dictionary>
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<key>org.eclipse.cdt.make.core.contents</key>
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<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
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<value>true</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
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<value>true</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.enableFullBuild</key>
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<value>true</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
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<value>all</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.stopOnError</key>
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<value>false</value>
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</dictionary>
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<dictionary>
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<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
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<buildCommand>
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<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
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<triggers>full,incremental,</triggers>
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</arguments>
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</buildCommand>
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||||
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||||
<natures>
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<nature>com.ti.ccstudio.core.ccsNature</nature>
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||||
<nature>org.eclipse.cdt.core.cnature</nature>
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||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
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||||
<nature>org.eclipse.cdt.core.ccnature</nature>
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||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>crc</name>
|
||||
<type>2</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/vcu2/crc</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>vcrc</name>
|
||||
<type>2</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/vcrc/crc</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>ISA_C28FPU32/c28x_vcrc_library_fpu32.lib</name>
|
||||
<type>1</type>
|
||||
<locationURI>EXTERNAL_BUILD_ARTIFACT</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>ISA_C28FPU64/c28x_vcrc_library_fpu64.lib</name>
|
||||
<type>1</type>
|
||||
<locationURI>EXTERNAL_BUILD_ARTIFACT</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>crc/crc_16.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/crc/crc_16.c</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>crc/crc_24.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/crc/crc_24.c</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>crc/crc_32.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/crc/crc_32.c</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>crc/crc_8.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/crc/crc_8.c</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>crc/crc_util.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/crc/crc_util.c</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<variableList>
|
||||
<variable>
|
||||
<name>VCU2_ROOT_DIR</name>
|
||||
<value>$%7BPARENT-2-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
</variableList>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<?ccsproject version="1.0"?>
|
||||
<projectOptions>
|
||||
<deviceVariant value="com.ti.ccstudio.deviceModel.C2000.GenericC28xxDevice"/>
|
||||
<deviceEndianness value="little"/>
|
||||
<codegenToolVersion value="6.1.2"/>
|
||||
<isElfFormat value="false"/>
|
||||
<connection value=""/>
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||||
<rts value=""/>
|
||||
<templateProperties value="id=com.ti.common.project.core.emptyProjectTemplate,"/>
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||||
<deviceFamily value="C2000"/>
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||||
<isTargetManual value="false"/>
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||||
</projectOptions>
|
||||
@@ -0,0 +1,161 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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||||
<storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
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||||
<cconfiguration id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1662582073">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1662582073" moduleId="org.eclipse.cdt.core.settings" name="ISA_C2800">
|
||||
<macros>
|
||||
<stringMacro name="VCU2_ROOT_DIR" type="VALUE_PATH_DIR" value="${PROJECT_ROOT}/../.."/>
|
||||
</macros>
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
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||||
<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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<configuration artifactExtension="lib" artifactName="${VCU2_ROOT_DIR}/lib/${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="Only supports ISA C2800" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1662582073" name="ISA_C2800" parent="com.ti.ccstudio.buildDefinitions.C2000.Debug">
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||||
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<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.224544026" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
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<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C2000.GenericC28xxDevice"/>
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<listOptionValue builtIn="false" value="DEVICE_CORE_ID="/>
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<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
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<listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
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<listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.5.0"/>
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<listOptionValue builtIn="false" value="LINK_ORDER="/>
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<listOptionValue builtIn="false" value="PRODUCTS="/>
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<listOptionValue builtIn="false" value="PRODUCT_MACRO_IMPORTS={}"/>
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<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY="/>
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<listOptionValue builtIn="false" value="OUTPUT_TYPE=staticLibrary"/>
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||||
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.575450974" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="22.6.0.LTS" valueType="string"/>
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||||
<targetPlatform id="com.ti.ccstudio.buildDefinitions.C2000_22.6.library.targetPlatformDebug.2129318789" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.library.targetPlatformDebug"/>
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||||
<builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.library.builderDebug.537589522" keepEnvironmentInBuildfile="false" name="GNU Make" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.library.builderDebug"/>
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||||
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<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.UNIFIED_MEMORY.1887376179" name="Unified memory (--unified_memory, -mt)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.UNIFIED_MEMORY" value="true" valueType="boolean"/>
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<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.ISSUE_REMARKS.1469354474" name="Issue remarks (--issue_remarks, -pdr)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.ISSUE_REMARKS" value="true" valueType="boolean"/>
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<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__CPP_SRCS.1852335808" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__CPP_SRCS"/>
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<entry excluding="crc/crc8_DEPRECATED.c|crc/crc32_DEPRECATED.c|crc/crc16_DEPRECATED.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
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|
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|
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|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.archiverID.VERBOSE.279599157" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.archiverID.VERBOSE" value="true" valueType="boolean"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="c28x_vcu_library.com.ti.ccstudio.buildDefinitions.C2000.ProjectType.1666877363" name="C2000" projectType="com.ti.ccstudio.buildDefinitions.C2000.ProjectType"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
|
||||
<project-mappings>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>
|
||||
</project-mappings>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
</cproject>
|
||||
@@ -0,0 +1,156 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>c28x_vcu2_library</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<arguments>
|
||||
<dictionary>
|
||||
<key>?name?</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.append_environment</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildArguments</key>
|
||||
<value>-k</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildCommand</key>
|
||||
<value>${CCS_UTILS_DIR}/bin/gmake</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildLocation</key>
|
||||
<value>${BuildDirectory}</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
|
||||
<value>clean</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.contents</key>
|
||||
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.stopOnError</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>com.ti.ccstudio.core.ccsNature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>crc</name>
|
||||
<type>2</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/vcu2/crc</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>deinterleaver</name>
|
||||
<type>2</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/vcu2/deinterleaver</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>fft</name>
|
||||
<type>2</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/vcu2/fft</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>interleaver</name>
|
||||
<type>2</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/interleaver</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>reed_solomon</name>
|
||||
<type>2</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/vcu2/reed_solomon</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>viterbi</name>
|
||||
<type>2</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/vcu2/viterbi</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>crc/crc_16.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/crc/crc_16.c</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>crc/crc_24.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/crc/crc_24.c</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>crc/crc_32.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/crc/crc_32.c</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>crc/crc_8.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/crc/crc_8.c</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>crc/crc_util.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/crc/crc_util.c</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>reed_solomon/reed_solomon_enc.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/reed_solomon/reed_solomon_enc.c</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>viterbi/viterbi_cnv_enc.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>VCU2_ROOT_DIR/source/common/C/viterbi/viterbi_cnv_enc.c</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<variableList>
|
||||
<variable>
|
||||
<name>VCU2_ROOT_DIR</name>
|
||||
<value>$%7BPARENT-2-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
</variableList>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,55 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
|
||||
|
||||
RAMM01 : origin = 0x00000128, length = 0x000006D0
|
||||
//RAMM01 : origin = 0x00000400, length = 0x000003F8
|
||||
// RAMM01_RSVD : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMLS : origin = 0x00008000, length = 0x00003FF8
|
||||
//RAMLS : origin = 0x00008000, length = 0x00002000
|
||||
//RAMLS1 : origin = 0x0000A000, length = 0x00001FF8
|
||||
// RAMLS1_RSVD : origin = 0x0000BFF8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
}
|
||||
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : > RAMLS
|
||||
.cinit : > RAMM01
|
||||
.switch : > RAMM01
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM01
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS
|
||||
.bss:output : > RAMLS
|
||||
.init_array : > RAMM01
|
||||
.const : > RAMLS
|
||||
.data : > RAMLS
|
||||
.sysmem : > RAMLS
|
||||
testInput : > RAMLS
|
||||
TestOutput : > RAMLS
|
||||
.TI.crctab : > RAMLS
|
||||
#else
|
||||
.pinit : > RAMM01
|
||||
.ebss : > RAMLS
|
||||
.econst : > RAMLS
|
||||
.esysmem : > RAMLS
|
||||
#endif
|
||||
|
||||
|
||||
.TI.ramfunc : {} > RAMM01
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,57 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
|
||||
|
||||
RAMM01 : origin = 0x00000128, length = 0x000006D0
|
||||
//RAMM01 : origin = 0x00000400, length = 0x000003F8
|
||||
// RAMM01_RSVD : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMLS : origin = 0x00008000, length = 0x00003FF8
|
||||
//RAMLS : origin = 0x00008000, length = 0x00002000
|
||||
//RAMLS1 : origin = 0x0000A000, length = 0x00001FF8
|
||||
// RAMLS1_RSVD : origin = 0x0000BFF8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS
|
||||
.cinit : > RAMM01
|
||||
.switch : > RAMM01
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM01
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS
|
||||
.bss:output : > RAMLS
|
||||
.init_array : > RAMM01
|
||||
.const : > RAMLS
|
||||
.data : > RAMLS
|
||||
.sysmem : > RAMLS
|
||||
.TI.crctab : > RAMLS
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS, RUN_START(testInputRunStart){
|
||||
testInput :{} LOAD = RAMLS,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
crc_table(linkerCrcTable, algorithm = CRC16_802_15_4)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC16_ALT)
|
||||
#else
|
||||
.pinit : > RAMM01
|
||||
.ebss : >> RAMLS
|
||||
.econst : > RAMLS
|
||||
.esysmem : > RAMLS
|
||||
#endif
|
||||
|
||||
.TI.ramfunc : {} > RAMM01
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,56 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
|
||||
|
||||
RAMM01 : origin = 0x00000128, length = 0x000006D0
|
||||
//RAMM01 : origin = 0x00000400, length = 0x000003F8
|
||||
// RAMM01_RSVD : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMLS : origin = 0x00008000, length = 0x00003FF8
|
||||
//RAMLS : origin = 0x00008000, length = 0x00002000
|
||||
//RAMLS1 : origin = 0x0000A000, length = 0x00001FF8
|
||||
// RAMLS1_RSVD : origin = 0x0000BFF8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS
|
||||
.cinit : > RAMM01
|
||||
.switch : > RAMM01
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM01
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS
|
||||
.bss:output : > RAMLS
|
||||
.init_array : > RAMM01
|
||||
.const : > RAMLS
|
||||
.data : > RAMLS
|
||||
.sysmem : > RAMLS
|
||||
.TI.crctab : > RAMLS
|
||||
/* Test specific sections */
|
||||
testInput : > RAMLS,
|
||||
crc_table(linkerCrcTable, algorithm = CRC24_FLEXRAY)
|
||||
#else
|
||||
.pinit : > RAMM01
|
||||
.ebss : >> RAMLS
|
||||
.econst : > RAMLS
|
||||
.esysmem : > RAMLS
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
.TI.ramfunc : {} > RAMM01
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,60 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
|
||||
|
||||
RAMM01 : origin = 0x00000128, length = 0x000006D0
|
||||
//RAMM01 : origin = 0x00000400, length = 0x000003F8
|
||||
// RAMM01_RSVD : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMLS : origin = 0x00008000, length = 0x00003FF8
|
||||
//RAMLS : origin = 0x00008000, length = 0x00002000
|
||||
//RAMLS1 : origin = 0x0000A000, length = 0x00001FF8
|
||||
// RAMLS1_RSVD : origin = 0x0000BFF8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
}
|
||||
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : > RAMLS
|
||||
.cinit : > RAMM01
|
||||
.switch : > RAMM01
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM01
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS
|
||||
.bss:output : > RAMLS
|
||||
.init_array : > RAMM01
|
||||
.const : > RAMLS
|
||||
.data : > RAMLS
|
||||
.sysmem : > RAMLS
|
||||
.TI.crctab : > RAMLS
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS, RUN_START(testInputRunStart){
|
||||
testInput :{} LOAD = RAMLS,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
crc_table(linkerCrcTable, algorithm = CRC32_PRIME)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC32_C)
|
||||
#else
|
||||
.pinit : > RAMM01
|
||||
.ebss : >> RAMLS
|
||||
.econst : > RAMLS
|
||||
.esysmem : > RAMLS
|
||||
#endif
|
||||
|
||||
|
||||
.TI.ramfunc : {} > RAMM01
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,53 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
|
||||
|
||||
RAMM01 : origin = 0x00000128, length = 0x000006D0
|
||||
//RAMM01 : origin = 0x00000400, length = 0x000003F8
|
||||
// RAMM01_RSVD : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMLS : origin = 0x00008000, length = 0x00003FF8
|
||||
//RAMLS : origin = 0x00008000, length = 0x00002000
|
||||
//RAMLS1 : origin = 0x0000A000, length = 0x00001FF8
|
||||
// RAMLS1_RSVD : origin = 0x0000BFF8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : > RAMLS
|
||||
.cinit : > RAMM01
|
||||
.switch : > RAMM01
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM01
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS
|
||||
.bss:output : > RAMLS
|
||||
.init_array : > RAMM01
|
||||
.const : > RAMLS
|
||||
.data : > RAMLS
|
||||
.sysmem : > RAMLS
|
||||
testInput : > RAMLS,
|
||||
crc_table(linkerCrcTable, algorithm = CRC8_PRIME)
|
||||
.TI.crctab : > RAMLS
|
||||
#else
|
||||
.pinit : > RAMM01
|
||||
.ebss : >> RAMLS
|
||||
.econst : > RAMLS
|
||||
.esysmem : > RAMLS
|
||||
#endif
|
||||
|
||||
.TI.ramfunc : {} > RAMM01
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,127 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
|
||||
|
||||
RAMM0 : origin = 0x00000128, length = 0x000002D8
|
||||
RAMM1 : origin = 0x00000400, length = 0x00000380 /* on-chip RAM block M1 */
|
||||
BOOT_RSVD_SYSBIOS: origin = 0x00000780, length = 0x00000080
|
||||
|
||||
|
||||
RAMLS0 : origin = 0x00008000, length = 0x00000800
|
||||
RAMLS1 : origin = 0x00008800, length = 0x00000800
|
||||
RAMLS2 : origin = 0x00009000, length = 0x00000800
|
||||
RAMLS3 : origin = 0x00009800, length = 0x00000800
|
||||
RAMLS4 : origin = 0x0000A000, length = 0x00000800
|
||||
RAMLS5 : origin = 0x0000A800, length = 0x00000800
|
||||
RAMLS6 : origin = 0x0000B000, length = 0x00000800
|
||||
RAMLS7 : origin = 0x0000B800, length = 0x00000800
|
||||
|
||||
RAMGS0 : origin = 0x0000C000, length = 0x00001000
|
||||
RAMGS1 : origin = 0x0000D000, length = 0x00001000
|
||||
RAMGS2 : origin = 0x0000E000, length = 0x00001000
|
||||
RAMGS3 : origin = 0x0000F000, length = 0x00001000
|
||||
|
||||
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
|
||||
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
|
||||
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
|
||||
/* Flash sectors */
|
||||
/* BANK 0 */
|
||||
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE
|
||||
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
|
||||
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
|
||||
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
|
||||
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
|
||||
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
|
||||
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
|
||||
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
|
||||
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
|
||||
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
|
||||
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
|
||||
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
|
||||
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
|
||||
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
|
||||
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
|
||||
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
|
||||
|
||||
/* BANK 1 */
|
||||
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
|
||||
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
|
||||
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
|
||||
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
|
||||
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
|
||||
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
|
||||
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
|
||||
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
|
||||
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
|
||||
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
|
||||
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
|
||||
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
|
||||
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
|
||||
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
|
||||
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
|
||||
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
|
||||
|
||||
/* BANK 2 */
|
||||
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
|
||||
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
|
||||
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
|
||||
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
|
||||
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
|
||||
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
|
||||
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
|
||||
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
|
||||
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
|
||||
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
|
||||
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
|
||||
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
|
||||
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
|
||||
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
|
||||
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
|
||||
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >>RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS7
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5 | RAMGS3
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
testInput : > RAMGS0
|
||||
TestOutput : > RAMGS0
|
||||
.TI.crctab : > RAMGS0
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,131 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
|
||||
|
||||
RAMM0 : origin = 0x00000128, length = 0x000002D8
|
||||
RAMM1 : origin = 0x00000400, length = 0x00000380 /* on-chip RAM block M1 */
|
||||
BOOT_RSVD_SYSBIOS: origin = 0x00000780, length = 0x00000080
|
||||
|
||||
|
||||
RAMLS0 : origin = 0x00008000, length = 0x00000800
|
||||
RAMLS1 : origin = 0x00008800, length = 0x00000800
|
||||
RAMLS2 : origin = 0x00009000, length = 0x00000800
|
||||
RAMLS3 : origin = 0x00009800, length = 0x00000800
|
||||
RAMLS4 : origin = 0x0000A000, length = 0x00000800
|
||||
RAMLS5 : origin = 0x0000A800, length = 0x00000800
|
||||
RAMLS6 : origin = 0x0000B000, length = 0x00000800
|
||||
RAMLS7 : origin = 0x0000B800, length = 0x00000800
|
||||
|
||||
RAMGS0 : origin = 0x0000C000, length = 0x00001000
|
||||
RAMGS1 : origin = 0x0000D000, length = 0x00001000
|
||||
RAMGS2 : origin = 0x0000E000, length = 0x00001000
|
||||
RAMGS3 : origin = 0x0000F000, length = 0x00001000
|
||||
|
||||
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
|
||||
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
|
||||
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
|
||||
/* Flash sectors */
|
||||
/* BANK 0 */
|
||||
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE
|
||||
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
|
||||
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
|
||||
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
|
||||
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
|
||||
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
|
||||
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
|
||||
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
|
||||
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
|
||||
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
|
||||
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
|
||||
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
|
||||
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
|
||||
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
|
||||
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
|
||||
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
|
||||
|
||||
/* BANK 1 */
|
||||
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
|
||||
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
|
||||
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
|
||||
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
|
||||
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
|
||||
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
|
||||
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
|
||||
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
|
||||
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
|
||||
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
|
||||
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
|
||||
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
|
||||
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
|
||||
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
|
||||
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
|
||||
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
|
||||
|
||||
/* BANK 2 */
|
||||
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
|
||||
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
|
||||
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
|
||||
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
|
||||
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
|
||||
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
|
||||
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
|
||||
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
|
||||
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
|
||||
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
|
||||
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
|
||||
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
|
||||
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
|
||||
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
|
||||
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
|
||||
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
|
||||
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMGS0, RUN_START(testInputRunStart){
|
||||
testInput :{} LOAD = RAMGS0,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
crc_table(linkerCrcTable, algorithm = CRC16_802_15_4)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC16_ALT)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,127 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
|
||||
|
||||
RAMM0 : origin = 0x00000128, length = 0x000002D8
|
||||
RAMM1 : origin = 0x00000400, length = 0x00000380 /* on-chip RAM block M1 */
|
||||
BOOT_RSVD_SYSBIOS: origin = 0x00000780, length = 0x00000080
|
||||
|
||||
|
||||
RAMLS0 : origin = 0x00008000, length = 0x00000800
|
||||
RAMLS1 : origin = 0x00008800, length = 0x00000800
|
||||
RAMLS2 : origin = 0x00009000, length = 0x00000800
|
||||
RAMLS3 : origin = 0x00009800, length = 0x00000800
|
||||
RAMLS4 : origin = 0x0000A000, length = 0x00000800
|
||||
RAMLS5 : origin = 0x0000A800, length = 0x00000800
|
||||
RAMLS6 : origin = 0x0000B000, length = 0x00000800
|
||||
RAMLS7 : origin = 0x0000B800, length = 0x00000800
|
||||
|
||||
RAMGS0 : origin = 0x0000C000, length = 0x00001000
|
||||
RAMGS1 : origin = 0x0000D000, length = 0x00001000
|
||||
RAMGS2 : origin = 0x0000E000, length = 0x00001000
|
||||
RAMGS3 : origin = 0x0000F000, length = 0x00001000
|
||||
|
||||
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
|
||||
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
|
||||
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
|
||||
/* Flash sectors */
|
||||
/* BANK 0 */
|
||||
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE
|
||||
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
|
||||
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
|
||||
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
|
||||
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
|
||||
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
|
||||
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
|
||||
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
|
||||
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
|
||||
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
|
||||
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
|
||||
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
|
||||
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
|
||||
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
|
||||
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
|
||||
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
|
||||
|
||||
/* BANK 1 */
|
||||
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
|
||||
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
|
||||
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
|
||||
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
|
||||
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
|
||||
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
|
||||
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
|
||||
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
|
||||
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
|
||||
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
|
||||
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
|
||||
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
|
||||
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
|
||||
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
|
||||
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
|
||||
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
|
||||
|
||||
/* BANK 2 */
|
||||
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
|
||||
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
|
||||
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
|
||||
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
|
||||
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
|
||||
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
|
||||
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
|
||||
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
|
||||
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
|
||||
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
|
||||
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
|
||||
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
|
||||
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
|
||||
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
|
||||
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
|
||||
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
testInput : > RAMGS0,
|
||||
crc_table(linkerCrcTable, algorithm = CRC24_FLEXRAY)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,131 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
|
||||
|
||||
RAMM0 : origin = 0x00000128, length = 0x000002D8
|
||||
RAMM1 : origin = 0x00000400, length = 0x00000380 /* on-chip RAM block M1 */
|
||||
BOOT_RSVD_SYSBIOS: origin = 0x00000780, length = 0x00000080
|
||||
|
||||
|
||||
RAMLS0 : origin = 0x00008000, length = 0x00000800
|
||||
RAMLS1 : origin = 0x00008800, length = 0x00000800
|
||||
RAMLS2 : origin = 0x00009000, length = 0x00000800
|
||||
RAMLS3 : origin = 0x00009800, length = 0x00000800
|
||||
RAMLS4 : origin = 0x0000A000, length = 0x00000800
|
||||
RAMLS5 : origin = 0x0000A800, length = 0x00000800
|
||||
RAMLS6 : origin = 0x0000B000, length = 0x00000800
|
||||
RAMLS7 : origin = 0x0000B800, length = 0x00000800
|
||||
|
||||
RAMGS0 : origin = 0x0000C000, length = 0x00001000
|
||||
RAMGS1 : origin = 0x0000D000, length = 0x00001000
|
||||
RAMGS2 : origin = 0x0000E000, length = 0x00001000
|
||||
RAMGS3 : origin = 0x0000F000, length = 0x00001000
|
||||
|
||||
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
|
||||
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
|
||||
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
|
||||
/* Flash sectors */
|
||||
/* BANK 0 */
|
||||
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE
|
||||
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
|
||||
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
|
||||
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
|
||||
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
|
||||
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
|
||||
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
|
||||
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
|
||||
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
|
||||
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
|
||||
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
|
||||
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
|
||||
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
|
||||
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
|
||||
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
|
||||
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
|
||||
|
||||
/* BANK 1 */
|
||||
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
|
||||
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
|
||||
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
|
||||
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
|
||||
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
|
||||
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
|
||||
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
|
||||
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
|
||||
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
|
||||
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
|
||||
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
|
||||
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
|
||||
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
|
||||
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
|
||||
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
|
||||
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
|
||||
|
||||
/* BANK 2 */
|
||||
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
|
||||
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
|
||||
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
|
||||
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
|
||||
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
|
||||
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
|
||||
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
|
||||
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
|
||||
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
|
||||
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
|
||||
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
|
||||
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
|
||||
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
|
||||
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
|
||||
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
|
||||
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : >> RAMLS6 | RAMLS7
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMGS0, RUN_START(testInputRunStart){
|
||||
testInput :{} LOAD = RAMGS0,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
crc_table(linkerCrcTable, algorithm = CRC32_PRIME)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC32_C)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,126 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x00000002, length = 0x00000126
|
||||
|
||||
RAMM0 : origin = 0x00000128, length = 0x000002D8
|
||||
RAMM1 : origin = 0x00000400, length = 0x00000380 /* on-chip RAM block M1 */
|
||||
BOOT_RSVD_SYSBIOS: origin = 0x00000780, length = 0x00000080
|
||||
|
||||
|
||||
RAMLS0 : origin = 0x00008000, length = 0x00000800
|
||||
RAMLS1 : origin = 0x00008800, length = 0x00000800
|
||||
RAMLS2 : origin = 0x00009000, length = 0x00000800
|
||||
RAMLS3 : origin = 0x00009800, length = 0x00000800
|
||||
RAMLS4 : origin = 0x0000A000, length = 0x00000800
|
||||
RAMLS5 : origin = 0x0000A800, length = 0x00000800
|
||||
RAMLS6 : origin = 0x0000B000, length = 0x00000800
|
||||
RAMLS7 : origin = 0x0000B800, length = 0x00000800
|
||||
|
||||
RAMGS0 : origin = 0x0000C000, length = 0x00001000
|
||||
RAMGS1 : origin = 0x0000D000, length = 0x00001000
|
||||
RAMGS2 : origin = 0x0000E000, length = 0x00001000
|
||||
RAMGS3 : origin = 0x0000F000, length = 0x00001000
|
||||
|
||||
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
|
||||
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
|
||||
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
|
||||
/* Flash sectors */
|
||||
/* BANK 0 */
|
||||
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE
|
||||
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
|
||||
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
|
||||
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
|
||||
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
|
||||
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
|
||||
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
|
||||
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
|
||||
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
|
||||
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
|
||||
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
|
||||
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
|
||||
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
|
||||
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
|
||||
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
|
||||
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
|
||||
|
||||
/* BANK 1 */
|
||||
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
|
||||
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
|
||||
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
|
||||
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
|
||||
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
|
||||
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
|
||||
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
|
||||
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
|
||||
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
|
||||
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
|
||||
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
|
||||
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
|
||||
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
|
||||
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
|
||||
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
|
||||
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
|
||||
|
||||
/* BANK 2 */
|
||||
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
|
||||
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
|
||||
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
|
||||
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
|
||||
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
|
||||
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
|
||||
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
|
||||
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
|
||||
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
|
||||
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
|
||||
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
|
||||
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
|
||||
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
|
||||
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
|
||||
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
|
||||
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
testInput : > RAMGS0,
|
||||
crc_table(linkerCrcTable, algorithm = CRC8_PRIME)
|
||||
.TI.crctab : > RAMGS0
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,106 @@
|
||||
MEMORY
|
||||
{
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x0001B0, length = 0x000250
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD0 : origin = 0x00C000, length = 0x000800
|
||||
RAMD1 : origin = 0x00C800, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMLS6 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS7 : origin = 0x00B800, length = 0x000800
|
||||
RAMGS0 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS3 : origin = 0x010000, length = 0x001000
|
||||
RAMGS4 : origin = 0x011000, length = 0x001000
|
||||
RAMGS5 : origin = 0x012000, length = 0x001000
|
||||
RAMGS6 : origin = 0x013000, length = 0x001000
|
||||
RAMGS7 : origin = 0x014000, length = 0x001000
|
||||
RAMGS8 : origin = 0x015000, length = 0x001000
|
||||
RAMGS9 : origin = 0x016000, length = 0x001000
|
||||
RAMGS10 : origin = 0x017000, length = 0x001000
|
||||
RAMGS11 : origin = 0x018000, length = 0x001000
|
||||
RAMGS12 : origin = 0x019000, length = 0x001000
|
||||
RAMGS13 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01B000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01C000, length = 0x000FF8
|
||||
// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
/* Flash sectors */
|
||||
FLASH0 : origin = 0x080000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
|
||||
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
|
||||
|
||||
CPUTOCMRAM : origin = 0x039000, length = 0x000800
|
||||
CMTOCPURAM : origin = 0x038000, length = 0x000800
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMD0 | RAMD1 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS7
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5 | RAMGS8
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
testInput : > RAMGS0
|
||||
TestOutput : > RAMGS0
|
||||
.TI.crctab : > RAMGS0
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0, type=NOINIT
|
||||
ramgs1 : > RAMGS1, type=NOINIT
|
||||
|
||||
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
|
||||
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
|
||||
MSGRAM_CPU_TO_CM > CPUTOCMRAM, type=NOINIT
|
||||
MSGRAM_CM_TO_CPU > CMTOCPURAM, type=NOINIT
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,119 @@
|
||||
MEMORY
|
||||
{
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x0001B0, length = 0x000250
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD0 : origin = 0x00C000, length = 0x000800
|
||||
RAMD1 : origin = 0x00C800, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMLS6 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS7 : origin = 0x00B800, length = 0x000800
|
||||
RAMGS0 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS3 : origin = 0x010000, length = 0x001000
|
||||
RAMGS4 : origin = 0x011000, length = 0x001000
|
||||
RAMGS5 : origin = 0x012000, length = 0x001000
|
||||
RAMGS6 : origin = 0x013000, length = 0x001000
|
||||
RAMGS7 : origin = 0x014000, length = 0x001000
|
||||
RAMGS8 : origin = 0x015000, length = 0x001000
|
||||
RAMGS9 : origin = 0x016000, length = 0x001000
|
||||
RAMGS10 : origin = 0x017000, length = 0x001000
|
||||
RAMGS11 : origin = 0x018000, length = 0x001000
|
||||
RAMGS12 : origin = 0x019000, length = 0x001000
|
||||
RAMGS13 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01B000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01C000, length = 0x000FF8
|
||||
// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
/* Flash sectors */
|
||||
FLASH0 : origin = 0x080000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
|
||||
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
|
||||
|
||||
CPUTOCMRAM : origin = 0x039000, length = 0x000800
|
||||
CMTOCPURAM : origin = 0x038000, length = 0x000800
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMD0 | RAMD1 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMGS0, RUN_START(testInputRunStart){
|
||||
testInput :{} LOAD = RAMGS0,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
crc_table(linkerCrcTable, algorithm = CRC16_802_15_4)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC16_ALT)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0, type=NOINIT
|
||||
ramgs1 : > RAMGS1, type=NOINIT
|
||||
|
||||
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
|
||||
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
|
||||
MSGRAM_CPU_TO_CM > CPUTOCMRAM, type=NOINIT
|
||||
MSGRAM_CM_TO_CPU > CMTOCPURAM, type=NOINIT
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter_RegsFile : > RAMGS0
|
||||
Filter1_RegsFile : > RAMGS1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, fill=0x3333
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,115 @@
|
||||
MEMORY
|
||||
{
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x0001B0, length = 0x000250
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD0 : origin = 0x00C000, length = 0x000800
|
||||
RAMD1 : origin = 0x00C800, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMLS6 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS7 : origin = 0x00B800, length = 0x000800
|
||||
RAMGS0 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS3 : origin = 0x010000, length = 0x001000
|
||||
RAMGS4 : origin = 0x011000, length = 0x001000
|
||||
RAMGS5 : origin = 0x012000, length = 0x001000
|
||||
RAMGS6 : origin = 0x013000, length = 0x001000
|
||||
RAMGS7 : origin = 0x014000, length = 0x001000
|
||||
RAMGS8 : origin = 0x015000, length = 0x001000
|
||||
RAMGS9 : origin = 0x016000, length = 0x001000
|
||||
RAMGS10 : origin = 0x017000, length = 0x001000
|
||||
RAMGS11 : origin = 0x018000, length = 0x001000
|
||||
RAMGS12 : origin = 0x019000, length = 0x001000
|
||||
RAMGS13 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01B000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01C000, length = 0x000FF8
|
||||
// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
/* Flash sectors */
|
||||
FLASH0 : origin = 0x080000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
|
||||
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
|
||||
|
||||
CPUTOCMRAM : origin = 0x039000, length = 0x000800
|
||||
CMTOCPURAM : origin = 0x038000, length = 0x000800
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMD0 | RAMD1 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
testInput : > RAMGS0,
|
||||
crc_table(linkerCrcTable, algorithm = CRC24_FLEXRAY)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0, type=NOINIT
|
||||
ramgs1 : > RAMGS1, type=NOINIT
|
||||
|
||||
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
|
||||
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
|
||||
MSGRAM_CPU_TO_CM > CPUTOCMRAM, type=NOINIT
|
||||
MSGRAM_CM_TO_CPU > CMTOCPURAM, type=NOINIT
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter_RegsFile : > RAMGS0
|
||||
Filter1_RegsFile : > RAMGS1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, fill=0x3333
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,119 @@
|
||||
MEMORY
|
||||
{
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x0001B0, length = 0x000250
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD0 : origin = 0x00C000, length = 0x000800
|
||||
RAMD1 : origin = 0x00C800, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMLS67 : origin = 0x00B000, length = 0x001000
|
||||
// RAMLS7 : origin = 0x00B800, length = 0x000800
|
||||
RAMGS0 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS3 : origin = 0x010000, length = 0x001000
|
||||
RAMGS4 : origin = 0x011000, length = 0x001000
|
||||
RAMGS5 : origin = 0x012000, length = 0x001000
|
||||
RAMGS6 : origin = 0x013000, length = 0x001000
|
||||
RAMGS7 : origin = 0x014000, length = 0x001000
|
||||
RAMGS8 : origin = 0x015000, length = 0x001000
|
||||
RAMGS9 : origin = 0x016000, length = 0x001000
|
||||
RAMGS10 : origin = 0x017000, length = 0x001000
|
||||
RAMGS11 : origin = 0x018000, length = 0x001000
|
||||
RAMGS12 : origin = 0x019000, length = 0x001000
|
||||
RAMGS13 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01B000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01C000, length = 0x000FF8
|
||||
// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
/* Flash sectors */
|
||||
FLASH0 : origin = 0x080000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
|
||||
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
|
||||
|
||||
CPUTOCMRAM : origin = 0x039000, length = 0x000800
|
||||
CMTOCPURAM : origin = 0x038000, length = 0x000800
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMD0 | RAMD1 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS67
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMGS0, RUN_START(testInputRunStart){
|
||||
testInput :{} LOAD = RAMGS0,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
crc_table(linkerCrcTable, algorithm = CRC32_PRIME)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC32_C)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0, type=NOINIT
|
||||
ramgs1 : > RAMGS1, type=NOINIT
|
||||
|
||||
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
|
||||
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
|
||||
MSGRAM_CPU_TO_CM > CPUTOCMRAM, type=NOINIT
|
||||
MSGRAM_CM_TO_CPU > CMTOCPURAM, type=NOINIT
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter_RegsFile : > RAMGS0
|
||||
Filter1_RegsFile : > RAMGS1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, fill=0x3333
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,114 @@
|
||||
MEMORY
|
||||
{
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x0001B0, length = 0x000250
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD0 : origin = 0x00C000, length = 0x000800
|
||||
RAMD1 : origin = 0x00C800, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMLS6 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS7 : origin = 0x00B800, length = 0x000800
|
||||
RAMGS0 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS3 : origin = 0x010000, length = 0x001000
|
||||
RAMGS4 : origin = 0x011000, length = 0x001000
|
||||
RAMGS5 : origin = 0x012000, length = 0x001000
|
||||
RAMGS6 : origin = 0x013000, length = 0x001000
|
||||
RAMGS7 : origin = 0x014000, length = 0x001000
|
||||
RAMGS8 : origin = 0x015000, length = 0x001000
|
||||
RAMGS9 : origin = 0x016000, length = 0x001000
|
||||
RAMGS10 : origin = 0x017000, length = 0x001000
|
||||
RAMGS11 : origin = 0x018000, length = 0x001000
|
||||
RAMGS12 : origin = 0x019000, length = 0x001000
|
||||
RAMGS13 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01B000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01C000, length = 0x000FF8
|
||||
// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
/* Flash sectors */
|
||||
FLASH0 : origin = 0x080000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
|
||||
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
|
||||
|
||||
CPUTOCMRAM : origin = 0x039000, length = 0x000800
|
||||
CMTOCPURAM : origin = 0x038000, length = 0x000800
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMD0 | RAMD1 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
testInput : > RAMGS0,
|
||||
crc_table(linkerCrcTable, algorithm = CRC8_PRIME)
|
||||
.TI.crctab : > RAMGS0
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0, type=NOINIT
|
||||
ramgs1 : > RAMGS1, type=NOINIT
|
||||
|
||||
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
|
||||
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
|
||||
MSGRAM_CPU_TO_CM > CPUTOCMRAM, type=NOINIT
|
||||
MSGRAM_CM_TO_CPU > CMTOCPURAM, type=NOINIT
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter_RegsFile : > RAMGS0
|
||||
Filter1_RegsFile : > RAMGS1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, fill=0x3333
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,83 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x080000, length = 0x000002 // Update the codestart location as needed
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000126 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x000128, length = 0x0002D8
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMLS6 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS7 : origin = 0x00B800, length = 0x000800
|
||||
RAMLS8 : origin = 0x014000, length = 0x002000 // When configured as CLA program use the address 0x4000
|
||||
RAMLS9 : origin = 0x016000, length = 0x002000 // When configured as CLA program use the address 0x6000
|
||||
|
||||
// RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory
|
||||
// RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x002000
|
||||
RAMGS1 : origin = 0x00E000, length = 0x002000
|
||||
RAMGS2 : origin = 0x010000, length = 0x002000
|
||||
RAMGS3 : origin = 0x012000, length = 0x002000
|
||||
|
||||
/* Flash Banks (128 sectors each) */
|
||||
FLASH_BANK0 : origin = 0x080002, length = 0x1FFFE
|
||||
FLASH_BANK1 : origin = 0x0A0000, length = 0x20000
|
||||
FLASH_BANK2 : origin = 0x0C0000, length = 0x20000
|
||||
FLASH_BANK3 : origin = 0x0E0000, length = 0x20000
|
||||
FLASH_BANK4 : origin = 0x100000, length = 0x20000
|
||||
|
||||
|
||||
CLATOCPURAM : origin = 0x001480, length = 0x000080
|
||||
CPUTOCLARAM : origin = 0x001500, length = 0x000080
|
||||
CLATODMARAM : origin = 0x001680, length = 0x000080
|
||||
DMATOCLARAM : origin = 0x001700, length = 0x000080
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >>RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS7
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5 | RAMGS3
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
testInput : > RAMGS0
|
||||
TestOutput : > RAMGS0
|
||||
.TI.crctab : > RAMGS0
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,87 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x080000, length = 0x000002 // Update the codestart location as needed
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000126 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x000128, length = 0x0002D8
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMLS6 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS7 : origin = 0x00B800, length = 0x000800
|
||||
RAMLS8 : origin = 0x014000, length = 0x002000 // When configured as CLA program use the address 0x4000
|
||||
RAMLS9 : origin = 0x016000, length = 0x002000 // When configured as CLA program use the address 0x6000
|
||||
|
||||
// RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory
|
||||
// RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x002000
|
||||
RAMGS1 : origin = 0x00E000, length = 0x002000
|
||||
RAMGS2 : origin = 0x010000, length = 0x002000
|
||||
RAMGS3 : origin = 0x012000, length = 0x002000
|
||||
|
||||
/* Flash Banks (128 sectors each) */
|
||||
FLASH_BANK0 : origin = 0x080002, length = 0x1FFFE
|
||||
FLASH_BANK1 : origin = 0x0A0000, length = 0x20000
|
||||
FLASH_BANK2 : origin = 0x0C0000, length = 0x20000
|
||||
FLASH_BANK3 : origin = 0x0E0000, length = 0x20000
|
||||
FLASH_BANK4 : origin = 0x100000, length = 0x20000
|
||||
|
||||
|
||||
CLATOCPURAM : origin = 0x001480, length = 0x000080
|
||||
CPUTOCLARAM : origin = 0x001500, length = 0x000080
|
||||
CLATODMARAM : origin = 0x001680, length = 0x000080
|
||||
DMATOCLARAM : origin = 0x001700, length = 0x000080
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMGS0, RUN_START(testInputRunStart){
|
||||
testInput :{} LOAD = RAMGS0,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
crc_table(linkerCrcTable, algorithm = CRC16_802_15_4)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC16_ALT)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,83 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x080000, length = 0x000002 // Update the codestart location as needed
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000126 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x000128, length = 0x0002D8
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMLS6 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS7 : origin = 0x00B800, length = 0x000800
|
||||
RAMLS8 : origin = 0x014000, length = 0x002000 // When configured as CLA program use the address 0x4000
|
||||
RAMLS9 : origin = 0x016000, length = 0x002000 // When configured as CLA program use the address 0x6000
|
||||
|
||||
// RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory
|
||||
// RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x002000
|
||||
RAMGS1 : origin = 0x00E000, length = 0x002000
|
||||
RAMGS2 : origin = 0x010000, length = 0x002000
|
||||
RAMGS3 : origin = 0x012000, length = 0x002000
|
||||
|
||||
/* Flash Banks (128 sectors each) */
|
||||
FLASH_BANK0 : origin = 0x080002, length = 0x1FFFE
|
||||
FLASH_BANK1 : origin = 0x0A0000, length = 0x20000
|
||||
FLASH_BANK2 : origin = 0x0C0000, length = 0x20000
|
||||
FLASH_BANK3 : origin = 0x0E0000, length = 0x20000
|
||||
FLASH_BANK4 : origin = 0x100000, length = 0x20000
|
||||
|
||||
|
||||
CLATOCPURAM : origin = 0x001480, length = 0x000080
|
||||
CPUTOCLARAM : origin = 0x001500, length = 0x000080
|
||||
CLATODMARAM : origin = 0x001680, length = 0x000080
|
||||
DMATOCLARAM : origin = 0x001700, length = 0x000080
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
testInput : > RAMGS0,
|
||||
crc_table(linkerCrcTable, algorithm = CRC24_FLEXRAY)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,87 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x080000, length = 0x000002 // Update the codestart location as needed
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000126 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x000128, length = 0x0002D8
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMLS6 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS7 : origin = 0x00B800, length = 0x000800
|
||||
RAMLS8 : origin = 0x014000, length = 0x002000 // When configured as CLA program use the address 0x4000
|
||||
RAMLS9 : origin = 0x016000, length = 0x002000 // When configured as CLA program use the address 0x6000
|
||||
|
||||
// RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory
|
||||
// RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x002000
|
||||
RAMGS1 : origin = 0x00E000, length = 0x002000
|
||||
RAMGS2 : origin = 0x010000, length = 0x002000
|
||||
RAMGS3 : origin = 0x012000, length = 0x002000
|
||||
|
||||
/* Flash Banks (128 sectors each) */
|
||||
FLASH_BANK0 : origin = 0x080002, length = 0x1FFFE
|
||||
FLASH_BANK1 : origin = 0x0A0000, length = 0x20000
|
||||
FLASH_BANK2 : origin = 0x0C0000, length = 0x20000
|
||||
FLASH_BANK3 : origin = 0x0E0000, length = 0x20000
|
||||
FLASH_BANK4 : origin = 0x100000, length = 0x20000
|
||||
|
||||
|
||||
CLATOCPURAM : origin = 0x001480, length = 0x000080
|
||||
CPUTOCLARAM : origin = 0x001500, length = 0x000080
|
||||
CLATODMARAM : origin = 0x001680, length = 0x000080
|
||||
DMATOCLARAM : origin = 0x001700, length = 0x000080
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : >> RAMLS6 | RAMLS7
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMGS0, RUN_START(testInputRunStart){
|
||||
testInput :{} LOAD = RAMGS0,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
crc_table(linkerCrcTable, algorithm = CRC32_PRIME)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC32_C)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,82 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x080000, length = 0x000002 // Update the codestart location as needed
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000126 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x000128, length = 0x0002D8
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMLS6 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS7 : origin = 0x00B800, length = 0x000800
|
||||
RAMLS8 : origin = 0x014000, length = 0x002000 // When configured as CLA program use the address 0x4000
|
||||
RAMLS9 : origin = 0x016000, length = 0x002000 // When configured as CLA program use the address 0x6000
|
||||
|
||||
// RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory
|
||||
// RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x002000
|
||||
RAMGS1 : origin = 0x00E000, length = 0x002000
|
||||
RAMGS2 : origin = 0x010000, length = 0x002000
|
||||
RAMGS3 : origin = 0x012000, length = 0x002000
|
||||
|
||||
/* Flash Banks (128 sectors each) */
|
||||
FLASH_BANK0 : origin = 0x080002, length = 0x1FFFE
|
||||
FLASH_BANK1 : origin = 0x0A0000, length = 0x20000
|
||||
FLASH_BANK2 : origin = 0x0C0000, length = 0x20000
|
||||
FLASH_BANK3 : origin = 0x0E0000, length = 0x20000
|
||||
FLASH_BANK4 : origin = 0x100000, length = 0x20000
|
||||
|
||||
|
||||
CLATOCPURAM : origin = 0x001480, length = 0x000080
|
||||
CPUTOCLARAM : origin = 0x001500, length = 0x000080
|
||||
CLATODMARAM : origin = 0x001680, length = 0x000080
|
||||
DMATOCLARAM : origin = 0x001700, length = 0x000080
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
testInput : > RAMGS0,
|
||||
crc_table(linkerCrcTable, algorithm = CRC8_PRIME)
|
||||
.TI.crctab : > RAMGS0
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,129 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x0001B1, length = 0x00024F
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
|
||||
|
||||
RAMLS0 : origin = 0x00008000, length = 0x00000800
|
||||
RAMLS1 : origin = 0x00008800, length = 0x00000800
|
||||
RAMLS2 : origin = 0x00009000, length = 0x00000800
|
||||
RAMLS3 : origin = 0x00009800, length = 0x00000800
|
||||
RAMLS4 : origin = 0x0000A000, length = 0x00000800
|
||||
RAMLS5 : origin = 0x0000A800, length = 0x00000800
|
||||
RAMLS6 : origin = 0x0000B000, length = 0x00000800
|
||||
RAMLS7 : origin = 0x0000B800, length = 0x00000800
|
||||
RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000
|
||||
RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000
|
||||
|
||||
RAMGS0 : origin = 0x010000, length = 0x002000
|
||||
RAMGS1 : origin = 0x012000, length = 0x002000
|
||||
RAMGS2 : origin = 0x014000, length = 0x002000
|
||||
RAMGS3 : origin = 0x016000, length = 0x002000
|
||||
RAMGS4 : origin = 0x018000, length = 0x002000
|
||||
|
||||
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
|
||||
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
|
||||
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
|
||||
/* Flash sectors */
|
||||
/* BANK 0 */
|
||||
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE
|
||||
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
|
||||
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
|
||||
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
|
||||
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
|
||||
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
|
||||
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
|
||||
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
|
||||
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
|
||||
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
|
||||
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
|
||||
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
|
||||
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
|
||||
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
|
||||
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
|
||||
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
|
||||
|
||||
/* BANK 1 */
|
||||
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
|
||||
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
|
||||
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
|
||||
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
|
||||
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
|
||||
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
|
||||
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
|
||||
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
|
||||
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
|
||||
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
|
||||
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
|
||||
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
|
||||
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
|
||||
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
|
||||
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
|
||||
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
|
||||
|
||||
/* BANK 2 */
|
||||
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
|
||||
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
|
||||
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
|
||||
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
|
||||
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
|
||||
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
|
||||
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
|
||||
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
|
||||
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
|
||||
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
|
||||
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
|
||||
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
|
||||
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
|
||||
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
|
||||
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
|
||||
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >>RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS7
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5 | RAMGS3
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
testInput : > RAMGS0
|
||||
TestOutput : > RAMGS0
|
||||
.TI.crctab : > RAMGS0
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,133 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMM0 : origin = 0x0001B1, length = 0x00024F
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
|
||||
RAMLS0 : origin = 0x00008000, length = 0x00000800
|
||||
RAMLS1 : origin = 0x00008800, length = 0x00000800
|
||||
RAMLS2 : origin = 0x00009000, length = 0x00000800
|
||||
RAMLS3 : origin = 0x00009800, length = 0x00000800
|
||||
RAMLS4 : origin = 0x0000A000, length = 0x00000800
|
||||
RAMLS5 : origin = 0x0000A800, length = 0x00000800
|
||||
RAMLS6 : origin = 0x0000B000, length = 0x00000800
|
||||
RAMLS7 : origin = 0x0000B800, length = 0x00000800
|
||||
RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000
|
||||
RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000
|
||||
|
||||
RAMGS0 : origin = 0x010000, length = 0x002000
|
||||
RAMGS1 : origin = 0x012000, length = 0x002000
|
||||
RAMGS2 : origin = 0x014000, length = 0x002000
|
||||
RAMGS3 : origin = 0x016000, length = 0x002000
|
||||
RAMGS4 : origin = 0x018000, length = 0x002000
|
||||
|
||||
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
|
||||
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
|
||||
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
|
||||
/* Flash sectors */
|
||||
/* BANK 0 */
|
||||
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE
|
||||
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
|
||||
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
|
||||
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
|
||||
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
|
||||
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
|
||||
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
|
||||
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
|
||||
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
|
||||
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
|
||||
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
|
||||
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
|
||||
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
|
||||
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
|
||||
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
|
||||
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
|
||||
|
||||
/* BANK 1 */
|
||||
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
|
||||
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
|
||||
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
|
||||
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
|
||||
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
|
||||
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
|
||||
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
|
||||
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
|
||||
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
|
||||
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
|
||||
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
|
||||
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
|
||||
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
|
||||
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
|
||||
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
|
||||
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
|
||||
|
||||
/* BANK 2 */
|
||||
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
|
||||
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
|
||||
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
|
||||
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
|
||||
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
|
||||
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
|
||||
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
|
||||
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
|
||||
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
|
||||
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
|
||||
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
|
||||
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
|
||||
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
|
||||
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
|
||||
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
|
||||
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
|
||||
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMGS0, RUN_START(testInputRunStart){
|
||||
testInput :{} LOAD = RAMGS0,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
crc_table(linkerCrcTable, algorithm = CRC16_802_15_4)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC16_ALT)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,129 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x0001B1, length = 0x00024F
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
|
||||
|
||||
RAMLS0 : origin = 0x00008000, length = 0x00000800
|
||||
RAMLS1 : origin = 0x00008800, length = 0x00000800
|
||||
RAMLS2 : origin = 0x00009000, length = 0x00000800
|
||||
RAMLS3 : origin = 0x00009800, length = 0x00000800
|
||||
RAMLS4 : origin = 0x0000A000, length = 0x00000800
|
||||
RAMLS5 : origin = 0x0000A800, length = 0x00000800
|
||||
RAMLS6 : origin = 0x0000B000, length = 0x00000800
|
||||
RAMLS7 : origin = 0x0000B800, length = 0x00000800
|
||||
RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000
|
||||
RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000
|
||||
|
||||
RAMGS0 : origin = 0x010000, length = 0x002000
|
||||
RAMGS1 : origin = 0x012000, length = 0x002000
|
||||
RAMGS2 : origin = 0x014000, length = 0x002000
|
||||
RAMGS3 : origin = 0x016000, length = 0x002000
|
||||
RAMGS4 : origin = 0x018000, length = 0x002000
|
||||
|
||||
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
|
||||
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
|
||||
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
|
||||
/* Flash sectors */
|
||||
/* BANK 0 */
|
||||
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE
|
||||
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
|
||||
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
|
||||
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
|
||||
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
|
||||
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
|
||||
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
|
||||
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
|
||||
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
|
||||
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
|
||||
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
|
||||
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
|
||||
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
|
||||
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
|
||||
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
|
||||
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
|
||||
|
||||
/* BANK 1 */
|
||||
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
|
||||
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
|
||||
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
|
||||
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
|
||||
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
|
||||
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
|
||||
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
|
||||
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
|
||||
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
|
||||
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
|
||||
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
|
||||
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
|
||||
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
|
||||
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
|
||||
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
|
||||
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
|
||||
|
||||
/* BANK 2 */
|
||||
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
|
||||
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
|
||||
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
|
||||
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
|
||||
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
|
||||
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
|
||||
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
|
||||
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
|
||||
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
|
||||
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
|
||||
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
|
||||
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
|
||||
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
|
||||
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
|
||||
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
|
||||
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
testInput : > RAMGS0,
|
||||
crc_table(linkerCrcTable, algorithm = CRC24_FLEXRAY)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,133 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x0001B1, length = 0x00024F
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
|
||||
|
||||
RAMLS0 : origin = 0x00008000, length = 0x00000800
|
||||
RAMLS1 : origin = 0x00008800, length = 0x00000800
|
||||
RAMLS2 : origin = 0x00009000, length = 0x00000800
|
||||
RAMLS3 : origin = 0x00009800, length = 0x00000800
|
||||
RAMLS4 : origin = 0x0000A000, length = 0x00000800
|
||||
RAMLS5 : origin = 0x0000A800, length = 0x00000800
|
||||
RAMLS6 : origin = 0x0000B000, length = 0x00000800
|
||||
RAMLS7 : origin = 0x0000B800, length = 0x00000800
|
||||
RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000
|
||||
RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000
|
||||
|
||||
RAMGS0 : origin = 0x010000, length = 0x002000
|
||||
RAMGS1 : origin = 0x012000, length = 0x002000
|
||||
RAMGS2 : origin = 0x014000, length = 0x002000
|
||||
RAMGS3 : origin = 0x016000, length = 0x002000
|
||||
RAMGS4 : origin = 0x018000, length = 0x002000
|
||||
|
||||
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
|
||||
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
|
||||
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
|
||||
/* Flash sectors */
|
||||
/* BANK 0 */
|
||||
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE
|
||||
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
|
||||
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
|
||||
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
|
||||
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
|
||||
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
|
||||
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
|
||||
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
|
||||
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
|
||||
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
|
||||
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
|
||||
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
|
||||
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
|
||||
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
|
||||
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
|
||||
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
|
||||
|
||||
/* BANK 1 */
|
||||
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
|
||||
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
|
||||
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
|
||||
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
|
||||
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
|
||||
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
|
||||
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
|
||||
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
|
||||
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
|
||||
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
|
||||
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
|
||||
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
|
||||
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
|
||||
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
|
||||
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
|
||||
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
|
||||
|
||||
/* BANK 2 */
|
||||
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
|
||||
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
|
||||
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
|
||||
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
|
||||
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
|
||||
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
|
||||
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
|
||||
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
|
||||
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
|
||||
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
|
||||
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
|
||||
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
|
||||
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
|
||||
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
|
||||
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
|
||||
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : >> RAMLS6 | RAMLS7
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
.TI.crctab : > RAMGS0
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMGS0, RUN_START(testInputRunStart){
|
||||
testInput :{} LOAD = RAMGS0,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
crc_table(linkerCrcTable, algorithm = CRC32_PRIME)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC32_C)
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,128 @@
|
||||
MEMORY
|
||||
{
|
||||
BEGIN : origin = 0x00000000, length = 0x00000002
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x0001B1, length = 0x00024F
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
|
||||
|
||||
RAMLS0 : origin = 0x00008000, length = 0x00000800
|
||||
RAMLS1 : origin = 0x00008800, length = 0x00000800
|
||||
RAMLS2 : origin = 0x00009000, length = 0x00000800
|
||||
RAMLS3 : origin = 0x00009800, length = 0x00000800
|
||||
RAMLS4 : origin = 0x0000A000, length = 0x00000800
|
||||
RAMLS5 : origin = 0x0000A800, length = 0x00000800
|
||||
RAMLS6 : origin = 0x0000B000, length = 0x00000800
|
||||
RAMLS7 : origin = 0x0000B800, length = 0x00000800
|
||||
RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000
|
||||
RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000
|
||||
|
||||
RAMGS0 : origin = 0x010000, length = 0x002000
|
||||
RAMGS1 : origin = 0x012000, length = 0x002000
|
||||
RAMGS2 : origin = 0x014000, length = 0x002000
|
||||
RAMGS3 : origin = 0x016000, length = 0x002000
|
||||
RAMGS4 : origin = 0x018000, length = 0x002000
|
||||
|
||||
BOOTROM : origin = 0x003F8000, length = 0x00007FC0
|
||||
SECURE_ROM : origin = 0x003F2000, length = 0x00006000
|
||||
|
||||
|
||||
RESET : origin = 0x003FFFC0, length = 0x00000002
|
||||
|
||||
/* Flash sectors */
|
||||
/* BANK 0 */
|
||||
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE
|
||||
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
|
||||
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
|
||||
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
|
||||
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
|
||||
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
|
||||
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
|
||||
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
|
||||
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
|
||||
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
|
||||
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
|
||||
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
|
||||
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
|
||||
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
|
||||
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
|
||||
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
|
||||
|
||||
/* BANK 1 */
|
||||
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
|
||||
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
|
||||
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
|
||||
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
|
||||
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
|
||||
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
|
||||
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
|
||||
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
|
||||
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
|
||||
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
|
||||
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
|
||||
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
|
||||
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
|
||||
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
|
||||
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
|
||||
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
|
||||
|
||||
/* BANK 2 */
|
||||
FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000
|
||||
FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000
|
||||
FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000
|
||||
FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000
|
||||
FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000
|
||||
FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000
|
||||
FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000
|
||||
FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000
|
||||
FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000
|
||||
FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000
|
||||
FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
|
||||
FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
|
||||
FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
|
||||
FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
|
||||
FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
|
||||
FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000
|
||||
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
|
||||
.cinit : > RAMM0
|
||||
.switch : > RAMM0
|
||||
.reset : > RESET, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5
|
||||
.bss:output : > RAMLS3
|
||||
.init_array : > RAMM0
|
||||
.const : > RAMLS5
|
||||
.data : > RAMLS5
|
||||
.sysmem : > RAMLS4
|
||||
testInput : > RAMGS0,
|
||||
crc_table(linkerCrcTable, algorithm = CRC8_PRIME)
|
||||
.TI.crctab : > RAMGS0
|
||||
#else
|
||||
.pinit : > RAMM0
|
||||
.ebss : >> RAMLS5 | RAMLS6
|
||||
.econst : > RAMLS5
|
||||
.esysmem : > RAMLS5
|
||||
#endif
|
||||
|
||||
ramgs0 : > RAMGS0
|
||||
ramgs1 : > RAMGS1
|
||||
|
||||
.TI.ramfunc : {} > RAMM0
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,154 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU0_CFFT16_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
.shadow : > RAMLS4, PAGE = 1
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.econst :>> RAMLS3 | RAMLS4 | RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,258 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU0_CRC_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File For VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2022 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
--diag_suppress=10082
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.init_array : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
|
||||
.TI.crctab : > RAMLS3, PAGE = 1
|
||||
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(testInputRunStart), PAGE = 1{
|
||||
UNION {
|
||||
UNION {
|
||||
testInput :{} LOAD = RAMLS3,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(linkerCrcTable,algorithm = CRC8_PRIME)
|
||||
}crc_table(linkerCrcTable,algorithm = CRC16_802_15_4)
|
||||
}crc_table(linkerCrcTable,algorithm = CRC16_ALT)
|
||||
}crc_table(linkerCrcTable,algorithm = CRC32_PRIME)
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(RamfuncsRunStart),
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.init_array : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
|
||||
.TI.crctab : > FLASHB, PAGE = 1
|
||||
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(testInputRunStart), PAGE = 1{
|
||||
UNION {
|
||||
UNION {
|
||||
testInput :{} LOAD = FLASHB,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(linkerCrcTable,algorithm = CRC8_PRIME)
|
||||
}crc_table(linkerCrcTable,algorithm = CRC16_802_15_4)
|
||||
}crc_table(linkerCrcTable,algorithm = CRC16_ALT)
|
||||
}crc_table(linkerCrcTable,algorithm = CRC32_PRIME)
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS4, PAGE = 1
|
||||
.bss : > RAMLS4, PAGE = 1
|
||||
.data : > RAMLS4, PAGE = 1
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
|
||||
.TI.crctab : > RAMLS3, PAGE = 1
|
||||
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(_testInputRunStart), PAGE = 1{
|
||||
UNION {
|
||||
UNION {
|
||||
testInput :{} LOAD = RAMLS3,
|
||||
LOAD_START(_testInputLoadStart),
|
||||
LOAD_SIZE(_testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(_linkerCrcTable,algorithm = CRC8_PRIME)
|
||||
}crc_table(_linkerCrcTable,algorithm = CRC16_802_15_4)
|
||||
}crc_table(_linkerCrcTable,algorithm = CRC16_ALT)
|
||||
}crc_table(_linkerCrcTable,algorithm = CRC32_PRIME)
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
|
||||
.TI.crctab : > FLASHB, PAGE = 1
|
||||
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(_testInputRunStart), PAGE = 1{
|
||||
UNION {
|
||||
UNION {
|
||||
testInput :{} LOAD = FLASHB,
|
||||
LOAD_START(_testInputLoadStart),
|
||||
LOAD_SIZE(_testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(_linkerCrcTable,algorithm = CRC8_PRIME)
|
||||
}crc_table(_linkerCrcTable,algorithm = CRC16_802_15_4)
|
||||
}crc_table(_linkerCrcTable,algorithm = CRC16_ALT)
|
||||
}crc_table(_linkerCrcTable,algorithm = CRC32_PRIME)
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS4, PAGE = 1
|
||||
.ebss : > RAMLS4, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
}
|
||||
|
||||
#endif
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,207 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU0_VITERBI_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2022 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS45 : origin = 0x010000, length = 0x002000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.init_array : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.const : > RAMGS45, PAGE = 1
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(RamfuncsRunStart),
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.init_array : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.const : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer_out : > RAMLS5, ALIGN = 2, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
.shadow : > RAMLS4, PAGE = 1
|
||||
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.bss : > RAMLS3, PAGE = 1
|
||||
.data : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMGS45, PAGE = 1
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer_out : > RAMLS5, ALIGN = 2, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.shadow : > RAMLS4, PAGE = 1
|
||||
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS4, PAGE = 1
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,160 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_CFFT_1024_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMGS0, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst :>> RAMGS3 | RAMGS4, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHD,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHC, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMGS5, ALIGN = 2048, PAGE = 1
|
||||
buffer2 : > RAMGS6, ALIGN = 2048, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS4, PAGE = 1
|
||||
.ebss : > RAMGS7, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,160 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_CFFT_128_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMLS3, ALIGN = 256, PAGE = 1
|
||||
buffer2 : > RAMLS4, ALIGN = 256, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS4, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,160 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_CFFT_256_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMGS3, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMGS4, ALIGN = 512, PAGE = 1
|
||||
buffer2 : > RAMGS5, ALIGN = 512, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS4, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,160 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_CFFT_32_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS3, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMLS3, ALIGN = 64, PAGE = 1
|
||||
buffer2 : > RAMLS4, ALIGN = 64, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,161 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_CFFT_512_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMGS3, PAGE = 1
|
||||
twiddleFactors : > RAMGS6, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMGS4, ALIGN = 1024, PAGE = 1
|
||||
buffer2 : > RAMGS5, ALIGN = 1024, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS4, PAGE = 1
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,160 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_CFFT_64_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS3, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMLS3, ALIGN = 128, PAGE = 1
|
||||
buffer2 : > RAMLS4, ALIGN = 128, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,243 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_CRC_16_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File For VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2022 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
--diag_suppress=10082
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.init_array : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
|
||||
.TI.crctab : > RAMLS3, PAGE = 1
|
||||
.const : > RAMLS4, PAGE = 1
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(testInputRunStart), PAGE = 1{
|
||||
testInput :{} LOAD = RAMLS3,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(linkerCrcTable, algorithm = CRC16_802_15_4)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC16_ALT)
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(RamfuncsRunStart),
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.init_array : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.const : > FLASHB, PAGE = 1
|
||||
.TI.crctab : > FLASHB, PAGE = 1
|
||||
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(testInputRunStart), PAGE = 1{
|
||||
testInput :{} LOAD = FLASHB,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(linkerCrcTable, algorithm = CRC16_802_15_4)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC16_ALT)
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.bss : > RAMLS3, PAGE = 1
|
||||
.data : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
|
||||
.TI.crctab : > RAMLS3, PAGE = 1
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(_testInputRunStart), PAGE = 1{
|
||||
testInput :{} LOAD = RAMLS3,
|
||||
LOAD_START(_testInputLoadStart),
|
||||
LOAD_SIZE(_testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(_linkerCrcTable, algorithm = CRC16_802_15_4)
|
||||
}crc_table(_linkerCrcTable, algorithm = CRC16_ALT)
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
.TI.crctab : > FLASHB, PAGE = 1
|
||||
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(_testInputRunStart), PAGE = 1{
|
||||
testInput :{} LOAD = FLASHB,
|
||||
LOAD_START(_testInputLoadStart),
|
||||
LOAD_SIZE(_testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(_linkerCrcTable, algorithm = CRC16_802_15_4)
|
||||
}crc_table(_linkerCrcTable, algorithm = CRC16_ALT)
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,215 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_CRC_24_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File For VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2022 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
#if defined(__TI_EABI__)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.init_array : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
|
||||
.TI.crctab : > RAMLS3, PAGE = 1
|
||||
.const : > RAMLS4, PAGE = 1
|
||||
/* Test specific sections */
|
||||
testInput : > RAMLS3, PAGE = 1,
|
||||
crc_table(linkerCrcTable, algorithm = CRC24_FLEXRAY)
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(RamfuncsRunStart),
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.init_array : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
|
||||
.TI.crctab : > FLASHB, PAGE = 1
|
||||
.const : > FLASHB, PAGE = 1
|
||||
/* Test specific sections */
|
||||
testInput : > FLASHB, PAGE = 1,
|
||||
crc_table(linkerCrcTable, algorithm = CRC24_FLEXRAY)
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.bss : > RAMLS3, PAGE = 1
|
||||
.data : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
|
||||
.TI.crctab : > RAMLS3, PAGE = 1
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
/* Test specific sections */
|
||||
testInput : > RAMLS3, PAGE = 1,
|
||||
crc_table(_linkerCrcTable, algorithm = CRC24_FLEXRAY)
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
|
||||
.TI.crctab : > FLASHB, PAGE = 1
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
/* Test specific sections */
|
||||
testInput : > FLASHB, PAGE = 1,
|
||||
crc_table(_linkerCrcTable, algorithm = CRC24_FLEXRAY)
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,242 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_CRC_32_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File For VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2022 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
--diag_suppress=10082
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.init_array : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.const :>> RAMLS4 | RAMLS5, PAGE = 1
|
||||
.TI.crctab : > RAMLS3, PAGE = 1
|
||||
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(testInputRunStart), PAGE = 1{
|
||||
testInput :{} LOAD = RAMLS3,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(linkerCrcTable, algorithm = CRC32_PRIME)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC32_C)
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHD,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(RamfuncsRunStart),
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.init_array : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.const :>> FLASHC, PAGE = 1
|
||||
.TI.crctab : > FLASHB, PAGE = 1
|
||||
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(testInputRunStart), PAGE = 1{
|
||||
testInput :{} LOAD = FLASHB,
|
||||
LOAD_START(testInputLoadStart),
|
||||
LOAD_SIZE(testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(linkerCrcTable, algorithm = CRC32_PRIME)
|
||||
}crc_table(linkerCrcTable, algorithm = CRC32_C)
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.bss : > RAMLS4, PAGE = 1
|
||||
.data : > RAMLS4, PAGE = 1
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst :>> RAMLS4 | RAMLS5, PAGE = 1
|
||||
.TI.crctab : > RAMLS3, PAGE = 1
|
||||
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(_testInputRunStart), PAGE = 1{
|
||||
testInput :{} LOAD = RAMLS3,
|
||||
LOAD_START(_testInputLoadStart),
|
||||
LOAD_SIZE(_testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(_linkerCrcTable, algorithm = CRC32_PRIME)
|
||||
}crc_table(_linkerCrcTable, algorithm = CRC32_C)
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHD,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst :>> FLASHC, PAGE = 1
|
||||
.TI.crctab : > FLASHB, PAGE = 1
|
||||
|
||||
/* Test specific sections */
|
||||
UNION (TEST_INPUT_CRC) : RUN = RAMLS3, RUN_START(_testInputRunStart), PAGE = 1{
|
||||
testInput :{} LOAD = FLASHB,
|
||||
LOAD_START(_testInputLoadStart),
|
||||
LOAD_SIZE(_testInputLoadSize),
|
||||
PAGE = 1,
|
||||
crc_table(_linkerCrcTable, algorithm = CRC32_PRIME)
|
||||
}crc_table(_linkerCrcTable, algorithm = CRC32_C)
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS4, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,224 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_CRC_8_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File For VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2022 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHEF : origin = 0x088000, length = 0x010000 /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
#if defined(__TI_EABI__)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.init_array : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
|
||||
.TI.crctab : > RAMLS3, PAGE = 1
|
||||
.const : > RAMLS3, PAGE = 1
|
||||
/* Test specific sections */
|
||||
testInput : > RAMLS3, PAGE = 1,
|
||||
crc_table(linkerCrcTable, algorithm = CRC8_PRIME)
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(RamfuncsRunStart),
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.init_array : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
|
||||
.TI.crctab : > FLASHB, PAGE = 1
|
||||
.const : > FLASHB, PAGE = 1
|
||||
/* Test specific sections */
|
||||
testInput : > FLASHB, PAGE = 1,
|
||||
crc_table(linkerCrcTable, algorithm = CRC8_PRIME)
|
||||
testInputLarge : > FLASHEF, PAGE = 1,
|
||||
crc_table(linkerCrcTableLarge, algorithm = CRC8_PRIME)
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.bss : > RAMLS3, PAGE = 1
|
||||
.data : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
|
||||
.TI.crctab : > RAMLS3, PAGE = 1
|
||||
.econst : > RAMLS3, PAGE = 1
|
||||
/* Test specific sections */
|
||||
testInput : > RAMLS3, PAGE = 1,
|
||||
crc_table(_linkerCrcTable, algorithm = CRC8_PRIME)
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
|
||||
.TI.crctab : > FLASHB, PAGE = 1
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
/* Test specific sections */
|
||||
testInput : > FLASHB, PAGE = 1,
|
||||
crc_table(_linkerCrcTable, algorithm = CRC8_PRIME)
|
||||
testInputLarge : > FLASHEF, PAGE = 1,
|
||||
crc_table(_linkerCrcTableLarge, algorithm = CRC8_PRIME)
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,161 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_DEINTERLEAVER_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMGS0, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst :>> RAMGS3, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHD,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHC, PAGE = 1
|
||||
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
interleavedOutput : > RAMGS4, PAGE = 1
|
||||
deinterleavedOutput : > RAMGS5, PAGE = 1
|
||||
testInput : > RAMGS6, PAGE = 1
|
||||
testOutput : > RAMGS7, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS4, PAGE = 1
|
||||
.ebss : > RAMGS7, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,157 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_REEDSOLOMON_N255K239_lnk.cmd.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
testInput : > RAMGS4, PAGE = 1
|
||||
testOutput : > RAMGS5, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS4, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,160 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_RFFT_128_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMLS3, ALIGN = 128, PAGE = 1
|
||||
buffer2 : > RAMLS4, ALIGN = 128, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS4, PAGE = 1
|
||||
.ebss : > RAMLS4, PAGE = 1
|
||||
.esysmem : > RAMLS4, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,160 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_RFFT_256_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMLS3, ALIGN = 256, PAGE = 1
|
||||
buffer2 : > RAMLS4, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMGS4, PAGE = 1
|
||||
.ebss : > RAMGS4, PAGE = 1
|
||||
.esysmem : > RAMGS4, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,160 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_RFFT_512_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMLS2, ALIGN = 512, PAGE = 1
|
||||
buffer2 : > RAMLS3, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMGS4, PAGE = 1
|
||||
.ebss : > RAMGS4, PAGE = 1
|
||||
.esysmem : > RAMGS4, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,161 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_RIFFT_128_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMLS3, ALIGN = 256, PAGE = 1
|
||||
buffer2 : > RAMLS4, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS4, PAGE = 1
|
||||
.ebss : > RAMLS4, PAGE = 1
|
||||
.esysmem : > RAMLS4, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,160 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_RIFFT_256_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMGS4, ALIGN = 512, PAGE = 1
|
||||
buffer2 : > RAMGS5, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS4, PAGE = 1
|
||||
.esysmem : > RAMLS4, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,160 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_RIFFT_64_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
twiddleFactors : > RAMLS5, PAGE = 1
|
||||
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
twiddleFactors : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
buffer1 : > RAMLS3, ALIGN = 128, PAGE = 1
|
||||
buffer2 : > RAMLS4, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS4, PAGE = 1
|
||||
.ebss : > RAMLS4, PAGE = 1
|
||||
.esysmem : > RAMLS4, PAGE = 1
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,208 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_VITERBI_K4CR12_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2022 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.init_array : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.const : > RAMLS4, PAGE = 1
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(RamfuncsRunStart),
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.init_array : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.const : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
testInput : > RAMGS4, PAGE = 1
|
||||
decodedBits : > RAMGS5, PAGE = 1
|
||||
receivedBits : > RAMGS6, PAGE = 1
|
||||
transitionBits : > RAMGS7, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.bss : > RAMLS3, PAGE = 1
|
||||
.data : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
testInput : > RAMGS4, PAGE = 1
|
||||
decodedBits : > RAMGS5, PAGE = 1
|
||||
receivedBits : > RAMGS6, PAGE = 1
|
||||
transitionBits : > RAMGS7, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS4, PAGE = 1
|
||||
}
|
||||
|
||||
#endif
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -0,0 +1,210 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837x_VCU2_VITERBI_K7CR12_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File for VCU-II library examples that run
|
||||
// on the 2837x platform
|
||||
//
|
||||
// This file includes all RAM and FLASH blocks present on the
|
||||
// 2837x and depending on the active build configuration(RAM or FLASH)
|
||||
// the appropriate sections will either be loaded into RAM or FLASH
|
||||
// blocks
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2022 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
// NOTES:
|
||||
// 1. In addition to this memory linker command file, add the header linker
|
||||
// command file directly to the project. The header linker command file is
|
||||
// required to link the peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in
|
||||
// c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd
|
||||
//
|
||||
// For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd
|
||||
// For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd
|
||||
//
|
||||
// 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user
|
||||
// must configure the appropriate control registers to transfer mastership
|
||||
// of a RAMGSx block over to CPU2
|
||||
//
|
||||
// 3. Memory blocks on F2837x are uniform (ie same physical memory) in both
|
||||
// PAGE 0 and PAGE 1. That is the same memory region should not be defined
|
||||
// for both PAGE 0 and PAGE 1. Doing so will result in corruption of program
|
||||
// and/or data.
|
||||
//
|
||||
// Contiguous SARAM memory blocks can be combined if required to create a
|
||||
// larger memory block.
|
||||
//
|
||||
//#############################################################################
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
#if defined(RAM)
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
#elif defined(FLASH)
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
#endif
|
||||
RAMM0 : origin = 0x000122, length = 0x0002DE
|
||||
RAMM1 : origin = 0x000400, length = 0x000400
|
||||
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
|
||||
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000
|
||||
RAMGS15 : origin = 0x01B000, length = 0x001000
|
||||
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
}
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.init_array : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.const : > RAMLS4, PAGE = 1
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(RamfuncsRunStart),
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.init_array : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.const : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
testInput : > RAMGS4, PAGE = 1
|
||||
decodedBits : > RAMGS5, PAGE = 1
|
||||
receivedBits : > RAMGS6, PAGE = 1
|
||||
transitionBits : > RAMGS7, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.bss : > RAMLS3, PAGE = 1
|
||||
.data : > RAMLS3, PAGE = 1
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
#if defined(RAM)
|
||||
.TI.ramfunc : > RAMM0, PAGE = 0
|
||||
.text :>> RAMM1 | RAMD0 | RAMD1 | RAMLS0, PAGE = 0
|
||||
.cinit : > RAMLS1, PAGE = 0
|
||||
|
||||
.pinit : > RAMLS1, PAGE = 0
|
||||
.switch : > RAMLS1, PAGE = 0
|
||||
.econst : > RAMLS4, PAGE = 1
|
||||
#elif defined(FLASH)
|
||||
.TI.ramfunc : LOAD = FLASHC,
|
||||
RUN = RAMLS1,
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
.text : > FLASHN, PAGE = 0
|
||||
.cinit : > FLASHM, PAGE = 0
|
||||
|
||||
.pinit : > FLASHM, PAGE = 0
|
||||
.switch : > FLASHM, PAGE = 0
|
||||
.econst : > FLASHB, PAGE = 1
|
||||
#else
|
||||
#error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
|
||||
#endif //RAM
|
||||
|
||||
/* Test specific sections */
|
||||
testInput : > RAMGS4, PAGE = 1
|
||||
decodedBits : > RAMGS5, PAGE = 1
|
||||
receivedBits : > RAMGS6, PAGE = 1
|
||||
transitionBits : > RAMGS7, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.cio : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
|
||||
.stack : > RAMLS3, PAGE = 1
|
||||
.ebss : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS4, PAGE = 1
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
Binary file not shown.
@@ -0,0 +1,121 @@
|
||||
//#############################################################################
|
||||
//
|
||||
//! \file dsp_examples_setup.c
|
||||
//!
|
||||
//! \brief DSP Examples Common Code
|
||||
//!
|
||||
//! \date Jan 8, 2018
|
||||
//
|
||||
// Group: C2000
|
||||
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2020 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
// the includes
|
||||
//*****************************************************************************
|
||||
#include "dsp_examples_setup.h"
|
||||
#include "sysctl.h"
|
||||
|
||||
|
||||
//=============================================================================
|
||||
// DSP_Example_setupSysCtrl()
|
||||
//=============================================================================
|
||||
void DSP_Example_setupSysCtrl( void )
|
||||
{
|
||||
//
|
||||
// Disable the watchdog
|
||||
//
|
||||
SysCtl_disableWatchdog();
|
||||
|
||||
//
|
||||
// Set up PLL control and clock dividers
|
||||
//
|
||||
SysCtl_setClock(DEVICE_SETCLOCK_CFG);
|
||||
|
||||
//
|
||||
// Make sure the LSPCLK divider is set to the default (divide by 4)
|
||||
//
|
||||
SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4);
|
||||
/*
|
||||
NOTE: This section needs to be uncommented if the examples are using the CM
|
||||
//
|
||||
// Set up AUXPLL control and clock dividers needed for CMCLK
|
||||
//
|
||||
SysCtl_setAuxClock(DEVICE_AUXSETCLOCK_CFG);
|
||||
|
||||
//
|
||||
// Set up CMCLK to use AUXPLL as the clock source and set the
|
||||
// clock divider to 1.
|
||||
//
|
||||
SysCtl_setCMClk(SYSCTL_CMCLKOUT_DIV_1,SYSCTL_SOURCE_AUXPLL);
|
||||
//
|
||||
*/
|
||||
// Enable Peripherals
|
||||
//
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
|
||||
|
||||
|
||||
}
|
||||
|
||||
//=============================================================================
|
||||
// DSP_Example_initGPIO()
|
||||
//=============================================================================
|
||||
void DSP_Example_initGPIO(void)
|
||||
{
|
||||
//
|
||||
// Disable pin locks.
|
||||
//
|
||||
GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
|
||||
// GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF); //Needs to be uncommented out for f2838x
|
||||
}
|
||||
|
||||
//=============================================================================
|
||||
// DSP_Example_setupFlash()
|
||||
//=============================================================================
|
||||
void DSP_Example_setupFlash( void )
|
||||
{
|
||||
#if defined(_FLASH)
|
||||
//
|
||||
// Copy time critical code and flash setup code to RAM. This includes the
|
||||
// following functions: InitFlash();
|
||||
//
|
||||
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
|
||||
// are created by the linker. Refer to the device .cmd file.
|
||||
//
|
||||
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (uint32_t)&RamfuncsLoadSize);
|
||||
|
||||
//
|
||||
// Call Flash Initialization to setup flash waitstates. This function must
|
||||
// reside in RAM.
|
||||
//
|
||||
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
|
||||
#endif //defined(_FLASH)
|
||||
}
|
||||
|
||||
//=============================================================================
|
||||
// done()
|
||||
//=============================================================================
|
||||
void done( void )
|
||||
{
|
||||
for(;;);
|
||||
}
|
||||
|
||||
//=============================================================================
|
||||
// __error__()
|
||||
//=============================================================================
|
||||
void __error__(const char *filename, uint32_t line)
|
||||
{
|
||||
__asm(" ESTOP0");
|
||||
}
|
||||
|
||||
// End of File
|
||||
@@ -0,0 +1,76 @@
|
||||
#ifndef _DSP_EXAMPLES_SETUP_H_
|
||||
#define _DSP_EXAMPLES_SETUP_H_
|
||||
//#############################################################################
|
||||
//
|
||||
//! \file dsp_examples_setup.h
|
||||
//!
|
||||
//! \brief DSP Examples Common Code
|
||||
//!
|
||||
//! \date Jan 8, 2016
|
||||
//
|
||||
// Group: C2000
|
||||
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2020 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
|
||||
//*****************************************************************************
|
||||
// the includes
|
||||
//*****************************************************************************
|
||||
#include <stdint.h>
|
||||
#include <float.h>
|
||||
#include <math.h>
|
||||
#include "device.h"
|
||||
#include "inc/hw_types.h"
|
||||
|
||||
//!
|
||||
//! \defgroup DSP_EXAMPLES_SETUP DSP Examples Setup Code
|
||||
|
||||
//!
|
||||
//! \ingroup DSP_EXAMPLES_SETUP
|
||||
//@{
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//globals
|
||||
//*****************************************************************************
|
||||
#if defined(_FLASH)
|
||||
extern uint16_t RamfuncsRunStart, RamfuncsLoadStart, RamfuncsLoadSize;
|
||||
#endif //defined(_FLASH)
|
||||
|
||||
//*****************************************************************************
|
||||
// the function prototypes
|
||||
//*****************************************************************************
|
||||
//! \brief Setup system controls
|
||||
//!
|
||||
extern void DSP_Example_setupSysCtrl( void );
|
||||
|
||||
//! \brief Function to disable pin locks and enable pullups on GPIOs.
|
||||
//!
|
||||
extern void DSP_Example_initGPIO(void);
|
||||
|
||||
//! \brief Setup flash
|
||||
//!
|
||||
extern void DSP_Example_setupFlash( void );
|
||||
|
||||
//! \brief Run a particular Fast RTS routine
|
||||
//!
|
||||
extern void DSP_runTest( void );
|
||||
|
||||
extern void done( void );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif // extern "C"
|
||||
//@} // ingroup
|
||||
|
||||
#endif // end of _DSP_EXAMPLES_SETUP_H_ definition
|
||||
|
||||
// End of File
|
||||
@@ -0,0 +1,112 @@
|
||||
//#############################################################################
|
||||
//! \file /examples_ccsv5/common/examples_setup.c
|
||||
//!
|
||||
//! \brief Initialization routines for the VCU2 library examples
|
||||
//!
|
||||
//! \date July 16, 2013
|
||||
//
|
||||
// Group: C2000
|
||||
// Target Family: F2837x
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
|
||||
//*****************************************************************************
|
||||
// includes
|
||||
//*****************************************************************************
|
||||
#include "examples_setup.h"
|
||||
|
||||
//*****************************************************************************
|
||||
// defines
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
// globals
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
// Function Prototypes
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
// function definitions
|
||||
//*****************************************************************************
|
||||
|
||||
void VCU2_initSystemClocks()
|
||||
{
|
||||
InitSysCtrl(); //Enable peripheral clocks
|
||||
|
||||
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0x00;
|
||||
}
|
||||
|
||||
void VCU2_initEpie()
|
||||
{
|
||||
DINT; //Globally disable maskable CPU interrupts
|
||||
InitPieCtrl(); //Clear and disable all PIE interrupts
|
||||
IER = 0x0000; //Individually disable maskable CPU interrupts
|
||||
IFR = 0x0000; //Clear all CPU interrupt flags
|
||||
InitPieVectTable(); //Populate the PIE interrupt vector table with shell ISRs
|
||||
}
|
||||
|
||||
#ifdef FLASH
|
||||
void VCU2_initFlash()
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//At reset bank and pump are in sleep
|
||||
//A Flash access will power up the bank and pump automatically
|
||||
//After a Flash access, bank and pump go to low power mode (configurable in FBFALLBACK/FPAC1 registers)-
|
||||
//if there is no further access to flash
|
||||
//Power up Flash bank and pump and this also sets the fall back mode of flash and pump as active
|
||||
Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1;
|
||||
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3;
|
||||
|
||||
//Disable Cache and prefetch mechanism before changing wait states
|
||||
Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0;
|
||||
Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0;
|
||||
|
||||
//Set waitstates according to frequency
|
||||
// CAUTION
|
||||
//Minimum waitstates required for the flash operating
|
||||
//at a given CPU rate must be characterized by TI.
|
||||
//Refer to the datasheet for the latest information.
|
||||
#if CPU_FRQ_200MHZ
|
||||
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3;
|
||||
#endif
|
||||
|
||||
#if CPU_FRQ_150MHZ
|
||||
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
|
||||
#endif
|
||||
|
||||
#if CPU_FRQ_120MHZ
|
||||
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
|
||||
#endif
|
||||
|
||||
//Enable Cache and prefetch mechanism to improve performance
|
||||
//of code executed from Flash.
|
||||
Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1;
|
||||
Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1;
|
||||
|
||||
//At reset, ECC is enabled
|
||||
//If it is disabled by application software and if application again wants to enable ECC
|
||||
Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;
|
||||
|
||||
EDIS;
|
||||
|
||||
//Force a pipeline flush to ensure that the write to
|
||||
//the last register configured occurs before returning.
|
||||
|
||||
__asm(" RPT #7 || NOP");
|
||||
}
|
||||
#endif //FLASH
|
||||
|
||||
|
||||
void done(void)
|
||||
{
|
||||
for(;;);
|
||||
}
|
||||
// End of file
|
||||
@@ -0,0 +1,78 @@
|
||||
#ifndef _VCU2_EXAMPLES_SETUP_H_
|
||||
#define _VCU2_EXAMPLES_SETUP_H_
|
||||
//#############################################################################
|
||||
//! \file /examples_ccsv5/common/examples_setup.h
|
||||
//!
|
||||
//! \brief Initialization routines for the VCU2 library examples
|
||||
//!
|
||||
//! \date July 16, 2013
|
||||
//
|
||||
// Group: C2000
|
||||
// Target Family: F2837x
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
//
|
||||
// $Copyright: Copyright (C) 2024 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
|
||||
//*****************************************************************************
|
||||
// includes
|
||||
//*****************************************************************************
|
||||
#include "F28x_Project.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
// defines
|
||||
//*****************************************************************************
|
||||
#define CPU_FRQ_200MHZ 1
|
||||
|
||||
//*****************************************************************************
|
||||
// typedefs
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
// globals
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
// function prototypes
|
||||
//*****************************************************************************
|
||||
// \brief Initialize system clocks
|
||||
//
|
||||
void VCU2_initSystemClocks(void);
|
||||
|
||||
// \brief Initialize Enhanced PIE
|
||||
//
|
||||
void VCU2_initEpie(void);
|
||||
|
||||
// \brief Initialize Flash
|
||||
//
|
||||
void VCU2_initFlash(void);
|
||||
|
||||
// \brief Disable Flash prefetch
|
||||
//
|
||||
extern void InitFlash_PrefetchCacheDisable(void);
|
||||
|
||||
// \brief Enable Flash prefetch
|
||||
//
|
||||
extern void InitFlash_PrefetchCacheEnable(void);
|
||||
|
||||
// \brief Set Flash wait states
|
||||
// \param[in] waitStates The number of wait states
|
||||
//
|
||||
void SetupFlash(unsigned short waitStates);
|
||||
|
||||
// \brief autobot done()
|
||||
//
|
||||
void done(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif // extern "C"
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|
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<variable>
|
||||
<name>DRIVERLIB_ROOT</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/driverlib/$%7BDEVICE%7D/driverlib</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>F2838X_ROOT_DIR</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/device_support/f2838x</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>VCU2_ROOT_DIR</name>
|
||||
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>copy_PARENT</name>
|
||||
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>copy_PARENT1</name>
|
||||
<value>$%7Bcopy_PARENT%7D/examples</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>copy_PARENT12</name>
|
||||
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>copy_PARENT123</name>
|
||||
<value>$%7Bcopy_PARENT12%7D/examples</value>
|
||||
</variable>
|
||||
</variableList>
|
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</projectDescription>
|
||||
File diff suppressed because it is too large
Load Diff
+1108
File diff suppressed because it is too large
Load Diff
+84
@@ -0,0 +1,84 @@
|
||||
//###############################################################################
|
||||
//! \file /2838x_vcrc_config_poly/vcrc_configpoly.h
|
||||
//!
|
||||
//! \brief Header file for the configurable polynomial and data sizes (VCRC and C)
|
||||
//!
|
||||
//! \date April 9, 2020
|
||||
//!
|
||||
//
|
||||
// Group: C2000
|
||||
// Target Family: F2838x
|
||||
//
|
||||
//#############################################################################
|
||||
// $TI Release: C28x VCU Library V2.28.00.00 $
|
||||
// $Release Date: Oct 29, 2024 $
|
||||
// $Copyright: Copyright (C) 2019 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
|
||||
//*****************************************************************************
|
||||
// defines
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
// Sizes - The following defines are used to set the polynomial size and
|
||||
// data size on which the CRC is computed by the CRC engine
|
||||
// Polynomial size-size of of 1 bit - indicated by programming a value of 0x0
|
||||
// Polynomial size-size of of 32bits - indicated by programming a value of 0x1F
|
||||
// Similarly Data size -size of 1 bit - indicated by programming a value of 0x0
|
||||
// Data size - size of 8 bits is indicated by programming a value of 0x7
|
||||
// These are to be set in the VCRCSIZE register - PSIZE and DSIZE fields
|
||||
|
||||
#define SIZE_32_BITS 31
|
||||
#define SIZE_31_BITS 30
|
||||
#define SIZE_30_BITS 29
|
||||
#define SIZE_29_BITS 28
|
||||
#define SIZE_28_BITS 27
|
||||
#define SIZE_27_BITS 26
|
||||
#define SIZE_26_BITS 25
|
||||
#define SIZE_25_BITS 24
|
||||
#define SIZE_24_BITS 23
|
||||
#define SIZE_23_BITS 22
|
||||
#define SIZE_22_BITS 21
|
||||
#define SIZE_21_BITS 20
|
||||
#define SIZE_20_BITS 19
|
||||
#define SIZE_19_BITS 18
|
||||
#define SIZE_18_BITS 17
|
||||
#define SIZE_17_BITS 16
|
||||
#define SIZE_16_BITS 15
|
||||
#define SIZE_15_BITS 14
|
||||
#define SIZE_14_BITS 13
|
||||
#define SIZE_13_BITS 12
|
||||
#define SIZE_12_BITS 11
|
||||
#define SIZE_11_BITS 10
|
||||
#define SIZE_10_BITS 9
|
||||
#define SIZE_9_BITS 8
|
||||
#define SIZE_8_BITS 7
|
||||
#define SIZE_7_BITS 6
|
||||
#define SIZE_6_BITS 5
|
||||
#define SIZE_5_BITS 4
|
||||
#define SIZE_4_BITS 3
|
||||
#define SIZE_3_BITS 2
|
||||
#define SIZE_2_BITS 1
|
||||
#define SIZE_1_BITS 0
|
||||
|
||||
//*****************************************************************************
|
||||
// function declarations
|
||||
// specific functions are written to either work on message size that are in
|
||||
// bytes or in bits
|
||||
//*****************************************************************************
|
||||
|
||||
//! \brief C table-lookup 4-bit CRC calculation for ENDAT,message size in bytes
|
||||
//! \param[in] hndCRC handle to the CRC object
|
||||
void CRC_run4BitENDATTableLookupC(CRC_Handle hndCRC);
|
||||
|
||||
//! \brief C table-lookup 4-bit CRC calculation for ENDAT,message size in bits
|
||||
//! \param[in] hndCRC handle to the CRC object
|
||||
void CRC_run4BitENDATBitTableLookupC_Generic(CRC_Handle hndCRC);
|
||||
|
||||
//! \brief C table-lookup 17-bit CRC for CANFD,message size in bytes
|
||||
//! \param[in] hndCRC handle to the CRC object
|
||||
void CRC_run17BitCANFDTableLookupC(CRC_Handle hndCRC);
|
||||
|
||||
// error function - this is used in the example to loop forever
|
||||
void error(void);
|
||||
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<?ccsproject version="1.0"?>
|
||||
<projectOptions>
|
||||
<deviceFamily value="C2000"/>
|
||||
</projectOptions>
|
||||
@@ -0,0 +1,121 @@
|
||||
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|
||||
<macros>
|
||||
<stringMacro name="DEVICE" type="VALUE_PATH_ANY" value="f280015x"/>
|
||||
<stringMacro name="VCU2_ROOT_DIR" type="VALUE_PATH_DIR" value="${PROJECT_ROOT}\..\..\..\"/>
|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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|
||||
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<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
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<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/examples/common"/>
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<listOptionValue builtIn="false" value="${DEVICE_SUPPORT_ROOT}"/>
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<listOptionValue builtIn="false" value="${DEVICE_SUPPORT_ROOT}/common/include"/>
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||||
<listOptionValue builtIn="false" value="${DEVICE_SUPPORT_ROOT}/headers/include"/>
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<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.OUTPUT_FILE.112457431" name="Specify output file name (--output_file, -o)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.OUTPUT_FILE" value="${ProjName}.out" valueType="string"/>
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|
||||
<listOptionValue builtIn="false" value="driverlib.lib"/>
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</option>
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<listOptionValue builtIn="false" value="${DRIVERLIB_ROOT}/ccs/Debug"/>
|
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<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/lib"/>
|
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<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
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<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__GEN_CMDS.5820793" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__GEN_CMDS"/>
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</tool>
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<tool id="com.ti.ccstudio.buildDefinitions.C2000_20.2.hex.1850378931" name="C2000 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.hex"/>
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</storageModule>
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</project-mappings>
|
||||
</storageModule>
|
||||
<storageModule moduleId="refreshScope"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
<storageModule moduleId="null.endianPreference"/>
|
||||
<storageModule moduleId="cpuFamily"/>
|
||||
</cproject>
|
||||
@@ -0,0 +1,125 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>280015x_vcrc_crc_16</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<arguments>
|
||||
<dictionary>
|
||||
<key>?name?</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.append_environment</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildArguments</key>
|
||||
<value>-k</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildCommand</key>
|
||||
<value>${CCS_UTILS_DIR}/bin/gmake</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildLocation</key>
|
||||
<value>${BuildDirectory}</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
|
||||
<value>clean</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.contents</key>
|
||||
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.stopOnError</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>com.ti.ccstudio.core.ccsNature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>280015x_RAM_lnk_cpu1_crc16.cmd</name>
|
||||
<type>1</type>
|
||||
<locationURI>PARENT-3-PROJECT_LOC/cmd/280015x_RAM_lnk_cpu1_crc16.cmd</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>dsp_examples_setup.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>PARENT-2-PROJECT_LOC/common/dsp_examples_setup.c</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<variableList>
|
||||
<variable>
|
||||
<name>DEVICE</name>
|
||||
<value>f280015x</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>DEVICE_SUPPORT_ROOT</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/device_support/$%7BDEVICE%7D</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>DRIVERLIB_ROOT</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/driverlib/$%7BDEVICE%7D/driverlib</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>F2838X_ROOT_DIR</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/device_support/f2838x</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>VCU2_ROOT_DIR</name>
|
||||
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>copy_PARENT</name>
|
||||
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>copy_PARENT1</name>
|
||||
<value>$%7Bcopy_PARENT%7D/examples</value>
|
||||
</variable>
|
||||
</variableList>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,24 @@
|
||||
<?xml version="1.0" encoding="ISO-8859-15"?>
|
||||
<DSS>
|
||||
<SETUP>
|
||||
<FPGA_REQUIRED>"FALSE"</FPGA_REQUIRED>
|
||||
<ITERATIONS>
|
||||
<NUMBER>"1"</NUMBER>
|
||||
</ITERATIONS>
|
||||
|
||||
<CONFIG id="1">
|
||||
<LOAD>
|
||||
<PATH>"RAM\2837x_vcu2_crc_16.out"</PATH>
|
||||
<CORE>"1"</CORE>
|
||||
<ALIAS>"TEST_CPU"</ALIAS>
|
||||
</LOAD>
|
||||
</CONFIG>
|
||||
|
||||
<CONFIG id="2">
|
||||
<LOAD>
|
||||
<PATH>"FLASH\2837x_vcu2_crc_16.out"</PATH>
|
||||
<CORE>"1"</CORE>
|
||||
</LOAD>
|
||||
</CONFIG>
|
||||
</SETUP>
|
||||
</DSS>
|
||||
@@ -0,0 +1,340 @@
|
||||
//#############################################################################
|
||||
//! \file /2838x_vcrc_crc_16/main.c
|
||||
//!
|
||||
//! \brief Demo code for the 16-bit CRC routine(VCU and C)
|
||||
//!
|
||||
//! \date April 9, 2020
|
||||
//!
|
||||
//! This example shows how to
|
||||
//! -# use the vcrc supported 16-bit CRC routines from the library
|
||||
//! -# use a C based table lookup routine to run a 16-bit CRC check using
|
||||
//! any 16-bit polynomial
|
||||
//! -# demonstrate the link time CRC generation(using the
|
||||
//! polynomials 0x8005 and 0x1021) on a specified section of memory
|
||||
//
|
||||
// Group: C2000
|
||||
// Target Family: F2838x
|
||||
//
|
||||
//#############################################################################
|
||||
// $TI Release: C28x VCU Library V2.28.00.00 $
|
||||
// $Release Date: Oct 29, 2024 $
|
||||
// $Copyright: Copyright (C) 2019 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
|
||||
//*****************************************************************************
|
||||
// includes
|
||||
//*****************************************************************************
|
||||
#include "crc_tbl.h"
|
||||
#include "vcu2_types.h"
|
||||
#include "vcu2_crc.h"
|
||||
#include "crctable0x8005.h"
|
||||
#include "crctable0x8005reflected.h"
|
||||
#include "crctable0x1021.h"
|
||||
#include "crctable0x1021reflected.h"
|
||||
#include "dsp_examples_setup.h"
|
||||
|
||||
//!
|
||||
//! \defgroup CRC16_EXAMPLES Cyclic Redundancy Check 16-bit Example
|
||||
|
||||
//!
|
||||
//! \ingroup CRC16_EXAMPLES
|
||||
// @{
|
||||
|
||||
//*****************************************************************************
|
||||
// defines
|
||||
//*****************************************************************************
|
||||
#define NBYTES (128)
|
||||
#define NWORDS (NBYTES/2)
|
||||
//*****************************************************************************
|
||||
// globals
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("testInput")
|
||||
#else
|
||||
#pragma DATA_SECTION(testInput,"testInput")
|
||||
#endif //__cplusplus
|
||||
|
||||
//\brief test input
|
||||
//
|
||||
// This vector is declared as a static const in order for the linker to
|
||||
// be able to run the CRC algorithm on it. It needn't be either static
|
||||
// or const for the C and VCU routines
|
||||
//
|
||||
static const uint16_t testInput[NWORDS] = {
|
||||
0x4001, 0x8002, 0xC003, 0x0004, 0x4005, 0x8006, 0xC007, 0x0008,
|
||||
0x4009, 0x800A, 0xC00B, 0x000C, 0x400D, 0x800E, 0xC00F, 0x0010,
|
||||
0x4011, 0x8012, 0xC013, 0x0014, 0x4015, 0x8016, 0xC017, 0x0018,
|
||||
0x4019, 0x801A, 0xC01B, 0x001C, 0x401D, 0x801E, 0xC01F, 0x0020,
|
||||
0x4021, 0x8022, 0xC023, 0x0024, 0x4025, 0x8026, 0xC027, 0x0028,
|
||||
0x4029, 0x802A, 0xC02B, 0x002C, 0x402D, 0x802E, 0xC02F, 0x0030,
|
||||
0x4031, 0x8032, 0xC033, 0x0034, 0x4035, 0x8036, 0xC037, 0x0038,
|
||||
0x4039, 0x803A, 0xC03B, 0x003C, 0x403D, 0x803E, 0xC03F, 0x0040,
|
||||
};
|
||||
|
||||
// \brief linker generated object(CRC table)
|
||||
//
|
||||
extern CRC_TABLE linkerCrcTable;
|
||||
// \brief linker generated "run" location for the CRC table object
|
||||
//
|
||||
extern uint16_t crcTableRun;
|
||||
// \brief linker generated "load" location for the CRC table object
|
||||
//
|
||||
extern uint16_t crcTableLoad;
|
||||
// \brief linker generated "size" label indicating the size of the CRC table
|
||||
// object
|
||||
//
|
||||
extern uint16_t crcTableSize;
|
||||
// \brief object of the structure CRC_Obj
|
||||
//
|
||||
CRC_Obj CRC;
|
||||
// \brief handle(pointer) to the CRC object
|
||||
//
|
||||
CRC_Handle handleCRC;
|
||||
// \brief A single record(element) from the CRC table object
|
||||
//
|
||||
CRC_RECORD linkerCrcRecord;
|
||||
// \brief pointer to the CRC table object
|
||||
//
|
||||
CRC_TABLE *pLinkerCrcTable;
|
||||
// \brief linker generated variables defining the load and run placements
|
||||
// of the testInput vector
|
||||
//
|
||||
extern uint32_t testInputLoadStart, testInputLoadSize, testInputRunStart;
|
||||
|
||||
|
||||
uint16_t pass = 0;
|
||||
uint16_t fail = 0;
|
||||
//*****************************************************************************
|
||||
// Function Prototypes
|
||||
//*****************************************************************************
|
||||
void error(void);
|
||||
|
||||
//*****************************************************************************
|
||||
// function definitions
|
||||
//*****************************************************************************
|
||||
|
||||
//!
|
||||
//! \brief main routine for the 16-bit CRC example
|
||||
//! \return returns a 1
|
||||
//!
|
||||
//! This example shows how to
|
||||
//! -# use the vcu2 supported 16-bit CRC routines from the library
|
||||
//! -# use a C based table lookup routine to run a 16-bit CRC check using
|
||||
//! any 16-bit polynomial
|
||||
//! -# demonstrate the link time CRC generation(using the
|
||||
//! polynomials 0x8005 and 0x1021) on a specified section of memory
|
||||
//!
|
||||
//! \note The variables used in the example are the same used in the CRC-8
|
||||
//! example and are not documented here again.
|
||||
//!
|
||||
int main( void )
|
||||
{
|
||||
// Locals
|
||||
int16_t i;
|
||||
uint32_t crcResultC_1, crcResultC_2 ;
|
||||
uint32_t crcResultVcu_1, crcResultVcu_2;
|
||||
uint32_t crcResultLnk;
|
||||
|
||||
#if defined(_FLASH)
|
||||
//
|
||||
// Setup the FLASH Banks
|
||||
//
|
||||
DSP_Example_setupFlash();
|
||||
#endif //defined(_FLASH)
|
||||
|
||||
//
|
||||
// Setup system clocking
|
||||
//
|
||||
DSP_Example_setupSysCtrl();
|
||||
|
||||
//*************************************************************************
|
||||
// Example #1: 128 bytes(x8, even), parity: low byte first
|
||||
//*************************************************************************
|
||||
//! \b Example \b #1, \b Part \b 1
|
||||
//! In this section we run a table lookup CRC on the vector testInput. The
|
||||
//! table is specified in the header files "CrcTable0x8005.h" and
|
||||
//! "CrcTable0x1021.h"respectively and the entries were generated from the
|
||||
//! polynomials \f$ x^{16}+x^{15}+x^{2}+1 \f$ (CRC16 802.15.4, 0x8005) and
|
||||
//! \f$ x^{16}+x^{12}+x^{5}+1 \f$ (CRC-CCITT, 0x1021) respectively.
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//! \code
|
||||
//************************************************************************
|
||||
// Step 1: Copy the test input vector from its load location to the run location.
|
||||
// This is necessary since the section was declared within a UNION in the linker
|
||||
// command file
|
||||
memcpy((uint32_t *)&testInputRunStart, (uint32_t *)&testInputLoadStart,
|
||||
(uint32_t)&testInputLoadSize );
|
||||
|
||||
// Step 2: Initialize the CRC object
|
||||
CRC.seedValue = INIT_CRC16;
|
||||
CRC.nMsgBytes = NBYTES;
|
||||
CRC.parity = CRC_parity_even;
|
||||
CRC.crcResult = 0;
|
||||
CRC.pMsgBuffer = (uint16_t *)&testInput[0];
|
||||
CRC.pCrcTable = (uint16_t *)&crc16P1Table[0];
|
||||
CRC.init = (void (*)(void *))CRC_init16Bit;
|
||||
CRC.run = (void (*)(void *))CRC_run16BitTableLookupC;
|
||||
|
||||
// Step 3: Initialize the handle
|
||||
handleCRC = &CRC;
|
||||
|
||||
// Step 4: Run the 16-bit table look-up CRC routine and save the first result
|
||||
CRC.init(handleCRC);
|
||||
CRC.run(handleCRC);
|
||||
crcResultC_1 = CRC.crcResult;
|
||||
|
||||
// Step 5: Load the second lookup table and run the C routine
|
||||
CRC.pCrcTable = (uint16_t *)&crc16P2Table[0];
|
||||
CRC.crcResult = 0;
|
||||
CRC.run(handleCRC);
|
||||
crcResultC_2 = CRC.crcResult;
|
||||
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #1, \b Part \b 2
|
||||
//! Now we run the VCU routine on the vector testInput. The two
|
||||
//! polynomials employed by the VCU are fixed i.e.
|
||||
//! \f$ x^{16}+x^{15}+x^{2}+1 \f$ (0x8005) and \f$ x^{16}+x^{12}+x^{5}+1 \f$
|
||||
//! (0x1021) respectively
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//!
|
||||
//! Most of the object elements remain unchanged from the initial setup
|
||||
//!
|
||||
//! \note The VCU routine does not require a lookup table; pCrcTable can be
|
||||
//! reset to NULL or left as-is
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: Reset a few elements of the CRC object
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run16BitPoly1;
|
||||
|
||||
// Step 2: Run the VCU 16-bit CRC routine and save the result
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu_1 = CRC.crcResult;
|
||||
|
||||
// Step 3: Now for the other polynomial
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run16BitPoly2;
|
||||
|
||||
// Step 4: Run the VCU 16-bit CRC routine and save the result
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu_2 = CRC.crcResult;
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #1, \b Part \b 3
|
||||
//! The linker will compute the CRC(s) of the section \c testInput
|
||||
//! and keep the result as a record in a CRC_TABLE structure
|
||||
//! \c linkerCrcTable.
|
||||
//!
|
||||
//! Each record from this table is an object of type CRC_RECORD. The
|
||||
//! elements of this structure are described in detail, at the time of
|
||||
//! writing, in SPRU513D, section 7.9
|
||||
//!
|
||||
//! \note
|
||||
//! -# In the event the linker is configured to run multiple algorithms
|
||||
//! on a section of memory, the result of those computations are placed in
|
||||
//! the records in an unspecified order. The user must poll the crc_alg_ID
|
||||
//! field of the record to determine which algorithm was run
|
||||
//! -# Note the use of the \b UNION keyword in the linker command file around
|
||||
//! the \b testInput section to allow the linker to calculate two different
|
||||
//! 16-bit CRCs for the same memory block
|
||||
//!
|
||||
//*************************************************************************
|
||||
// Step 1: Initialize the CRC table pointer.
|
||||
pLinkerCrcTable = &linkerCrcTable;
|
||||
|
||||
// Step 2: Get the CRC results from the linker CRC table
|
||||
for(i = 0; i < pLinkerCrcTable->num_recs; i++){
|
||||
// Get the current CRC record
|
||||
linkerCrcRecord = pLinkerCrcTable->recs[i];
|
||||
// Get the linker generated CRC
|
||||
crcResultLnk = linkerCrcRecord.crc_value;
|
||||
if(linkerCrcRecord.crc_alg_ID == CRC16_ALT){ //0x8005
|
||||
(crcResultLnk == crcResultVcu_1)? pass++ : fail++;
|
||||
(crcResultVcu_1 == crcResultC_1)? pass++ : fail++;
|
||||
}else if(linkerCrcRecord.crc_alg_ID == CRC16_802_15_4){ //0x1021
|
||||
(crcResultLnk == crcResultVcu_2)? pass++ : fail++;
|
||||
(crcResultVcu_2 == crcResultC_2)? pass++ : fail++;
|
||||
}else{
|
||||
fail++;
|
||||
}
|
||||
}
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #2
|
||||
//! We now run the reflected algorithm using both a table lookup method and
|
||||
//! compare it against its equivalent VCU routine. The reflected CRC
|
||||
//! table is specified in the header files "CrcTable0x8005Reflected.h" and
|
||||
//! "CrcTable0x1021Reflected.h"; the entries were generated from the table
|
||||
//! indices 0,1,...255 by shifting out the LSB of the index and XOR'ing the
|
||||
//! remainder with the polynomial if the LSB was a 1
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: For the C routine, assign the correct look-up table and function
|
||||
// to the object and reset the CRC result
|
||||
CRC.crcResult = 0;
|
||||
CRC.pCrcTable = (uint16_t *)&crc16P1TableReflected[0];
|
||||
CRC.run = (void (*)(void *))CRC_run16BitReflectedTableLookupC;
|
||||
|
||||
// Step 2: Run the C routine, reflect and save the result
|
||||
CRC.run(handleCRC);
|
||||
crcResultC_1 = (uint16_t)(CRC_bitReflect((uint32_t)CRC.crcResult, 16));
|
||||
|
||||
// Step 3: Replace the lookup table with that of the second polynomial
|
||||
CRC.crcResult = 0;
|
||||
CRC.pCrcTable = (uint16_t *)&crc16P2TableReflected[0];
|
||||
CRC.run(handleCRC);
|
||||
crcResultC_2 = (uint16_t)(CRC_bitReflect((uint32_t)CRC.crcResult, 16));
|
||||
|
||||
// Step 4: Assign the VCU routine to the object and run it
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run16BitPoly1Reflected;
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu_1 = CRC.crcResult;
|
||||
|
||||
// Step 5: Assign the VCU routine(2nd polynomial) to the object and run it
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run16BitPoly2Reflected;
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu_2 = CRC.crcResult;
|
||||
|
||||
// Step 6: Compare the results of steps 2/3 with 4/5
|
||||
(crcResultC_1 == crcResultVcu_1)? pass++ : fail++ ;
|
||||
(crcResultC_2 == crcResultVcu_2)? pass++ : fail++ ;
|
||||
|
||||
//*************************************************************************
|
||||
//!
|
||||
//! \endcode
|
||||
//!
|
||||
//*************************************************************************
|
||||
// End of test
|
||||
|
||||
//if the any of the example fails - code will loop forever in error function
|
||||
if (fail > 0) {
|
||||
error();
|
||||
}
|
||||
//if all the examples pass code will loop forever in the while below
|
||||
while(1);
|
||||
|
||||
// Execution never reaches this point
|
||||
return 1;
|
||||
}
|
||||
// End of main
|
||||
|
||||
void error(void)
|
||||
{
|
||||
ESTOP0; //Test failed!! Stop!
|
||||
for (;;);
|
||||
}
|
||||
|
||||
// @} //addtogroup
|
||||
|
||||
// End of file
|
||||
@@ -0,0 +1,11 @@
|
||||
// Setup Debug Environment
|
||||
expRemoveAll
|
||||
|
||||
expAdd('pass',getNatural())
|
||||
expAdd('fail',getNatural())
|
||||
expAdd('CRC',getNatural())
|
||||
expAdd('crcResultC_1',getHex())
|
||||
expAdd('crcResultC_2',getHex())
|
||||
expAdd('crcResultVcu_1',getHex())
|
||||
expAdd('crcResultVcu_2',getHex())
|
||||
expAdd('crcResultLnk',getHex())
|
||||
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<?ccsproject version="1.0"?>
|
||||
<projectOptions>
|
||||
<deviceFamily value="C2000"/>
|
||||
</projectOptions>
|
||||
@@ -0,0 +1,122 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
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||||
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||||
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|
||||
<macros>
|
||||
<stringMacro name="DEVICE" type="VALUE_PATH_ANY" value="f280015x"/>
|
||||
<stringMacro name="VCU2_ROOT_DIR" type="VALUE_PATH_DIR" value="${PROJECT_ROOT}\..\..\..\"/>
|
||||
</macros>
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="RAM only configuration" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884" name="RAM" parent="com.ti.ccstudio.buildDefinitions.C2000.Debug">
|
||||
<folderInfo id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884." name="/" resourcePath="">
|
||||
<toolChain id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.DebugToolchain.361439253" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.linkerDebug.1507145766">
|
||||
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|
||||
<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C2000.GenericC28xxDevice"/>
|
||||
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|
||||
<listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
|
||||
<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE=280015x_RAM_lnk_cpu1_crc24.cmd"/>
|
||||
<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
|
||||
<listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.5.0"/>
|
||||
<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
|
||||
<listOptionValue builtIn="false" value="PRODUCTS="/>
|
||||
<listOptionValue builtIn="false" value="PRODUCT_MACRO_IMPORTS={}"/>
|
||||
</option>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.758661246" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="20.2.1.LTS" valueType="string"/>
|
||||
<targetPlatform id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.targetPlatformDebug.1439828403" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.targetPlatformDebug"/>
|
||||
<builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.builderDebug.829869553" keepEnvironmentInBuildfile="false" name="GNU Make" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.builderDebug"/>
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||||
<tool id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.compilerDebug.796250742" name="C2000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.compilerDebug">
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.SILICON_VERSION.152754177" name="Processor version (--silicon_version, -v)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.SILICON_VERSION" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.SILICON_VERSION.28" valueType="enumerated"/>
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||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.LARGE_MEMORY_MODEL.828958735" name="Option deprecated, set by default (--large_memory_model, -ml)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.LARGE_MEMORY_MODEL" value="true" valueType="boolean"/>
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||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.UNIFIED_MEMORY.2049331689" name="Unified memory (--unified_memory, -mt)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.UNIFIED_MEMORY" value="true" valueType="boolean"/>
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||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.CLA_SUPPORT.996247086" name="Specify CLA support (--cla_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.CLA_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.CLA_SUPPORT.cla1" valueType="enumerated"/>
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||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.FLOAT_SUPPORT.856778822" name="Specify floating point support (--float_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.FLOAT_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.FLOAT_SUPPORT.fpu32" valueType="enumerated"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.TMU_SUPPORT.1952633755" name="Specify TMU support (--tmu_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.TMU_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.TMU_SUPPORT.tmu0" valueType="enumerated"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.VCU_SUPPORT.619924726" name="Specify VCU support (--vcu_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.VCU_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.VCU_SUPPORT.vcrc" valueType="enumerated"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.INCLUDE_PATH.813820328" name="Add dir to #include search path (--include_path, -I)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.INCLUDE_PATH" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
|
||||
<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/include/vcu2"/>
|
||||
<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/include/common"/>
|
||||
<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/examples/common"/>
|
||||
<listOptionValue builtIn="false" value="${DRIVERLIB_ROOT}/inc"/>
|
||||
<listOptionValue builtIn="false" value="${DRIVERLIB_ROOT}"/>
|
||||
<listOptionValue builtIn="false" value="${DEVICE_SUPPORT_ROOT}"/>
|
||||
<listOptionValue builtIn="false" value="${DEVICE_SUPPORT_ROOT}/common/include"/>
|
||||
<listOptionValue builtIn="false" value="${DEVICE_SUPPORT_ROOT}/headers/include"/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DEFINE.108716283" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DEFINE" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="RAM"/>
|
||||
<listOptionValue builtIn="false" value="CPU1"/>
|
||||
</option>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DEBUGGING_MODEL.699353022" name="Debugging model" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DEBUGGING_MODEL" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DEBUGGING_MODEL.SYMDEBUG__DWARF" valueType="enumerated"/>
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||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DIAG_WARNING.2024698653" name="Treat diagnostic <id> as warning (--diag_warning, -pdsw)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DIAG_WARNING" valueType="stringList">
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||||
<listOptionValue builtIn="false" value="225"/>
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||||
</option>
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||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DISPLAY_ERROR_NUMBER.1764770028" name="Emit diagnostic identifier numbers (--display_error_number, -pden)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
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||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.ABI.839880149" name="Application binary interface [See 'General' page to edit] (--abi)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.ABI" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.ABI.eabi" valueType="enumerated"/>
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||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.ADVICE__PERFORMANCE.2118869599" name="Provide advice on optimization techniques (--advice:performance)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.ADVICE__PERFORMANCE" value="--advice:performance=all" valueType="string"/>
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||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__C_SRCS.1389640914" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__C_SRCS"/>
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||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__CPP_SRCS.862940826" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__CPP_SRCS"/>
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||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__ASM_SRCS.1385584034" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__ASM_SRCS"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__ASM2_SRCS.1156274825" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compiler.inputType__ASM2_SRCS"/>
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||||
</tool>
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||||
<tool id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.linkerDebug.1507145766" name="C2000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.linkerDebug">
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.MAP_FILE.113914767" name="Link information (map) listed into <file> (--map_file, -m)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.MAP_FILE" value=""${ProjName}.map"" valueType="string"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.OUTPUT_FILE.538790041" name="Specify output file name (--output_file, -o)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.OUTPUT_FILE" value="${ProjName}.out" valueType="string"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.STACK_SIZE.1369775274" name="Set C system stack size (--stack_size, -stack)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.STACK_SIZE" value="0x200" valueType="string"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.LIBRARY.534417005" name="Include library file or command file as input (--library, -l)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.LIBRARY" valueType="libs">
|
||||
<listOptionValue builtIn="false" value="libc.a"/>
|
||||
<listOptionValue builtIn="false" value="c28x_vcrc_library_fpu32.lib"/>
|
||||
<listOptionValue builtIn="false" value="driverlib.lib"/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.SEARCH_PATH.159667453" name="Add <dir> to library search path (--search_path, -i)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.SEARCH_PATH" valueType="libPaths">
|
||||
<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/lib"/>
|
||||
<listOptionValue builtIn="false" value="${DRIVERLIB_ROOT}/ccs/Debug"/>
|
||||
<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/lib"/>
|
||||
<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.DEFINE.1534677119" name="Pre-define preprocessor macro _name_ to _value_ (--define)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.DEFINE" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="RAM"/>
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||||
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|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.DISPLAY_ERROR_NUMBER.1024972114" name="Emit diagnostic identifier numbers (--display_error_number)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.XML_LINK_INFO.186019100" name="Detailed link information data-base into <file> (--xml_link_info, -xml_link_info)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.linkerID.XML_LINK_INFO" value=""${ProjName}_linkInfo.xml"" valueType="string"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__CMD_SRCS.296204763" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__CMD_SRCS"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__CMD2_SRCS.568999501" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__CMD2_SRCS"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__GEN_CMDS.1619943212" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exeLinker.inputType__GEN_CMDS"/>
|
||||
</tool>
|
||||
<tool id="com.ti.ccstudio.buildDefinitions.C2000_20.2.hex.661837286" name="C2000 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.hex"/>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="2837x_vcu2_crc_16.com.ti.ccstudio.buildDefinitions.C2000.ProjectType.1933305957" name="C2000" projectType="com.ti.ccstudio.buildDefinitions.C2000.ProjectType"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
|
||||
<project-mappings>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>
|
||||
</project-mappings>
|
||||
</storageModule>
|
||||
<storageModule moduleId="refreshScope"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
<storageModule moduleId="null.endianPreference"/>
|
||||
<storageModule moduleId="cpuFamily"/>
|
||||
</cproject>
|
||||
@@ -0,0 +1,125 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>280015x_vcrc_crc_24</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<arguments>
|
||||
<dictionary>
|
||||
<key>?name?</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.append_environment</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildArguments</key>
|
||||
<value>-k</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildCommand</key>
|
||||
<value>${CCS_UTILS_DIR}/bin/gmake</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildLocation</key>
|
||||
<value>${BuildDirectory}</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
|
||||
<value>clean</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.contents</key>
|
||||
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.stopOnError</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>com.ti.ccstudio.core.ccsNature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>280015x_RAM_lnk_cpu1_crc24.cmd</name>
|
||||
<type>1</type>
|
||||
<locationURI>PARENT-3-PROJECT_LOC/cmd/280015x_RAM_lnk_cpu1_crc24.cmd</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>dsp_examples_setup.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>PARENT-2-PROJECT_LOC/common/dsp_examples_setup.c</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<variableList>
|
||||
<variable>
|
||||
<name>DEVICE</name>
|
||||
<value>f280015x</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>DEVICE_SUPPORT_ROOT</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/device_support/$%7BDEVICE%7D</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>DRIVERLIB_ROOT</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/driverlib/$%7BDEVICE%7D/driverlib</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>F2838X_ROOT_DIR</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/device_support/f2838x</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>VCU2_ROOT_DIR</name>
|
||||
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>copy_PARENT</name>
|
||||
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>copy_PARENT1</name>
|
||||
<value>$%7Bcopy_PARENT%7D/examples</value>
|
||||
</variable>
|
||||
</variableList>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,24 @@
|
||||
<?xml version="1.0" encoding="ISO-8859-15"?>
|
||||
<DSS>
|
||||
<SETUP>
|
||||
<FPGA_REQUIRED>"FALSE"</FPGA_REQUIRED>
|
||||
<ITERATIONS>
|
||||
<NUMBER>"1"</NUMBER>
|
||||
</ITERATIONS>
|
||||
|
||||
<CONFIG id="1">
|
||||
<LOAD>
|
||||
<PATH>"RAM\2837x_vcu2_crc_24.out"</PATH>
|
||||
<CORE>"1"</CORE>
|
||||
<ALIAS>"TEST_CPU"</ALIAS>
|
||||
</LOAD>
|
||||
</CONFIG>
|
||||
|
||||
<CONFIG id="2">
|
||||
<LOAD>
|
||||
<PATH>"FLASH\2837x_vcu2_crc_24.out"</PATH>
|
||||
<CORE>"1"</CORE>
|
||||
</LOAD>
|
||||
</CONFIG>
|
||||
</SETUP>
|
||||
</DSS>
|
||||
@@ -0,0 +1,285 @@
|
||||
//#############################################################################
|
||||
//! \file /2838x_vcrc_crc_24/main.c
|
||||
//!
|
||||
//! \brief Demo code for the 24-bit CRC routine(VCU and C)
|
||||
//!
|
||||
//! \date April 9, 2020
|
||||
//!
|
||||
//! This example shows how to
|
||||
//! -# use the vcrc supported 24-bit CRC routines from the library
|
||||
//! -# use a C based table lookup routine to run a 24-bit CRC check using
|
||||
//! any 24-bit polynomial
|
||||
//! -# demonstrate the link time CRC generation(using the
|
||||
//! polynomials 0x8005 and 0x1021) on a specified section of memory
|
||||
//
|
||||
// Group: C2000
|
||||
// Target Family: F2838x
|
||||
//
|
||||
//#############################################################################
|
||||
// $TI Release: C28x VCU Library V2.28.00.00 $
|
||||
// $Release Date: Oct 29, 2024 $
|
||||
// $Copyright: Copyright (C) 2019 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
|
||||
//*****************************************************************************
|
||||
// includes
|
||||
//*****************************************************************************
|
||||
#include "crc_tbl.h"
|
||||
#include "vcu2_types.h"
|
||||
#include "vcu2_crc.h"
|
||||
#include "crctable0x5d6dcb.h"
|
||||
#include "crctable0x5d6dcbreflected.h"
|
||||
#include "dsp_examples_setup.h"
|
||||
|
||||
//!
|
||||
//! \defgroup CRC24_EXAMPLES Cyclic Redundancy Check 24-bit Example
|
||||
|
||||
//!
|
||||
//! \ingroup CRC24_EXAMPLES
|
||||
// @{
|
||||
|
||||
//*****************************************************************************
|
||||
// defines
|
||||
//*****************************************************************************
|
||||
#define NBYTES (128)
|
||||
#define NWORDS (NBYTES/2)
|
||||
//*****************************************************************************
|
||||
// globals
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("testInput")
|
||||
#else
|
||||
#pragma DATA_SECTION(testInput,"testInput")
|
||||
#endif //__cplusplus
|
||||
|
||||
//\brief test input
|
||||
//
|
||||
// This vector is declared as a static const in order for the linker to
|
||||
// be able to run the CRC algorithm on it. It needn't be either static
|
||||
// or const for the C and VCU routines
|
||||
//
|
||||
static const uint16_t testInput[NWORDS] = {
|
||||
0x4001, 0x8002, 0xC003, 0x0004, 0x4005, 0x8006, 0xC007, 0x0008,
|
||||
0x4009, 0x800A, 0xC00B, 0x000C, 0x400D, 0x800E, 0xC00F, 0x0010,
|
||||
0x4011, 0x8012, 0xC013, 0x0014, 0x4015, 0x8016, 0xC017, 0x0018,
|
||||
0x4019, 0x801A, 0xC01B, 0x001C, 0x401D, 0x801E, 0xC01F, 0x0020,
|
||||
0x4021, 0x8022, 0xC023, 0x0024, 0x4025, 0x8026, 0xC027, 0x0028,
|
||||
0x4029, 0x802A, 0xC02B, 0x002C, 0x402D, 0x802E, 0xC02F, 0x0030,
|
||||
0x4031, 0x8032, 0xC033, 0x0034, 0x4035, 0x8036, 0xC037, 0x0038,
|
||||
0x4039, 0x803A, 0xC03B, 0x003C, 0x403D, 0x803E, 0xC03F, 0x0040,
|
||||
};
|
||||
|
||||
// \brief linker generated object(CRC table)
|
||||
//
|
||||
extern CRC_TABLE linkerCrcTable;
|
||||
|
||||
// \brief object of the structure CRC_Obj
|
||||
//
|
||||
CRC_Obj CRC;
|
||||
// \brief handle(pointer) to the CRC object
|
||||
//
|
||||
CRC_Handle handleCRC;
|
||||
// \brief A single record(element) from the CRC table object
|
||||
//
|
||||
CRC_RECORD linkerCrcRecord;
|
||||
// \brief pointer to the CRC table object
|
||||
//
|
||||
CRC_TABLE *pLinkerCrcTable;
|
||||
|
||||
uint16_t pass = 0;
|
||||
uint16_t fail = 0;
|
||||
//*****************************************************************************
|
||||
// Function Prototypes
|
||||
//*****************************************************************************
|
||||
void error(void);
|
||||
|
||||
//*****************************************************************************
|
||||
// function definitions
|
||||
//*****************************************************************************
|
||||
|
||||
//!
|
||||
//! \brief main routine for the 24-bit CRC example
|
||||
//! \return returns a 1
|
||||
//!
|
||||
//! This example shows how to
|
||||
//! -# use the vcu2 supported 24-bit CRC routines from the library
|
||||
//! -# use a C based table lookup routine to run a 24-bit CRC check using
|
||||
//! any 24-bit polynomial
|
||||
//! -# demonstrate the link time CRC generation(using the
|
||||
//! polynomial 0x5d6dcb) on a specified section of memory
|
||||
//!
|
||||
//! \note The variables used in the example are the same used in the CRC-8
|
||||
//! example and are not documented here again.
|
||||
//!
|
||||
int main( void )
|
||||
{
|
||||
// Locals
|
||||
int16_t i;
|
||||
uint32_t crcResultC;
|
||||
uint32_t crcResultVcu;
|
||||
uint32_t crcResultLnk;
|
||||
|
||||
#if defined(_FLASH)
|
||||
//
|
||||
// Setup the FLASH Banks
|
||||
//
|
||||
DSP_Example_setupFlash();
|
||||
#endif //defined(_FLASH)
|
||||
|
||||
//
|
||||
// Setup system clocking
|
||||
//
|
||||
DSP_Example_setupSysCtrl();
|
||||
|
||||
//*************************************************************************
|
||||
// Example #1: 128 bytes(x8, even), parity: low byte first
|
||||
//*************************************************************************
|
||||
//! \b Example \b #1, \b Part \b 1
|
||||
//! In this section we run a table lookup CRC on the vector testInput. The
|
||||
//! table is specified in the header file "CrcTable0x5D6DCB.h" and
|
||||
//! the entries were generated from the polynomial
|
||||
//! \f$ x^{23}+x^{22}+x^{20}+x^{19}+x^{18}+x^{16}+x^{14}+x^{13}+x^{11}+x^{10}+x^{8}+x^{7}+x^{6}+x^{3}+x^{1}+1 \f$
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: Initialize the CRC object
|
||||
CRC.seedValue = INIT_CRC24;
|
||||
CRC.nMsgBytes = NBYTES;
|
||||
CRC.parity = CRC_parity_even;
|
||||
CRC.crcResult = 0;
|
||||
CRC.pMsgBuffer = (uint16_t *)&testInput[0];
|
||||
CRC.pCrcTable = (uint16_t *)&crc24Table[0];
|
||||
CRC.init = (void (*)(void *))CRC_init24Bit;
|
||||
CRC.run = (void (*)(void *))CRC_run24BitTableLookupC;
|
||||
|
||||
// Step 2: Initialize the handle
|
||||
handleCRC = &CRC;
|
||||
|
||||
// Step 3: Run the 24-bit table look-up CRC routine and save the first result
|
||||
CRC.init(handleCRC);
|
||||
CRC.run(handleCRC);
|
||||
crcResultC = CRC.crcResult;
|
||||
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #1, \b Part \b 2
|
||||
//! Now we run the VCU routine on the vector testInput. The polynomial
|
||||
//! employed by the VCU are fixed i.e.
|
||||
//! \f$ x^{23}+x^{22}+x^{20}+x^{19}+x^{18}+x^{16}+x^{14}+x^{13}+x^{11}+x^{10}+x^{8}+x^{7}+x^{6}+x^{3}+x^{1}+1 \f$
|
||||
//! (0x5d6dcb)
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//!
|
||||
//! Most of the object elements remain unchanged from the initial setup
|
||||
//!
|
||||
//! \note The VCU routine does not require a lookup table; pCrcTable can be
|
||||
//! reset to NULL or left as-is
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: Reset a few elements of the CRC object
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run24Bit;
|
||||
|
||||
// Step 2: Run the VCU 24-bit CRC routine and save the result
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu = CRC.crcResult;
|
||||
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #1, \b Part \b 3
|
||||
//! The linker will compute the CRC(s) of the section \c testInput
|
||||
//! and keep the result as a record in a CRC_TABLE structure
|
||||
//! \c linkerCrcTable.
|
||||
//!
|
||||
//! Each record from this table is an object of type CRC_RECORD. The
|
||||
//! elements of this structure are described in detail, at the time of
|
||||
//! writing, in SPRU513D, section 7.9
|
||||
//!
|
||||
//! \note
|
||||
//! -# In the event the linker is configured to run multiple algorithms
|
||||
//! on a section of memory, the result of those computations are placed in
|
||||
//! the records in an unspecified order. The user must poll the crc_alg_ID
|
||||
//! field of the record to determine which algorithm was run
|
||||
//!
|
||||
//*************************************************************************
|
||||
// Step 1: Initialize the CRC table pointer.
|
||||
pLinkerCrcTable = &linkerCrcTable;
|
||||
|
||||
// Step 2: Get the CRC results from the linker CRC table
|
||||
for(i = 0; i < pLinkerCrcTable->num_recs; i++){
|
||||
// Get the current CRC record
|
||||
linkerCrcRecord = pLinkerCrcTable->recs[i];
|
||||
// Get the linker generated CRC
|
||||
crcResultLnk = linkerCrcRecord.crc_value;
|
||||
if(linkerCrcRecord.crc_alg_ID == CRC24_FLEXRAY){ //0x5d6dcb
|
||||
(crcResultLnk == crcResultVcu)? pass++ : fail++;
|
||||
(crcResultVcu == crcResultC)? pass++ : fail++;
|
||||
}else{
|
||||
fail++;
|
||||
}
|
||||
}
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #2
|
||||
//! We now run the reflected algorithm using both a table lookup method and
|
||||
//! compare it against its equivalent VCU routine. The reflected CRC
|
||||
//! table is specified in the header files "CrcTable0x5d6dcbReflected.h" and
|
||||
//! "CrcTable0x5d6dcbReflected.h"; the entries were generated from the table
|
||||
//! indices 0,1,...255 by shifting out the LSB of the index and XOR'ing the
|
||||
//! remainder with the polynomial if the LSB was a 1
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: For the C routine, assign the correct look-up table and function
|
||||
// to the object and reset the CRC result
|
||||
CRC.crcResult = 0;
|
||||
CRC.pCrcTable = (uint16_t *)&crc24TableReflected[0];
|
||||
CRC.run = (void (*)(void *))CRC_run24BitReflectedTableLookupC;
|
||||
|
||||
// Step 2: Run the C routine, reflect and save the result
|
||||
CRC.run(handleCRC);
|
||||
crcResultC = ((uint32_t)(CRC_bitReflect((uint32_t)CRC.crcResult, 32))) >> 8;
|
||||
|
||||
// Step 3: Assign the VCU routine to the object and run it
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run24BitReflected;
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu = CRC.crcResult;
|
||||
|
||||
// Step 4: Compare the results of steps 2 and 3
|
||||
(crcResultC == crcResultVcu)? pass++ : fail++ ;
|
||||
|
||||
//*************************************************************************
|
||||
//!
|
||||
//! \endcode
|
||||
//!
|
||||
//*************************************************************************
|
||||
// End of test
|
||||
|
||||
//if the any of the example fails - code will loop forever in error function
|
||||
if (fail > 0) {
|
||||
error();
|
||||
}
|
||||
//if all the examples pass code will loop forever in the while below
|
||||
while(1);
|
||||
|
||||
// Execution never reaches this point
|
||||
return 1;
|
||||
}
|
||||
// End of main
|
||||
|
||||
void error(void)
|
||||
{
|
||||
ESTOP0; //Test failed!! Stop!
|
||||
for (;;);
|
||||
}
|
||||
|
||||
// @} //addtogroup
|
||||
|
||||
// End of file
|
||||
@@ -0,0 +1,9 @@
|
||||
// Setup Debug Environment
|
||||
expRemoveAll
|
||||
|
||||
expAdd('pass',getNatural())
|
||||
expAdd('fail',getNatural())
|
||||
expAdd('CRC',getNatural())
|
||||
expAdd('crcResultC',getHex())
|
||||
expAdd('crcResultVcu',getHex())
|
||||
expAdd('crcResultLnk',getHex())
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<?ccsproject version="1.0"?>
|
||||
<projectOptions>
|
||||
<deviceFamily value="C2000"/>
|
||||
<isTargetManual value="false"/>
|
||||
</projectOptions>
|
||||
@@ -0,0 +1,124 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
<storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
|
||||
<cconfiguration id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884" moduleId="org.eclipse.cdt.core.settings" name="RAM">
|
||||
<macros>
|
||||
<stringMacro name="DEVICE" type="VALUE_PATH_ANY" value="f280015x"/>
|
||||
<stringMacro name="VCU2_ROOT_DIR" type="VALUE_PATH_DIR" value="${PROJECT_ROOT}\..\..\..\"/>
|
||||
</macros>
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="RAM only configuration" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884" name="RAM" parent="com.ti.ccstudio.buildDefinitions.C2000.Debug">
|
||||
<folderInfo id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884." name="/" resourcePath="">
|
||||
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//#############################################################################
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//! \file /2837x_vcrc_crc_32/main.c
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//!
|
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//! \brief Demo code for the 32-bit CRC routine(VCU and C)
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//!
|
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//! \date April 9, 2020
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//!
|
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//! This example shows how to
|
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//! -# use the vcrc supported 32-bit CRC routines from the library
|
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//! -# use a C based table lookup routine to run a 32-bit CRC check using
|
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//! any 32-bit polynomial
|
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//! -# demonstrate the link time CRC generation(using the
|
||||
//! polynomials 0x04C11DB7 and 0x1EDC6F41) on a specified section of memory
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//
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// Group: C2000
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// Target Family: F2838x
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//
|
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//#############################################################################
|
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// $TI Release: C28x VCU Library V2.28.00.00 $
|
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// $Release Date: Oct 29, 2024 $
|
||||
// $Copyright: Copyright (C) 2019 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
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//#############################################################################
|
||||
|
||||
//*****************************************************************************
|
||||
// includes
|
||||
//*****************************************************************************
|
||||
#include "crc_tbl.h"
|
||||
#include "vcu2_types.h"
|
||||
#include "vcu2_crc.h"
|
||||
#include "crctable0x04c11db7.h"
|
||||
#include "crctable0x04c11db7reflected.h"
|
||||
#include "crctable0x1edc6f41.h"
|
||||
#include "crctable0x1edc6f41reflected.h"
|
||||
#include "dsp_examples_setup.h"
|
||||
|
||||
//!
|
||||
//! \defgroup CRC32_EXAMPLES Cyclic Redundancy Check 32-bit Example
|
||||
|
||||
//!
|
||||
//! \ingroup CRC32_EXAMPLES
|
||||
// @{
|
||||
|
||||
//*****************************************************************************
|
||||
// defines
|
||||
//*****************************************************************************
|
||||
#define NBYTES (128)
|
||||
#define NWORDS (NBYTES/2)
|
||||
//*****************************************************************************
|
||||
// globals
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("testInput")
|
||||
#else
|
||||
#pragma DATA_SECTION(testInput,"testInput")
|
||||
#endif //__cplusplus
|
||||
|
||||
//\brief test input
|
||||
//
|
||||
// This vector is declared as a static const in order for the linker to
|
||||
// be able to run the CRC algorithm on it. It needn't be either static
|
||||
// or const for the C and VCU routines
|
||||
//
|
||||
static const uint16_t testInput[NWORDS] = {
|
||||
0x4001, 0x8002, 0xC003, 0x0004, 0x4005, 0x8006, 0xC007, 0x0008,
|
||||
0x4009, 0x800A, 0xC00B, 0x000C, 0x400D, 0x800E, 0xC00F, 0x0010,
|
||||
0x4011, 0x8012, 0xC013, 0x0014, 0x4015, 0x8016, 0xC017, 0x0018,
|
||||
0x4019, 0x801A, 0xC01B, 0x001C, 0x401D, 0x801E, 0xC01F, 0x0020,
|
||||
0x4021, 0x8022, 0xC023, 0x0024, 0x4025, 0x8026, 0xC027, 0x0028,
|
||||
0x4029, 0x802A, 0xC02B, 0x002C, 0x402D, 0x802E, 0xC02F, 0x0030,
|
||||
0x4031, 0x8032, 0xC033, 0x0034, 0x4035, 0x8036, 0xC037, 0x0038,
|
||||
0x4039, 0x803A, 0xC03B, 0x003C, 0x403D, 0x803E, 0xC03F, 0x0040,
|
||||
};
|
||||
|
||||
// \brief linker generated object(CRC table)
|
||||
//
|
||||
extern CRC_TABLE linkerCrcTable;
|
||||
// \brief object of the structure CRC_Obj
|
||||
//
|
||||
CRC_Obj CRC;
|
||||
// \brief handle(pointer) to the CRC object
|
||||
//
|
||||
CRC_Handle handleCRC;
|
||||
// \brief A single record(element) from the CRC table object
|
||||
//
|
||||
CRC_RECORD linkerCrcRecord;
|
||||
// \brief pointer to the CRC table object
|
||||
//
|
||||
CRC_TABLE *pLinkerCrcTable;
|
||||
// \brief linker generated variables defining the load and run placements
|
||||
// of the testInput vector
|
||||
//
|
||||
extern uint32_t testInputLoadStart, testInputLoadSize, testInputRunStart;
|
||||
|
||||
uint16_t pass = 0;
|
||||
uint16_t fail = 0;
|
||||
//*****************************************************************************
|
||||
// Function Prototypes
|
||||
//*****************************************************************************
|
||||
void error(void);
|
||||
|
||||
//*****************************************************************************
|
||||
// function definitions
|
||||
//*****************************************************************************
|
||||
|
||||
//!
|
||||
//! \brief main routine for the 32-bit CRC example
|
||||
//! \return returns a 1
|
||||
//!
|
||||
//! This example shows how to
|
||||
//! -# use the vcu2 supported 32-bit CRC routines from the library
|
||||
//! -# use a C based table lookup routine to run a 32-bit CRC check using
|
||||
//! any 32-bit polynomial
|
||||
//! -# demonstrate the link time CRC generation(using the
|
||||
//! polynomials 0x04C11DB7 and 0x1EDC6F41) on a specified section of memory
|
||||
//!
|
||||
//! \note The variables used in the example are the same used in the CRC-8
|
||||
//! example and are not documented here again.
|
||||
//!
|
||||
int main( void )
|
||||
{
|
||||
// Locals
|
||||
int16_t i;
|
||||
uint32_t crcResultC_1, crcResultC_2 ;
|
||||
uint32_t crcResultVcu_1, crcResultVcu_2;
|
||||
uint32_t crcResultLnk;
|
||||
|
||||
#if defined(_FLASH)
|
||||
//
|
||||
// Setup the FLASH Banks
|
||||
//
|
||||
DSP_Example_setupFlash();
|
||||
#endif //defined(_FLASH)
|
||||
|
||||
//
|
||||
// Setup system clocking
|
||||
//
|
||||
// DSP_Example_setupSysCtrl();
|
||||
|
||||
//*************************************************************************
|
||||
// Example #1: 128 bytes(x8, even), parity: low byte first
|
||||
//*************************************************************************
|
||||
//! \b Example \b #1, \b Part \b 1
|
||||
//! In this section we run a table lookup CRC on the vector testInput. The
|
||||
//! table is specified in the header files "CrcTable0x04C11DB7.h" and
|
||||
//! "CrcTable0x1EDC6F41.h"respectively and the entries were generated from the
|
||||
//! polynomials \f$ x^{32}+x^{26}+x^{23}+x^{22}+x^{16}+x^{12}+x^{11}+x^{10}+x^{8}+x^{7}+x^{5}+x^{4}+x^{2}+x^{1}+1 \f$(CCITT-32, 0x04C11DB7) and
|
||||
//! \f$ x^{32}+x^{28}+x^{27}+x^{26}+x^{25}+x^{23}+x^{22}+x^{20}+x^{19}+x^{18}+x^{14}+x^{13}+x^{11}+x^{10}+x^{9}+x^{8}+x^{6}+1 \f$(0x1EDC6F41) respectively.
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: Copy the test input vector from its load location to the run location.
|
||||
// This is necessary since the section was declared within a UNION in the linker
|
||||
// command file
|
||||
memcpy((uint32_t *)&testInputRunStart, (uint32_t *)&testInputLoadStart,
|
||||
(uint32_t)&testInputLoadSize );
|
||||
|
||||
// Step 2: Initialize the CRC object
|
||||
CRC.seedValue = INIT_CRC32;
|
||||
CRC.nMsgBytes = NBYTES;
|
||||
CRC.parity = CRC_parity_even;
|
||||
CRC.crcResult = 0;
|
||||
CRC.pMsgBuffer = (uint16_t *)&testInput[0];
|
||||
CRC.pCrcTable = (uint16_t *)&crc32P1Table[0];
|
||||
CRC.init = (void (*)(void *))CRC_init32Bit;
|
||||
CRC.run = (void (*)(void *))CRC_run32BitTableLookupC;
|
||||
|
||||
// Step 3: Initialize the handle
|
||||
handleCRC = &CRC;
|
||||
|
||||
// Step 4: Run the 32-bit table look-up CRC routine and save the first result
|
||||
CRC.init(handleCRC);
|
||||
CRC.run(handleCRC);
|
||||
crcResultC_1 = CRC.crcResult;
|
||||
|
||||
// Step 5: Load the second lookup table and run the C routine
|
||||
CRC.pCrcTable = (uint16_t *)&crc32P2Table[0];
|
||||
CRC.crcResult = 0;
|
||||
CRC.run(handleCRC);
|
||||
crcResultC_2 = CRC.crcResult;
|
||||
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #1, \b Part \b 2
|
||||
//! Now we run the VCU routine on the vector testInput. The two
|
||||
//! polynomials employed by the VCU are fixed i.e.
|
||||
//! \f$ x^{32}+x^{26}+x^{23}+x^{22}+x^{16}+x^{12}+x^{11}+x^{10}+x^{8}+x^{7}+x^{5}+x^{4}+x^{2}+x^{1}+1 \f$(CCITT-32, 0x04C11DB7) and
|
||||
//! \f$ x^{32}+x^{28}+x^{27}+x^{26}+x^{25}+x^{23}+x^{22}+x^{20}+x^{19}+x^{18}+x^{14}+x^{13}+x^{11}+x^{10}+x^{9}+x^{8}+x^{6}+1 \f$(0x1EDC6F41) respectively
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//!
|
||||
//! Most of the object elements remain unchanged from the initial setup
|
||||
//!
|
||||
//! \note The VCU routine does not require a lookup table; pCrcTable can be
|
||||
//! reset to NULL or left as-is
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: Reset a few elements of the CRC object
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run32BitPoly1;
|
||||
|
||||
// Step 2: Run the VCU 32-bit CRC routine and save the result
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu_1 = CRC.crcResult;
|
||||
|
||||
// Step 3: Now for the other polynomial
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run32BitPoly2;
|
||||
|
||||
// Step 4: Run the VCU 32-bit CRC routine and save the result
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu_2 = CRC.crcResult;
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #1, \b Part \b 3
|
||||
//! The linker will compute the CRC(s) of the section \c testInput
|
||||
//! and keep the result as a record in a CRC_TABLE structure
|
||||
//! \c linkerCrcTable.
|
||||
//!
|
||||
//! Each record from this table is an object of type CRC_RECORD. The
|
||||
//! elements of this structure are described in detail, at the time of
|
||||
//! writing, in SPRU513D, section 7.9
|
||||
//!
|
||||
//! \note
|
||||
//! -# In the event the linker is configured to run multiple algorithms
|
||||
//! on a section of memory, the result of those computations are placed in
|
||||
//! the records in an unspecified order. The user must poll the crc_alg_ID
|
||||
//! field of the record to determine which algorithm was run
|
||||
//! -# Note the use of the \b UNION keyword in the linker command file around
|
||||
//! the \b testInput section to allow the linker to calculate two different
|
||||
//! 32-bit CRCs for the same memory block
|
||||
//!
|
||||
//*************************************************************************
|
||||
// Step 1: Initialize the CRC table pointer.
|
||||
|
||||
pLinkerCrcTable = &linkerCrcTable;
|
||||
|
||||
// Step 2: Get the CRC results from the linker CRC table
|
||||
for(i = 0; i < pLinkerCrcTable->num_recs; i++){
|
||||
// Get the current CRC record
|
||||
linkerCrcRecord = pLinkerCrcTable->recs[i];
|
||||
// Get the linker generated CRC
|
||||
crcResultLnk = linkerCrcRecord.crc_value;
|
||||
if(linkerCrcRecord.crc_alg_ID == CRC32_PRIME){ //0x04C11DB7
|
||||
(crcResultLnk == crcResultVcu_1)? pass++ : fail++;
|
||||
(crcResultVcu_1 == crcResultC_1)? pass++ : fail++;
|
||||
}else if(linkerCrcRecord.crc_alg_ID == CRC32_C){ //0x1EDC6F41
|
||||
(crcResultLnk == crcResultVcu_2)? pass++ : fail++;
|
||||
(crcResultVcu_2 == crcResultC_2)? pass++ : fail++;
|
||||
}else{
|
||||
fail++;
|
||||
}
|
||||
}
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #2
|
||||
//! We now run the reflected algorithm using both a table lookup method and
|
||||
//! compare it against its equivalent VCU routine. The reflected CRC
|
||||
//! table is specified in the header files "CrcTable0x04C11DB7Reflected.h" and
|
||||
//! "CrcTable0x1EDC6F41Reflected.h"; the entries were generated from the table
|
||||
//! indices 0,1,...255 by shifting out the LSB of the index and XOR'ing the
|
||||
//! remainder with the polynomial if the LSB was a 1
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: For the C routine, assign the correct look-up table and function
|
||||
// to the object and reset the CRC result
|
||||
CRC.crcResult = 0;
|
||||
CRC.pCrcTable = (uint16_t *)&crc32P1TableReflected[0];
|
||||
CRC.run = (void (*)(void *))CRC_run32BitReflectedTableLookupC;
|
||||
|
||||
// Step 2: Run the C routine, reflect and save the result
|
||||
CRC.run(handleCRC);
|
||||
crcResultC_1 = (uint32_t)(CRC_bitReflect((uint32_t)CRC.crcResult, 32));
|
||||
|
||||
// Step 3: Replace the lookup table with that of the second polynomial
|
||||
CRC.crcResult = 0;
|
||||
CRC.pCrcTable = (uint16_t *)&crc32P2TableReflected[0];
|
||||
CRC.run(handleCRC);
|
||||
crcResultC_2 = (uint32_t)(CRC_bitReflect((uint32_t)CRC.crcResult, 32));
|
||||
|
||||
// Step 4: Assign the VCU routine to the object and run it
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run32BitPoly1Reflected;
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu_1 = CRC.crcResult;
|
||||
|
||||
// Step 5: Assign the VCU routine(2nd polynomial) to the object and run it
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run32BitPoly2Reflected;
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu_2 = CRC.crcResult;
|
||||
|
||||
// Step 6: Compare the results of steps 2/3 with 4/5
|
||||
(crcResultC_1 == crcResultVcu_1)? pass++ : fail++ ;
|
||||
(crcResultC_2 == crcResultVcu_2)? pass++ : fail++ ;
|
||||
|
||||
//*************************************************************************
|
||||
//!
|
||||
//! \endcode
|
||||
//!
|
||||
//*************************************************************************
|
||||
// End of test
|
||||
|
||||
//if the any of the example fails - code will loop forever in error function
|
||||
if (fail > 0) {
|
||||
error();
|
||||
}
|
||||
//if all the examples pass code will loop forever in the while below
|
||||
while(1);
|
||||
|
||||
// Execution never reaches this point
|
||||
return 1;
|
||||
}
|
||||
// End of main
|
||||
|
||||
void error(void)
|
||||
{
|
||||
ESTOP0; //Test failed!! Stop!
|
||||
for (;;);
|
||||
}
|
||||
|
||||
// @} //addtogroup
|
||||
|
||||
// End of file
|
||||
@@ -0,0 +1,11 @@
|
||||
// Setup Debug Environment
|
||||
expRemoveAll
|
||||
|
||||
expAdd('pass',getNatural())
|
||||
expAdd('fail',getNatural())
|
||||
expAdd('CRC',getNatural())
|
||||
expAdd('crcResultC_1',getHex())
|
||||
expAdd('crcResultC_2',getHex())
|
||||
expAdd('crcResultVcu_1',getHex())
|
||||
expAdd('crcResultVcu_2',getHex())
|
||||
expAdd('crcResultLnk',getHex())
|
||||
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<?ccsproject version="1.0"?>
|
||||
<projectOptions>
|
||||
<deviceFamily value="C2000"/>
|
||||
</projectOptions>
|
||||
@@ -0,0 +1,120 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
<storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
|
||||
<cconfiguration id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884" moduleId="org.eclipse.cdt.core.settings" name="RAM">
|
||||
<macros>
|
||||
<stringMacro name="DEVICE" type="VALUE_PATH_ANY" value="f280015x"/>
|
||||
<stringMacro name="VCU2_ROOT_DIR" type="VALUE_PATH_DIR" value="${PROJECT_ROOT}\..\..\..\"/>
|
||||
</macros>
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="RAM only configuration" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884" name="RAM" parent="com.ti.ccstudio.buildDefinitions.C2000.Debug">
|
||||
<folderInfo id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884." name="/" resourcePath="">
|
||||
<toolChain id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.DebugToolchain.377806418" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.linkerDebug.1987669213">
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1176006880" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C2000.GenericC28xxDevice"/>
|
||||
<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
|
||||
<listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
|
||||
<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE=280015x_RAM_lnk_cpu1_crc8.cmd"/>
|
||||
<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
|
||||
<listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.5.0"/>
|
||||
<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
|
||||
<listOptionValue builtIn="false" value="PRODUCTS="/>
|
||||
<listOptionValue builtIn="false" value="PRODUCT_MACRO_IMPORTS={}"/>
|
||||
</option>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.510564304" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="20.2.1.LTS" valueType="string"/>
|
||||
<targetPlatform id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.targetPlatformDebug.1594721176" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.targetPlatformDebug"/>
|
||||
<builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.builderDebug.2140972548" keepEnvironmentInBuildfile="false" name="GNU Make" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.builderDebug"/>
|
||||
<tool id="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.compilerDebug.797928775" name="C2000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.exe.compilerDebug">
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.SILICON_VERSION.1544838164" name="Processor version (--silicon_version, -v)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.SILICON_VERSION" value="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.SILICON_VERSION.28" valueType="enumerated"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.LARGE_MEMORY_MODEL.1965876147" name="Option deprecated, set by default (--large_memory_model, -ml)" superClass="com.ti.ccstudio.buildDefinitions.C2000_20.2.compilerID.LARGE_MEMORY_MODEL" value="true" valueType="boolean"/>
|
||||
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,24 @@
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<SETUP>
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@@ -0,0 +1,437 @@
|
||||
//#############################################################################
|
||||
//! \file /2838x_vcrc_crc_8/main.c
|
||||
//!
|
||||
//! \brief Demo code for the 8-bit CRC routine(VCU and C)
|
||||
//!
|
||||
//! \date April 9, 2020
|
||||
//!
|
||||
//! This example shows how to
|
||||
//! -# use the VCRC supported 8-bit CRC routines from the library
|
||||
//! -# use a C based table lookup routine to run an 8-bit CRC check using
|
||||
//! any 8-bit polynomial
|
||||
//! -# demonstrate the link time CRC generation(using the
|
||||
//! polynomial 0x07) on a specified section of memory
|
||||
//
|
||||
// Group: C2000
|
||||
// Target Family: F2838x
|
||||
//
|
||||
//#############################################################################
|
||||
// $TI Release: C28x VCU Library V2.28.00.00 $
|
||||
// $Release Date: Oct 29, 2024 $
|
||||
// $Copyright: Copyright (C) 2019 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//#############################################################################
|
||||
|
||||
//*****************************************************************************
|
||||
// includes
|
||||
//*****************************************************************************
|
||||
#include "crc_tbl.h"
|
||||
#include "vcu2_types.h"
|
||||
#include "vcu2_crc.h"
|
||||
#include "crctable0x7.h"
|
||||
#include "crctable0x7reflected.h"
|
||||
#include "dsp_examples_setup.h"
|
||||
|
||||
//!
|
||||
//! \defgroup CRC8_EXAMPLES Cyclic Redundancy Check 8-bit Example
|
||||
|
||||
//!
|
||||
//! \ingroup CRC8_EXAMPLES
|
||||
// @{
|
||||
|
||||
//*****************************************************************************
|
||||
// defines
|
||||
//*****************************************************************************
|
||||
#define NBYTES (128)
|
||||
#define NWORDS (NBYTES/2)
|
||||
#define NBYTESLARGE (65560UL)
|
||||
#define NWORDSLARGE (NBYTESLARGE/2)
|
||||
//*****************************************************************************
|
||||
// globals
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("testInput")
|
||||
#else
|
||||
#pragma DATA_SECTION(testInput,"testInput")
|
||||
#endif //__cplusplus
|
||||
|
||||
//!\brief test input
|
||||
//!
|
||||
//! This vector is declared as a static const in order for the linker to
|
||||
//! be able to run the CRC algorithm on it. It needn't be either static
|
||||
//! or const for the C and VCU routines
|
||||
//!
|
||||
static const uint16_t testInput[NWORDS] = {
|
||||
0x4001, 0x8002, 0xC003, 0x0004, 0x4005, 0x8006, 0xC007, 0x0008,
|
||||
0x4009, 0x800A, 0xC00B, 0x000C, 0x400D, 0x800E, 0xC00F, 0x0010,
|
||||
0x4011, 0x8012, 0xC013, 0x0014, 0x4015, 0x8016, 0xC017, 0x0018,
|
||||
0x4019, 0x801A, 0xC01B, 0x001C, 0x401D, 0x801E, 0xC01F, 0x0020,
|
||||
0x4021, 0x8022, 0xC023, 0x0024, 0x4025, 0x8026, 0xC027, 0x0028,
|
||||
0x4029, 0x802A, 0xC02B, 0x002C, 0x402D, 0x802E, 0xC02F, 0x0030,
|
||||
0x4031, 0x8032, 0xC033, 0x0034, 0x4035, 0x8036, 0xC037, 0x0038,
|
||||
0x4039, 0x803A, 0xC03B, 0x003C, 0x403D, 0x803E, 0xC03F, 0x0040,
|
||||
};
|
||||
|
||||
#ifdef FLASH
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("testInputLarge")
|
||||
#else
|
||||
#pragma DATA_SECTION(testInputLarge,"testInputLarge")
|
||||
#endif //__cplusplus
|
||||
//!\brief test input (Large)
|
||||
//!
|
||||
//! This vector is declared as a static const in order for the linker to
|
||||
//! be able to run the CRC algorithm on it. It needn't be either static
|
||||
//! or const for the C and VCU routines. Its size is > 65536 bytes
|
||||
//!
|
||||
static const uint16_t testInputLarge[NWORDSLARGE] = {
|
||||
#include "data_input.h"
|
||||
};
|
||||
#endif //FLASH
|
||||
|
||||
//!\brief linker generated object(CRC table)
|
||||
//!
|
||||
extern CRC_TABLE linkerCrcTable;
|
||||
|
||||
//!\brief linker generated object(CRC table)
|
||||
//!
|
||||
extern CRC_TABLE linkerCrcTableLarge;
|
||||
|
||||
//!\brief object of the structure CRC_Obj
|
||||
//!
|
||||
CRC_Obj CRC;
|
||||
//!\brief handle(pointer) to the CRC object
|
||||
//!
|
||||
CRC_Handle handleCRC;
|
||||
//! \brief A single record(element) from the CRC table object
|
||||
//!
|
||||
CRC_RECORD linkerCrcRecord;
|
||||
//! \brief pointer to the CRC table object
|
||||
//!
|
||||
CRC_TABLE *pLinkerCrcTable;
|
||||
|
||||
uint16_t pass = 0;
|
||||
uint16_t fail = 0;
|
||||
|
||||
void error(void);
|
||||
|
||||
//*****************************************************************************
|
||||
// Function Prototypes
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
// function definitions
|
||||
//*****************************************************************************
|
||||
|
||||
//!
|
||||
//! \brief main routine for the 8-bit CRC example
|
||||
//! \return returns a 1
|
||||
//!
|
||||
//! This example shows how to
|
||||
//! -# use the vcu2 supported 8-bit CRC routine from the library
|
||||
//! -# use a C based table lookup routine to run an 8-bit CRC check using
|
||||
//! any 8-bit polynomial
|
||||
//! -# demonstrate the link time CRC generation(using the
|
||||
//! polynomial 0x07) on a specified section of memory
|
||||
//!
|
||||
int main( void )
|
||||
{
|
||||
// Locals
|
||||
int16_t i;
|
||||
uint32_t crcResultC;
|
||||
uint32_t crcResultVcu;
|
||||
uint32_t crcResultLnk;
|
||||
|
||||
#if defined(_FLASH)
|
||||
//
|
||||
// Setup the FLASH Banks
|
||||
//
|
||||
DSP_Example_setupFlash();
|
||||
#endif //defined(_FLASH)
|
||||
|
||||
//
|
||||
// Setup system clocking
|
||||
//
|
||||
DSP_Example_setupSysCtrl();
|
||||
|
||||
//*************************************************************************
|
||||
// Example #1: 128 bytes(x8, even), parity: low byte first
|
||||
//*************************************************************************
|
||||
//! \b Example \b #1, \b Part \b 1
|
||||
//! In this section we run a table lookup CRC on the vector testInput. The
|
||||
//! table is specified in the header file "CrcTable0x7.h" and the entries
|
||||
//! were generated from the polynomial \f$ x^{8}+x^{2}+x^{1}+1 \f$ (0x07)
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: Initialize the CRC object
|
||||
CRC.seedValue = INIT_CRC8;
|
||||
CRC.nMsgBytes = NBYTES;
|
||||
CRC.parity = CRC_parity_even;
|
||||
CRC.crcResult = 0;
|
||||
CRC.pMsgBuffer = (uint16_t *)&testInput[0];
|
||||
CRC.pCrcTable = (uint16_t *)&crc8Table[0];
|
||||
CRC.init = (void (*)(void *))CRC_init8Bit;
|
||||
CRC.run = (void (*)(void *))CRC_run8BitTableLookupC;
|
||||
|
||||
// Step 2: Initialize the handle
|
||||
handleCRC = &CRC;
|
||||
|
||||
// Step 3: Run the 8-bit table look-up CRC routine and save the result
|
||||
CRC.init(handleCRC);
|
||||
CRC.run(handleCRC);
|
||||
crcResultC = CRC.crcResult;
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #1, \b Part \b 2
|
||||
//! Now we run the VCU routine on the vector testInput. The
|
||||
//! polynomial employed by the VCU is fixed i.e.
|
||||
//! \f$ x^{8}+x^{2}+x^{1}+1 \f$ (0x07)
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//!
|
||||
//! Most of the object elements remain unchanged from the initial setup
|
||||
//!
|
||||
//! \note The VCU routine does not require a lookup table; pCrcTable can be
|
||||
//! reset to NULL or left as-is
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: Reset a few elements of the CRC object
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run8Bit;
|
||||
|
||||
// Step 2: Run the VCU 8-bit CRC routine and save the result
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu = CRC.crcResult;
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #1, \b Part \b 3
|
||||
//! The linker will compute the CRC of the section \c testInput
|
||||
//! and keep the result as a record in a CRC_TABLE structure
|
||||
//! \c linkerCrcTable.
|
||||
//!
|
||||
//! Each record from this table is an object of type CRC_RECORD. The
|
||||
//! elements of this structure are described in detail, at the time of
|
||||
//! writing, in SPRU513D, section 7.9
|
||||
//!
|
||||
//! \note
|
||||
//! -# In the event the linker is configured to run multiple algorithms
|
||||
//! on a section of memory, the result of those computations are placed in
|
||||
//! the records in an unspecified order. The user must poll the crc_alg_ID
|
||||
//! field of the record to determine which algorithm was run
|
||||
//!
|
||||
//*************************************************************************
|
||||
// Step 1: Initialize the CRC table pointer.
|
||||
|
||||
pLinkerCrcTable = &linkerCrcTable;
|
||||
|
||||
// Step 2: Get the CRC results from the linker CRC table
|
||||
for(i = 0; i < pLinkerCrcTable->num_recs; i++){
|
||||
// Get the current CRC record
|
||||
linkerCrcRecord = pLinkerCrcTable->recs[i];
|
||||
// Get the linker generated CRC
|
||||
crcResultLnk = linkerCrcRecord.crc_value;
|
||||
if(linkerCrcRecord.crc_alg_ID == CRC8_PRIME){ //0x7
|
||||
(crcResultLnk == crcResultVcu)? pass++ : fail++;
|
||||
(crcResultVcu == crcResultC)? pass++ : fail++;
|
||||
}else{
|
||||
fail++;
|
||||
}
|
||||
}
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #2
|
||||
//! We now run the reflected algorithm using both a table lookup method and
|
||||
//! compare it against its equivalent VCU routine. The reflected CRC
|
||||
//! table is specified in the header file "CrcTable0x7Reflected.h"; the
|
||||
//! entries were generated from the table indices 0,1,...255 by shifting out
|
||||
//! the LSB of the index and XOR'ing the remainder with the polynomial if the
|
||||
//! LSB was a 1
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: For the C routine, assign the correct look-up table and function
|
||||
// to the object and reset the CRC result
|
||||
CRC.crcResult = 0;
|
||||
CRC.pCrcTable = (uint16_t *)&crc8TableReflected[0];
|
||||
CRC.run = (void (*)(void *))CRC_run8BitTableLookupC;
|
||||
|
||||
// Step 2: Run the C routine, reflect and save the result
|
||||
CRC.run(handleCRC);
|
||||
crcResultC = (uint32_t)(CRC_bitReflect((uint32_t)CRC.crcResult, 8));
|
||||
|
||||
// Step 3: Assign the VCU routine to the object and run it
|
||||
CRC.crcResult = 0;
|
||||
CRC.run = (void (*)(void *))CRC_run8BitReflected;
|
||||
CRC.run(handleCRC);
|
||||
crcResultVcu = CRC.crcResult;
|
||||
|
||||
// Step 4: Compare the results of steps 2 and 3
|
||||
if(crcResultC == crcResultVcu){
|
||||
pass++;
|
||||
}else{
|
||||
fail++;
|
||||
}
|
||||
|
||||
//*************************************************************************
|
||||
//!
|
||||
//! \endcode
|
||||
//!
|
||||
//*************************************************************************
|
||||
#ifdef FLASH
|
||||
//*************************************************************************
|
||||
// Example #3: 65560 bytes(x8, even), parity: low byte first
|
||||
//*************************************************************************
|
||||
//! \b Example \b #3, \b Part \b 1
|
||||
//! In this section we run a table lookup CRC on the vector testInputLarge,
|
||||
//! whose size exceeds the 16-bit boundary.
|
||||
//! The table is specified in the header file "CrcTable0x7.h" and the entries
|
||||
//! were generated from the polynomial \f$ x^{8}+x^{2}+x^{1}+1 \f$ (0x07)
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: Initialize the CRC object
|
||||
CRC.pMsgBuffer = (uint16_t *)&testInputLarge[0];
|
||||
CRC.parity = CRC_parity_even;
|
||||
CRC.crcResult = 0;
|
||||
CRC.pCrcTable = (uint16_t *)&crc8Table[0];
|
||||
CRC.init = (void (*)(void *))CRC_init8Bit;
|
||||
CRC.run = (void (*)(void *))CRC_run8BitTableLookupC;
|
||||
|
||||
CRC.seedValue = INIT_CRC8;
|
||||
q = (uint16_t)((uint32_t)(NBYTESLARGE & 0xFFFF0000) >> 16); // multiples of 65536
|
||||
// Since we can do a max of 65535 bytes at a time, we need to add q
|
||||
// to r to do the remainder
|
||||
r = (uint16_t)((NBYTESLARGE & 0x0000FFFF)) + q; // modulus 65535
|
||||
|
||||
// Step 2: Initialize the handle
|
||||
handleCRC = &CRC;
|
||||
|
||||
// Step 3: Run the 8-bit table look-up CRC routine and save the result
|
||||
CRC.init(handleCRC);
|
||||
|
||||
// Run the CRC for 65535 bytes q times
|
||||
for(i = 0; i < q; i++){
|
||||
//When CRC starts on low byte, it ends on a low byte, the next
|
||||
// set of 65535 bytes must start with high byte of the last address
|
||||
CRC.nMsgBytes = 0xFFFF; // 65535 bytes
|
||||
CRC.run(handleCRC);
|
||||
CRC.seedValue = CRC.crcResult;
|
||||
CRC.parity ^= 1;
|
||||
CRC.pMsgBuffer = (uint16_t *)&testInputLarge[(i+1)*0x8000 - CRC.parity];
|
||||
}
|
||||
// Run the CRC on the remaining r bytes
|
||||
CRC.nMsgBytes = r; // <= 65535 bytes
|
||||
CRC.run(handleCRC);
|
||||
|
||||
crcResultC = CRC.crcResult;
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #3, \b Part \b 2
|
||||
//! Now we run the VCU routine on the vector testInput. The
|
||||
//! polynomial employed by the VCU is fixed i.e.
|
||||
//! \f$ x^{8}+x^{2}+x^{1}+1 \f$ (0x07)
|
||||
//! The parity chosen was CRC_parity_even indicating that the CRC will start
|
||||
//! from the low byte of the first word.
|
||||
//!
|
||||
//! Most of the object elements remain unchanged from the initial setup
|
||||
//!
|
||||
//! \note The VCU routine does not require a lookup table; pCrcTable can be
|
||||
//! reset to NULL or left as-is
|
||||
//! \code
|
||||
//*************************************************************************
|
||||
// Step 1: Reset a few elements of the CRC object
|
||||
CRC.pMsgBuffer = (uint16_t *)&testInputLarge[0];
|
||||
CRC.parity = CRC_parity_even;
|
||||
CRC.crcResult = 0;
|
||||
CRC.seedValue = INIT_CRC8;
|
||||
CRC.run = (void (*)(void *))CRC_run8Bit;
|
||||
|
||||
// Step 2: Run the VCU 8-bit CRC routine and save the result
|
||||
// Run the CRC for 65535 bytes q times
|
||||
for(i = 0; i < q; i++){
|
||||
CRC.nMsgBytes = 0xFFFF; // 65535 bytes
|
||||
CRC.run(handleCRC);
|
||||
CRC.seedValue = CRC.crcResult;
|
||||
CRC.parity ^= 1;
|
||||
CRC.pMsgBuffer = (uint16_t *)&testInputLarge[(i+1)*0x8000 - CRC.parity];
|
||||
}
|
||||
// Run the CRC on the remaining r bytes
|
||||
CRC.nMsgBytes = r; // <= 65535 bytes
|
||||
CRC.run(handleCRC);
|
||||
|
||||
crcResultVcu = CRC.crcResult;
|
||||
//*************************************************************************
|
||||
//! \endcode
|
||||
//!
|
||||
//! \b Example \b #3, \b Part \b 3
|
||||
//! The linker will compute the CRC of the section \c testInput
|
||||
//! and keep the result as a record in a CRC_TABLE structure
|
||||
//! \c linkerCrcTable.
|
||||
//!
|
||||
//! Each record from this table is an object of type CRC_RECORD. The
|
||||
//! elements of this structure are described in detail, at the time of
|
||||
//! writing, in SPRU513D, section 7.9
|
||||
//!
|
||||
//! \note
|
||||
//! -# In the event the linker is configured to run multiple algorithms
|
||||
//! on a section of memory, the result of those computations are placed in
|
||||
//! the records in an unspecified order. The user must poll the crc_alg_ID
|
||||
//! field of the record to determine which algorithm was run
|
||||
//!
|
||||
//*************************************************************************
|
||||
// Step 1: Initialize the CRC table pointer.
|
||||
|
||||
pLinkerCrcTable = &linkerCrcTableLarge;
|
||||
|
||||
// Step 2: Get the CRC results from the linker CRC table
|
||||
for(i = 0; i < pLinkerCrcTable->num_recs; i++){
|
||||
// Get the current CRC record
|
||||
linkerCrcRecord = pLinkerCrcTable->recs[i];
|
||||
// Get the linker generated CRC
|
||||
crcResultLnk = linkerCrcRecord.crc_value;
|
||||
if(linkerCrcRecord.crc_alg_ID == CRC8_PRIME){ //0x7
|
||||
(crcResultLnk == crcResultVcu)? pass++ : fail++;
|
||||
(crcResultVcu == crcResultC)? pass++ : fail++;
|
||||
}else{
|
||||
fail++;
|
||||
}
|
||||
}
|
||||
|
||||
//*************************************************************************
|
||||
//!
|
||||
//! \endcode
|
||||
//!
|
||||
//*************************************************************************
|
||||
#endif //FLASH
|
||||
// End of test
|
||||
|
||||
//if the any of the example fails - code will loop forever in error function
|
||||
if (fail > 0) {
|
||||
error();
|
||||
}
|
||||
|
||||
//if all the examples pass code will loop forever in the while below
|
||||
while(1);
|
||||
|
||||
// Execution never reaches this point
|
||||
return 1;
|
||||
}
|
||||
// End of main
|
||||
|
||||
void error(void)
|
||||
{
|
||||
ESTOP0; //Test failed!! Stop!
|
||||
for (;;);
|
||||
}
|
||||
|
||||
// @} //addtogroup
|
||||
|
||||
// End of file
|
||||
@@ -0,0 +1,9 @@
|
||||
// Setup Debug Environment
|
||||
expRemoveAll
|
||||
|
||||
expAdd('pass',getNatural())
|
||||
expAdd('fail',getNatural())
|
||||
expAdd('CRC',getNatural())
|
||||
expAdd('crcResultC',getHex())
|
||||
expAdd('crcResultVcu',getHex())
|
||||
expAdd('crcResultLnk',getHex())
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<?ccsproject version="1.0"?>
|
||||
<projectOptions>
|
||||
<deviceFamily value="C2000"/>
|
||||
<isTargetManual value="false"/>
|
||||
</projectOptions>
|
||||
@@ -0,0 +1,124 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
<storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
|
||||
<cconfiguration id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884" moduleId="org.eclipse.cdt.core.settings" name="RAM">
|
||||
<macros>
|
||||
<stringMacro name="DEVICE" type="VALUE_PATH_ANY" value="f28003x"/>
|
||||
<stringMacro name="VCU2_ROOT_DIR" type="VALUE_PATH_DIR" value="${PROJECT_ROOT}\..\..\..\"/>
|
||||
</macros>
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="RAM only configuration" id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884" name="RAM" parent="com.ti.ccstudio.buildDefinitions.C2000.Debug">
|
||||
<folderInfo id="com.ti.ccstudio.buildDefinitions.C2000.Debug.1897159884." name="/" resourcePath="">
|
||||
<toolChain id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.DebugToolchain.1680908961" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.linkerDebug.207463649">
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1371347383" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C2000.GenericC28xxDevice"/>
|
||||
<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
|
||||
<listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
|
||||
<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
|
||||
<listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.5.0"/>
|
||||
<listOptionValue builtIn="false" value="PRODUCTS="/>
|
||||
<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE=28003x_RAM_lnk_cpu1_configpoly.cmd"/>
|
||||
<listOptionValue builtIn="false" value="PRODUCT_MACRO_IMPORTS={}"/>
|
||||
<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
|
||||
</option>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.2115784230" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="22.6.0.LTS" valueType="string"/>
|
||||
<targetPlatform id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.targetPlatformDebug.1739410058" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.targetPlatformDebug"/>
|
||||
<builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.builderDebug.670605291" keepEnvironmentInBuildfile="false" name="GNU Make" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.builderDebug"/>
|
||||
<tool id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.compilerDebug.1610396939" name="C2000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.compilerDebug">
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.SILICON_VERSION.565978496" name="Processor version (--silicon_version, -v)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.SILICON_VERSION" value="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.SILICON_VERSION.28" valueType="enumerated"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.LARGE_MEMORY_MODEL.496735666" name="Option deprecated, set by default (--large_memory_model, -ml)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.LARGE_MEMORY_MODEL" value="true" valueType="boolean"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.UNIFIED_MEMORY.1707893846" name="Unified memory (--unified_memory, -mt)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.UNIFIED_MEMORY" value="true" valueType="boolean"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.CLA_SUPPORT.769709414" name="Specify CLA support (--cla_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.CLA_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.CLA_SUPPORT.cla1" valueType="enumerated"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.FLOAT_SUPPORT.35131833" name="Specify floating point support (--float_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.FLOAT_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.FLOAT_SUPPORT.fpu32" valueType="enumerated"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.TMU_SUPPORT.294400075" name="Specify TMU support (--tmu_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.TMU_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.TMU_SUPPORT.tmu0" valueType="enumerated"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.VCU_SUPPORT.93224506" name="Specify VCU support (--vcu_support)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.VCU_SUPPORT" value="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.VCU_SUPPORT.vcrc" valueType="enumerated"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.INCLUDE_PATH.1301578665" name="Add dir to #include search path (--include_path, -I)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.INCLUDE_PATH" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
|
||||
<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/include/vcu2"/>
|
||||
<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/include/vcrc"/>
|
||||
<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/include/common"/>
|
||||
<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/examples/common"/>
|
||||
<listOptionValue builtIn="false" value="${DRIVERLIB_ROOT}/inc"/>
|
||||
<listOptionValue builtIn="false" value="${DRIVERLIB_ROOT}"/>
|
||||
<listOptionValue builtIn="false" value="${DEVICE_SUPPORT_ROOT}/common/include"/>
|
||||
<listOptionValue builtIn="false" value="${DEVICE_SUPPORT_ROOT}/headers/include"/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DEFINE.689190274" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DEFINE" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="RAM"/>
|
||||
<listOptionValue builtIn="false" value="CPU1"/>
|
||||
</option>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DEBUGGING_MODEL.2118863065" name="Debugging model" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DEBUGGING_MODEL" value="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DEBUGGING_MODEL.SYMDEBUG__DWARF" valueType="enumerated"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DIAG_WARNING.1286012287" name="Treat diagnostic <id> as warning (--diag_warning, -pdsw)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DIAG_WARNING" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="225"/>
|
||||
</option>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DISPLAY_ERROR_NUMBER.615456587" name="Emit diagnostic identifier numbers (--display_error_number, -pden)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.ABI.1517022473" name="Application binary interface [See 'General' page to edit] (--abi)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.ABI" value="com.ti.ccstudio.buildDefinitions.C2000_22.6.compilerID.ABI.eabi" valueType="enumerated"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__C_SRCS.263117757" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__C_SRCS"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__CPP_SRCS.1193223276" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__CPP_SRCS"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__ASM_SRCS.1795283306" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__ASM_SRCS"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__ASM2_SRCS.1736436886" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.compiler.inputType__ASM2_SRCS"/>
|
||||
</tool>
|
||||
<tool id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.linkerDebug.207463649" name="C2000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exe.linkerDebug">
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.MAP_FILE.939129976" name="Link information (map) listed into <file> (--map_file, -m)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.MAP_FILE" value=""${ProjName}.map"" valueType="string"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.OUTPUT_FILE.405951203" name="Specify output file name (--output_file, -o)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.OUTPUT_FILE" value="${ProjName}.out" valueType="string"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.STACK_SIZE.1685421866" name="Set C system stack size (--stack_size, -stack)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.STACK_SIZE" value="0x200" valueType="string"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.LIBRARY.562561145" name="Include library file or command file as input (--library, -l)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.LIBRARY" valueType="libs">
|
||||
<listOptionValue builtIn="false" value="libc.a"/>
|
||||
<listOptionValue builtIn="false" value="driverlib.lib"/>
|
||||
<listOptionValue builtIn="false" value="c28x_vcrc_library_fpu32.lib"/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.SEARCH_PATH.1153778198" name="Add <dir> to library search path (--search_path, -i)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.SEARCH_PATH" valueType="libPaths">
|
||||
<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/lib"/>
|
||||
<listOptionValue builtIn="false" value="${DRIVERLIB_ROOT}/ccs/Debug"/>
|
||||
<listOptionValue builtIn="false" value="${VCU2_ROOT_DIR}/lib"/>
|
||||
<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.DEFINE.1424884264" name="Pre-define preprocessor macro _name_ to _value_ (--define)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.DEFINE" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="RAM"/>
|
||||
</option>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.DISPLAY_ERROR_NUMBER.824199220" name="Emit diagnostic identifier numbers (--display_error_number)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
|
||||
<option id="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.XML_LINK_INFO.699133548" name="Detailed link information data-base into <file> (--xml_link_info, -xml_link_info)" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.linkerID.XML_LINK_INFO" value=""${ProjName}_linkInfo.xml"" valueType="string"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__CMD_SRCS.1374072744" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__CMD_SRCS"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__CMD2_SRCS.1213280282" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__CMD2_SRCS"/>
|
||||
<inputType id="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__GEN_CMDS.854520486" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.exeLinker.inputType__GEN_CMDS"/>
|
||||
</tool>
|
||||
<tool id="com.ti.ccstudio.buildDefinitions.C2000_22.6.hex.707615611" name="C2000 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.C2000_22.6.hex"/>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="2837x_vcu2_crc_8.com.ti.ccstudio.buildDefinitions.C2000.ProjectType.1933305957" name="C2000" projectType="com.ti.ccstudio.buildDefinitions.C2000.ProjectType"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
|
||||
<project-mappings>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>
|
||||
</project-mappings>
|
||||
</storageModule>
|
||||
<storageModule moduleId="refreshScope"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
<storageModule moduleId="null.endianPreference"/>
|
||||
<storageModule moduleId="cpuFamily"/>
|
||||
</cproject>
|
||||
@@ -0,0 +1,117 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>28003x_vcrc_config_poly</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<arguments>
|
||||
<dictionary>
|
||||
<key>?name?</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.append_environment</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildArguments</key>
|
||||
<value>-k</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildCommand</key>
|
||||
<value>${CCS_UTILS_DIR}/bin/gmake</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildLocation</key>
|
||||
<value>${BuildDirectory}</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
|
||||
<value>clean</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.contents</key>
|
||||
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.stopOnError</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>com.ti.ccstudio.core.ccsNature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>28003x_RAM_lnk_cpu1_configpoly.cmd</name>
|
||||
<type>1</type>
|
||||
<locationURI>PARENT-3-PROJECT_LOC/cmd/28003x_RAM_lnk_cpu1_configpoly.cmd</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>dsp_examples_setup.c</name>
|
||||
<type>1</type>
|
||||
<locationURI>PARENT-2-PROJECT_LOC/common/dsp_examples_setup.c</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<variableList>
|
||||
<variable>
|
||||
<name>DEVICE</name>
|
||||
<value>f28003x</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>DEVICE_SUPPORT_ROOT</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/device_support/$%7BDEVICE%7D</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>DRIVERLIB_ROOT</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/driverlib/$%7BDEVICE%7D/driverlib</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>F2838X_ROOT_DIR</name>
|
||||
<value>$%7BPARENT-7-PROJECT_LOC%7D/device_support/f2838x</value>
|
||||
</variable>
|
||||
<variable>
|
||||
<name>VCU2_ROOT_DIR</name>
|
||||
<value>$%7BPARENT-3-PROJECT_LOC%7D</value>
|
||||
</variable>
|
||||
</variableList>
|
||||
</projectDescription>
|
||||
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Reference in New Issue
Block a user