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@@ -1,87 +0,0 @@
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MEMORY
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{
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PAGE 0 :
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/* BEGIN is used for the "boot to SARAM" bootloader mode */
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BEGIN : origin = 0x000000, length = 0x000002
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RAMM0 : origin = 0x000123, length = 0x0002DD
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RAMD0 : origin = 0x00B000, length = 0x000800
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RAMLS0_3 : origin = 0x008000, length = 0x002000
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RAMLS4 : origin = 0x00A000, length = 0x000800
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RESET : origin = 0x3FFFC0, length = 0x000002
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PAGE 1 :
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BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
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RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
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// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
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RAMD1 : origin = 0x00B800, length = 0x000800
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RAMLS5 : origin = 0x00A800, length = 0x000800
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RAMGS0 : origin = 0x00C000, length = 0x001000
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RAMGS1 : origin = 0x00D000, length = 0x001000
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RAMGS2 : origin = 0x00E000, length = 0x001000
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RAMGS3 : origin = 0x00F000, length = 0x001000
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RAMGS4 : origin = 0x010000, length = 0x001000
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RAMGS5 : origin = 0x011000, length = 0x001000
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RAMGS6 : origin = 0x012000, length = 0x001000
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RAMGS7 : origin = 0x013000, length = 0x000FF8
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// RAMGS7_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
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CANA_MSG_RAM : origin = 0x049000, length = 0x000800
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CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
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}
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SECTIONS
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{
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codestart : > BEGIN, PAGE = 0
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.text : > RAMLS0_3, PAGE = 0
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.cinit : > RAMM0, PAGE = 0
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.switch : > RAMM0, PAGE = 0
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.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
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.stack : > RAMM1, PAGE = 1
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#if defined(__TI_EABI__)
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.bss : > RAMLS5, PAGE = 1
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.bss:output : > RAMLS4, PAGE = 0
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.init_array : > RAMM0, PAGE = 0
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.const : > RAMLS5, PAGE = 1
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.data : > RAMLS5, PAGE = 1
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.sysmem : > RAMLS5, PAGE = 1
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#else
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.pinit : > RAMM0, PAGE = 0
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.ebss : > RAMLS5, PAGE = 1
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.econst : > RAMLS5, PAGE = 1
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.esysmem : > RAMLS5, PAGE = 1
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#endif
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Filter_RegsFile : > RAMGS0, PAGE = 1
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ramgs0 : > RAMGS0, PAGE = 1
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ramgs1 : > RAMGS1, PAGE = 1
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#ifdef __TI_COMPILER_VERSION__
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#if __TI_COMPILER_VERSION__ >= 15009000
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.TI.ramfunc : {} > RAMM0, PAGE = 0
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#else
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ramfuncs : > RAMM0 PAGE = 0
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#endif
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#endif
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/* The following section definition are for SDFM examples */
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Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
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Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
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Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
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Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
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Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
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}
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/*
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//===========================================================================
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// End of file.
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//===========================================================================
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*/
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@@ -1,231 +0,0 @@
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// The user must define CLA_C in the project linker settings if using the
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// CLA C compiler
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// Project Properties -> C2000 Linker -> Advanced Options -> Command File
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// Preprocessing -> --define
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#ifdef CLA_C
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// Define a size for the CLA scratchpad area that will be used
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// by the CLA compiler for local symbols and temps
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// Also force references to the special symbols that mark the
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// scratchpad are.
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CLA_SCRATCHPAD_SIZE = 0x100;
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--undef_sym=__cla_scratchpad_end
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--undef_sym=__cla_scratchpad_start
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#endif //CLA_C
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MEMORY
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{
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PAGE 0 :
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/* BEGIN is used for the "boot to SARAM" bootloader mode */
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BEGIN : origin = 0x080000, length = 0x000002
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RAMM0 : origin = 0x000123, length = 0x0002DD
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RAMD0 : origin = 0x00B000, length = 0x000800
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RAMLS0 : origin = 0x008000, length = 0x000800
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RAMLS1 : origin = 0x008800, length = 0x000800
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/* RAMLS4 : origin = 0x00A000, length = 0x000800 */
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/* RAMLS5 : origin = 0x00A800, length = 0x000800 */
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RAMLS4_5 : origin = 0x00A000, length = 0x001000
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RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
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RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
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// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
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RESET : origin = 0x3FFFC0, length = 0x000002
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/* Flash sectors */
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FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
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FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
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FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
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FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
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FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
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FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
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FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
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FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
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FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
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FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
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FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
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FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
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FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
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FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
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// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
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PAGE 1 :
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BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
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RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
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// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
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RAMLS2 : origin = 0x009000, length = 0x000800
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RAMLS3 : origin = 0x009800, length = 0x000800
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RAMGS0 : origin = 0x00C000, length = 0x001000
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RAMGS1 : origin = 0x00D000, length = 0x001000
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RAMGS2 : origin = 0x00E000, length = 0x001000
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RAMGS3 : origin = 0x00F000, length = 0x001000
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RAMGS4 : origin = 0x010000, length = 0x001000
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RAMGS5 : origin = 0x011000, length = 0x001000
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RAMGS6 : origin = 0x012000, length = 0x001000
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RAMGS7 : origin = 0x013000, length = 0x001000
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RAMGS8 : origin = 0x014000, length = 0x001000
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RAMGS9 : origin = 0x015000, length = 0x001000
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RAMGS10 : origin = 0x016000, length = 0x001000
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// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
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// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
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RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
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RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
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RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
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EMIF1_CS0n : origin = 0x80000000, length = 0x10000000
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EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
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EMIF1_CS3n : origin = 0x00300000, length = 0x00080000
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EMIF1_CS4n : origin = 0x00380000, length = 0x00060000
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EMIF2_CS0n : origin = 0x90000000, length = 0x10000000
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EMIF2_CS2n : origin = 0x00002000, length = 0x00001000
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CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
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CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
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}
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SECTIONS
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{
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/* Allocate program areas: */
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.cinit : > FLASHB PAGE = 0, ALIGN(8)
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.text : > FLASHB PAGE = 0, ALIGN(8)
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codestart : > BEGIN PAGE = 0, ALIGN(8)
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.stack : > RAMM1 PAGE = 1
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.switch : > FLASHB PAGE = 0, ALIGN(8)
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/* Allocate uninitalized data sections: */
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#if defined(__TI_EABI__)
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.init_array : > FLASHB, PAGE = 0, ALIGN(8)
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.bss : > RAMLS2, PAGE = 1
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.bss:output : > RAMLS2, PAGE = 1
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.data : > RAMLS2, PAGE = 1
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.sysmem : > RAMLS2, PAGE = 1
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.const : > FLASHB, PAGE = 0, ALIGN(8)
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#else
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.pinit : > FLASHB, PAGE = 0, ALIGN(8)
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.ebss : > RAMLS2, PAGE = 1
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.esysmem : > RAMLS2, PAGE = 1
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.econst : > FLASHB PAGE = 0, ALIGN(8)
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#endif
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.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
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Filter_RegsFile : > RAMGS0, PAGE = 1
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.em2_cs0 : > EMIF2_CS0n, PAGE = 1
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.em2_cs2 : > EMIF2_CS2n, PAGE = 1
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/* CLA specific sections */
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#if defined(__TI_EABI__)
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Cla1Prog : LOAD = FLASHD,
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RUN = RAMLS4_5,
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LOAD_START(Cla1funcsLoadStart),
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LOAD_END(Cla1funcsLoadEnd),
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RUN_START(Cla1funcsRunStart),
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LOAD_SIZE(Cla1funcsLoadSize),
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PAGE = 0, ALIGN(8)
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#else
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Cla1Prog : LOAD = FLASHD,
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RUN = RAMLS4_5,
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LOAD_START(_Cla1funcsLoadStart),
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LOAD_END(_Cla1funcsLoadEnd),
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RUN_START(_Cla1funcsRunStart),
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LOAD_SIZE(_Cla1funcsLoadSize),
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PAGE = 0, ALIGN(8)
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#endif
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CLADataLS0 : > RAMLS0, PAGE=0
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CLADataLS1 : > RAMLS1, PAGE=0
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Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
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CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
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#ifdef __TI_COMPILER_VERSION__
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#if __TI_COMPILER_VERSION__ >= 15009000
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#if defined(__TI_EABI__)
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.TI.ramfunc : {} LOAD = FLASHD,
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RUN = RAMD0,
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LOAD_START(RamfuncsLoadStart),
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LOAD_SIZE(RamfuncsLoadSize),
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LOAD_END(RamfuncsLoadEnd),
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RUN_START(RamfuncsRunStart),
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RUN_SIZE(RamfuncsRunSize),
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RUN_END(RamfuncsRunEnd),
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PAGE = 0, ALIGN(8)
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#else
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.TI.ramfunc : {} LOAD = FLASHD,
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RUN = RAMD0,
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LOAD_START(_RamfuncsLoadStart),
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LOAD_SIZE(_RamfuncsLoadSize),
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LOAD_END(_RamfuncsLoadEnd),
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RUN_START(_RamfuncsRunStart),
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RUN_SIZE(_RamfuncsRunSize),
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RUN_END(_RamfuncsRunEnd),
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PAGE = 0, ALIGN(8)
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#endif
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#else
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ramfuncs : LOAD = FLASHD,
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RUN = RAMD0,
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LOAD_START(_RamfuncsLoadStart),
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LOAD_SIZE(_RamfuncsLoadSize),
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LOAD_END(_RamfuncsLoadEnd),
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RUN_START(_RamfuncsRunStart),
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RUN_SIZE(_RamfuncsRunSize),
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RUN_END(_RamfuncsRunEnd),
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PAGE = 0, ALIGN(8)
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#endif
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#endif
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/* The following section definition are for SDFM examples */
|
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Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
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Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
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Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
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Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
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#ifdef CLA_C
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/* CLA C compiler sections */
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//
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// Must be allocated to memory the CLA has write access to
|
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//
|
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CLAscratch :
|
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{ *.obj(CLAscratch)
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. += CLA_SCRATCHPAD_SIZE;
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*.obj(CLAscratch_end) } > RAMLS1, PAGE = 0
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|
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.scratchpad : > RAMLS1, PAGE = 0
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.bss_cla : > RAMLS1, PAGE = 0
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#if defined(__TI_EABI__)
|
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.const_cla : LOAD = FLASHB,
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RUN = RAMLS1,
|
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RUN_START(Cla1ConstRunStart),
|
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LOAD_START(Cla1ConstLoadStart),
|
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LOAD_SIZE(Cla1ConstLoadSize),
|
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PAGE = 0,
|
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ALIGN(4)
|
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#else
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.const_cla : LOAD = FLASHB,
|
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RUN = RAMLS1,
|
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RUN_START(_Cla1ConstRunStart),
|
||||
LOAD_START(_Cla1ConstLoadStart),
|
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LOAD_SIZE(_Cla1ConstLoadSize),
|
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PAGE = 0,
|
||||
ALIGN(4)
|
||||
#endif
|
||||
#endif //CLA_C
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,179 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.const : > FLASHF, PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
.cio : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHF PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
#if defined(__TI_EABI__)
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
LOAD_END(RamfuncsLoadEnd),
|
||||
RUN_START(RamfuncsRunStart),
|
||||
RUN_SIZE(RamfuncsRunSize),
|
||||
RUN_END(RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
|
||||
/* Allocate IQ math areas: */
|
||||
IQmath : > FLASHB, PAGE = 0, ALIGN(8) /* Math Code */
|
||||
IQmathTables : > FLASHC, PAGE = 0, ALIGN(8)
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,182 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
|
||||
/* BEGIN is used for the "boot to Flash" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMGS2, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.const : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
.cio : > RAMGS2, PAGE = 1
|
||||
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
/* Sine Table */
|
||||
SINTBL : > FLASHN, PAGE = 1
|
||||
|
||||
/* Data Log */
|
||||
DLOG : > RAMGS3, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
#if defined(__TI_EABI__)
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
LOAD_END(RamfuncsLoadEnd),
|
||||
RUN_START(RamfuncsRunStart),
|
||||
RUN_SIZE(RamfuncsRunSize),
|
||||
RUN_END(RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,147 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
|
||||
/* BEGIN is used for the "boot to Flash" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2_GS4 : origin = 0x00E000, length = 0x003000
|
||||
/*
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
*/
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMGS1 PAGE = 1
|
||||
.ebss : > RAMGS2_GS4 PAGE = 1
|
||||
.esysmem : > RAMLS5 PAGE = 1
|
||||
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(8)
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
.sysmem : > RAMGS1, PAGE = 1
|
||||
.cio : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,180 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
|
||||
/* BEGIN is used for the "boot to Flash" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS012 : origin = 0x008000, length = 0x001800
|
||||
//RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
//RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
//RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS345 : origin = 0x009800, length = 0x001800
|
||||
//RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
//RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
//RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
.ebss : >> RAMGS0 | RAMGS1 PAGE = 1
|
||||
.esysmem : > RAMGS6 PAGE = 1
|
||||
.cio : > RAMGS6 PAGE = 1
|
||||
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHG | FLASHH PAGE = 0, ALIGN(8)
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
fsk_corr_lib_data : > RAMGS5 PAGE = 1 /* Flash block for lib data */
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS012,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS012,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
SINETABLE : {} LOAD = FLASHF,
|
||||
RUN = RAMLS345,
|
||||
LOAD_START(_SineTableLoadStart),
|
||||
LOAD_SIZE(_SineTableLoadSize),
|
||||
LOAD_END(_SineTableLoadEnd),
|
||||
RUN_START(_SineTableRunStart),
|
||||
RUN_SIZE(_SineTableRunSize),
|
||||
RUN_END(_SineTableRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
SINETABLE : LOAD = FLASHF,
|
||||
RUN = RAMLS345,
|
||||
LOAD_START(_SineTableLoadStart),
|
||||
LOAD_SIZE(_SineTableLoadSize),
|
||||
LOAD_END(_SineTableLoadEnd),
|
||||
RUN_START(_SineTableRunStart),
|
||||
RUN_SIZE(_SineTableRunSize),
|
||||
RUN_END(_SineTableRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
FlashAPIDataSection : > RAMM1, PAGE = 1, ALIGN(8)
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,185 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
|
||||
/* BEGIN is used for the "boot to Flash" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* DCSM Z1 Zone Select Contents (!!Movable!!) */
|
||||
/* Z1 OTP. Z1 password locations / Flash and RAM partitioning */
|
||||
DCSM_ZSEL_Z1_LINK : origin = 0x78000, length = 0x00020
|
||||
DCSM_ZSEL_Z1_P0 : origin = 0x78020, length = 0x000020
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.const : > FLASHF, PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
.cio : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
#if defined(__TI_EABI__)
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
LOAD_END(RamfuncsLoadEnd),
|
||||
RUN_START(RamfuncsRunStart),
|
||||
RUN_SIZE(RamfuncsRunSize),
|
||||
RUN_END(RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
ZONE1_RAM : > RAMLS2, PAGE = 0
|
||||
UNSECURE_RAM : > RAMLS4, PAGE = 0
|
||||
dcsm_zsel_z1 : > DCSM_ZSEL_Z1_P0, PAGE = 0
|
||||
dcsm_zsel_link_pointer : > DCSM_ZSEL_Z1_LINK, PAGE = 0
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,176 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
|
||||
/* BEGIN is used for the "boot to Flash" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.const : > FLASHF, PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
.cio : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHF PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
SHARERAMGS2 : > RAMGS2, PAGE = 1
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
#if defined(__TI_EABI__)
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
LOAD_END(RamfuncsLoadEnd),
|
||||
RUN_START(RamfuncsRunStart),
|
||||
RUN_SIZE(RamfuncsRunSize),
|
||||
RUN_END(RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,175 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
|
||||
/* BEGIN is used for the "boot to Flash" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHE PAGE = 0, ALIGN(8)
|
||||
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMLS5, PAGE = 1
|
||||
.data : > RAMGS6, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.const : > FLASHF, PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
.cio : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
#if defined(__TI_EABI__)
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
LOAD_END(RamfuncsLoadEnd),
|
||||
RUN_START(RamfuncsRunStart),
|
||||
RUN_SIZE(RamfuncsRunSize),
|
||||
RUN_END(RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,194 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
|
||||
/* BEGIN is used for the "boot to Flash" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
EMIF1_CS0n : origin = 0x80000000, length = 0x10000000
|
||||
EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
|
||||
EMIF1_CS3n : origin = 0x00300000, length = 0x00080000
|
||||
EMIF1_CS4n : origin = 0x00380000, length = 0x00060000
|
||||
EMIF2_CS0n : origin = 0x90000000, length = 0x10000000
|
||||
EMIF2_CS2n : origin = 0x00002000, length = 0x00001000
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
.farbss : > EMIF1_CS0n, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.const : > FLASHF, PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
.cio : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHF PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
.em1_cs0 : > EMIF1_CS0n, PAGE = 1
|
||||
.em1_cs2 : > EMIF1_CS2n, PAGE = 1
|
||||
.em1_cs3 : > EMIF1_CS3n, PAGE = 1
|
||||
.em1_cs4 : > EMIF1_CS4n, PAGE = 1
|
||||
.em2_cs0 : > EMIF2_CS0n, PAGE = 1
|
||||
.em2_cs2 : > EMIF2_CS2n, PAGE = 1
|
||||
|
||||
/* Initalized sections go in Flash */
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.farconst : > EMIF1_CS0n, PAGE = 1
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
#if defined(__TI_EABI__)
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
LOAD_END(RamfuncsLoadEnd),
|
||||
RUN_START(RamfuncsRunStart),
|
||||
RUN_SIZE(RamfuncsRunSize),
|
||||
RUN_END(RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,148 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x0000A2, length = 0x00035E
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.text : > FLASHB PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
|
||||
/* Initalized sections go in Flash */
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.const : > FLASHF, PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
.cio : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHF PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
SHARERAMGS2 : > RAMGS2, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
#if defined(__TI_EABI__)
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
LOAD_END(RamfuncsLoadEnd),
|
||||
RUN_START(RamfuncsRunStart),
|
||||
RUN_SIZE(RamfuncsRunSize),
|
||||
RUN_END(RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,153 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
RAMM0 : origin = 0x0000A2, length = 0x00035E
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
|
||||
EMIF1_CS0n : origin = 0x80000000, length = 0x10000000
|
||||
EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
|
||||
EMIF1_CS3n : origin = 0x00300000, length = 0x00080000
|
||||
EMIF1_CS4n : origin = 0x00380000, length = 0x00060000
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.text : > FLASHB PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
.farbss : > EMIF1_CS0n, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.const : > FLASHF, PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
.cio : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHF PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
/* Initalized sections go in Flash */
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.farconst : > EMIF1_CS0n, PAGE = 1
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
#if defined(__TI_EABI__)
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
LOAD_END(RamfuncsLoadEnd),
|
||||
RUN_START(RamfuncsRunStart),
|
||||
RUN_SIZE(RamfuncsRunSize),
|
||||
RUN_END(RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,195 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
|
||||
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 20012000
|
||||
GROUP { /* GROUP memory ranges for crc/checksum of entire flash */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* BEGIN is used for the "boot to Flash" bootloader mode */
|
||||
BEGIN : origin = 0x080000, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 20012000
|
||||
} crc(_table_name, algorithm=C28_CHECKSUM_16)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
|
||||
codestart : > BEGIN PAGE = 0, ALIGN(8)
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAMM1 PAGE = 1
|
||||
.switch : > FLASHB PAGE = 0, ALIGN(8)
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.const : > FLASHF, PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
|
||||
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
.cio : > RAMLS5, PAGE = 1
|
||||
/* Initalized sections go in Flash */
|
||||
.econst : >> FLASHF PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
SHARERAMGS2 : > RAMGS2, PAGE = 1
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
#if defined(__TI_EABI__)
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(RamfuncsLoadStart),
|
||||
LOAD_SIZE(RamfuncsLoadSize),
|
||||
LOAD_END(RamfuncsLoadEnd),
|
||||
RUN_START(RamfuncsRunStart),
|
||||
RUN_SIZE(RamfuncsRunSize),
|
||||
RUN_END(RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#else
|
||||
.TI.ramfunc : {} LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
#else
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAMLS0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
RUN_SIZE(_RamfuncsRunSize),
|
||||
RUN_END(_RamfuncsRunEnd),
|
||||
PAGE = 0, ALIGN(8)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
|
||||
/* crc/checksum section configured as COPY section to avoid including in executable */
|
||||
.TI.memcrc : type = COPY
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,153 +0,0 @@
|
||||
// The user must define CLA_C in the project linker settings if using the
|
||||
// CLA C compiler
|
||||
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
|
||||
// Preprocessing -> --define
|
||||
#ifdef CLA_C
|
||||
// Define a size for the CLA scratchpad area that will be used
|
||||
// by the CLA compiler for local symbols and temps
|
||||
// Also force references to the special symbols that mark the
|
||||
// scratchpad are.
|
||||
CLA_SCRATCHPAD_SIZE = 0x100;
|
||||
--undef_sym=__cla_scratchpad_end
|
||||
--undef_sym=__cla_scratchpad_start
|
||||
#endif //CLA_C
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
/* RAMLS4 : origin = 0x00A000, length = 0x000800 */
|
||||
/* RAMLS5 : origin = 0x00A800, length = 0x000800 */
|
||||
RAMLS4_5 : origin = 0x00A000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
//RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
EMIF1_CS0n : origin = 0x80000000, length = 0x10000000
|
||||
EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
|
||||
EMIF1_CS3n : origin = 0x00300000, length = 0x00080000
|
||||
EMIF1_CS4n : origin = 0x00380000, length = 0x00060000
|
||||
EMIF2_CS0n : origin = 0x90000000, length = 0x10000000
|
||||
EMIF2_CS2n : origin = 0x00002000, length = 0x00001000
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
|
||||
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
|
||||
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >> RAMD0 | RAMD1 | RAMGS5, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS2, PAGE = 1
|
||||
.bss:output : > RAMLS2, PAGE = 1
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS3, PAGE = 1
|
||||
.data : > RAMLS3, PAGE = 1
|
||||
.sysmem : > RAMLS3, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS2, PAGE = 1
|
||||
.econst : > RAMLS3, PAGE = 1
|
||||
.esysmem : > RAMLS3, PAGE = 1
|
||||
#endif
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
.em1_cs0 : > EMIF1_CS0n, PAGE = 1
|
||||
.em1_cs2 : > EMIF1_CS2n, PAGE = 1
|
||||
.em1_cs3 : > EMIF1_CS3n, PAGE = 1
|
||||
.em1_cs4 : > EMIF1_CS4n, PAGE = 1
|
||||
.em2_cs0 : > EMIF2_CS0n, PAGE = 1
|
||||
.em2_cs2 : > EMIF2_CS2n, PAGE = 1
|
||||
|
||||
/* CLA specific sections */
|
||||
Cla1Prog : > RAMLS4_5, PAGE=0
|
||||
|
||||
CLADataLS0 : > RAMLS0, PAGE=1
|
||||
CLADataLS1 : > RAMLS1, PAGE=1
|
||||
|
||||
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
|
||||
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CLA_C
|
||||
/* CLA C compiler sections */
|
||||
//
|
||||
// Must be allocated to memory the CLA has write access to
|
||||
//
|
||||
CLAscratch :
|
||||
{ *.obj(CLAscratch)
|
||||
. += CLA_SCRATCHPAD_SIZE;
|
||||
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 1
|
||||
|
||||
.scratchpad : > RAMLS1, PAGE = 1
|
||||
.bss_cla : > RAMLS1, PAGE = 1
|
||||
.const_cla : > RAMLS1, PAGE = 1
|
||||
#endif //CLA_C
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,38 +0,0 @@
|
||||
/* Linker map for Soprano Shared Memory. */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program memory. This is a legacy description since the C28 has a unified memory model. */
|
||||
|
||||
|
||||
PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unified memory model. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* ===========================================================================
|
||||
* End of file.
|
||||
* ===========================================================================
|
||||
*/
|
||||
@@ -1,37 +0,0 @@
|
||||
/* Linker map for Soprano Shared Memory. */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program memory. This is a legacy description since the C28 has a unified memory model. */
|
||||
|
||||
PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unified memory model. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* ===========================================================================
|
||||
* End of file.
|
||||
* ===========================================================================
|
||||
*/
|
||||
@@ -1,121 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1_LS2 : origin = 0x008800, length = 0x001000
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >>RAMD0 | RAMLS0 | RAMLS1_LS2 | RAMLS3 | RAMLS4, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
|
||||
/* Allocate IQ math areas: */
|
||||
IQmath : > RAMLS0, PAGE = 0 /* Math Code */
|
||||
IQmathTables : > RAMLS1_LS2, PAGE = 0
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,124 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >> RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
.cio : > RAMGS2, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Sine Table */
|
||||
SINTBL : > RAMGS2, PAGE = 1
|
||||
|
||||
/* Data Log */
|
||||
DLOG : > RAMGS3, PAGE = 1
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,98 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
RAMGS0_2 : origin = 0x00C000, length = 0x003000
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >>RAMGS0_2, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,106 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2_GS4 : origin = 0x00E000, length = 0x003000
|
||||
/*
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
*/
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text :>> RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMLS5 | RAMGS0, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMGS1, PAGE = 1
|
||||
.ebss : > RAMGS2_GS4,PAGE = 1
|
||||
.econst : > RAMGS1, PAGE = 1
|
||||
.esysmem : > RAMGS1, PAGE = 1
|
||||
Filter_RegsFile : > RAMGS1, PAGE = 1
|
||||
|
||||
.sysmem : > RAMGS1, PAGE = 1
|
||||
.cio : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,126 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
.ebss : >> RAMGS0, PAGE = 1
|
||||
.econst : >> RAMLS5, PAGE = 0
|
||||
.esysmem : > RAMGS4, PAGE = 1
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS3, PAGE = 1
|
||||
|
||||
SINETABLE : > RAMGS6 PAGE = 1 /* Ram block for SINETABLE data */
|
||||
fsk_corr_lib_data : > RAMGS5 PAGE = 1 /* Flash block for lib data */
|
||||
|
||||
FlashAPIDataSection : > RAMM1, PAGE = 1, ALIGN(8)
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMD0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMD0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,132 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
/* DCSM Z1 Zone Select Contents (!!Movable!!) */
|
||||
/* Z1 OTP. Z1 password locations / Flash and RAM partitioning */
|
||||
DCSM_ZSEL_Z1_LINK : origin = 0x78000, length = 0x00020
|
||||
DCSM_ZSEL_Z1_P0 : origin = 0x78020, length = 0x000020
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : > RAMGS0, PAGE = 1
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMGS2, PAGE = 1
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMGS0, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
ZONE1_RAM : > RAMLS2, PAGE = 0
|
||||
UNSECURE_RAM : > RAMLS4, PAGE = 0
|
||||
dcsm_zsel_z1 : > DCSM_ZSEL_Z1_P0, PAGE = 0
|
||||
dcsm_zsel_link_pointer : > DCSM_ZSEL_Z1_LINK, PAGE = 0
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,141 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >> RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,116 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6to11_combined : origin = 0x012000, length = 0x006000
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : > RAMGS6to11_combined, PAGE = 1
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : >> RAMGS5 | RAMGS6to11_combined | RAMGS12, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.bss:cio : > RAMGS2, PAGE = 1
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : >> RAMGS5 | RAMGS6to11_combined, PAGE = 1
|
||||
.data : > RAMGS6to11_combined, PAGE = 1
|
||||
.sysmem : > RAMGS6to11_combined, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMGS4, PAGE = 1
|
||||
.econst : >> RAMGS5 | RAMGS6to11_combined, PAGE = 1
|
||||
.esysmem : > RAMGS6to11_combined, PAGE = 1
|
||||
.cio : > RAMGS2, PAGE = 1
|
||||
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,140 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
EMIF1_CS0n : origin = 0x80000000, length = 0x10000000
|
||||
EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
|
||||
EMIF1_CS3n : origin = 0x00300000, length = 0x00080000
|
||||
EMIF1_CS4n : origin = 0x00380000, length = 0x00060000
|
||||
EMIF2_CS0n : origin = 0x90000000, length = 0x10000000
|
||||
EMIF2_CS2n : origin = 0x00002000, length = 0x00001000
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
.farbss : > EMIF1_CS0n, PAGE = 1
|
||||
.farconst : > EMIF1_CS0n, PAGE = 1
|
||||
|
||||
.em1_cs0 : > EMIF1_CS0n, PAGE = 1
|
||||
.em1_cs2 : > EMIF1_CS2n, PAGE = 1
|
||||
.em1_cs3 : > EMIF1_CS3n, PAGE = 1
|
||||
.em1_cs4 : > EMIF1_CS4n, PAGE = 1
|
||||
.em2_cs0 : > EMIF2_CS0n, PAGE = 1
|
||||
.em2_cs2 : > EMIF2_CS2n, PAGE = 1
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,104 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x0000A2, length = 0x00035E
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
/* Flash sectors */
|
||||
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
|
||||
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
|
||||
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
|
||||
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
|
||||
|
||||
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,110 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x0000A2, length = 0x00035E
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
EMIF1_CS0n : origin = 0x80000000, length = 0x10000000
|
||||
EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
|
||||
EMIF1_CS3n : origin = 0x00300000, length = 0x00080000
|
||||
EMIF1_CS4n : origin = 0x00380000, length = 0x00060000
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
.farbss : > EMIF1_CS0n, PAGE = 1
|
||||
.farconst : > EMIF1_CS0n, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* Sections for EMIF ASRAM example */
|
||||
#if defined(__TI_EABI__)
|
||||
xintffuncs : LOAD = RAMM0,
|
||||
RUN = EMIF1_CS2n,
|
||||
LOAD_START(XintffuncsLoadStart),
|
||||
LOAD_END(XintffuncsLoadEnd),
|
||||
RUN_START(XintffuncsRunStart),
|
||||
PAGE = 0
|
||||
#else
|
||||
xintffuncs : LOAD = RAMM0,
|
||||
RUN = EMIF1_CS2n,
|
||||
LOAD_START(_XintffuncsLoadStart),
|
||||
LOAD_END(_XintffuncsLoadEnd),
|
||||
RUN_START(_XintffuncsRunStart),
|
||||
PAGE = 0
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,111 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
SHARERAMGS2 : > RAMGS2, PAGE = 1
|
||||
SHARERAMGS3 : > RAMGS3, PAGE = 1
|
||||
SHARERAMGS4 : > RAMGS4, PAGE = 1
|
||||
SHARERAMGS5 : > RAMGS5, PAGE = 1
|
||||
SHARERAMGS6 : > RAMGS6, PAGE = 1
|
||||
SHARERAMGS7 : > RAMGS7, PAGE = 1
|
||||
SHARERAMGS8 : > RAMGS8, PAGE = 1
|
||||
SHARERAMGS9 : > RAMGS9, PAGE = 1
|
||||
SHARERAMGS10 : > RAMGS10, PAGE = 1
|
||||
SHARERAMGS11 : > RAMGS11, PAGE = 1
|
||||
SHARERAMGS12 : > RAMGS12, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
SHARERAMGS13 : > RAMGS13, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
SHARERAMGS14 : > RAMGS14, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
SHARERAMGS15 : > RAMGS15, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,110 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x0000A2, length = 0x00035E
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0 : origin = 0x008000, length = 0x000800
|
||||
RAMLS1 : origin = 0x008800, length = 0x000800
|
||||
RAMLS2 : origin = 0x009000, length = 0x000800
|
||||
RAMLS3 : origin = 0x009800, length = 0x000800
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */
|
||||
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS3, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
SHARERAMGS0 : > RAMGS0, PAGE = 1
|
||||
SHARERAMGS1 : > RAMGS1, PAGE = 1
|
||||
SHARERAMGS2 : > RAMGS2, PAGE = 1
|
||||
SHARERAMGS3 : > RAMGS3, PAGE = 1
|
||||
SHARERAMGS4 : > RAMGS4, PAGE = 1
|
||||
SHARERAMGS5 : > RAMGS5, PAGE = 1
|
||||
SHARERAMGS6 : > RAMGS6, PAGE = 1
|
||||
SHARERAMGS7 : > RAMGS7, PAGE = 1
|
||||
SHARERAMGS8 : > RAMGS8, PAGE = 1
|
||||
SHARERAMGS9 : > RAMGS9, PAGE = 1
|
||||
SHARERAMGS10 : > RAMGS10, PAGE = 1
|
||||
SHARERAMGS11 : > RAMGS11, PAGE = 1
|
||||
SHARERAMGS12 : > RAMGS12, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
SHARERAMGS13 : > RAMGS13, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
SHARERAMGS14 : > RAMGS14, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
SHARERAMGS15 : > RAMGS15, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,120 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0_3 : origin = 0x008000, length = 0x002000
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
|
||||
/* Uncomment for F28374D, F28376D devices */
|
||||
/* RAMGS11 : origin = 0x017000, length = 0x000FF8
|
||||
RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 */ /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
|
||||
|
||||
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
|
||||
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : > RAMLS0_3, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS4, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are required when using the IPC API Drivers */
|
||||
GROUP : > CPU1TOCPU2RAM, PAGE = 1
|
||||
{
|
||||
PUTBUFFER
|
||||
PUTWRITEIDX
|
||||
GETREADIDX
|
||||
}
|
||||
|
||||
GROUP : > CPU2TOCPU1RAM, PAGE = 1
|
||||
{
|
||||
GETBUFFER : TYPE = DSECT
|
||||
GETWRITEIDX : TYPE = DSECT
|
||||
PUTREADIDX : TYPE = DSECT
|
||||
}
|
||||
|
||||
/* The following section definition are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,68 +0,0 @@
|
||||
|
||||
/* this linker command file is to be included if user wants to use the DCSM feature on the device
|
||||
* DCSM means Dual Zone Code Security Module.
|
||||
* This linker command file works as an addendum ot the already existing Flash/RAM linker command file
|
||||
* that the project has.
|
||||
* The sections in the *_ZoneSelectBlock.asm source file is linked as per the commands given in the file
|
||||
* NOTE - please note fill=0xFFFF, this helps if users include this file in the project by mistake and
|
||||
* doesn't provide the needed proper *_ZoneSelectBlock.asm sources .
|
||||
* Please refer to the Blinky DCSM example in the controlsuite examples for proper usage of this.
|
||||
*
|
||||
* Once users are confident that they want to program the passwords in OTP, the DSECT section type can be removed.
|
||||
*
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
|
||||
/* Z1 OTP. LinkPointers */
|
||||
DCSM_OTP_Z1_LINKPOINTER : origin = 0x78000, length = 0x00000C
|
||||
/* Z1 OTP. PSWDLOCK/RESERVED */
|
||||
DCSM_OTP_Z1_PSWDLOCK : origin = 0x78010, length = 0x000004
|
||||
/* Z1 OTP. CRCLOCK/RESERVED */
|
||||
DCSM_OTP_Z1_CRCLOCK : origin = 0x78014, length = 0x000004
|
||||
/* Z1 OTP. RESERVED/BOOTCTRL */
|
||||
DCSM_OTP_Z1_BOOTCTRL : origin = 0x7801C, length = 0x000004
|
||||
|
||||
/* DCSM Z1 Zone Select Contents (!!Movable!!) */
|
||||
/* Z1 OTP. Z1 password locations / Flash and RAM partitioning */
|
||||
DCSM_ZSEL_Z1_P0 : origin = 0x78020, length = 0x000010
|
||||
|
||||
/* Z2 OTP. LinkPointers */
|
||||
DCSM_OTP_Z2_LINKPOINTER : origin = 0x78200, length = 0x00000C
|
||||
/* Z2 OTP. GPREG1/GPREG2 */
|
||||
DCSM_OTP_Z2_GPREG : origin = 0x7820C, length = 0x000004
|
||||
/* Z2 OTP. PSWDLOCK/RESERVED */
|
||||
DCSM_OTP_Z2_PSWDLOCK : origin = 0x78210, length = 0x000004
|
||||
/* Z2 OTP. CRCLOCK/RESERVED */
|
||||
DCSM_OTP_Z2_CRCLOCK : origin = 0x78214, length = 0x000004
|
||||
/* Z2 OTP. GPREG3/BOOTCTRL */
|
||||
DCSM_OTP_Z2_BOOTCTRL : origin = 0x7821C, length = 0x000004
|
||||
|
||||
/* DCSM Z1 Zone Select Contents (!!Movable!!) */
|
||||
/* Z2 OTP. Z2 password locations / Flash and RAM partitioning */
|
||||
DCSM_ZSEL_Z2_P0 : origin = 0x78220, length = 0x000010
|
||||
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
dcsm_otp_z1_linkpointer : > DCSM_OTP_Z1_LINKPOINTER PAGE = 0, type = DSECT
|
||||
dcsm_otp_z1_pswdlock : > DCSM_OTP_Z1_PSWDLOCK PAGE = 0, type = DSECT
|
||||
dcsm_otp_z1_crclock : > DCSM_OTP_Z1_CRCLOCK PAGE = 0, type = DSECT
|
||||
dcsm_otp_z1_bootctrl : > DCSM_OTP_Z1_BOOTCTRL PAGE = 0, type = DSECT
|
||||
dcsm_zsel_z1 : > DCSM_ZSEL_Z1_P0 PAGE = 0, type = DSECT
|
||||
|
||||
dcsm_otp_z2_linkpointer : > DCSM_OTP_Z2_LINKPOINTER PAGE = 0, type = DSECT
|
||||
dcsm_otp_z2_pswdlock : > DCSM_OTP_Z2_PSWDLOCK PAGE = 0, type = DSECT
|
||||
dcsm_otp_z2_crclock : > DCSM_OTP_Z2_CRCLOCK PAGE = 0, type = DSECT
|
||||
dcsm_otp_z2_bootctrl : > DCSM_OTP_Z2_BOOTCTRL PAGE = 0, type = DSECT
|
||||
dcsm_zsel_z2 : > DCSM_ZSEL_Z2_P0 PAGE = 0, type = DSECT
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,44 +0,0 @@
|
||||
|
||||
/* this linker command file is to be included if user wants to use the DCSM feature on the device
|
||||
* DCSM means Dual Zone Code Security Module.
|
||||
* This linker command file works as an addendum ot the already existing Flash/RAM linker command file
|
||||
* that the project has.
|
||||
* The sections in the *_ZoneSelectBlock.asm source file is linked as per the commands given in the file
|
||||
* NOTEG - please note fill=0xFFFF, this helps if users include this file in the project by mistake and
|
||||
* doesn't provide the needed *_ZoneSelectBlock.asm sources.
|
||||
* Please refer to the Blinky DCSM example in the controlsuite examples for proper usage of this.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 : /* Program Memory */
|
||||
|
||||
/* Part of Z1 OTP. LinkPointers/PSWD LOCK/CRC LOCK/JTAG lock/ Boot Ctrl */
|
||||
DCSM_OTP_Z1_P0 : origin = 0x78000, length = 0x000020
|
||||
/* Part of Z2 OTP. LinkPointers/PSWD LOCK/CRC LOCK/JTAG lock/ Boot Ctrl */
|
||||
DCSM_OTP_Z2_P0 : origin = 0x78200, length = 0x000020
|
||||
|
||||
/* DCSM Z1 Zone Select Contents (!!Movable!!) */
|
||||
/* Part of Z1 OTP. Z1 password locations / Flash and RAM partitioning */
|
||||
DCSM_ZSEL_Z1_P0 : origin = 0x78020, length = 0x000010
|
||||
|
||||
/* DCSM Z1 Zone Select Contents (!!Movable!!) */
|
||||
/* Part of Z2 OTP. Z2 password locations / Flash and RAM partitioning */
|
||||
DCSM_ZSEL_Z2_P0 : origin = 0x78220, length = 0x000010
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
dcsm_otp_z1 : > DCSM_OTP_Z1_P0, PAGE = 0, type = DSECT
|
||||
dcsm_otp_z2 : > DCSM_OTP_Z2_P0, PAGE = 0, type = DSECT
|
||||
|
||||
dcsm_zsel_z1 : > DCSM_ZSEL_Z1_P0, PAGE = 0, type = DSECT
|
||||
dcsm_zsel_z2 : > DCSM_ZSEL_Z2_P0, PAGE = 0, type = DSECT
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,91 +0,0 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002
|
||||
RAMM0 : origin = 0x000123, length = 0x0002DD
|
||||
RAMD0 : origin = 0x00B000, length = 0x000800
|
||||
RAMLS0_3 : origin = 0x008000, length = 0x002000
|
||||
RAMLS4 : origin = 0x00A000, length = 0x000800
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
|
||||
PAGE 1 :
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
|
||||
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
RAMD1 : origin = 0x00B800, length = 0x000800
|
||||
|
||||
RAMLS5 : origin = 0x00A800, length = 0x000800
|
||||
|
||||
RAMGS0 : origin = 0x00C000, length = 0x001000
|
||||
RAMGS1 : origin = 0x00D000, length = 0x001000
|
||||
RAMGS2 : origin = 0x00E000, length = 0x001000
|
||||
RAMGS3 : origin = 0x00F000, length = 0x001000
|
||||
RAMGS4 : origin = 0x010000, length = 0x001000
|
||||
RAMGS5 : origin = 0x011000, length = 0x001000
|
||||
RAMGS6 : origin = 0x012000, length = 0x001000
|
||||
RAMGS7 : origin = 0x013000, length = 0x001000
|
||||
RAMGS8 : origin = 0x014000, length = 0x001000
|
||||
RAMGS9 : origin = 0x015000, length = 0x001000
|
||||
RAMGS10 : origin = 0x016000, length = 0x001000
|
||||
RAMGS11 : origin = 0x017000, length = 0x000FF8
|
||||
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
|
||||
|
||||
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
|
||||
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
.text : > RAMLS0_3, PAGE = 0
|
||||
.cinit : > RAMM0, PAGE = 0
|
||||
.switch : > RAMM0, PAGE = 0
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
|
||||
#if defined(__TI_EABI__)
|
||||
.bss : > RAMLS5, PAGE = 1
|
||||
.bss:output : > RAMLS4, PAGE = 0
|
||||
.init_array : > RAMM0, PAGE = 0
|
||||
.const : > RAMLS5, PAGE = 1
|
||||
.data : > RAMLS5, PAGE = 1
|
||||
.sysmem : > RAMLS5, PAGE = 1
|
||||
#else
|
||||
.pinit : > RAMM0, PAGE = 0
|
||||
.ebss : > RAMLS5, PAGE = 1
|
||||
.econst : > RAMLS5, PAGE = 1
|
||||
.esysmem : > RAMLS5, PAGE = 1
|
||||
#endif
|
||||
|
||||
Filter_RegsFile : > RAMGS0, PAGE = 1
|
||||
|
||||
|
||||
ramgs0 : > RAMGS0, PAGE = 1
|
||||
ramgs1 : > RAMGS1, PAGE = 1
|
||||
|
||||
#ifdef __TI_COMPILER_VERSION__
|
||||
#if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.TI.ramfunc : {} > RAMM0, PAGE = 0
|
||||
#else
|
||||
ramfuncs : > RAMM0 PAGE = 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The following section definitions are for SDFM examples */
|
||||
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
|
||||
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
|
||||
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
|
||||
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
|
||||
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@@ -1,104 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Adc_defines.h
|
||||
//
|
||||
// TITLE: #defines used in ADC examples
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_ADC_DEFINES_H
|
||||
#define F2837xD_ADC_DEFINES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define ADC_CHANNEL_0 0
|
||||
#define ADC_CHANNEL_1 1
|
||||
#define ADC_CHANNEL_2 2
|
||||
#define ADC_CHANNEL_3 3
|
||||
#define ADC_CHANNEL_4 4
|
||||
#define ADC_CHANNEL_5 5
|
||||
#define ADC_CHANNEL_6 6
|
||||
#define ADC_CHANNEL_7 7
|
||||
|
||||
#define ADC_CHANNEL_8 8
|
||||
#define ADC_CHANNEL_9 9
|
||||
#define ADC_CHANNEL_10 10
|
||||
#define ADC_CHANNEL_11 11
|
||||
#define ADC_CHANNEL_12 12
|
||||
#define ADC_CHANNEL_13 13
|
||||
#define ADC_CHANNEL_14 14
|
||||
#define ADC_CHANNEL_15 15
|
||||
|
||||
//
|
||||
//definitions for specifying an ADC
|
||||
//
|
||||
#define ADC_ADCA 0
|
||||
#define ADC_ADCB 1
|
||||
#define ADC_ADCC 2
|
||||
#define ADC_ADCD 3
|
||||
|
||||
//
|
||||
//definitions for selecting ADC resolution
|
||||
//
|
||||
#ifndef _DUAL_HEADERS
|
||||
#define ADC_RESOLUTION_12BIT 0
|
||||
#define ADC_RESOLUTION_16BIT 1
|
||||
#else
|
||||
#define ADC_BITRESOLUTION_12BIT 0
|
||||
#define ADC_BITRESOLUTION_16BIT 1
|
||||
#endif
|
||||
//
|
||||
//definitions for selecting ADC signal mode
|
||||
//(single-ended mode is only a valid mode for 12-bit resolution)
|
||||
//
|
||||
#define ADC_SIGNALMODE_SINGLE 0
|
||||
#define ADC_SIGNALMODE_DIFFERENTIAL 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of F2837xD_ADC_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,133 +0,0 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: F2837xD_Can_defines.h
|
||||
//
|
||||
// TITLE: Common defines used in CAN Test Cases
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
#ifndef F2837xD_CAN_DEFINES_H
|
||||
#define F2837xD_CAN_DEFINES_H
|
||||
|
||||
#ifndef _DUAL_HEADERS
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// Reset Values
|
||||
//
|
||||
#define CAN_RESET_VALUE_ZERO 0x00000000
|
||||
#define CAN_CTL_RESET_VALUE 0x00001401
|
||||
#define CAN_ES_RESET_VALUE 0x00000007
|
||||
#define CAN_BTR_RESET_VALUE 0x00002301
|
||||
#define CAN_REL_RESET_VALUE 0xA3170504
|
||||
#define CAN_RAM_INIT_RESET_VALUE 0x00000005
|
||||
#define CAN_IF_CMD_RESET_VALUE 0x00000001
|
||||
#define CAN_IF_MASK_RESET_VALUE 0xFFFFFFFF
|
||||
|
||||
//
|
||||
// Register value when Peripheral Clock is Disabled
|
||||
//
|
||||
#define CAN_MODULE_CLK_DISABLE_VALUE 0x00000000
|
||||
|
||||
//
|
||||
// Bit field definition of CAN_CTL register.
|
||||
//
|
||||
#define CAN_CTL_INIT 0x00000001 // Initialization
|
||||
#define CAN_CTL_IE0 0x00000002 // Interrupt Enable 0
|
||||
#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
|
||||
#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
|
||||
#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
|
||||
#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
|
||||
#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
|
||||
#define CAN_CTL_IDS 0x00000100 // Interruption Debug Support Enable
|
||||
#define CAN_CTL_ABO 0x00000200 // Auto-Bus On Enable
|
||||
#define CAN_CTL_PMD_S 10
|
||||
#define CAN_CTL_PMD_M 0x00003C00 // Parity/SECDED Enable
|
||||
#define CAN_CTL_SWR 0x00008000 // Software Reset Enable
|
||||
#define CAN_CTL_INITDBG 0x00010000 // Debug Mode Status
|
||||
#define CAN_CTL_IE1 0x00020000 // Interrupt Enable 1
|
||||
#define CAN_CTL_PDR 0x01000000 // Power Down Mode Request
|
||||
#define CAN_CTL_WUBA 0x02000000 // Wake Up on Bus Activity
|
||||
|
||||
//
|
||||
// Bit field definition of CAN_IF1_CMD register.
|
||||
//
|
||||
#define CAN_IF1_CMD_MESSNUM_S 0
|
||||
#define CAN_IF1_CMD_MESSNUM_M 0x000000FF // Message Number
|
||||
#define CAN_IF1_CMD_BUSY 0x00008000 // Busy Flag
|
||||
#define CAN_IF1_CMD_DATAB 0x00010000 // Access Data B
|
||||
#define CAN_IF1_CMD_DATAA 0x00020000 // Access Data A
|
||||
#define CAN_IF1_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit
|
||||
#define CAN_IF1_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit
|
||||
#define CAN_IF1_CMD_CONTROL 0x00100000 // Access Control Bits
|
||||
#define CAN_IF1_CMD_ARB 0x00200000 // Access Arbitration Bits
|
||||
#define CAN_IF1_CMD_MASK 0x00400000 // Access Mask Bits
|
||||
#define CAN_IF1_CMD_WR_RD 0x00800000 // Write and Read
|
||||
|
||||
//
|
||||
// Bit field definition of CAN_IF2_CMD register.
|
||||
//
|
||||
#define CAN_IF2_CMD_MESSNUM_S 0
|
||||
#define CAN_IF2_CMD_MESSNUM_M 0x000000FF // Message Number
|
||||
#define CAN_IF2_CMD_BUSY 0x00008000 // Busy Flag
|
||||
#define CAN_IF2_CMD_DATAB 0x00010000 // Access Data B
|
||||
#define CAN_IF2_CMD_DATAA 0x00020000 // Access Data A
|
||||
#define CAN_IF2_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit
|
||||
#define CAN_IF2_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit
|
||||
#define CAN_IF2_CMD_CONTROL 0x00100000 // Access Control Bits
|
||||
#define CAN_IF2_CMD_ARB 0x00200000 // Access Arbitration Bits
|
||||
#define CAN_IF2_CMD_MASK 0x00400000 // Access Mask Bits
|
||||
#define CAN_IF2_CMD_WR_RD 0x00800000 // Write and Read
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of _DUAL_HEADERS
|
||||
|
||||
#endif // - end of F2837xD_CAN_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,206 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Cla_defines.h
|
||||
//
|
||||
// TITLE: #defines used in CLA examples
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_CLA_DEFINES_H
|
||||
#define F2837xD_CLA_DEFINES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// MCTL Register
|
||||
//
|
||||
#define CLA_FORCE_RESET 0x1
|
||||
#define CLA_IACK_ENABLE 0x1
|
||||
#define CLA_IACK_DISABLE 0x0
|
||||
|
||||
//
|
||||
// MMEMCFG Register
|
||||
//
|
||||
#define CLA_CLA_SPACE 0x1
|
||||
#define CLA_CPU_SPACE 0x0
|
||||
|
||||
//
|
||||
// MIER Interrupt Enable Register
|
||||
//
|
||||
#define CLA_INT_ENABLE 0x1
|
||||
#define CLA_INT_DISABLE 0x0
|
||||
|
||||
//
|
||||
// Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register
|
||||
//
|
||||
#define CLA_TRIG_NOPERPH 0
|
||||
#define CLA_TRIG_ADCAINT1 1
|
||||
#define CLA_TRIG_ADCAINT2 2
|
||||
#define CLA_TRIG_ADCAINT3 3
|
||||
#define CLA_TRIG_ADCAINT4 4
|
||||
#define CLA_TRIG_ADCAEVT 5
|
||||
#define CLA_TRIG_ADCBINT1 6
|
||||
#define CLA_TRIG_ADCBINT2 7
|
||||
#define CLA_TRIG_ADCBINT3 8
|
||||
#define CLA_TRIG_ADCBINT4 9
|
||||
#define CLA_TRIG_ADCBEVT 10
|
||||
#define CLA_TRIG_ADCCINT1 11
|
||||
#define CLA_TRIG_ADCCINT2 12
|
||||
#define CLA_TRIG_ADCCINT3 13
|
||||
#define CLA_TRIG_ADCCINT4 14
|
||||
#define CLA_TRIG_ADCCEVT 15
|
||||
#define CLA_TRIG_ADCDINT1 16
|
||||
#define CLA_TRIG_ADCDINT2 17
|
||||
#define CLA_TRIG_ADCDINT3 18
|
||||
#define CLA_TRIG_ADCDINT4 19
|
||||
#define CLA_TRIG_ADCDEVT 20
|
||||
|
||||
#define CLA_TRIG_XINT1 29
|
||||
#define CLA_TRIG_XINT2 30
|
||||
#define CLA_TRIG_XINT3 31
|
||||
#define CLA_TRIG_XINT4 32
|
||||
#define CLA_TRIG_XINT5 33
|
||||
|
||||
#define CLA_TRIG_EPWM1INT 36
|
||||
#define CLA_TRIG_EPWM2INT 37
|
||||
#define CLA_TRIG_EPWM3INT 38
|
||||
#define CLA_TRIG_EPWM4INT 39
|
||||
#define CLA_TRIG_EPWM5INT 40
|
||||
#define CLA_TRIG_EPWM6INT 41
|
||||
#define CLA_TRIG_EPWM7INT 42
|
||||
#define CLA_TRIG_EPWM8INT 43
|
||||
#define CLA_TRIG_EPWM9INT 44
|
||||
#define CLA_TRIG_EPWM10INT 45
|
||||
#define CLA_TRIG_EPWM11INT 46
|
||||
#define CLA_TRIG_EPWM12INT 47
|
||||
|
||||
#define CLA_TRIG_TINT0 68
|
||||
#define CLA_TRIG_TINT1 69
|
||||
#define CLA_TRIG_TINT2 70
|
||||
|
||||
#define CLA_TRIG_MXEVTA 71
|
||||
#define CLA_TRIG_MREVTA 72
|
||||
#define CLA_TRIG_MXEVTB 73
|
||||
#define CLA_TRIG_MREVTB 74
|
||||
|
||||
#define CLA_TRIG_ECAP1INT 75
|
||||
#define CLA_TRIG_ECAP2INT 76
|
||||
#define CLA_TRIG_ECAP3INT 77
|
||||
#define CLA_TRIG_ECAP4INT 78
|
||||
#define CLA_TRIG_ECAP5INT 79
|
||||
#define CLA_TRIG_ECAP6INT 80
|
||||
|
||||
#define CLA_TRIG_EQEP1INT 83
|
||||
#define CLA_TRIG_EQEP2INT 84
|
||||
#define CLA_TRIG_EQEP3INT 85
|
||||
|
||||
#define CLA_TRIG_HRCAP1INT 87
|
||||
#define CLA_TRIG_HRCAP2INT 88
|
||||
|
||||
#define CLA_TRIG_SD1INT 95
|
||||
#define CLA_TRIG_SD2INT 96
|
||||
|
||||
#define CLA_TRIG_UPP1_INT 107
|
||||
|
||||
#define CLA_TRIG_SPITXINTA 109
|
||||
#define CLA_TRIG_SPIRXINTA 110
|
||||
#define CLA_TRIG_SPITXINTB 111
|
||||
#define CLA_TRIG_SPIRXINTB 112
|
||||
#define CLA_TRIG_SPITXINTC 113
|
||||
#define CLA_TRIG_SPIRXINTC 114
|
||||
|
||||
#define CLA_TRIG_CLB1INT 127
|
||||
#define CLA_TRIG_CLB2INT 128
|
||||
#define CLA_TRIG_CLB3INT 129
|
||||
#define CLA_TRIG_CLB4INT 130
|
||||
|
||||
#define Cla1ForceTask1andWait()asm(" IACK #0x0001"); \
|
||||
asm(" RPT #3 || NOP"); \
|
||||
while(Cla1Regs.MIRUN.bit.INT1 == 1);
|
||||
|
||||
#define Cla1ForceTask2andWait()asm(" IACK #0x0002"); \
|
||||
asm(" RPT #3 || NOP"); \
|
||||
while(Cla1Regs.MIRUN.bit.INT2 == 1);
|
||||
|
||||
#define Cla1ForceTask3andWait()asm(" IACK #0x0004"); \
|
||||
asm(" RPT #3 || NOP"); \
|
||||
while(Cla1Regs.MIRUN.bit.INT3 == 1);
|
||||
|
||||
#define Cla1ForceTask4andWait()asm(" IACK #0x0008"); \
|
||||
asm(" RPT #3 || NOP"); \
|
||||
while(Cla1Regs.MIRUN.bit.INT4 == 1);
|
||||
|
||||
#define Cla1ForceTask5andWait()asm(" IACK #0x0010"); \
|
||||
asm(" RPT #3 || NOP"); \
|
||||
while(Cla1Regs.MIRUN.bit.INT5 == 1);
|
||||
|
||||
#define Cla1ForceTask6andWait()asm(" IACK #0x0020"); \
|
||||
asm(" RPT #3 || NOP"); \
|
||||
while(Cla1Regs.MIRUN.bit.INT6 == 1);
|
||||
|
||||
#define Cla1ForceTask7andWait()asm(" IACK #0x0040"); \
|
||||
asm(" RPT #3 || NOP"); \
|
||||
while(Cla1Regs.MIRUN.bit.INT7 == 1);
|
||||
|
||||
#define Cla1ForceTask8andWait()asm(" IACK #0x0080"); \
|
||||
asm(" RPT #3 || NOP"); \
|
||||
while(Cla1Regs.MIRUN.bit.INT8 == 1);
|
||||
|
||||
#define Cla1ForceTask1() asm(" IACK #0x0001")
|
||||
#define Cla1ForceTask2() asm(" IACK #0x0002")
|
||||
#define Cla1ForceTask3() asm(" IACK #0x0004")
|
||||
#define Cla1ForceTask4() asm(" IACK #0x0008")
|
||||
#define Cla1ForceTask5() asm(" IACK #0x0010")
|
||||
#define Cla1ForceTask6() asm(" IACK #0x0020")
|
||||
#define Cla1ForceTask7() asm(" IACK #0x0040")
|
||||
#define Cla1ForceTask8() asm(" IACK #0x0080")
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // - end of F2837xD_CLA_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,128 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Cla_typedefs.h
|
||||
//
|
||||
// TITLE: Variable type definitions
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_CLA_TYPEDEFS_H_
|
||||
#define F2837xD_CLA_TYPEDEFS_H_
|
||||
|
||||
//
|
||||
// Macros to manipulate pre-processor to generate a header file name
|
||||
// at compile time that is based on the test name and can be used as
|
||||
// an argument to #include
|
||||
//
|
||||
#define XSTRINGIZE(s) STRINGIZE(s)
|
||||
#define STRINGIZE(s) #s
|
||||
#define XCONCAT(x,y) CONCAT(x,y)
|
||||
#define CONCAT(x,y) x##y
|
||||
|
||||
//
|
||||
// Suppress warnings casting CLA pointers
|
||||
//
|
||||
#pragma diag_suppress 70,770,232
|
||||
|
||||
#ifdef __TMS320C28XX_CLA__
|
||||
//
|
||||
// For Portability, User Is Recommended To Use Following Data Type Size
|
||||
// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
|
||||
//
|
||||
// CLA does not support 64-bit types
|
||||
// This definition is only to allow inclusion of the standard header files
|
||||
// which do use 64-bit types
|
||||
//
|
||||
|
||||
#if (!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES))
|
||||
#define F28_DATA_TYPES
|
||||
#define DSP28_DATA_TYPES
|
||||
typedef short int16;
|
||||
typedef long int32;
|
||||
typedef unsigned char Uint8;
|
||||
typedef unsigned short Uint16;
|
||||
typedef unsigned long Uint32;
|
||||
typedef float float32;
|
||||
typedef long double float64;
|
||||
typedef struct { Uint32 low32; Uint32 high32; } Uint64;
|
||||
typedef struct { int32 low32; int32 high32; } int64;
|
||||
#else
|
||||
#error F2837xD_Cla_Typedefs.h must be included before F2837xD_Device.h or any other header \
|
||||
file that redefines data types using the guard macros F28_DATA_TYPES or DSP28_DATA_TYPES
|
||||
#endif //(!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES))
|
||||
|
||||
#ifndef _TI_STD_TYPES
|
||||
#define _TI_STD_TYPES
|
||||
//
|
||||
//These types are also defined in DSP/BIOS 5.x's <std.h> and the
|
||||
//SYS/BIOS 6.x's <xdc/std.h> files. We need to protect their
|
||||
//definition with the #ifndef/#define guard to avoid the duplicate
|
||||
//definition warning.
|
||||
//
|
||||
//SYS/BIOS requires that the <xdc/std.h> file be included before
|
||||
//any other .h files.
|
||||
//
|
||||
#endif
|
||||
|
||||
struct MSTF_SHADOW_BITS { // bits description
|
||||
Uint16 LVF:1; // 0 Latched Overflow Flag
|
||||
Uint16 LUF:1; // 1 Latched Underflow Flag
|
||||
Uint16 NF:1; // 2 Negative Float Flag
|
||||
Uint16 ZF:1; // 3 Zero Float Flag
|
||||
Uint16 rsvd1:2; // 5:4 Reserved
|
||||
Uint16 TF:1; // 6 Test Flag
|
||||
Uint16 rsvd2:2; // 8:7 Reserved
|
||||
Uint16 RNDF32:1; // 9 Rounding Mode
|
||||
Uint16 rsvd3:1; // 10 Reserved
|
||||
Uint16 MEALLOW:1; // 11 MEALLOW Status
|
||||
Uint16 RPCL:4; // 15:12 Return PC: Low Portion
|
||||
Uint16 RPCH:8; // 23:16 Return PC: High Portion
|
||||
Uint16 rsvd4:8; // 31:24 Reserved
|
||||
};
|
||||
extern __cregister volatile unsigned int MSTF;
|
||||
|
||||
#endif //__TMS320C28XX_CLA__
|
||||
|
||||
#ifndef __TMS320C28XX__
|
||||
#define __cregister
|
||||
#endif //__TMS320C28xx__
|
||||
|
||||
#endif //F2837xD_CLA_TYPEDEFS_H_
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,217 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Dma_defines.h
|
||||
//
|
||||
// TITLE: #defines used in DMA examples
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_DMA_DEFINES_H
|
||||
#define F2837xD_DMA_DEFINES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// PERINTSEL bits
|
||||
//
|
||||
#define DMA_ADCAINT1 1
|
||||
#define DMA_ADCAINT2 2
|
||||
#define DMA_ADCAINT3 3
|
||||
#define DMA_ADCAINT4 4
|
||||
#define DMA_ADCAEVT 5
|
||||
#define DMA_ADCBINT1 6
|
||||
#define DMA_ADCBINT2 7
|
||||
#define DMA_ADCBINT3 8
|
||||
#define DMA_ADCBINT4 9
|
||||
#define DMA_ADCBEVT 10
|
||||
#define DMA_ADCCINT1 11
|
||||
#define DMA_ADCCINT2 12
|
||||
#define DMA_ADCCINT3 13
|
||||
#define DMA_ADCCINT4 14
|
||||
#define DMA_ADCCEVT 15
|
||||
#define DMA_ADCDINT1 16
|
||||
#define DMA_ADCDINT2 17
|
||||
#define DMA_ADCDINT3 18
|
||||
#define DMA_ADCDINT4 19
|
||||
#define DMA_ADCDEVT 20
|
||||
|
||||
#define DMA_XINT1 29
|
||||
#define DMA_XINT2 30
|
||||
#define DMA_XINT3 31
|
||||
#define DMA_XINT4 32
|
||||
#define DMA_XINT5 33
|
||||
|
||||
#define DMA_EPWM1A 36
|
||||
#define DMA_EPWM1B 37
|
||||
#define DMA_EPWM2A 38
|
||||
#define DMA_EPWM2B 39
|
||||
#define DMA_EPWM3A 40
|
||||
#define DMA_EPWM3B 41
|
||||
#define DMA_EPWM4A 42
|
||||
#define DMA_EPWM4B 43
|
||||
#define DMA_EPWM5A 44
|
||||
#define DMA_EPWM5B 45
|
||||
#define DMA_EPWM6A 46
|
||||
#define DMA_EPWM6B 47
|
||||
#define DMA_EPWM7A 48
|
||||
#define DMA_EPWM7B 49
|
||||
#define DMA_EPWM8A 50
|
||||
#define DMA_EPWM8B 51
|
||||
#define DMA_EPWM9A 52
|
||||
#define DMA_EPWM9B 53
|
||||
#define DMA_EPWM10A 54
|
||||
#define DMA_EPWM10B 55
|
||||
#define DMA_EPWM11A 56
|
||||
#define DMA_EPWM11B 57
|
||||
#define DMA_EPWM12A 58
|
||||
#define DMA_EPWM12B 59
|
||||
#define DMA_EPWM13A 60
|
||||
#define DMA_EPWM13B 61
|
||||
#define DMA_EPWM14A 62
|
||||
#define DMA_EPWM14B 63
|
||||
#define DMA_EPWM15A 64
|
||||
#define DMA_EPWM15B 65
|
||||
#define DMA_EPWM16A 66
|
||||
#define DMA_EPWM16B 67
|
||||
|
||||
#define DMA_TINT0 68
|
||||
#define DMA_TINT1 69
|
||||
#define DMA_TINT2 70
|
||||
|
||||
#define DMA_MXEVTA 71
|
||||
#define DMA_MREVTA 72
|
||||
#define DMA_MXEVTB 73
|
||||
#define DMA_MREVTB 74
|
||||
|
||||
#define DMA_SD1FLT1 95
|
||||
#define DMA_SD1FLT2 96
|
||||
#define DMA_SD1FLT3 97
|
||||
#define DMA_SD1FLT4 98
|
||||
|
||||
#define DMA_SD2FLT1 99
|
||||
#define DMA_SD2FLT2 100
|
||||
#define DMA_SD2FLT3 101
|
||||
#define DMA_SD2FLT4 102
|
||||
|
||||
#define DMA_SPIATX 109
|
||||
#define DMA_SPIARX 110
|
||||
#define DMA_SPIBTX 111
|
||||
#define DMA_SPIBRX 112
|
||||
#define DMA_SPICTX 113
|
||||
#define DMA_SPICRX 114
|
||||
|
||||
#define DMA_CLB1INT 127
|
||||
#define DMA_CLB2INT 128
|
||||
#define DMA_CLB3INT 129
|
||||
#define DMA_CLB4INT 130
|
||||
|
||||
#define DMA_USBRX1 131
|
||||
#define DMA_USBTX1 132
|
||||
#define DMA_USBRX2 133
|
||||
#define DMA_USBTX2 134
|
||||
#define DMA_USBRX3 135
|
||||
#define DMA_USBTX3 136
|
||||
|
||||
//
|
||||
// OVERINTE bit
|
||||
//
|
||||
#define OVRFLOW_DISABLE 0x0
|
||||
#define OVEFLOW_ENABLE 0x1
|
||||
|
||||
//
|
||||
// PERINTE bit
|
||||
//
|
||||
#define PERINT_DISABLE 0x0
|
||||
#define PERINT_ENABLE 0x1
|
||||
|
||||
//
|
||||
// CHINTMODE bits
|
||||
//
|
||||
#define CHINT_BEGIN 0x0
|
||||
#define CHINT_END 0x1
|
||||
|
||||
//
|
||||
// ONESHOT bits
|
||||
//
|
||||
#define ONESHOT_DISABLE 0x0
|
||||
#define ONESHOT_ENABLE 0x1
|
||||
|
||||
//
|
||||
// CONTINOUS bit
|
||||
//
|
||||
#define CONT_DISABLE 0x0
|
||||
#define CONT_ENABLE 0x1
|
||||
|
||||
//
|
||||
// SYNCE bit
|
||||
//
|
||||
#define SYNC_DISABLE 0x0
|
||||
#define SYNC_ENABLE 0x1
|
||||
|
||||
//
|
||||
// SYNCSEL bit
|
||||
//
|
||||
#define SYNC_SRC 0x0
|
||||
#define SYNC_DST 0x1
|
||||
|
||||
//
|
||||
// DATASIZE bit
|
||||
//
|
||||
#define SIXTEEN_BIT 0x0
|
||||
#define THIRTYTWO_BIT 0x1
|
||||
|
||||
//
|
||||
// CHINTE bit
|
||||
//
|
||||
#define CHINT_DISABLE 0x0
|
||||
#define CHINT_ENABLE 0x1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // - end of F2837xD_DMA_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,342 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_EPwm_defines.h
|
||||
//
|
||||
// TITLE: #defines used in EPwm examples
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_EPWM_DEFINES_H
|
||||
#define F2837xD_EPWM_DEFINES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// TBCTL (Time-Base Control)
|
||||
//
|
||||
|
||||
//
|
||||
// CTRMODE bits
|
||||
//
|
||||
#define TB_COUNT_UP 0x0
|
||||
#define TB_COUNT_DOWN 0x1
|
||||
#define TB_COUNT_UPDOWN 0x2
|
||||
#define TB_FREEZE 0x3
|
||||
|
||||
//
|
||||
// PHSEN bit
|
||||
//
|
||||
#define TB_DISABLE 0x0
|
||||
#define TB_ENABLE 0x1
|
||||
|
||||
//
|
||||
// PRDLD bit
|
||||
//
|
||||
#define TB_SHADOW 0x0
|
||||
#define TB_IMMEDIATE 0x1
|
||||
|
||||
//
|
||||
// SYNCOSEL bits
|
||||
//
|
||||
#define TB_SYNC_IN 0x0
|
||||
#define TB_CTR_ZERO 0x1
|
||||
#define TB_CTR_CMPB 0x2
|
||||
#define TB_SYNC_DISABLE 0x3
|
||||
|
||||
//
|
||||
// HSPCLKDIV and CLKDIV bits
|
||||
//
|
||||
#define TB_DIV1 0x0
|
||||
#define TB_DIV2 0x1
|
||||
#define TB_DIV4 0x2
|
||||
|
||||
//
|
||||
// PHSDIR bit
|
||||
//
|
||||
#define TB_DOWN 0x0
|
||||
#define TB_UP 0x1
|
||||
|
||||
//
|
||||
// CMPCTL (Compare Control)
|
||||
//
|
||||
|
||||
//
|
||||
// LOADAMODE and LOADBMODE bits
|
||||
//
|
||||
#define CC_CTR_ZERO 0x0
|
||||
#define CC_CTR_PRD 0x1
|
||||
#define CC_CTR_ZERO_PRD 0x2
|
||||
#define CC_LD_DISABLE 0x3
|
||||
|
||||
//
|
||||
// SHDWAMODE and SHDWBMODE bits
|
||||
//
|
||||
#define CC_SHADOW 0x0
|
||||
#define CC_IMMEDIATE 0x1
|
||||
|
||||
//
|
||||
// AQCTLA and AQCTLB (Action Qualifier Control)
|
||||
//
|
||||
|
||||
//
|
||||
// ZRO, PRD, CAU, CAD, CBU, CBD bits
|
||||
//
|
||||
#define AQ_NO_ACTION 0x0
|
||||
#define AQ_CLEAR 0x1
|
||||
#define AQ_SET 0x2
|
||||
#define AQ_TOGGLE 0x3
|
||||
|
||||
//
|
||||
// DBCTL (Dead-Band Control)
|
||||
//
|
||||
|
||||
//
|
||||
// OUT MODE bits
|
||||
//
|
||||
#define DB_DISABLE 0x0
|
||||
#define DBB_ENABLE 0x1
|
||||
#define DBA_ENABLE 0x2
|
||||
#define DB_FULL_ENABLE 0x3
|
||||
|
||||
//
|
||||
// POLSEL bits
|
||||
//
|
||||
#define DB_ACTV_HI 0x0
|
||||
#define DB_ACTV_LOC 0x1
|
||||
#define DB_ACTV_HIC 0x2
|
||||
#define DB_ACTV_LO 0x3
|
||||
|
||||
//
|
||||
// IN MODE
|
||||
//
|
||||
#define DBA_ALL 0x0
|
||||
#define DBB_RED_DBA_FED 0x1
|
||||
#define DBA_RED_DBB_FED 0x2
|
||||
#define DBB_ALL 0x3
|
||||
|
||||
//
|
||||
// CHPCTL (chopper control)
|
||||
//
|
||||
|
||||
//
|
||||
// CHPEN bit
|
||||
//
|
||||
#define CHP_DISABLE 0x0
|
||||
#define CHP_ENABLE 0x1
|
||||
|
||||
//
|
||||
// CHPFREQ bits
|
||||
//
|
||||
#define CHP_DIV1 0x0
|
||||
#define CHP_DIV2 0x1
|
||||
#define CHP_DIV3 0x2
|
||||
#define CHP_DIV4 0x3
|
||||
#define CHP_DIV5 0x4
|
||||
#define CHP_DIV6 0x5
|
||||
#define CHP_DIV7 0x6
|
||||
#define CHP_DIV8 0x7
|
||||
|
||||
//
|
||||
// CHPDUTY bits
|
||||
//
|
||||
#define CHP1_8TH 0x0
|
||||
#define CHP2_8TH 0x1
|
||||
#define CHP3_8TH 0x2
|
||||
#define CHP4_8TH 0x3
|
||||
#define CHP5_8TH 0x4
|
||||
#define CHP6_8TH 0x5
|
||||
#define CHP7_8TH 0x6
|
||||
|
||||
//
|
||||
// TZSEL (Trip Zone Select)
|
||||
//
|
||||
|
||||
//
|
||||
// CBCn and OSHTn bits
|
||||
//
|
||||
#define TZ_DISABLE 0x0
|
||||
#define TZ_ENABLE 0x1
|
||||
|
||||
//
|
||||
// TZCTL (Trip Zone Control)
|
||||
//
|
||||
|
||||
//
|
||||
// TZA and TZB bits
|
||||
//
|
||||
#define TZ_HIZ 0x0
|
||||
#define TZ_FORCE_HI 0x1
|
||||
#define TZ_FORCE_LO 0x2
|
||||
#define TZ_NO_CHANGE 0x3
|
||||
|
||||
//
|
||||
// TZDCSEL (Trip Zone Digital Compare)
|
||||
//
|
||||
|
||||
//
|
||||
// DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits
|
||||
//
|
||||
#define TZ_EVT_DISABLE 0x0
|
||||
#define TZ_DCAH_LOW 0x1
|
||||
#define TZ_DCAH_HI 0x2
|
||||
#define TZ_DCAL_LOW 0x3
|
||||
#define TZ_DCAL_HI 0x4
|
||||
#define TZ_DCAL_HI_DCAH_LOW 0x5
|
||||
|
||||
#define TZ_DCBH_LOW 0x1
|
||||
#define TZ_DCBH_HI 0x2
|
||||
#define TZ_DCBL_LOW 0x3
|
||||
#define TZ_DCBL_HI 0x4
|
||||
#define TZ_DCBL_HI_DCBH_LOW 0x5
|
||||
|
||||
//
|
||||
// ETSEL (Event Trigger Select)
|
||||
//
|
||||
#define ET_DCAEVT1SOC 0x0
|
||||
#define ET_CTR_ZERO 0x1
|
||||
#define ET_CTR_PRD 0x2
|
||||
#define ET_CTR_PRDZERO 0x3
|
||||
#define ET_CTRU_CMPA 0x4
|
||||
#define ET_CTRD_CMPA 0x5
|
||||
#define ET_CTRU_CMPB 0x6
|
||||
#define ET_CTRD_CMPB 0x7
|
||||
|
||||
//
|
||||
// ETPS (Event Trigger Pre-scale)
|
||||
//
|
||||
|
||||
//
|
||||
// INTPRD, SOCAPRD, SOCBPRD bits
|
||||
//
|
||||
#define ET_DISABLE 0x0
|
||||
#define ET_1ST 0x1
|
||||
#define ET_2ND 0x2
|
||||
#define ET_3RD 0x3
|
||||
|
||||
//
|
||||
// HRPWM (High Resolution PWM)
|
||||
//
|
||||
|
||||
//
|
||||
// HRCNFG
|
||||
//
|
||||
#define HR_DISABLE 0x0
|
||||
#define HR_REP 0x1
|
||||
#define HR_FEP 0x2
|
||||
#define HR_BEP 0x3
|
||||
|
||||
#define HR_CMP 0x0
|
||||
#define HR_PHS 0x1
|
||||
|
||||
#define HR_CTR_ZERO 0x0
|
||||
#define HR_CTR_PRD 0x1
|
||||
#define HR_CTR_ZERO_PRD 0x2
|
||||
|
||||
#define HR_NORM_B 0x0
|
||||
#define HR_INVERT_B 0x1
|
||||
|
||||
//
|
||||
// DC (Digital Compare)
|
||||
//
|
||||
|
||||
//
|
||||
// DCTRIPSEL
|
||||
//
|
||||
#define DC_TZ1 0x0
|
||||
#define DC_TZ2 0x1
|
||||
#define DC_TZ3 0x2
|
||||
#define DC_TRIPIN1 0x0
|
||||
#define DC_TRIPIN2 0x1
|
||||
#define DC_TRIPIN3 0x2
|
||||
#define DC_TRIPIN4 0x3
|
||||
#define DC_TRIPIN5 0x4
|
||||
#define DC_TRIPIN6 0x5
|
||||
#define DC_TRIPIN7 0x6
|
||||
#define DC_TRIPIN8 0x7
|
||||
#define DC_TRIPIN9 0x8
|
||||
#define DC_TRIPIN10 0x9
|
||||
#define DC_TRIPIN11 0xA
|
||||
#define DC_TRIPIN12 0xB
|
||||
// Reserved 0xC
|
||||
#define DC_TRIPIN14 0xD
|
||||
#define DC_TRIPIN15 0xE
|
||||
#define DC_COMBINATION 0xF
|
||||
|
||||
//
|
||||
// DCFCTL
|
||||
//
|
||||
#define DC_SRC_DCAEVT1 0x0
|
||||
#define DC_SRC_DCAEVT2 0x1
|
||||
#define DC_SRC_DCBEVT1 0x2
|
||||
#define DC_SRC_DCBEVT2 0x3
|
||||
|
||||
#define DC_PULSESEL_PRD 0x0
|
||||
#define DC_PULSESEL_ZERO 0x1
|
||||
#define DC_PULSESEL_ZERO_PRD 0x2
|
||||
|
||||
#define DC_BLANK_DISABLE 0x0
|
||||
#define DC_BLANK_ENABLE 0x1
|
||||
|
||||
#define DC_BLANK_NOTINV 0x0
|
||||
#define DC_BLANK_INV 0x1
|
||||
|
||||
//
|
||||
//DCACTL/DCBCTL
|
||||
//
|
||||
#define DC_EVT1 0x0
|
||||
#define DC_EVT2 0x0
|
||||
#define DC_EVT_FLT 0x1
|
||||
#define DC_EVT_SYNC 0x0
|
||||
#define DC_EVT_ASYNC 0x1
|
||||
#define DC_SOC_DISABLE 0x0
|
||||
#define DC_SOC_ENABLE 0x1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of F2837xD_EPWM_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,319 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Emif_defines.h
|
||||
//
|
||||
// TITLE: #defines used in EMIF examples
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_EMIF_DEFINES_H
|
||||
#define F2837xD_EMIF_DEFINES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
//cpu1 to cpu2 message for handshaking
|
||||
//
|
||||
#define CPU1_CPU2_MSG 0x3fd00
|
||||
|
||||
//
|
||||
//cpu2_to_cpu1 message ram for handshaking
|
||||
//
|
||||
#define CPU2_CPU1_MSG 0x3fb00
|
||||
|
||||
#define MSEL_EMIF1_CPU1 0x93A5CE71
|
||||
#define MSEL_EMIF1_CPU2 0x93A5CE72
|
||||
#define MSEL_DEF_3 0x93A5CE73
|
||||
#define MSEL_DEF_0 0x93A5CE70
|
||||
#define MSEL_DEF_1 0x93A5CE71
|
||||
#define MSEL_DEF_2 0x93A5CE72
|
||||
|
||||
//
|
||||
//soft reset bit register
|
||||
//
|
||||
#define EMIF_SOFT_PRES_REG 0x5D084
|
||||
|
||||
//
|
||||
//Device capability/EMIF customization register
|
||||
//
|
||||
#define EMIF_DEV_DC_REG 0x5D014
|
||||
|
||||
//
|
||||
// Values for ASYNC_CSx_CR Registers
|
||||
//
|
||||
#define EMIF_ASYNC_ASIZE_8 0x0
|
||||
#define EMIF_ASYNC_ASIZE_16 0x1
|
||||
#define EMIF_ASYNC_ASIZE_32 0x2
|
||||
|
||||
#define EMIF_ASYNC_TA_1 0x0
|
||||
#define EMIF_ASYNC_TA_2 0x4
|
||||
#define EMIF_ASYNC_TA_3 0x8
|
||||
#define EMIF_ASYNC_TA_4 0xC
|
||||
|
||||
#define EMIF_ASYNC_RHOLD_1 0x00
|
||||
#define EMIF_ASYNC_RHOLD_2 0x10
|
||||
#define EMIF_ASYNC_RHOLD_3 0x20
|
||||
#define EMIF_ASYNC_RHOLD_4 0x30
|
||||
#define EMIF_ASYNC_RHOLD_5 0x40
|
||||
#define EMIF_ASYNC_RHOLD_6 0x50
|
||||
#define EMIF_ASYNC_RHOLD_7 0x60
|
||||
#define EMIF_ASYNC_RHOLD_8 0x70
|
||||
|
||||
#define EMIF_ASYNC_RSTROBE_1 0x0000
|
||||
#define EMIF_ASYNC_RSTROBE_2 0x0080
|
||||
#define EMIF_ASYNC_RSTROBE_3 0x0100
|
||||
#define EMIF_ASYNC_RSTROBE_4 0x0180
|
||||
#define EMIF_ASYNC_RSTROBE_5 0x0200
|
||||
#define EMIF_ASYNC_RSTROBE_6 0x0280
|
||||
#define EMIF_ASYNC_RSTROBE_7 0x0300
|
||||
#define EMIF_ASYNC_RSTROBE_8 0x0380
|
||||
#define EMIF_ASYNC_RSTROBE_9 0x0400
|
||||
#define EMIF_ASYNC_RSTROBE_10 0x0480
|
||||
#define EMIF_ASYNC_RSTROBE_11 0x0500
|
||||
#define EMIF_ASYNC_RSTROBE_12 0x0580
|
||||
#define EMIF_ASYNC_RSTROBE_13 0x0600
|
||||
#define EMIF_ASYNC_RSTROBE_14 0x0680
|
||||
#define EMIF_ASYNC_RSTROBE_15 0x0700
|
||||
#define EMIF_ASYNC_RSTROBE_16 0x0780
|
||||
#define EMIF_ASYNC_RSTROBE_17 0x0800
|
||||
#define EMIF_ASYNC_RSTROBE_18 0x0880
|
||||
#define EMIF_ASYNC_RSTROBE_19 0x0900
|
||||
#define EMIF_ASYNC_RSTROBE_20 0x0980
|
||||
#define EMIF_ASYNC_RSTROBE_21 0x0A00
|
||||
#define EMIF_ASYNC_RSTROBE_22 0x0A80
|
||||
#define EMIF_ASYNC_RSTROBE_23 0x0B00
|
||||
#define EMIF_ASYNC_RSTROBE_24 0x0B80
|
||||
#define EMIF_ASYNC_RSTROBE_25 0x0C00
|
||||
#define EMIF_ASYNC_RSTROBE_26 0x0C80
|
||||
#define EMIF_ASYNC_RSTROBE_27 0x0D00
|
||||
#define EMIF_ASYNC_RSTROBE_28 0x0D80
|
||||
#define EMIF_ASYNC_RSTROBE_29 0x0E00
|
||||
#define EMIF_ASYNC_RSTROBE_30 0x0E80
|
||||
#define EMIF_ASYNC_RSTROBE_31 0x0F00
|
||||
#define EMIF_ASYNC_RSTROBE_32 0x0F80
|
||||
#define EMIF_ASYNC_RSTROBE_33 0x1000
|
||||
#define EMIF_ASYNC_RSTROBE_34 0x1080
|
||||
#define EMIF_ASYNC_RSTROBE_35 0x1100
|
||||
#define EMIF_ASYNC_RSTROBE_36 0x1180
|
||||
#define EMIF_ASYNC_RSTROBE_37 0x1200
|
||||
#define EMIF_ASYNC_RSTROBE_38 0x1280
|
||||
#define EMIF_ASYNC_RSTROBE_39 0x1300
|
||||
#define EMIF_ASYNC_RSTROBE_40 0x1380
|
||||
#define EMIF_ASYNC_RSTROBE_41 0x1400
|
||||
#define EMIF_ASYNC_RSTROBE_42 0x1480
|
||||
#define EMIF_ASYNC_RSTROBE_43 0x1500
|
||||
#define EMIF_ASYNC_RSTROBE_44 0x1580
|
||||
#define EMIF_ASYNC_RSTROBE_45 0x1600
|
||||
#define EMIF_ASYNC_RSTROBE_46 0x1680
|
||||
#define EMIF_ASYNC_RSTROBE_47 0x1700
|
||||
#define EMIF_ASYNC_RSTROBE_48 0x1780
|
||||
#define EMIF_ASYNC_RSTROBE_49 0x1800
|
||||
#define EMIF_ASYNC_RSTROBE_50 0x1880
|
||||
#define EMIF_ASYNC_RSTROBE_51 0x1900
|
||||
#define EMIF_ASYNC_RSTROBE_52 0x1980
|
||||
#define EMIF_ASYNC_RSTROBE_53 0x1A00
|
||||
#define EMIF_ASYNC_RSTROBE_54 0x1A80
|
||||
#define EMIF_ASYNC_RSTROBE_55 0x1B00
|
||||
#define EMIF_ASYNC_RSTROBE_56 0x1B80
|
||||
#define EMIF_ASYNC_RSTROBE_57 0x1C00
|
||||
#define EMIF_ASYNC_RSTROBE_58 0x1C80
|
||||
#define EMIF_ASYNC_RSTROBE_59 0x1D00
|
||||
#define EMIF_ASYNC_RSTROBE_60 0x1D80
|
||||
#define EMIF_ASYNC_RSTROBE_61 0x1E00
|
||||
#define EMIF_ASYNC_RSTROBE_62 0x1E80
|
||||
#define EMIF_ASYNC_RSTROBE_63 0x1F00
|
||||
#define EMIF_ASYNC_RSTROBE_64 0x1F80
|
||||
|
||||
#define EMIF_ASYNC_RSETUP_1 0x0000
|
||||
#define EMIF_ASYNC_RSETUP_2 0x2000
|
||||
#define EMIF_ASYNC_RSETUP_3 0x4000
|
||||
#define EMIF_ASYNC_RSETUP_4 0x6000
|
||||
#define EMIF_ASYNC_RSETUP_5 0x8000
|
||||
#define EMIF_ASYNC_RSETUP_6 0xA000
|
||||
#define EMIF_ASYNC_RSETUP_7 0xC000
|
||||
#define EMIF_ASYNC_RSETUP_8 0xE000
|
||||
#define EMIF_ASYNC_RSETUP_9 0x10000
|
||||
#define EMIF_ASYNC_RSETUP_10 0x12000
|
||||
#define EMIF_ASYNC_RSETUP_11 0x14000
|
||||
#define EMIF_ASYNC_RSETUP_12 0x16000
|
||||
#define EMIF_ASYNC_RSETUP_13 0x18000
|
||||
#define EMIF_ASYNC_RSETUP_14 0x1A000
|
||||
#define EMIF_ASYNC_RSETUP_15 0x1C000
|
||||
#define EMIF_ASYNC_RSETUP_16 0x1E000
|
||||
|
||||
#define EMIF_ASYNC_WHOLD_1 0x00000
|
||||
#define EMIF_ASYNC_WHOLD_2 0x20000
|
||||
#define EMIF_ASYNC_WHOLD_3 0x40000
|
||||
#define EMIF_ASYNC_WHOLD_4 0x60000
|
||||
#define EMIF_ASYNC_WHOLD_5 0x80000
|
||||
#define EMIF_ASYNC_WHOLD_6 0xA0000
|
||||
#define EMIF_ASYNC_WHOLD_7 0xC0000
|
||||
#define EMIF_ASYNC_WHOLD_8 0xE0000
|
||||
|
||||
#define EMIF_ASYNC_WSTROBE_1 0x0000000
|
||||
#define EMIF_ASYNC_WSTROBE_2 0x0100000
|
||||
#define EMIF_ASYNC_WSTROBE_3 0x0200000
|
||||
#define EMIF_ASYNC_WSTROBE_4 0x0300000
|
||||
#define EMIF_ASYNC_WSTROBE_5 0x0400000
|
||||
#define EMIF_ASYNC_WSTROBE_6 0x0500000
|
||||
#define EMIF_ASYNC_WSTROBE_7 0x0600000
|
||||
#define EMIF_ASYNC_WSTROBE_8 0x0700000
|
||||
#define EMIF_ASYNC_WSTROBE_9 0x0800000
|
||||
#define EMIF_ASYNC_WSTROBE_10 0x0900000
|
||||
#define EMIF_ASYNC_WSTROBE_11 0x0A00000
|
||||
#define EMIF_ASYNC_WSTROBE_12 0x0B00000
|
||||
#define EMIF_ASYNC_WSTROBE_13 0x0C00000
|
||||
#define EMIF_ASYNC_WSTROBE_14 0x0D00000
|
||||
#define EMIF_ASYNC_WSTROBE_15 0x0E00000
|
||||
#define EMIF_ASYNC_WSTROBE_16 0x0F00000
|
||||
#define EMIF_ASYNC_WSTROBE_17 0x1000000
|
||||
#define EMIF_ASYNC_WSTROBE_18 0x1100000
|
||||
#define EMIF_ASYNC_WSTROBE_19 0x1200000
|
||||
#define EMIF_ASYNC_WSTROBE_20 0x1300000
|
||||
#define EMIF_ASYNC_WSTROBE_21 0x1400000
|
||||
#define EMIF_ASYNC_WSTROBE_22 0x1500000
|
||||
#define EMIF_ASYNC_WSTROBE_23 0x1600000
|
||||
#define EMIF_ASYNC_WSTROBE_24 0x1700000
|
||||
#define EMIF_ASYNC_WSTROBE_25 0x1800000
|
||||
#define EMIF_ASYNC_WSTROBE_26 0x1900000
|
||||
#define EMIF_ASYNC_WSTROBE_27 0x1A00000
|
||||
#define EMIF_ASYNC_WSTROBE_28 0x1B00000
|
||||
#define EMIF_ASYNC_WSTROBE_29 0x1C00000
|
||||
#define EMIF_ASYNC_WSTROBE_30 0x1D00000
|
||||
#define EMIF_ASYNC_WSTROBE_31 0x1E00000
|
||||
#define EMIF_ASYNC_WSTROBE_32 0x1F00000
|
||||
#define EMIF_ASYNC_WSTROBE_33 0x2000000
|
||||
#define EMIF_ASYNC_WSTROBE_34 0x2100000
|
||||
#define EMIF_ASYNC_WSTROBE_35 0x2200000
|
||||
#define EMIF_ASYNC_WSTROBE_36 0x2300000
|
||||
#define EMIF_ASYNC_WSTROBE_37 0x2400000
|
||||
#define EMIF_ASYNC_WSTROBE_38 0x2500000
|
||||
#define EMIF_ASYNC_WSTROBE_39 0x2600000
|
||||
#define EMIF_ASYNC_WSTROBE_40 0x2700000
|
||||
#define EMIF_ASYNC_WSTROBE_41 0x2800000
|
||||
#define EMIF_ASYNC_WSTROBE_42 0x2900000
|
||||
#define EMIF_ASYNC_WSTROBE_43 0x2A00000
|
||||
#define EMIF_ASYNC_WSTROBE_44 0x2B00000
|
||||
#define EMIF_ASYNC_WSTROBE_45 0x2C00000
|
||||
#define EMIF_ASYNC_WSTROBE_46 0x2D00000
|
||||
#define EMIF_ASYNC_WSTROBE_47 0x2E00000
|
||||
#define EMIF_ASYNC_WSTROBE_48 0x2F00000
|
||||
#define EMIF_ASYNC_WSTROBE_49 0x3000000
|
||||
#define EMIF_ASYNC_WSTROBE_50 0x3100000
|
||||
#define EMIF_ASYNC_WSTROBE_51 0x3200000
|
||||
#define EMIF_ASYNC_WSTROBE_52 0x3300000
|
||||
#define EMIF_ASYNC_WSTROBE_53 0x3400000
|
||||
#define EMIF_ASYNC_WSTROBE_54 0x3500000
|
||||
#define EMIF_ASYNC_WSTROBE_55 0x3600000
|
||||
#define EMIF_ASYNC_WSTROBE_56 0x3700000
|
||||
#define EMIF_ASYNC_WSTROBE_57 0x3800000
|
||||
#define EMIF_ASYNC_WSTROBE_58 0x3900000
|
||||
#define EMIF_ASYNC_WSTROBE_59 0x3A00000
|
||||
#define EMIF_ASYNC_WSTROBE_60 0x3B00000
|
||||
#define EMIF_ASYNC_WSTROBE_61 0x3C00000
|
||||
#define EMIF_ASYNC_WSTROBE_62 0x3D00000
|
||||
#define EMIF_ASYNC_WSTROBE_63 0x3E00000
|
||||
#define EMIF_ASYNC_WSTROBE_64 0x3F00000
|
||||
|
||||
#define EMIF_ASYNC_WSETUP_1 0x00000000
|
||||
#define EMIF_ASYNC_WSETUP_2 0x04000000
|
||||
#define EMIF_ASYNC_WSETUP_3 0x08000000
|
||||
#define EMIF_ASYNC_WSETUP_4 0x0C000000
|
||||
#define EMIF_ASYNC_WSETUP_5 0x10000000
|
||||
#define EMIF_ASYNC_WSETUP_6 0x14000000
|
||||
#define EMIF_ASYNC_WSETUP_7 0x18000000
|
||||
#define EMIF_ASYNC_WSETUP_8 0x1C000000
|
||||
#define EMIF_ASYNC_WSETUP_9 0x20000000
|
||||
#define EMIF_ASYNC_WSETUP_10 0x24000000
|
||||
#define EMIF_ASYNC_WSETUP_11 0x28000000
|
||||
#define EMIF_ASYNC_WSETUP_12 0x2C000000
|
||||
#define EMIF_ASYNC_WSETUP_13 0x30000000
|
||||
#define EMIF_ASYNC_WSETUP_14 0x34000000
|
||||
#define EMIF_ASYNC_WSETUP_15 0x38000000
|
||||
#define EMIF_ASYNC_WSETUP_16 0x3C000000
|
||||
|
||||
#define EMIF_ASYNC_EW_DISABLE 0x00000000
|
||||
#define EMIF_ASYNC_EW_ENABLE 0x40000000
|
||||
|
||||
#define EMIF_ASYNC_SS_DISABLE 0x00000000
|
||||
#define EMIF_ASYNC_SS_ENABLE 0x80000000
|
||||
|
||||
//
|
||||
// Values for ASYNC_WCCR Register
|
||||
//
|
||||
#define EMIF_ASYNC_WCCR_WP_LOW 0x00000000
|
||||
#define EMIF_ASYNC_WCCR_WP_HIGH 0x01000000
|
||||
|
||||
//
|
||||
// Read mask for the registers which has reserved bits.
|
||||
//
|
||||
#define ASYNC_WCCR_RDMASK 0xF0FF00FF
|
||||
#define SDRAM_CR_RDMASK 0xE3FF7F7F
|
||||
#define SDRAM_RCR_RDMASK 0x00071FFF
|
||||
#define SDRAM_TR_RDMASK 0xFF77FF70
|
||||
#define SDR_EXT_TMNG_RDMASK 0x1F
|
||||
#define INT_RAW_RDMASK 0x3F
|
||||
#define INT_MASK_RDMASK 0x3F
|
||||
#define IO_CTRL_RDMASK_RDMASK 0xFFFF
|
||||
#define IO_STAT_RDMASK_RDMASK 0xF
|
||||
#define NAND_FLASH_CTRL_RDMASK 0x3F3F
|
||||
#define NAND_FLASH_STAT_RDMASK 0x30F0F
|
||||
#define IODFT_TLECR_REG_RDMASK 0xFFFF
|
||||
#define IODFT_TLGCR_REG_RDMASK 0x71FF
|
||||
#define IODFT_TLAMR_REG_RDMASK 0x0FFFFFFF
|
||||
#define IODFT_TLDCMR_REG_RDMASK 0x3fff3f07
|
||||
#define MODEL_REL_NUM_REG_RDMASK 0xFF
|
||||
#define NAND_FLASH_4BIT_ECCLR_RDMASK 0x3F
|
||||
#define NAND_FLASH_4BIT_ECCx_RDMASK 0x03ff03ff
|
||||
#define NAND_FLASH_ERR_ADDRx_RDMASK 0x03ff03ff
|
||||
#define NAND_FLASH_ERR_VALx_RDMASK 0x03ff03ff
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of F2837xD_EMIF_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,448 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Examples.h
|
||||
//
|
||||
// TITLE: F2837xD Device Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_EXAMPLES_H
|
||||
#define F2837xD_EXAMPLES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// The following are values that can be passed to the
|
||||
// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL integer multiplier
|
||||
//
|
||||
#define IMULT_0 0
|
||||
#define IMULT_1 1
|
||||
#define IMULT_2 2
|
||||
#define IMULT_3 3
|
||||
#define IMULT_4 4
|
||||
#define IMULT_5 5
|
||||
#define IMULT_6 6
|
||||
#define IMULT_7 7
|
||||
#define IMULT_8 8
|
||||
#define IMULT_9 9
|
||||
#define IMULT_10 10
|
||||
#define IMULT_11 11
|
||||
#define IMULT_12 12
|
||||
#define IMULT_13 13
|
||||
#define IMULT_14 14
|
||||
#define IMULT_15 15
|
||||
#define IMULT_16 16
|
||||
#define IMULT_17 17
|
||||
#define IMULT_18 18
|
||||
#define IMULT_19 19
|
||||
#define IMULT_20 20
|
||||
#define IMULT_21 21
|
||||
#define IMULT_22 22
|
||||
#define IMULT_23 23
|
||||
#define IMULT_24 24
|
||||
#define IMULT_25 25
|
||||
#define IMULT_26 26
|
||||
#define IMULT_27 27
|
||||
#define IMULT_28 28
|
||||
#define IMULT_29 29
|
||||
#define IMULT_30 30
|
||||
#define IMULT_31 31
|
||||
#define IMULT_32 32
|
||||
#define IMULT_33 33
|
||||
#define IMULT_34 34
|
||||
#define IMULT_35 35
|
||||
#define IMULT_36 36
|
||||
#define IMULT_37 37
|
||||
#define IMULT_38 38
|
||||
#define IMULT_39 39
|
||||
#define IMULT_40 40
|
||||
#define IMULT_41 41
|
||||
#define IMULT_42 42
|
||||
#define IMULT_43 43
|
||||
#define IMULT_44 44
|
||||
#define IMULT_45 45
|
||||
#define IMULT_46 46
|
||||
#define IMULT_47 47
|
||||
#define IMULT_48 48
|
||||
#define IMULT_49 49
|
||||
#define IMULT_50 50
|
||||
#define IMULT_51 51
|
||||
#define IMULT_52 52
|
||||
#define IMULT_53 53
|
||||
#define IMULT_54 54
|
||||
#define IMULT_55 55
|
||||
#define IMULT_56 56
|
||||
#define IMULT_57 57
|
||||
#define IMULT_58 58
|
||||
#define IMULT_59 59
|
||||
#define IMULT_60 60
|
||||
#define IMULT_61 61
|
||||
#define IMULT_62 62
|
||||
#define IMULT_63 63
|
||||
#define IMULT_64 64
|
||||
#define IMULT_65 65
|
||||
#define IMULT_66 66
|
||||
#define IMULT_67 67
|
||||
#define IMULT_68 68
|
||||
#define IMULT_69 69
|
||||
#define IMULT_70 70
|
||||
#define IMULT_71 71
|
||||
#define IMULT_72 72
|
||||
#define IMULT_73 73
|
||||
#define IMULT_74 74
|
||||
#define IMULT_75 75
|
||||
#define IMULT_76 76
|
||||
#define IMULT_77 77
|
||||
#define IMULT_78 78
|
||||
#define IMULT_79 79
|
||||
#define IMULT_80 80
|
||||
#define IMULT_81 81
|
||||
#define IMULT_82 82
|
||||
#define IMULT_83 83
|
||||
#define IMULT_84 84
|
||||
#define IMULT_85 85
|
||||
#define IMULT_86 86
|
||||
#define IMULT_87 87
|
||||
#define IMULT_88 88
|
||||
#define IMULT_89 89
|
||||
#define IMULT_90 90
|
||||
#define IMULT_91 91
|
||||
#define IMULT_92 92
|
||||
#define IMULT_93 93
|
||||
#define IMULT_94 94
|
||||
#define IMULT_95 95
|
||||
#define IMULT_96 96
|
||||
#define IMULT_97 97
|
||||
#define IMULT_98 98
|
||||
#define IMULT_99 99
|
||||
#define IMULT_100 100
|
||||
#define IMULT_101 101
|
||||
#define IMULT_102 102
|
||||
#define IMULT_103 103
|
||||
#define IMULT_104 104
|
||||
#define IMULT_105 105
|
||||
#define IMULT_106 106
|
||||
#define IMULT_107 107
|
||||
#define IMULT_108 108
|
||||
#define IMULT_109 109
|
||||
#define IMULT_110 110
|
||||
#define IMULT_111 111
|
||||
#define IMULT_112 112
|
||||
#define IMULT_113 113
|
||||
#define IMULT_114 114
|
||||
#define IMULT_115 115
|
||||
#define IMULT_116 116
|
||||
#define IMULT_117 117
|
||||
#define IMULT_118 118
|
||||
#define IMULT_119 119
|
||||
#define IMULT_120 120
|
||||
#define IMULT_121 121
|
||||
#define IMULT_122 122
|
||||
#define IMULT_123 123
|
||||
#define IMULT_124 124
|
||||
#define IMULT_125 125
|
||||
#define IMULT_126 126
|
||||
#define IMULT_127 127
|
||||
|
||||
//
|
||||
// The following are values that can be passed to the
|
||||
// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL fractional multiplier
|
||||
//
|
||||
#define FMULT_0 0
|
||||
#define FMULT_0pt25 1
|
||||
#define FMULT_0pt5 2
|
||||
#define FMULT_0pt75 3
|
||||
|
||||
//
|
||||
// The following are values that can be passed to the
|
||||
// InitSysPll() to select divsel for SYSPLL
|
||||
//
|
||||
#define PLLCLK_BY_1 0
|
||||
#define PLLCLK_BY_2 1
|
||||
#define PLLCLK_BY_4 2
|
||||
#define PLLCLK_BY_6 3
|
||||
#define PLLCLK_BY_8 4
|
||||
#define PLLCLK_BY_10 5
|
||||
#define PLLCLK_BY_12 6
|
||||
#define PLLCLK_BY_14 7
|
||||
#define PLLCLK_BY_16 8
|
||||
#define PLLCLK_BY_18 9
|
||||
#define PLLCLK_BY_20 10
|
||||
#define PLLCLK_BY_22 11
|
||||
#define PLLCLK_BY_24 12
|
||||
#define PLLCLK_BY_26 13
|
||||
#define PLLCLK_BY_28 14
|
||||
#define PLLCLK_BY_30 15
|
||||
#define PLLCLK_BY_32 16
|
||||
#define PLLCLK_BY_34 17
|
||||
#define PLLCLK_BY_36 18
|
||||
#define PLLCLK_BY_38 19
|
||||
#define PLLCLK_BY_40 20
|
||||
#define PLLCLK_BY_42 21
|
||||
#define PLLCLK_BY_44 22
|
||||
#define PLLCLK_BY_46 23
|
||||
#define PLLCLK_BY_48 24
|
||||
#define PLLCLK_BY_50 25
|
||||
#define PLLCLK_BY_52 26
|
||||
#define PLLCLK_BY_54 27
|
||||
#define PLLCLK_BY_56 28
|
||||
#define PLLCLK_BY_58 29
|
||||
#define PLLCLK_BY_60 30
|
||||
#define PLLCLK_BY_62 31
|
||||
#define PLLCLK_BY_64 32
|
||||
#define PLLCLK_BY_66 33
|
||||
#define PLLCLK_BY_68 34
|
||||
#define PLLCLK_BY_70 35
|
||||
#define PLLCLK_BY_72 36
|
||||
#define PLLCLK_BY_74 37
|
||||
#define PLLCLK_BY_76 38
|
||||
#define PLLCLK_BY_78 39
|
||||
#define PLLCLK_BY_80 40
|
||||
#define PLLCLK_BY_82 41
|
||||
#define PLLCLK_BY_84 42
|
||||
#define PLLCLK_BY_86 43
|
||||
#define PLLCLK_BY_88 44
|
||||
#define PLLCLK_BY_90 45
|
||||
#define PLLCLK_BY_92 46
|
||||
#define PLLCLK_BY_94 47
|
||||
#define PLLCLK_BY_96 48
|
||||
#define PLLCLK_BY_98 49
|
||||
#define PLLCLK_BY_100 50
|
||||
#define PLLCLK_BY_102 51
|
||||
#define PLLCLK_BY_104 52
|
||||
#define PLLCLK_BY_106 53
|
||||
#define PLLCLK_BY_108 54
|
||||
#define PLLCLK_BY_110 55
|
||||
#define PLLCLK_BY_112 56
|
||||
#define PLLCLK_BY_114 57
|
||||
#define PLLCLK_BY_116 58
|
||||
#define PLLCLK_BY_118 59
|
||||
#define PLLCLK_BY_120 60
|
||||
#define PLLCLK_BY_122 61
|
||||
#define PLLCLK_BY_124 62
|
||||
#define PLLCLK_BY_126 63
|
||||
|
||||
//
|
||||
// The following are values that can be passed to the
|
||||
// InitAuxPll() to select divsel for AUXPLL
|
||||
//
|
||||
#define AUXPLLRAWCLK_BY_1 0
|
||||
#define AUXPLLRAWCLK_BY_2 1
|
||||
#define AUXPLLRAWCLK_BY_4 2
|
||||
#define AUXPLLRAWCLK_BY_8 3
|
||||
|
||||
//
|
||||
// The following are values that can be passed to the
|
||||
// IntOsc2Sel() & XtalOscSel() to select system PLL (or) AUX PLL
|
||||
//
|
||||
#define SYSTEM_PLL (Uint16) 0
|
||||
#define AUX_PLL (Uint16) 1
|
||||
|
||||
//
|
||||
// The following are values that can be passed to the
|
||||
// InitSysPll() & InitAuxPll() to select clock source
|
||||
//
|
||||
#define INT_OSC2 0
|
||||
#define XTAL_OSC 1
|
||||
#define INT_OSC1 2
|
||||
#define AUXCLKIN 4
|
||||
|
||||
//
|
||||
// Specify the clock rate of the CPU (SYSCLKOUT) in nS.
|
||||
//
|
||||
// Take into account the input clock frequency and the PLL multiplier
|
||||
// selected in step 1.
|
||||
//
|
||||
// Use one of the values provided, or define your own.
|
||||
// The trailing L is required tells the compiler to treat
|
||||
// the number as a 64-bit value.
|
||||
//
|
||||
// Only one statement should be uncommented.
|
||||
//
|
||||
// Example: 200 MHz devices:
|
||||
// CLKIN is a 10 MHz crystal or internal 10 MHz oscillator
|
||||
//
|
||||
// In step 1 the user specified the PLL multiplier = 40 for a
|
||||
// 200 MHz CPU clock (SYSCLKOUT = 200 MHz).
|
||||
//
|
||||
// In this case, the CPU_RATE will be 5.000L
|
||||
// Uncomment the line: #define CPU_RATE 5.000L
|
||||
//
|
||||
|
||||
#define CPU_RATE 5.00L // for a 200MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 5.263L // for a 190MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 5.556L // for a 180MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 5.882L // for a 170MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 6.250L // for a 160MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 7.692L // for a 130MHz CPU clock speed (SYSCLKOUT)
|
||||
//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
|
||||
|
||||
//
|
||||
// The following pointer to a function call calibrates the ADC reference,
|
||||
// DAC offset, and internal oscillators
|
||||
//
|
||||
#define Device_cal ((void (*)(void))((uintptr_t)0x070282))
|
||||
|
||||
//
|
||||
// The following pointers to functions calibrate the ADC linearity. Use this
|
||||
// in the AdcSetMode(...) function only
|
||||
//
|
||||
#define CalAdcaINL (void (*)(void))0x0703B4
|
||||
#define CalAdcbINL (void (*)(void))0x0703B2
|
||||
#define CalAdccINL (void (*)(void))0x0703B0
|
||||
#define CalAdcdINL (void (*)(void))0x0703AE
|
||||
|
||||
//
|
||||
// The following pointer to a function call looks up the ADC offset trim for a
|
||||
// given condition. Use this in the AdcSetMode(...) function only.
|
||||
//
|
||||
#define GetAdcOffsetTrimOTP (Uint16 (*)(Uint16 OTPoffset))0x0703AC
|
||||
|
||||
//
|
||||
// Includes
|
||||
//
|
||||
#include "F2837xD_GlobalPrototypes.h" // Prototypes for global functions
|
||||
// within the .c files.
|
||||
#include "F2837xD_cputimervars.h"
|
||||
#include "F2837xD_Cla_defines.h" // Macros used for CLA examples.
|
||||
#include "F2837xD_EPwm_defines.h" // Macros used for PWM examples.
|
||||
#include "F2837xD_Adc_defines.h" // Macros used for ADC examples.
|
||||
#include "F2837xD_Emif_defines.h" // Macros used for EMIF examples.
|
||||
#include "F2837xD_Gpio_defines.h" // Macros used for GPIO support code
|
||||
#include "F2837xD_I2c_defines.h" // Macros used for I2C examples.
|
||||
#include "F2837xD_Ipc_defines.h" // Macros used for IPC support code.
|
||||
#include "F2837xD_Pie_defines.h" // Macros used for PIE examples.
|
||||
#include "F2837xD_Dma_defines.h" // Macros used for DMA examples.
|
||||
#include "F2837xD_SysCtrl_defines.h" // Macros used for LPM support code
|
||||
#include "F2837xD_Upp_defines.h" // Macros used for UPP examples.
|
||||
|
||||
#define PARTNO_2837xPACKAGEHERE 0x00
|
||||
|
||||
#define CPU_FRQ_200MHZ 1
|
||||
#define CPU_FRQ_150MHZ 0
|
||||
#define CPU_FRQ_120MHZ 0
|
||||
|
||||
//
|
||||
// Include files not used with F/BIOS
|
||||
//
|
||||
#ifndef F28_BIOS
|
||||
#include "F2837xD_defaultisr.h"
|
||||
#endif
|
||||
|
||||
extern void F28x_usDelay(long LoopCount);
|
||||
|
||||
//
|
||||
// DO NOT MODIFY THIS LINE.
|
||||
//
|
||||
#define DELAY_US(A) F28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L)
|
||||
|
||||
//
|
||||
// Timer Operations:
|
||||
//
|
||||
|
||||
//
|
||||
// Start Timer:
|
||||
//
|
||||
#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0
|
||||
|
||||
//
|
||||
// Stop Timer:
|
||||
//
|
||||
#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1
|
||||
|
||||
//
|
||||
// Reload Timer With period Value:
|
||||
//
|
||||
#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1
|
||||
|
||||
//
|
||||
// Read 32-Bit Timer Value:
|
||||
//
|
||||
#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all
|
||||
|
||||
//
|
||||
// Read 32-Bit Period Value:
|
||||
//
|
||||
#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all
|
||||
|
||||
//
|
||||
// Start Timer:
|
||||
//
|
||||
#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
|
||||
#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
|
||||
|
||||
//
|
||||
// Stop Timer:
|
||||
//
|
||||
#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
|
||||
#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
|
||||
|
||||
//
|
||||
// Reload Timer With period Value:
|
||||
//
|
||||
#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
|
||||
#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
|
||||
|
||||
//
|
||||
// Read 32-Bit Timer Value:
|
||||
//
|
||||
#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all
|
||||
#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all
|
||||
|
||||
//
|
||||
// Read 32-Bit Period Value:
|
||||
//
|
||||
#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all
|
||||
#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of F2837xD_EXAMPLES_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,366 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_GlobalPrototypes.h
|
||||
//
|
||||
// TITLE: Global prototypes for F2837xD Examples
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_GLOBALPROTOTYPES_H
|
||||
#define F2837xD_GLOBALPROTOTYPES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Function Prototypes (Shared)
|
||||
//
|
||||
extern void EnableInterrupts(void);
|
||||
extern void InitAPwm1Gpio(void);
|
||||
extern void InitCAN(void);
|
||||
extern void InitECap(void);
|
||||
extern void InitECapGpio(void);
|
||||
extern void InitECap1Gpio(Uint16 pin);
|
||||
extern void InitECap2Gpio(Uint16 pin);
|
||||
extern void InitECap3Gpio(Uint16 pin);
|
||||
extern void InitECap4Gpio(Uint16 pin);
|
||||
extern void InitECap5Gpio(Uint16 pin);
|
||||
extern void InitECap6Gpio(Uint16 pin);
|
||||
extern void InitEQep1Gpio(void);
|
||||
extern void InitEQep2Gpio(void);
|
||||
extern void InitEQep3Gpio(void);
|
||||
extern void InitEPwmGpio(void);
|
||||
extern void InitEPwm1Gpio(void);
|
||||
extern void InitEPwm2Gpio(void);
|
||||
extern void InitEPwm3Gpio(void);
|
||||
extern void InitEPwm4Gpio(void);
|
||||
extern void InitEPwm5Gpio(void);
|
||||
extern void InitEPwm6Gpio(void);
|
||||
extern void InitEPwm7Gpio(void);
|
||||
extern void InitEPwm8Gpio(void);
|
||||
extern void InitEPwm9Gpio(void);
|
||||
extern void InitEPwm10Gpio(void);
|
||||
extern void InitEPwm11Gpio(void);
|
||||
extern void InitEPwm12Gpio(void);
|
||||
extern void InitPeripheralClocks(void);
|
||||
extern void DisablePeripheralClocks(void);
|
||||
extern void InitPieCtrl(void);
|
||||
extern void InitPieVectTable(void);
|
||||
extern void InitSpi(void);
|
||||
extern void InitSpiGpio(void);
|
||||
extern void InitSpiaGpio(void);
|
||||
extern void InitSysCtrl(void);
|
||||
extern void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult,
|
||||
Uint16 divsel);
|
||||
extern void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult,
|
||||
Uint16 divsel);
|
||||
|
||||
#define KickDog ServiceDog // For compatibility with previous versions
|
||||
extern void ServiceDog(void);
|
||||
extern void DisableDog(void);
|
||||
|
||||
extern Uint16 CsmUnlock(void);
|
||||
extern void SysIntOsc1Sel (void);
|
||||
extern void SysIntOsc2Sel (void);
|
||||
extern void SysXtalOscSel (void);
|
||||
|
||||
extern void AuxIntOsc2Sel (void);
|
||||
extern void AuxXtalOscSel (void);
|
||||
extern void AuxAuxClkSel (void);
|
||||
|
||||
extern void SetDBGIER(Uint16 dbgier);
|
||||
|
||||
//
|
||||
// CAUTION
|
||||
// This function MUST be executed out of RAM. Executing it
|
||||
// out of OTP/Flash will yield unpredictable results
|
||||
//
|
||||
extern void InitFlash(void);
|
||||
extern void InitFlash_Bank0(void);
|
||||
extern void InitFlash_Bank1(void);
|
||||
extern void FlashOff(void);
|
||||
extern void FlashOff_Bank0(void);
|
||||
extern void FlashOff_Bank1(void);
|
||||
extern void SeizeFlashPump(void);
|
||||
extern void SeizeFlashPump_Bank0(void);
|
||||
extern void SeizeFlashPump_Bank1(void);
|
||||
extern void ReleaseFlashPump(void);
|
||||
|
||||
//
|
||||
//LPM functions in F2837xD_SysCtrl.c
|
||||
//
|
||||
void IDLE();
|
||||
void STANDBY();
|
||||
void HALT();
|
||||
void HIB();
|
||||
|
||||
//
|
||||
//ADC functions
|
||||
//
|
||||
extern void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode);
|
||||
extern void CalAdcINL(Uint16 adc);
|
||||
#ifdef CPU1
|
||||
extern void ConfigureTMXAnalogTrim(void);
|
||||
#endif
|
||||
|
||||
//
|
||||
// DMA Functions
|
||||
//
|
||||
extern void DMAInitialize(void);
|
||||
|
||||
//
|
||||
// DMA Channel 1
|
||||
//
|
||||
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
||||
volatile Uint32 *DMA_Source);
|
||||
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize,
|
||||
Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH1(void);
|
||||
|
||||
//
|
||||
// DMA Channel 2
|
||||
//
|
||||
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
||||
volatile Uint32 *DMA_Source);
|
||||
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize,
|
||||
Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH2(void);
|
||||
|
||||
//
|
||||
// DMA Channel 3
|
||||
//
|
||||
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
||||
volatile Uint32 *DMA_Source);
|
||||
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize,
|
||||
Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH3(void);
|
||||
|
||||
//
|
||||
// DMA Channel 4
|
||||
//
|
||||
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
||||
volatile Uint32 *DMA_Source);
|
||||
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize,
|
||||
Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH4(void);
|
||||
|
||||
//
|
||||
// DMA Channel 5
|
||||
//
|
||||
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
||||
volatile Uint32 *DMA_Source);
|
||||
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize,
|
||||
Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH5(void);
|
||||
|
||||
//
|
||||
// DMA Channel 6
|
||||
//
|
||||
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,
|
||||
volatile Uint16 *DMA_Source);
|
||||
extern void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest,
|
||||
volatile Uint32 *DMA_Source);
|
||||
extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
|
||||
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
|
||||
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
|
||||
int16 deswstep);
|
||||
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
|
||||
Uint16 cont, Uint16 synce, Uint16 syncsel,
|
||||
Uint16 ovrinte, Uint16 datasize,
|
||||
Uint16 chintmode,
|
||||
Uint16 chinte);
|
||||
extern void StartDMACH6(void);
|
||||
|
||||
//
|
||||
//GPIO Functions
|
||||
//
|
||||
extern void InitGpio();
|
||||
extern void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition);
|
||||
extern void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags);
|
||||
extern void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags);
|
||||
extern void GPIO_SetupXINT1Gpio(Uint16 gpioNumber);
|
||||
extern void GPIO_SetupXINT2Gpio(Uint16 gpioNumber);
|
||||
extern void GPIO_SetupXINT3Gpio(Uint16 gpioNumber);
|
||||
extern void GPIO_SetupXINT4Gpio(Uint16 gpioNumber);
|
||||
extern void GPIO_SetupXINT5Gpio(Uint16 gpioNumber);
|
||||
extern void GPIO_SelectIpcInt(Uint16 newFlag);
|
||||
extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void);
|
||||
extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void);
|
||||
extern void GPIO_EnableUnbondedIOPullups(void);
|
||||
Uint16 GPIO_ReadPin(Uint16 gpioNumber);
|
||||
void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal);
|
||||
|
||||
//
|
||||
//IPC Functions
|
||||
//
|
||||
extern void InitIpc();
|
||||
extern Uint64 ReadIpcTimer();
|
||||
extern void SendIpcData(void *data, Uint16 word_length, Uint16 flag);
|
||||
extern void RecvIpcData(void *recv_buf, Uint16 word_length);
|
||||
extern void FillIpcSendData(Uint16 fill_data);
|
||||
extern void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data,
|
||||
Uint16 flag);
|
||||
extern void SendIpcFlag(Uint16 flag);
|
||||
extern void AckIpcFlag(Uint16 flag);
|
||||
extern void CancelIpcFlag(Uint16 flag);
|
||||
extern void WaitForIpcFlag(Uint16 flag);
|
||||
extern void WaitForIpcAck(Uint16 flag);
|
||||
extern void IpcSync(Uint16 flag);
|
||||
|
||||
//
|
||||
// CAN Functions
|
||||
//
|
||||
extern void CanGpioPinMuxing(Uint32 ulBase, Uint16 canTxRxPin);
|
||||
extern void CanAGpioConfig(Uint16 canaTxRxPin);
|
||||
extern void CanBGpioConfig(Uint16 canbTxRxPin);
|
||||
extern void CanModuleClkSelect(Uint32 ulBase, Uint16 ucSource);
|
||||
|
||||
//
|
||||
// I2C Functions
|
||||
//
|
||||
extern void I2cAGpioConfig(Uint16 I2caDataClkPin);
|
||||
extern void I2cBGpioConfig(Uint16 I2cbDataClkPin);
|
||||
|
||||
//
|
||||
// McBSP functions
|
||||
// McBSPA
|
||||
//
|
||||
extern void InitMcbspa(void);
|
||||
extern void InitMcbspaInt(void);
|
||||
extern void InitMcbspa8bit(void);
|
||||
extern void InitMcbspa12bit(void);
|
||||
extern void InitMcbspa16bit(void);
|
||||
extern void InitMcbspa20bit(void);
|
||||
extern void InitMcbspa24bit(void);
|
||||
extern void InitMcbspa32bit(void);
|
||||
extern void InitMcbspaGpio(void);
|
||||
extern void delay_loop(void);
|
||||
|
||||
//
|
||||
// McBSPB
|
||||
//
|
||||
extern void InitMcbspb(void);
|
||||
extern void InitMcbspbInt(void);
|
||||
extern void InitMcbspb8bit(void);
|
||||
extern void InitMcbspb12bit(void);
|
||||
extern void InitMcbspb16bit(void);
|
||||
extern void InitMcbspb20bit(void);
|
||||
extern void InitMcbspb24bit(void);
|
||||
extern void InitMcbspb32bit(void);
|
||||
extern void InitMcbspbGpio(void);
|
||||
|
||||
//
|
||||
//Temp Sensor Functions
|
||||
//
|
||||
extern void InitTempSensor(float32 vrefhi_voltage);
|
||||
extern int16 GetTemperatureC(int16 sensorSample);
|
||||
extern int16 GetTemperatureK(int16 sensorSample);
|
||||
|
||||
//
|
||||
// External symbols created by the linker cmd file
|
||||
// DSP28 examples will use these to relocate code from one LOAD location
|
||||
// in Flash to a different RUN location in internal
|
||||
// RAM
|
||||
//
|
||||
extern Uint16 RamfuncsLoadStart;
|
||||
extern Uint16 RamfuncsLoadEnd;
|
||||
extern Uint16 RamfuncsLoadSize;
|
||||
extern Uint16 RamfuncsRunStart;
|
||||
extern Uint16 RamfuncsRunEnd;
|
||||
extern Uint16 RamfuncsRunSize;
|
||||
|
||||
//
|
||||
// External Boot ROM variable definitions
|
||||
//
|
||||
extern Uint16 EmuBMode;
|
||||
extern Uint16 EmuBootPins;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of F2837xD_GLOBALPROTOTYPES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,116 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Gpio_defines.h
|
||||
//
|
||||
// TITLE: F2837xD GPIO support definitions
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_GPIO_DEFINES_H
|
||||
#define F2837xD_GPIO_DEFINES_H
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
//CPU pin masters for GPIO_SelectPinMux()
|
||||
//
|
||||
#define GPIO_MUX_CPU1 0x0
|
||||
#define GPIO_MUX_CPU1CLA 0x1
|
||||
#define GPIO_MUX_CPU2 0x2
|
||||
#define GPIO_MUX_CPU2CLA 0x3
|
||||
|
||||
//
|
||||
//Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3,
|
||||
//QUAL6, and ASYNC) take up two bits and must be in the order specified.
|
||||
//
|
||||
#define GPIO_INPUT 0
|
||||
#define GPIO_OUTPUT 1
|
||||
#define GPIO_PUSHPULL 0
|
||||
#define GPIO_PULLUP (1 << 0)
|
||||
#define GPIO_INVERT (1 << 1)
|
||||
#define GPIO_OPENDRAIN (1 << 2)
|
||||
#define GPIO_SYNC (0x0 << 4)
|
||||
#define GPIO_QUAL3 (0x1 << 4)
|
||||
#define GPIO_QUAL6 (0x2 << 4)
|
||||
#define GPIO_ASYNC (0x3 << 4)
|
||||
|
||||
//
|
||||
//Flags for GPIO_SetupLock().
|
||||
//
|
||||
#define GPIO_UNLOCK 0
|
||||
#define GPIO_LOCK 1
|
||||
|
||||
//
|
||||
//Commands for the CPU2->CPU1 GPIO configuration interrupt handler
|
||||
//
|
||||
#define GPIO_CMD_INIT 1L
|
||||
#define GPIO_CMD_PINMUX 2L
|
||||
#define GPIO_CMD_PINOPTS 3L
|
||||
#define GPIO_CMD_WRITE32 4L
|
||||
#define GPIO_CMD_WRITE16 5L
|
||||
#define GPIO_CMD_READ32 6L
|
||||
#define GPIO_CMD_READ16 7L
|
||||
|
||||
//
|
||||
//Helpful constants for array-based access to GPIO registers
|
||||
//
|
||||
#define GPY_CTRL_OFFSET (0x40/2)
|
||||
#define GPY_DATA_OFFSET (0x8/2)
|
||||
|
||||
#define GPYQSEL (0x2/2)
|
||||
#define GPYMUX (0x6/2)
|
||||
#define GPYDIR (0xA/2)
|
||||
#define GPYPUD (0xC/2)
|
||||
#define GPYINV (0x10/2)
|
||||
#define GPYODR (0x12/2)
|
||||
#define GPYGMUX (0x20/2)
|
||||
#define GPYCSEL (0x28/2)
|
||||
#define GPYLOCK (0x3C/2)
|
||||
#define GPYCR (0x3E/2)
|
||||
|
||||
#define GPYDAT (0x0/2)
|
||||
#define GPYSET (0x2/2)
|
||||
#define GPYCLEAR (0x4/2)
|
||||
#define GPYTOGGLE (0x6/2)
|
||||
|
||||
#endif // end of F2837xD_GPIO_DEFINES_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,184 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_I2c_defines.h
|
||||
//
|
||||
// TITLE: F2837xD I2C Common Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_I2C_DEFINES_H
|
||||
#define F2837xD_I2C_DEFINES_H
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// Error Messages
|
||||
//
|
||||
#define I2C_ERROR 0xFFFF
|
||||
#define I2C_ARB_LOST_ERROR 0x0001
|
||||
#define I2C_NACK_ERROR 0x0002
|
||||
#define I2C_BUS_BUSY_ERROR 0x1000
|
||||
#define I2C_STP_NOT_READY_ERROR 0x5555
|
||||
#define I2C_NO_FLAGS 0xAAAA
|
||||
#define I2C_SUCCESS 0x0000
|
||||
|
||||
//
|
||||
// Clear Status Flags
|
||||
//
|
||||
#define I2C_CLR_AL_BIT 0x0001
|
||||
#define I2C_CLR_NACK_BIT 0x0002
|
||||
#define I2C_CLR_ARDY_BIT 0x0004
|
||||
#define I2C_CLR_RRDY_BIT 0x0008
|
||||
#define I2C_CLR_SCD_BIT 0x0020
|
||||
|
||||
//
|
||||
// Interrupt Source Messages
|
||||
//
|
||||
#define I2C_NO_ISRC 0x0000
|
||||
#define I2C_ARB_ISRC 0x0001
|
||||
#define I2C_NACK_ISRC 0x0002
|
||||
#define I2C_ARDY_ISRC 0x0003
|
||||
#define I2C_RX_ISRC 0x0004
|
||||
#define I2C_TX_ISRC 0x0005
|
||||
#define I2C_SCD_ISRC 0x0006
|
||||
#define I2C_AAS_ISRC 0x0007
|
||||
|
||||
//
|
||||
// I2CMSG structure defines
|
||||
//
|
||||
#define I2C_NO_STOP 0
|
||||
#define I2C_YES_STOP 1
|
||||
#define I2C_RECEIVE 0
|
||||
#define I2C_TRANSMIT 1
|
||||
#define I2C_MAX_BUFFER_SIZE 16
|
||||
|
||||
//
|
||||
// I2C Slave State defines
|
||||
//
|
||||
#define I2C_NOTSLAVE 0
|
||||
#define I2C_ADDR_AS_SLAVE 1
|
||||
#define I2C_ST_MSG_READY 2
|
||||
|
||||
//
|
||||
// I2C Slave Receiver messages defines
|
||||
//
|
||||
#define I2C_SND_MSG1 1
|
||||
#define I2C_SND_MSG2 2
|
||||
|
||||
//
|
||||
// I2C State defines
|
||||
//
|
||||
#define I2C_IDLE 0
|
||||
#define I2C_SLAVE_RECEIVER 1
|
||||
#define I2C_SLAVE_TRANSMITTER 2
|
||||
#define I2C_MASTER_RECEIVER 3
|
||||
#define I2C_MASTER_TRANSMITTER 4
|
||||
|
||||
//
|
||||
// I2C Message Commands for I2CMSG struct
|
||||
//
|
||||
#define I2C_MSGSTAT_INACTIVE 0x0000
|
||||
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
|
||||
#define I2C_MSGSTAT_WRITE_BUSY 0x0011
|
||||
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
|
||||
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
|
||||
#define I2C_MSGSTAT_RESTART 0x0022
|
||||
#define I2C_MSGSTAT_READ_BUSY 0x0023
|
||||
|
||||
//
|
||||
// Generic defines
|
||||
//
|
||||
#define I2C_TRUE 1
|
||||
#define I2C_FALSE 0
|
||||
#define I2C_YES 1
|
||||
#define I2C_NO 0
|
||||
#define I2C_DUMMY_BYTE 0
|
||||
|
||||
|
||||
//
|
||||
// These are the Defines to select I2C pin muxing when calling the functions
|
||||
// I2cAGpioConfig() & I2cBGpioConfig() in F2837xD_I2C.c
|
||||
//
|
||||
#define I2C_A_GPIO0_GPIO1 1 //switch case 1
|
||||
#define I2C_A_GPIO32_GPIO33 2 //switch case 2
|
||||
#define I2C_A_GPIO42_GPIO43 3 //switch case 3
|
||||
#define I2C_A_GPIO91_GPIO92 4 //switch case 4
|
||||
#define I2C_A_GPIO63104_GPIO105 5 //switch case 5
|
||||
|
||||
#define I2C_B_GPIO2_GPIO3 1 //switch case 1
|
||||
#define I2C_B_GPIO134_GPIO35 2 //switch case 2
|
||||
#define I2C_B_GPIO40_GPIO41 3 //switch case 3
|
||||
#define I2C_B_GPIO66_GPIO69 4 //switch case 4
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
|
||||
//
|
||||
// I2C Message Structure
|
||||
//
|
||||
struct I2CMSG {
|
||||
Uint16 MsgStatus; // Word stating what state msg is in:
|
||||
// I2C_MSGCMD_INACTIVE = do not send msg
|
||||
// I2C_MSGCMD_BUSY = msg start has been sent,
|
||||
// awaiting stop
|
||||
// I2C_MSGCMD_SEND_WITHSTOP = command to send
|
||||
// master trans msg complete with a stop bit
|
||||
// I2C_MSGCMD_SEND_NOSTOP = command to send
|
||||
// master trans msg without the stop bit
|
||||
// I2C_MSGCMD_RESTART = command to send a
|
||||
// restart as a master receiver with a
|
||||
// stop bit
|
||||
Uint16 SlaveAddress; // I2C address of slave msg is intended for
|
||||
Uint16 NumOfBytes; // Num of valid bytes in (or to be put
|
||||
// in MsgBuffer)
|
||||
Uint16 MemoryHighAddr; // EEPROM address of data associated with
|
||||
// msg (high byte)
|
||||
Uint16 MemoryLowAddr; // EEPROM address of data associated with
|
||||
// msg (low byte)
|
||||
Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that
|
||||
// MAX_BUFFER_SIZE can be is 16 due
|
||||
// to the FIFO's
|
||||
};
|
||||
|
||||
#endif // end of F2837xD_I2C_DEFINES_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,70 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Ipc_defines.h
|
||||
//
|
||||
// TITLE: F2837xD IPC support definitions
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_IPC_DEFINES_H
|
||||
#define F2837xD_IPC_DEFINES_H
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define C1TOC2_MSG_RAM ((void *)0x3FC00)
|
||||
#define C2TOC1_MSG_RAM ((void *)0x3F800)
|
||||
|
||||
#if defined(CPU1)
|
||||
#define SEND_MSG_RAM C1TOC2_MSG_RAM
|
||||
#define RECV_MSG_RAM C2TOC1_MSG_RAM
|
||||
#elif defined(CPU2)
|
||||
#define SEND_MSG_RAM C2TOC1_MSG_RAM
|
||||
#define RECV_MSG_RAM C1TOC2_MSG_RAM
|
||||
#endif
|
||||
#define MSG_RAM_SIZE 0x400
|
||||
|
||||
//
|
||||
//Used with SendIpcData() and SendIpcCommand() to avoid setting a flag
|
||||
//
|
||||
#define NO_IPC_FLAG 32
|
||||
|
||||
#endif // end of F2837xD_IPC_DEFINES_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,511 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Ipc_drivers.h
|
||||
//
|
||||
// TITLE: Defines and Macros for the IPC Controller
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
//! \addtogroup ipc_driver_api
|
||||
//! @{
|
||||
//
|
||||
|
||||
#ifndef F2837xD_IPC_DRIVERS_H
|
||||
#define F2837xD_IPC_DRIVERS_H
|
||||
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// The following are values that are used to define the maximum size of the
|
||||
// global circular buffer variables g_asIPCCPU1toCPU2Buffers and
|
||||
// g_asIPCCPU2toCPU1Buffers. They are also used in the IpcPut() and IpcGet()
|
||||
// functions. IPC_BUFFER_SIZE and NUM_IPC_INTERRUPTS are user-configurable.
|
||||
//
|
||||
#define IPC_BUFFER_SIZE 4 // # of tIpcMessage messages in
|
||||
// circular buffer
|
||||
// (must be interval of 2)
|
||||
#define NUM_IPC_INTERRUPTS 4 // # of IPC interrupts using circular
|
||||
// buffer
|
||||
// (must be same number on both CPUs
|
||||
#define MAX_BUFFER_INDEX IPC_BUFFER_SIZE - 1
|
||||
|
||||
//
|
||||
// The following are values that can be passed to IPCInitialize()
|
||||
// as the usCPU1IpcInterrupt and usCPU2IpcInterrupt parameters
|
||||
//
|
||||
#define IPC_INT0 0x0001
|
||||
#define IPC_INT1 0x0002
|
||||
#define IPC_INT2 0x0003
|
||||
#define IPC_INT3 0x0004
|
||||
|
||||
//
|
||||
// The following are values that are returned from all of the IPCCtoM command
|
||||
// functions to determine whether the command was successfully sent or not.
|
||||
//
|
||||
#define STATUS_FAIL 0x0001
|
||||
#define STATUS_PASS 0x0000
|
||||
|
||||
//
|
||||
// The following are values that can be passed to IPCReqMemAccess() as
|
||||
// usMaster parameter to determine which processor to give master access to
|
||||
// GSx blocks.
|
||||
//
|
||||
#define IPC_GSX_CPU1_MASTER 0x0001
|
||||
#define IPC_GSX_CPU2_MASTER 0x0000
|
||||
|
||||
//
|
||||
// The following are values that can be passed to all IPC CPU1 to CPU2 or
|
||||
// CPU2 to CPU1 command functions as bBlock parameter to determine whether to
|
||||
// wait/block until a slot in PutBuffer is available if it is full, or to exit
|
||||
// with a failure status.
|
||||
//
|
||||
#define ENABLE_BLOCKING 0x0001
|
||||
#define DISABLE_BLOCKING 0x0000
|
||||
|
||||
//
|
||||
// The following are values that can be passed to IPCCtoMDataRead(),
|
||||
// IPCCCtoMSetBits(),IPCCCtoMSetBits_Protected(), IPCCCtoMClearBits(),
|
||||
// IPCCCtoMClearBits_Protected(), IPCCCtoMDataWrite(),
|
||||
// IPCCtoMDataWrite_Protected()
|
||||
// as usLength parameter to determine whether command applies to 16- or 32-bit
|
||||
// data word.
|
||||
//
|
||||
#define IPC_LENGTH_16_BITS 0x00000001
|
||||
#define IPC_LENGTH_32_BITS 0x00000002
|
||||
|
||||
//
|
||||
// The following are values that can be passed to IPCReqMemAccess() as
|
||||
// ulMask parameter to configure GSxMSEL_REG register for master access to Sx
|
||||
// RAM block.
|
||||
//
|
||||
#define GS0_ACCESS 0x00000001 // Master Access to GS0
|
||||
#define GS1_ACCESS 0x00000002 // Master Access to GS1
|
||||
#define GS2_ACCESS 0x00000004 // Master Access to GS2
|
||||
#define GS3_ACCESS 0x00000008 // Master Access to GS3
|
||||
#define GS4_ACCESS 0x00000010 // Master Access to GS4
|
||||
#define GS5_ACCESS 0x00000020 // Master Access to GS5
|
||||
#define GS6_ACCESS 0x00000040 // Master Access to GS6
|
||||
#define GS7_ACCESS 0x00000080 // Master Access to GS7
|
||||
#define GS8_ACCESS 0x00000100 // Master Access to GS8
|
||||
#define GS9_ACCESS 0x00000200 // Master Access to GS9
|
||||
#define GS10_ACCESS 0x00000400 // Master Access to GS10
|
||||
#define GS11_ACCESS 0x00000800 // Master Access to GS11
|
||||
#define GS12_ACCESS 0x00001000 // Master Access to GS12
|
||||
#define GS13_ACCESS 0x00002000 // Master Access to GS13
|
||||
#define GS14_ACCESS 0x00004000 // Master Access to GS14
|
||||
#define GS15_ACCESS 0x00008000 // Master Access to GS15
|
||||
|
||||
//
|
||||
// The following are values that can be passed to IPCCtoMTaskBusy() as the
|
||||
// ulFlags parameter.
|
||||
// IPC_FLAG17 - IPC_FLAG32 can also be passed to IPCtoMDataRead() and
|
||||
// IPCCtoMReadBlock() as the ulResponseFlag parameter.
|
||||
//
|
||||
#define NO_FLAG 0x00000000 // NO FLAG
|
||||
#define IPC_FLAG0 0x00000001 // IPC FLAG 0
|
||||
#define IPC_FLAG1 0x00000002 // IPC FLAG 1
|
||||
#define IPC_FLAG2 0x00000004 // IPC FLAG 2
|
||||
#define IPC_FLAG3 0x00000008 // IPC FLAG 3
|
||||
#define IPC_FLAG4 0x00000010 // IPC FLAG 4
|
||||
#define IPC_FLAG5 0x00000020 // IPC FLAG 5
|
||||
#define IPC_FLAG6 0x00000040 // IPC FLAG 6
|
||||
#define IPC_FLAG7 0x00000080 // IPC FLAG 7
|
||||
#define IPC_FLAG8 0x00000100 // IPC FLAG 8
|
||||
#define IPC_FLAG9 0x00000200 // IPC FLAG 9
|
||||
#define IPC_FLAG10 0x00000400 // IPC FLAG 10
|
||||
#define IPC_FLAG11 0x00000800 // IPC FLAG 11
|
||||
#define IPC_FLAG12 0x00001000 // IPC FLAG 12
|
||||
#define IPC_FLAG13 0x00002000 // IPC FLAG 13
|
||||
#define IPC_FLAG14 0x00004000 // IPC FLAG 14
|
||||
#define IPC_FLAG15 0x00008000 // IPC FLAG 15
|
||||
#define IPC_FLAG16 0x00010000 // IPC FLAG 16
|
||||
#define IPC_FLAG17 0x00020000 // IPC FLAG 17
|
||||
#define IPC_FLAG18 0x00040000 // IPC FLAG 18
|
||||
#define IPC_FLAG19 0x00080000 // IPC FLAG 19
|
||||
#define IPC_FLAG20 0x00100000 // IPC FLAG 20
|
||||
#define IPC_FLAG21 0x00200000 // IPC FLAG 21
|
||||
#define IPC_FLAG22 0x00400000 // IPC FLAG 22
|
||||
#define IPC_FLAG23 0x00800000 // IPC FLAG 23
|
||||
#define IPC_FLAG24 0x01000000 // IPC FLAG 24
|
||||
#define IPC_FLAG25 0x02000000 // IPC FLAG 25
|
||||
#define IPC_FLAG26 0x04000000 // IPC FLAG 26
|
||||
#define IPC_FLAG27 0x08000000 // IPC FLAG 27
|
||||
#define IPC_FLAG28 0x10000000 // IPC FLAG 28
|
||||
#define IPC_FLAG29 0x20000000 // IPC FLAG 29
|
||||
#define IPC_FLAG30 0x40000000 // IPC FLAG 30
|
||||
#define IPC_FLAG31 0x80000000 // IPC FLAG 31
|
||||
|
||||
//
|
||||
// The following are values that are used by all command functions and passed
|
||||
// between processors in tIpcMessage.ulmessage or in the xTOyIPCCOM register
|
||||
// to determine what command is requested by the sending processor.
|
||||
//
|
||||
#define IPC_SET_BITS_16 0x00000001 // Used for IPC-Lite
|
||||
#define IPC_SET_BITS_32 0x00000002 // Used for IPC-Lite
|
||||
#define IPC_CLEAR_BITS_16 0x00000003 // Used for IPC-Lite
|
||||
#define IPC_CLEAR_BITS_32 0x00000004 // Used for IPC-Lite
|
||||
#define IPC_DATA_WRITE_16 0x00000005 // Used for IPC-Lite
|
||||
#define IPC_DATA_WRITE_32 0x00000006 // Used for IPC-Lite
|
||||
#define IPC_DATA_READ_16 0x00000007 // Used for Boot ROM
|
||||
#define IPC_DATA_READ_32 0x00000008 // Used for Boot ROM
|
||||
#define IPC_DATA_READ 0x00000008
|
||||
#define IPC_SET_BITS_16_PROTECTED 0x00000009 // Used for IPC-Lite
|
||||
#define IPC_SET_BITS_32_PROTECTED 0x0000000A // Used for IPC-Lite
|
||||
#define IPC_CLEAR_BITS_16_PROTECTED 0x0000000B // Used for IPC-Lite
|
||||
#define IPC_CLEAR_BITS_32_PROTECTED 0x0000000C // Used for IPC-Lite
|
||||
#define IPC_DATA_WRITE_16_PROTECTED 0x0000000D // Used for IPC-Lite
|
||||
#define IPC_DATA_WRITE_32_PROTECTED 0x0000000E // Used for IPC-Lite
|
||||
|
||||
//
|
||||
// 0x0000000F and 0x0000010 are reserved by boot ROM
|
||||
//
|
||||
|
||||
#define IPC_BRANCH 0x00000011
|
||||
#define IPC_FUNC_CALL 0x00000012
|
||||
#define IPC_MTOC_EXECUTE_BOOTMODE_CMD 0x00000013
|
||||
|
||||
#define IPC_SET_BITS 0x00010001
|
||||
#define IPC_CLEAR_BITS 0x00010002
|
||||
#define IPC_DATA_WRITE 0x00010003
|
||||
#define IPC_BLOCK_READ 0x00010004
|
||||
#define IPC_BLOCK_WRITE 0x00010005
|
||||
#define IPC_DATA_READ_PROTECTED 0x00010007
|
||||
#define IPC_SET_BITS_PROTECTED 0x00010008
|
||||
#define IPC_CLEAR_BITS_PROTECTED 0x00010009
|
||||
#define IPC_DATA_WRITE_PROTECTED 0x0001000A
|
||||
#define IPC_BLOCK_WRITE_PROTECTED 0x0001000B
|
||||
|
||||
//
|
||||
// The following are values that can be passed into the
|
||||
// IPCBootControlSystem() function in the ulBootMode parameter.
|
||||
//
|
||||
#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013
|
||||
|
||||
//
|
||||
// Below are the values programmed into IPCBOOTMODE register
|
||||
//
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000A
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000B
|
||||
|
||||
//
|
||||
// The following value is used by the
|
||||
// IPCBootControlSystem() function to limit the allowed boot mode values.
|
||||
//
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000C
|
||||
|
||||
//
|
||||
// The following values report on the CPU02 boot ROM status at all times while
|
||||
// the CPU02 is booting, and will reside in IPCBOOTSTS[11:0].
|
||||
//
|
||||
|
||||
//
|
||||
// CPU02 has not filled in a valid value yet
|
||||
//
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000
|
||||
|
||||
//
|
||||
// CPU02 has started to boot, but not completed
|
||||
// the boot process yet
|
||||
//
|
||||
#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001
|
||||
|
||||
//
|
||||
// CPU02 has completed the boot and is ready for
|
||||
// CPU01 TO CPU02 IPC commands
|
||||
//
|
||||
#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002
|
||||
|
||||
//
|
||||
// CPU02 ACKs the command in CPU01 TO CPU01
|
||||
// BOOTMODE register
|
||||
//
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003
|
||||
|
||||
//
|
||||
// CPU02 un-supported command in CPU01 TO CPU01
|
||||
// BOOTMODE register
|
||||
//
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004
|
||||
|
||||
//
|
||||
// CPU2 NAKs the current boot command in
|
||||
// CPU01 TO CPU01 BOOTMODE register
|
||||
//
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005
|
||||
|
||||
//
|
||||
//! A structure that defines an IPC message. These fields are used by the
|
||||
//! IPC drivers to determine handling of data passed between processors.
|
||||
//! Although they have a defined naming scheme, they can also be used
|
||||
//! generically
|
||||
//! to pass 32-bit data words between processors.
|
||||
//
|
||||
typedef struct
|
||||
{
|
||||
//! The command passed between processor systems.
|
||||
uint32_t ulcommand;
|
||||
|
||||
//! The receiving processor address the command is requesting action on.
|
||||
uint32_t uladdress;
|
||||
|
||||
//! A 32-bit variable, the usage of which is determined by ulcommand.
|
||||
//! The most common usage is to pass length requirements
|
||||
//! with the upper 16-bits storing a Response Flag for read commands.
|
||||
uint32_t uldataw1;
|
||||
|
||||
//! A 32-bit variable, the usage of which is determined by ulcommand.
|
||||
//! For block transfers, this variable is generally the address in
|
||||
//! shared memory used to pass data between processors.
|
||||
uint32_t uldataw2;
|
||||
|
||||
} tIpcMessage;
|
||||
|
||||
//
|
||||
//! A structure that defines an IPC control instance. These
|
||||
//! fields are used by the IPC drivers, and normally it is not necessary for
|
||||
//! user software to directly read or write fields in the table.
|
||||
//
|
||||
typedef struct
|
||||
{
|
||||
//! The address of the PutBuffer IPC message (in MSGRAM)
|
||||
tIpcMessage *psPutBuffer;
|
||||
|
||||
//! The IPC INT flag to set when sending messages
|
||||
//! for this IPC controller instance.
|
||||
uint32_t ulPutFlag;
|
||||
|
||||
//! The address of the PutBuffer Write index (in MSGRAM)
|
||||
uint16_t *pusPutWriteIndex;
|
||||
|
||||
//! The address of the PutBuffer Read index (in MSGRAM)
|
||||
uint16_t *pusPutReadIndex;
|
||||
|
||||
//! The address of the GetBuffer IPC message(in MSGRAM)
|
||||
tIpcMessage *psGetBuffer;
|
||||
|
||||
//! The address of the GetBuffer Write Index (in MSGRAM)
|
||||
uint16_t *pusGetWriteIndex;
|
||||
|
||||
//! The address of the GetBuffer Read Index (in MSGRAM)
|
||||
uint16_t *pusGetReadIndex;
|
||||
|
||||
} tIpcController;
|
||||
|
||||
//
|
||||
// A type definition for the IPC function call command.
|
||||
//
|
||||
typedef uint32_t (*tfIpcFuncCall)(uint32_t ulParam);
|
||||
|
||||
//
|
||||
// Prototypes for Circular Buffers
|
||||
//
|
||||
extern tIpcMessage g_asIPCCPU1toCPU2Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE];
|
||||
extern tIpcMessage g_asIPCCPU2toCPU1Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE];
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
extern void IPCInitialize (volatile tIpcController *psController,
|
||||
uint16_t usCPU2IpcInterrupt,
|
||||
uint16_t usCPU1IpcInterrupt);
|
||||
extern uint16_t IpcPut (volatile tIpcController *psController,
|
||||
tIpcMessage *psMessage,
|
||||
uint16_t bBlock);
|
||||
extern uint16_t IpcGet (volatile tIpcController *psController,
|
||||
tIpcMessage *psMessage,
|
||||
uint16_t bBlock);
|
||||
extern uint16_t IPCLtoRDataRead (volatile tIpcController *psController,
|
||||
uint32_t ulAddress, void *pvData,
|
||||
uint16_t usLength, uint16_t bBlock,
|
||||
uint32_t ulResponseFlag);
|
||||
extern uint16_t IPCLtoRDataRead_Protected (volatile tIpcController *psController,
|
||||
uint32_t ulAddress, void *pvData,
|
||||
uint16_t usLength, uint16_t bBlock,
|
||||
uint32_t ulResponseFlag);
|
||||
extern uint16_t IPCLtoRSetBits(volatile tIpcController *psController,
|
||||
uint32_t ulAddress, uint32_t ulMask,
|
||||
uint16_t usLength,uint16_t bBlock);
|
||||
extern uint16_t IPCLtoRSetBits_Protected(volatile tIpcController *psController,
|
||||
uint32_t ulAddress, uint32_t ulMask,
|
||||
uint16_t usLength, uint16_t bBlock);
|
||||
extern uint16_t IPCLtoRClearBits(volatile tIpcController *psController,
|
||||
uint32_t ulAddress, uint32_t ulMask,
|
||||
uint16_t usLength,uint16_t bBlock);
|
||||
extern uint16_t IPCLtoRClearBits_Protected(volatile tIpcController *psController,
|
||||
uint32_t ulAddress, uint32_t ulMask,
|
||||
uint16_t usLength, uint16_t bBlock);
|
||||
extern uint16_t IPCLtoRDataWrite(volatile tIpcController *psController,
|
||||
uint32_t ulAddress, uint32_t ulData,
|
||||
uint16_t usLength, uint16_t bBlock,
|
||||
uint32_t ulResponseFlag);
|
||||
extern uint16_t IPCLtoRDataWrite_Protected(volatile tIpcController *psController,
|
||||
uint32_t ulAddress, uint32_t ulData,
|
||||
uint16_t usLength, uint16_t bBlock,
|
||||
uint32_t ulResponseFlag);
|
||||
extern uint16_t IPCLtoRBlockRead(volatile tIpcController *psController,
|
||||
uint32_t ulAddress, uint32_t ulShareAddress,
|
||||
uint16_t usLength, uint16_t bBlock,
|
||||
uint32_t ulResponseFlag);
|
||||
extern uint16_t IPCLtoRBlockWrite(volatile tIpcController *psController,
|
||||
uint32_t ulAddress, uint32_t ulShareAddress,
|
||||
uint16_t usLength, uint16_t usWordLength,
|
||||
uint16_t bBlock);
|
||||
extern uint16_t IPCLtoRBlockWrite_Protected(volatile tIpcController *psController,
|
||||
uint32_t ulAddress,
|
||||
uint32_t ulShareAddress,
|
||||
uint16_t usLength,
|
||||
uint16_t usWordLength,
|
||||
uint16_t bBlock);
|
||||
extern uint16_t IPCLtoRFunctionCall(volatile tIpcController *psController,
|
||||
uint32_t ulAddress, uint32_t ulParam,
|
||||
uint16_t bBlock);
|
||||
extern uint16_t IPCLtoRSendMessage(volatile tIpcController *psController,
|
||||
uint32_t ulCommand, uint32_t ulAddress,
|
||||
uint32_t ulDataW1, uint32_t ulDataW2,
|
||||
uint16_t bBlock);
|
||||
#if defined (CPU2)
|
||||
uint16_t
|
||||
IPCReqMemAccess (volatile tIpcController *psController, uint32_t ulMask,
|
||||
uint16_t usMaster, uint16_t bBlock);
|
||||
#endif
|
||||
|
||||
extern void IPCRtoLDataWrite(tIpcMessage *psMessage);
|
||||
extern void IPCRtoLDataWrite_Protected(tIpcMessage *psMessage);
|
||||
extern void IPCRtoLDataRead(volatile tIpcController *psController,
|
||||
tIpcMessage *psMessage, uint16_t bBlock);
|
||||
extern void IPCRtoLDataRead_Protected(volatile tIpcController *psController,
|
||||
tIpcMessage *psMessage,uint16_t bBlock);
|
||||
extern void IPCRtoLSetBits(tIpcMessage *psMessage);
|
||||
extern void IPCRtoLSetBits_Protected(tIpcMessage *psMessage);
|
||||
extern void IPCRtoLClearBits(tIpcMessage *psMessage);
|
||||
extern void IPCRtoLClearBits_Protected(tIpcMessage *psMessage);
|
||||
extern void IPCRtoLBlockRead(tIpcMessage *psMessage);
|
||||
extern void IPCRtoLBlockWrite(tIpcMessage *psMessage);
|
||||
extern void IPCRtoLBlockWrite_Protected(tIpcMessage *psMessage);
|
||||
extern void IPCRtoLFunctionCall(tIpcMessage *psMessage);
|
||||
|
||||
//
|
||||
// IPC Lite Driver Prototype Definitions
|
||||
//
|
||||
extern uint16_t IPCLiteLtoRGetResult (void *pvData, uint16_t usLength,
|
||||
uint32_t ulStatusFlag);
|
||||
extern uint16_t IPCLiteLtoRDataRead(uint32_t ulFlag, uint32_t ulAddress,
|
||||
uint16_t usLength, uint32_t ulStatusFlag);
|
||||
extern uint16_t IPCLiteLtoRSetBits(uint32_t ulFlag, uint32_t ulAddress,
|
||||
uint32_t ulMask, uint16_t usLength,
|
||||
uint32_t ulStatusFlag);
|
||||
extern uint16_t IPCLiteLtoRSetBits_Protected (uint32_t ulFlag,
|
||||
uint32_t ulAddress,
|
||||
uint32_t ulMask,
|
||||
uint16_t usLength,
|
||||
uint32_t ulStatusFlag);
|
||||
extern uint16_t IPCLiteLtoRClearBits(uint32_t ulFlag, uint32_t ulAddress,
|
||||
uint32_t ulMask, uint16_t usLength,
|
||||
uint32_t ulStatusFlag);
|
||||
extern uint16_t IPCLiteLtoRClearBits_Protected (uint32_t ulFlag,
|
||||
uint32_t ulAddress,
|
||||
uint32_t ulMask,
|
||||
uint16_t usLength,
|
||||
uint32_t ulStatusFlag);
|
||||
extern uint16_t IPCLiteLtoRDataWrite(uint32_t ulFlag, uint32_t ulAddress,
|
||||
uint32_t ulData, uint16_t usLength,
|
||||
uint32_t ulStatusFlag);
|
||||
extern uint16_t IPCLiteLtoRDataWrite_Protected(uint32_t ulFlag,
|
||||
uint32_t ulAddress,
|
||||
uint32_t ulData,
|
||||
uint16_t usLength,
|
||||
uint32_t ulStatusFlag);
|
||||
extern uint16_t IPCLiteLtoRFunctionCall(uint32_t ulFlag, uint32_t ulAddress,
|
||||
uint32_t ulParam, uint32_t ulStatusFlag);
|
||||
extern uint16_t IPCLiteReqMemAccess (uint32_t ulFlag, uint32_t ulMask,
|
||||
uint16_t ulMaster, uint32_t ulStatusFlag);
|
||||
extern void IPCLiteRtoLDataRead(uint32_t ulFlag, uint32_t ulStatusFlag);
|
||||
extern void IPCLiteRtoLSetBits(uint32_t ulFlag, uint32_t ulStatusFlag);
|
||||
extern void IPCLiteRtoLSetBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag);
|
||||
extern void IPCLiteRtoLClearBits(uint32_t ulFlag, uint32_t ulStatusFlag);
|
||||
extern void IPCLiteRtoLClearBits_Protected (uint32_t ulFlag,
|
||||
uint32_t ulStatusFlag);
|
||||
extern void IPCLiteRtoLDataWrite(uint32_t ulFlag, uint32_t ulStatusFlag);
|
||||
extern void IPCLiteRtoLDataWrite_Protected(uint32_t ulFlag,
|
||||
uint32_t ulStatusFlag);
|
||||
extern void IPCLiteRtoLFunctionCall(uint32_t ulFlag, uint32_t ulStatusFlag);
|
||||
|
||||
//
|
||||
// IPC Utility Driver Prototype Definitions
|
||||
//
|
||||
extern void IPCRtoLFlagAcknowledge (uint32_t ulFlags);
|
||||
extern Uint16 IPCRtoLFlagBusy (uint32_t ulFlags);
|
||||
extern Uint16 IPCLtoRFlagBusy (uint32_t ulFlags);
|
||||
extern void IPCLtoRFlagSet (uint32_t ulFlags);
|
||||
extern void IPCLtoRFlagClear (uint32_t ulFlags);
|
||||
extern uint32_t IPCGetBootStatus (void);
|
||||
extern uint16_t IPCBootCPU2(uint32_t ulBootMode);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
|
||||
#endif // end of F2837xD_IPC_DRIVERS_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,74 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Pie_defines.h
|
||||
//
|
||||
// TITLE: #defines used in PIE examples
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_PIE_DEFINES_H
|
||||
#define F2837xD_PIE_DEFINES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define PIEACK_GROUP1 0x0001
|
||||
#define PIEACK_GROUP2 0x0002
|
||||
#define PIEACK_GROUP3 0x0004
|
||||
#define PIEACK_GROUP4 0x0008
|
||||
#define PIEACK_GROUP5 0x0010
|
||||
#define PIEACK_GROUP6 0x0020
|
||||
#define PIEACK_GROUP7 0x0040
|
||||
#define PIEACK_GROUP8 0x0080
|
||||
#define PIEACK_GROUP9 0x0100
|
||||
#define PIEACK_GROUP10 0x0200
|
||||
#define PIEACK_GROUP11 0x0400
|
||||
#define PIEACK_GROUP12 0x0800
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of F2837xD_PIE_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,350 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_SWPrioritizedIsrLevels.h
|
||||
//
|
||||
// TITLE: F28 Devices Software Prioritized Interrupt Service Routine
|
||||
// Level definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_SW_PRIORITZIED_ISR_H
|
||||
#define F2837xD_SW_PRIORITZIED_ISR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Interrupt Enable Register Allocation For F2837xD Devices:
|
||||
//
|
||||
// Interrupts can be enabled/disabled using the CPU interrupt enable register
|
||||
// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12).
|
||||
//
|
||||
//
|
||||
// Set "Global" Interrupt Priority Level (IER register):
|
||||
//
|
||||
// The user must set the appropriate priority level for each of the CPU
|
||||
// interrupts. This is termed as the "global" priority. The priority level
|
||||
// must be a number between 1 (highest) to 16 (lowest). A value of 0 must
|
||||
// be entered for reserved interrupts or interrupts that are not used. This
|
||||
// will also reduce code size by not including ISR's that are not used.
|
||||
//
|
||||
// Note: The priority levels below are used to calculate the IER register
|
||||
// interrupt masks MINT1 to MINT16.
|
||||
//
|
||||
//
|
||||
// Note: The priority levels shown here may not make sense in a
|
||||
// real application. This is for demonstration purposes only!!!
|
||||
//
|
||||
// The user should change these to values that make sense for
|
||||
// their application.
|
||||
//
|
||||
// 0 = not used
|
||||
// 1 = highest priority
|
||||
// ...
|
||||
// 16 = lowest priority
|
||||
//
|
||||
#define INT1PL 2 // Group1 Interrupts (PIEIER1)
|
||||
#define INT2PL 1 // Group2 Interrupts (PIEIER2)
|
||||
#define INT3PL 4 // Group3 Interrupts (PIEIER3)
|
||||
#define INT4PL 2 // Group4 Interrupts (PIEIER4)
|
||||
#define INT5PL 2 // Group5 Interrupts (PIEIER5)
|
||||
#define INT6PL 3 // Group6 Interrupts (PIEIER6)
|
||||
#define INT7PL 5 // Group7 Interrupts (PIEIER6)
|
||||
#define INT8PL 5 // Group8 Interrupts (PIEIER6)
|
||||
#define INT9PL 3 // Group9 Interrupts (PIEIER9)
|
||||
#define INT10PL 6 // Group10 Interrupts (PIEIER6)
|
||||
#define INT11PL 6 // Group11 Interrupts (PIEIER6)
|
||||
#define INT12PL 8 // Group12 Interrupts (PIEIER6)
|
||||
#define INT13PL 4 // XINT13
|
||||
#define INT14PL 4 // INT14 (TINT2)
|
||||
#define INT15PL 4 // DATALOG
|
||||
#define INT16PL 4 // RTOSINT
|
||||
|
||||
//
|
||||
// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers):
|
||||
//
|
||||
// The user must set the appropriate priority level for each of the PIE
|
||||
// interrupts. This is termed as the "group" priority. The priority level
|
||||
// must be a number between 1 (highest) to 16 (lowest). A value of 0 must
|
||||
// be entered for reserved interrupts or interrupts that are not used. This
|
||||
// will also reduce code size by not including ISR's that are not used:
|
||||
//
|
||||
// Note: The priority levels below are used to calculate the following
|
||||
// PIEIER register interrupt masks:
|
||||
// MG1_1 to MG1_16
|
||||
// MG2_1 to MG2_16
|
||||
// MG3_1 to MG3_16
|
||||
// MG4_1 to MG4_16
|
||||
// MG5_1 to MG5_16
|
||||
// MG6_1 to MG6_16
|
||||
// MG7_1 to MG7_16
|
||||
// MG8_1 to MG8_16
|
||||
// MG9_1 to MG9_16
|
||||
// MG10_1 to MG10_16
|
||||
// MG11_1 to MG11_16
|
||||
// MG12_1 to MG12_16
|
||||
//
|
||||
// Note: The priority levels shown here may not make sense in a
|
||||
// real application. This is for demonstration purposes only!!!
|
||||
//
|
||||
// The user should change these to values that make sense for
|
||||
// their application.
|
||||
//
|
||||
// 0 = not used
|
||||
// 1 = highest priority
|
||||
// ...
|
||||
// 16 = lowest priority
|
||||
//
|
||||
#define G1_1PL 5 // ADCA1_INT
|
||||
#define G1_2PL 3 // ADCB1_INT
|
||||
#define G1_3PL 1 // ADCC1_INT
|
||||
#define G1_4PL 4 // XINT1_INT
|
||||
#define G1_5PL 4 // XINT2_INT
|
||||
#define G1_6PL 1 // ADCD1_INT
|
||||
#define G1_7PL 12 // TIMER0_INT
|
||||
#define G1_8PL 5 // WAKE_INT
|
||||
#define G1_9PL 0 // Reserved
|
||||
#define G1_10PL 0 // Reserved
|
||||
#define G1_11PL 0 // Reserved
|
||||
#define G1_12PL 0 // Reserved
|
||||
#define G1_13PL 8 // IPC1_INT
|
||||
#define G1_14PL 13 // IPC2_INT
|
||||
#define G1_15PL 15 // IPC3_INT
|
||||
#define G1_16PL 9 // IPC4_INT
|
||||
|
||||
#define G2_1PL 13 // EPWM1_TZ_INT
|
||||
#define G2_2PL 1 // EPWM2_TZ_INT
|
||||
#define G2_3PL 1 // EPWM3_TZ_INT
|
||||
#define G2_4PL 9 // EPWM4_TZ_INT
|
||||
#define G2_5PL 3 // EPWM5_TZ_INT
|
||||
#define G2_6PL 13 // EPWM6_TZ_INT
|
||||
#define G2_7PL 9 // EPWM7_TZ_INT
|
||||
#define G2_8PL 13 // EPWM8_TZ_INT
|
||||
#define G2_9PL 15 // EPWM9_TZ_INT
|
||||
#define G2_10PL 11 // EPWM10_TZ_INT
|
||||
#define G2_11PL 7 // EPWM11_TZ_INT
|
||||
#define G2_12PL 10 // EPWM12_TZ_INT
|
||||
#define G2_13PL 0 // Reserved
|
||||
#define G2_14PL 0 // Reserved
|
||||
#define G2_15PL 0 // Reserved
|
||||
#define G2_16PL 0 // Reserved
|
||||
|
||||
#define G3_1PL 5 // EPWM1_INT
|
||||
#define G3_2PL 9 // EPWM2_INT
|
||||
#define G3_3PL 5 // EPWM3_INT
|
||||
#define G3_4PL 2 // EPWM4_INT
|
||||
#define G3_5PL 12 // EPWM5_INT
|
||||
#define G3_6PL 4 // EPWM6_INT
|
||||
#define G3_7PL 2 // EPWM7_INT
|
||||
#define G3_8PL 13 // EPWM8_INT
|
||||
#define G3_9PL 4 // EPWM9_INT
|
||||
#define G3_10PL 12 // EPWM10_INT
|
||||
#define G3_11PL 4 // EPWM11_INT
|
||||
#define G3_12PL 14 // EPWM12_INT
|
||||
#define G3_13PL 0 // Reserved
|
||||
#define G3_14PL 0 // Reserved
|
||||
#define G3_15PL 0 // Reserved
|
||||
#define G3_16PL 0 // Reserved
|
||||
|
||||
#define G4_1PL 3 // ECAP1_INT
|
||||
#define G4_2PL 3 // ECAP2_INT
|
||||
#define G4_3PL 3 // ECAP3_INT
|
||||
#define G4_4PL 6 // ECAP4_INT
|
||||
#define G4_5PL 7 // ECAP5_INT
|
||||
#define G4_6PL 7 // ECAP6_INT
|
||||
#define G4_7PL 0 // Reserved
|
||||
#define G4_8PL 0 // Reserved
|
||||
#define G4_9PL 0 // Reserved
|
||||
#define G4_10PL 0 // Reserved
|
||||
#define G4_11PL 0 // Reserved
|
||||
#define G4_12PL 0 // Reserved
|
||||
#define G4_13PL 0 // Reserved
|
||||
#define G4_14PL 0 // Reserved
|
||||
#define G4_15PL 0 // Reserved
|
||||
#define G4_16PL 0 // Reserved
|
||||
|
||||
#define G5_1PL 6 // EQEP1_INT
|
||||
#define G5_2PL 5 // EQEP2_INT
|
||||
#define G5_3PL 5 // EQEP3_INT
|
||||
#define G5_4PL 1 // Reserved
|
||||
#define G5_5PL 9 // CLB1_INT
|
||||
#define G5_6PL 10 // CLB2_INT
|
||||
#define G5_7PL 15 // CLB3_INT
|
||||
#define G5_8PL 13 // CLB4_INT
|
||||
#define G5_9PL 12 // SD1_INT
|
||||
#define G5_10PL 9 // SD2_INT
|
||||
#define G5_11PL 0 // Reserved
|
||||
#define G5_12PL 0 // Reserved
|
||||
#define G5_13PL 0 // Reserved
|
||||
#define G5_14PL 0 // Reserved
|
||||
#define G5_15PL 0 // Reserved
|
||||
#define G5_16PL 0 // Reserved
|
||||
|
||||
#define G6_1PL 1 // SPIA_RX_INT
|
||||
#define G6_2PL 7 // SPIA_TX_INT
|
||||
#define G6_3PL 3 // SPIB_RX_INT
|
||||
#define G6_4PL 3 // SPIB_TX_INT
|
||||
#define G6_5PL 10 // MCBSPA_RX_INT
|
||||
#define G6_6PL 7 // MCBSPA_TX_INT
|
||||
#define G6_7PL 6 // MCBSPB_RX_INT
|
||||
#define G6_8PL 13 // MCBSPB_TX_INT
|
||||
#define G6_9PL 14 // SPIC_RX_INT
|
||||
#define G6_10PL 3 // SPIC_TX_INT
|
||||
#define G6_11PL 0 // Reserved
|
||||
#define G6_12PL 0 // Reserved
|
||||
#define G6_13PL 0 // Reserved
|
||||
#define G6_14PL 0 // Reserved
|
||||
#define G6_15PL 0 // Reserved
|
||||
#define G6_16PL 0 // Reserved
|
||||
|
||||
#define G7_1PL 1 // DMA_CH1_INT
|
||||
#define G7_2PL 11 // DMA_CH2_INT
|
||||
#define G7_3PL 14 // DMA_CH3_INT
|
||||
#define G7_4PL 3 // DMA_CH4_INT
|
||||
#define G7_5PL 13 // DMA_CH5_INT
|
||||
#define G7_6PL 14 // DMA_CH6_INT
|
||||
#define G7_7PL 0 // Reserved
|
||||
#define G7_8PL 0 // Reserved
|
||||
#define G7_9PL 0 // Reserved
|
||||
#define G7_10PL 0 // Reserved
|
||||
#define G7_11PL 0 // Reserved
|
||||
#define G7_12PL 0 // Reserved
|
||||
#define G7_13PL 0 // Reserved
|
||||
#define G7_14PL 0 // Reserved
|
||||
#define G7_15PL 0 // Reserved
|
||||
#define G7_16PL 0 // Reserved
|
||||
|
||||
#define G8_1PL 14 // I2CA_INT
|
||||
#define G8_2PL 10 // I2CA_FIFO_INT
|
||||
#define G8_3PL 11 // I2CB_INT
|
||||
#define G8_4PL 9 // I2CB_FIFO_INT
|
||||
#define G8_5PL 12 // SCIC_RX_INT
|
||||
#define G8_6PL 2 // SCIC_TX_INT
|
||||
#define G8_7PL 8 // SCID_RX_INT
|
||||
#define G8_8PL 7 // SCID_TX_INT
|
||||
#define G8_9PL 0 // Reserved
|
||||
#define G8_10PL 0 // Reserved
|
||||
#define G8_11PL 0 // Reserved
|
||||
#define G8_12PL 0 // Reserved
|
||||
#define G8_13PL 0 // Reserved
|
||||
#define G8_14PL 0 // Reserved
|
||||
#define G8_15PL 1 // UPPA_INT
|
||||
#define G8_16PL 0 // Reserved
|
||||
|
||||
#define G9_1PL 12 // SCIA_RX_INT
|
||||
#define G9_2PL 14 // SCIA_TX_INT
|
||||
#define G9_3PL 11 // SCIB_RX_INT
|
||||
#define G9_4PL 6 // SCIB_TX_INT
|
||||
#define G9_5PL 14 // CANA0_INT
|
||||
#define G9_6PL 10 // CANA1_INT
|
||||
#define G9_7PL 10 // CANB0_INT
|
||||
#define G9_8PL 5 // CANB1_INT
|
||||
#define G9_9PL 0 // Reserved
|
||||
#define G9_10PL 0 // Reserved
|
||||
#define G9_11PL 0 // Reserved
|
||||
#define G9_12PL 0 // Reserved
|
||||
#define G9_13PL 0 // Reserved
|
||||
#define G9_14PL 0 // Reserved
|
||||
#define G9_15PL 12 // USBA_INT
|
||||
#define G9_16PL 0 // Reserved
|
||||
|
||||
#define G10_1PL 14 // ADCA_EVT_INT
|
||||
#define G10_2PL 3 // ADCA2_INT
|
||||
#define G10_3PL 1 // ADCA3_INT
|
||||
#define G10_4PL 12 // ADCA4_INT
|
||||
#define G10_5PL 5 // ADCB_EVT_INT
|
||||
#define G10_6PL 11 // ADCB2_INT
|
||||
#define G10_7PL 12 // ADCB3_INT
|
||||
#define G10_8PL 13 // ADCB4_INT
|
||||
#define G10_9PL 7 // ADCC_EVT_INT
|
||||
#define G10_10PL 8 // ADCC2_INT
|
||||
#define G10_11PL 4 // ADCC3_INT
|
||||
#define G10_12PL 9 // ADCC4_INT
|
||||
#define G10_13PL 2 // ADCD_EVT_INT
|
||||
#define G10_14PL 10 // ADCD2_INT
|
||||
#define G10_15PL 11 // ADCD3_INT
|
||||
#define G10_16PL 5 // ADCD4_INT
|
||||
|
||||
#define G11_1PL 9 // CLA1_1_INT
|
||||
#define G11_2PL 6 // CLA1_2_INT
|
||||
#define G11_3PL 9 // CLA1_3_INT
|
||||
#define G11_4PL 9 // CLA1_4_INT
|
||||
#define G11_5PL 6 // CLA1_5_INT
|
||||
#define G11_6PL 13 // CLA1_6_INT
|
||||
#define G11_7PL 10 // CLA1_7_INT
|
||||
#define G11_8PL 15 // CLA1_8_INT
|
||||
#define G11_9PL 0 // Reserved
|
||||
#define G11_10PL 0 // Reserved
|
||||
#define G11_11PL 0 // Reserved
|
||||
#define G11_12PL 0 // Reserved
|
||||
#define G11_13PL 0 // Reserved
|
||||
#define G11_14PL 0 // Reserved
|
||||
#define G11_15PL 0 // Reserved
|
||||
#define G11_16PL 0 // Reserved
|
||||
|
||||
#define G12_1PL 3 // XINT3_INT
|
||||
#define G12_2PL 6 // XINT4_INT
|
||||
#define G12_3PL 10 // XINT5_INT
|
||||
#define G12_4PL 5 // Reserved
|
||||
#define G12_5PL 2 // FMC_INT
|
||||
#define G12_6PL 11 // VCU_INT
|
||||
#define G12_7PL 14 // FPU_OVERFLOW_ISR
|
||||
#define G12_8PL 14 // FPU_UNDERFLOW_ISR
|
||||
#define G12_9PL 6 // EMIF_ERROR_ISR
|
||||
#define G12_10PL 5 // RAM_CORRECTABLE_ERROR_ISR
|
||||
#define G12_11PL 4 // FLASH_CORRECTABLE_ERROR_ISR
|
||||
#define G12_12PL 12 // RAM_ACCESS_VIOLATION_INT
|
||||
#define G12_13PL 8 // SYS_PLL_SLIP_INT
|
||||
#define G12_14PL 2 // AUX_PLL_SLIP_INT
|
||||
#define G12_15PL 12 // CLA_UNDERFLOW_INT
|
||||
#define G12_16PL 2 // CLA_OVERFLOW_INT
|
||||
|
||||
//
|
||||
// Include the header file with software interrupt prioritization logic
|
||||
//
|
||||
#include "sw_interrupt_prioritization_logic.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // eof
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,63 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_SysCtrl_defines.h
|
||||
//
|
||||
// TITLE: F2837xD LPM support definitions
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_SYSCTRL_DEFINES_H
|
||||
#define F2837xD_SYSCTRL_DEFINES_H
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define LPM_IDLE 0x0
|
||||
#define LPM_STANDBY 0x1
|
||||
#define LPM_HALT 0x2
|
||||
#define LPM_HIB 0x3
|
||||
|
||||
//
|
||||
//Key value used for write access to the flash pump semaphore register
|
||||
//
|
||||
#define IPC_PUMP_KEY 0x5a5a0000
|
||||
|
||||
#endif // end of F2837xD_SYSCTRL_DEFINES_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,80 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: systick.h
|
||||
//
|
||||
// TITLE: Stellaris style wrapper driver for C28x CPU Timer 0.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef __SYSTICK_H__
|
||||
#define __SYSTICK_H__
|
||||
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
extern void SysTickInit(void);
|
||||
extern void SysTickEnable(void);
|
||||
extern void SysTickDisable(void);
|
||||
extern void SysTickIntRegister(void (*pfnHandler)(void));
|
||||
extern void SysTickIntUnregister(void);
|
||||
extern void SysTickIntEnable(void);
|
||||
extern void SysTickIntDisable(void);
|
||||
extern void SysTickPeriodSet(unsigned long ulPeriod);
|
||||
extern unsigned long SysTickPeriodGet(void);
|
||||
extern unsigned long SysTickValueGet(void);
|
||||
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __SYSTICK_H__
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,86 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Upp_defines.h
|
||||
//
|
||||
// TITLE: #defines used in Upp examples
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_UPP_DEFINES_H
|
||||
#define F2837xD_UPP_DEFINES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define uPP_TX_MSGRAM_ADDR 0x6C00
|
||||
#define uPP_TX_MSGRAM_SIZE 512
|
||||
|
||||
#define uPP_RX_MSGRAM_ADDR 0x6E00
|
||||
#define uPP_RX_MSGRAM_SIZE 512
|
||||
|
||||
#define uPP_RX_MODE 0
|
||||
#define uPP_TX_MODE 1
|
||||
|
||||
#define uPP_SDR 0
|
||||
#define uPP_DDR 1
|
||||
|
||||
#define uPP_TX_SIZE_64B 0
|
||||
#define uPP_TX_SIZE_128B 1
|
||||
#define uPP_TX_SIZE_256B 3
|
||||
|
||||
#define uPP_RX_SIZE_64B 0
|
||||
#define uPP_RX_SIZE_128B 1
|
||||
#define uPP_RX_SIZE_256B 3
|
||||
|
||||
#define uPP_INT_EOWI 0x8
|
||||
#define uPP_INT_EOLI 0x10
|
||||
#define uPP_INT_EOWQ 0x800
|
||||
#define uPP_INT_EOLQ 0x1000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of F2837xD_UPP_DEFINES_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,138 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Cputimers.h
|
||||
//
|
||||
// TITLE: F2837xD Device CPUTIMERS Register Definitions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_CPUTIMERVARS_H
|
||||
#define F2837xD_CPUTIMERVARS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
struct CPUTIMER_VARS {
|
||||
volatile struct CPUTIMER_REGS *RegsAddr;
|
||||
Uint32 InterruptCount;
|
||||
float CPUFreqInMHz;
|
||||
float PeriodInUSec;
|
||||
};
|
||||
|
||||
extern struct CPUTIMER_VARS CpuTimer0;
|
||||
extern struct CPUTIMER_VARS CpuTimer1;
|
||||
extern struct CPUTIMER_VARS CpuTimer2;
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// Start Timer:
|
||||
//
|
||||
#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0
|
||||
|
||||
//
|
||||
// Stop Timer:
|
||||
//
|
||||
#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1
|
||||
|
||||
//
|
||||
// Reload Timer With period Value:
|
||||
//
|
||||
#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1
|
||||
|
||||
//
|
||||
// Read 32-Bit Timer Value:
|
||||
//
|
||||
#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all
|
||||
|
||||
//
|
||||
// Read 32-Bit Period Value:
|
||||
//
|
||||
#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all
|
||||
|
||||
//
|
||||
// Start Timer:
|
||||
//
|
||||
#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
|
||||
#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
|
||||
|
||||
//
|
||||
// Stop Timer:
|
||||
//
|
||||
#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
|
||||
#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
|
||||
|
||||
//
|
||||
// Reload Timer With period Value:
|
||||
//
|
||||
#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
|
||||
#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
|
||||
|
||||
//
|
||||
// Read 32-Bit Timer Value:
|
||||
//
|
||||
#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all
|
||||
#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all
|
||||
|
||||
//
|
||||
// Read 32-Bit Period Value:
|
||||
//
|
||||
#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all
|
||||
#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void InitCpuTimers(void);
|
||||
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
|
||||
#endif // end of F2837xD_CPUTIMERVARS_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,216 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_defaultisr.h
|
||||
//
|
||||
// TITLE: F2837xD Device Default Interrupt Service Routines Definitions
|
||||
//
|
||||
//###########################################################################
|
||||
// $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_DEFAULT_ISR_H
|
||||
#define F2837xD_DEFAULT_ISR_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Default Interrupt Service Routine Declarations:
|
||||
// The following function prototypes are for the
|
||||
// default ISR routines used with the default PIE vector table.
|
||||
// This default vector table is found in the F2837xD_pievect.h
|
||||
// file.
|
||||
//
|
||||
interrupt void TIMER1_ISR(void); // CPU Timer 1 Interrupt
|
||||
interrupt void TIMER2_ISR(void); // CPU Timer 2 Interrupt
|
||||
interrupt void DATALOG_ISR(void); // Datalogging Interrupt
|
||||
interrupt void RTOS_ISR(void); // RTOS Interrupt
|
||||
interrupt void EMU_ISR(void); // Emulation Interrupt
|
||||
interrupt void NMI_ISR(void); // Non-Maskable Interrupt
|
||||
interrupt void ILLEGAL_ISR(void); // Illegal Operation Trap
|
||||
interrupt void USER1_ISR(void); // User Defined Trap 1
|
||||
interrupt void USER2_ISR(void); // User Defined Trap 2
|
||||
interrupt void USER3_ISR(void); // User Defined Trap 3
|
||||
interrupt void USER4_ISR(void); // User Defined Trap 4
|
||||
interrupt void USER5_ISR(void); // User Defined Trap 5
|
||||
interrupt void USER6_ISR(void); // User Defined Trap 6
|
||||
interrupt void USER7_ISR(void); // User Defined Trap 7
|
||||
interrupt void USER8_ISR(void); // User Defined Trap 8
|
||||
interrupt void USER9_ISR(void); // User Defined Trap 9
|
||||
interrupt void USER10_ISR(void); // User Defined Trap 10
|
||||
interrupt void USER11_ISR(void); // User Defined Trap 11
|
||||
interrupt void USER12_ISR(void); // User Defined Trap 12
|
||||
interrupt void ADCA1_ISR(void); // 1.1 - ADCA Interrupt 1
|
||||
interrupt void ADCB1_ISR(void); // 1.2 - ADCB Interrupt 1
|
||||
interrupt void ADCC1_ISR(void); // 1.3 - ADCC Interrupt 1
|
||||
interrupt void XINT1_ISR(void); // 1.4 - XINT1 Interrupt
|
||||
interrupt void XINT2_ISR(void); // 1.5 - XINT2 Interrupt
|
||||
interrupt void ADCD1_ISR(void); // 1.6 - ADCD Interrupt 1
|
||||
interrupt void TIMER0_ISR(void); // 1.7 - Timer 0 Interrupt
|
||||
interrupt void WAKE_ISR(void); // 1.8 - Standby and Halt Wakeup Interrupt
|
||||
interrupt void EPWM1_TZ_ISR(void); // 2.1 - ePWM1 Trip Zone Interrupt
|
||||
interrupt void EPWM2_TZ_ISR(void); // 2.2 - ePWM2 Trip Zone Interrupt
|
||||
interrupt void EPWM3_TZ_ISR(void); // 2.3 - ePWM3 Trip Zone Interrupt
|
||||
interrupt void EPWM4_TZ_ISR(void); // 2.4 - ePWM4 Trip Zone Interrupt
|
||||
interrupt void EPWM5_TZ_ISR(void); // 2.5 - ePWM5 Trip Zone Interrupt
|
||||
interrupt void EPWM6_TZ_ISR(void); // 2.6 - ePWM6 Trip Zone Interrupt
|
||||
interrupt void EPWM7_TZ_ISR(void); // 2.7 - ePWM7 Trip Zone Interrupt
|
||||
interrupt void EPWM8_TZ_ISR(void); // 2.8 - ePWM8 Trip Zone Interrupt
|
||||
interrupt void EPWM1_ISR(void); // 3.1 - ePWM1 Interrupt
|
||||
interrupt void EPWM2_ISR(void); // 3.2 - ePWM2 Interrupt
|
||||
interrupt void EPWM3_ISR(void); // 3.3 - ePWM3 Interrupt
|
||||
interrupt void EPWM4_ISR(void); // 3.4 - ePWM4 Interrupt
|
||||
interrupt void EPWM5_ISR(void); // 3.5 - ePWM5 Interrupt
|
||||
interrupt void EPWM6_ISR(void); // 3.6 - ePWM6 Interrupt
|
||||
interrupt void EPWM7_ISR(void); // 3.7 - ePWM7 Interrupt
|
||||
interrupt void EPWM8_ISR(void); // 3.8 - ePWM8 Interrupt
|
||||
interrupt void ECAP1_ISR(void); // 4.1 - eCAP1 Interrupt
|
||||
interrupt void ECAP2_ISR(void); // 4.2 - eCAP2 Interrupt
|
||||
interrupt void ECAP3_ISR(void); // 4.3 - eCAP3 Interrupt
|
||||
interrupt void ECAP4_ISR(void); // 4.4 - eCAP4 Interrupt
|
||||
interrupt void ECAP5_ISR(void); // 4.5 - eCAP5 Interrupt
|
||||
interrupt void ECAP6_ISR(void); // 4.6 - eCAP6 Interrupt
|
||||
interrupt void EQEP1_ISR(void); // 5.1 - eQEP1 Interrupt
|
||||
interrupt void EQEP2_ISR(void); // 5.2 - eQEP2 Interrupt
|
||||
interrupt void EQEP3_ISR(void); // 5.3 - eQEP3 Interrupt
|
||||
interrupt void SPIA_RX_ISR(void); // 6.1 - SPIA Receive Interrupt
|
||||
interrupt void SPIA_TX_ISR(void); // 6.2 - SPIA Transmit Interrupt
|
||||
interrupt void SPIB_RX_ISR(void); // 6.3 - SPIB Receive Interrupt
|
||||
interrupt void SPIB_TX_ISR(void); // 6.4 - SPIB Transmit Interrupt
|
||||
interrupt void MCBSPA_RX_ISR(void); // 6.5 - McBSPA Receive Interrupt
|
||||
interrupt void MCBSPA_TX_ISR(void); // 6.6 - McBSPA Transmit Interrupt
|
||||
interrupt void MCBSPB_RX_ISR(void); // 6.7 - McBSPB Receive Interrupt
|
||||
interrupt void MCBSPB_TX_ISR(void); // 6.8 - McBSPB Transmit Interrupt
|
||||
interrupt void DMA_CH1_ISR(void); // 7.1 - DMA Channel 1 Interrupt
|
||||
interrupt void DMA_CH2_ISR(void); // 7.2 - DMA Channel 2 Interrupt
|
||||
interrupt void DMA_CH3_ISR(void); // 7.3 - DMA Channel 3 Interrupt
|
||||
interrupt void DMA_CH4_ISR(void); // 7.4 - DMA Channel 4 Interrupt
|
||||
interrupt void DMA_CH5_ISR(void); // 7.5 - DMA Channel 5 Interrupt
|
||||
interrupt void DMA_CH6_ISR(void); // 7.6 - DMA Channel 6 Interrupt
|
||||
interrupt void I2CA_ISR(void); // 8.1 - I2CA Interrupt 1
|
||||
interrupt void I2CA_FIFO_ISR(void); // 8.2 - I2CA Interrupt 2
|
||||
interrupt void I2CB_ISR(void); // 8.3 - I2CB Interrupt 1
|
||||
interrupt void I2CB_FIFO_ISR(void); // 8.4 - I2CB Interrupt 2
|
||||
interrupt void SCIC_RX_ISR(void); // 8.5 - SCIC Receive Interrupt
|
||||
interrupt void SCIC_TX_ISR(void); // 8.6 - SCIC Transmit Interrupt
|
||||
interrupt void SCID_RX_ISR(void); // 8.7 - SCID Receive Interrupt
|
||||
interrupt void SCID_TX_ISR(void); // 8.8 - SCID Transmit Interrupt
|
||||
interrupt void SCIA_RX_ISR(void); // 9.1 - SCIA Receive Interrupt
|
||||
interrupt void SCIA_TX_ISR(void); // 9.2 - SCIA Transmit Interrupt
|
||||
interrupt void SCIB_RX_ISR(void); // 9.3 - SCIB Receive Interrupt
|
||||
interrupt void SCIB_TX_ISR(void); // 9.4 - SCIB Transmit Interrupt
|
||||
interrupt void CANA0_ISR(void); // 9.5 - CANA Interrupt 0
|
||||
interrupt void CANA1_ISR(void); // 9.6 - CANA Interrupt 1
|
||||
interrupt void CANB0_ISR(void); // 9.7 - CANB Interrupt 0
|
||||
interrupt void CANB1_ISR(void); // 9.8 - CANB Interrupt 1
|
||||
interrupt void ADCA_EVT_ISR(void); // 10.1 - ADCA Event Interrupt
|
||||
interrupt void ADCA2_ISR(void); // 10.2 - ADCA Interrupt 2
|
||||
interrupt void ADCA3_ISR(void); // 10.3 - ADCA Interrupt 3
|
||||
interrupt void ADCA4_ISR(void); // 10.4 - ADCA Interrupt 4
|
||||
interrupt void ADCB_EVT_ISR(void); // 10.5 - ADCB Event Interrupt
|
||||
interrupt void ADCB2_ISR(void); // 10.6 - ADCB Interrupt 2
|
||||
interrupt void ADCB3_ISR(void); // 10.7 - ADCB Interrupt 3
|
||||
interrupt void ADCB4_ISR(void); // 10.8 - ADCB Interrupt 4
|
||||
interrupt void CLA1_1_ISR(void); // 11.1 - CLA1 Interrupt 1
|
||||
interrupt void CLA1_2_ISR(void); // 11.2 - CLA1 Interrupt 2
|
||||
interrupt void CLA1_3_ISR(void); // 11.3 - CLA1 Interrupt 3
|
||||
interrupt void CLA1_4_ISR(void); // 11.4 - CLA1 Interrupt 4
|
||||
interrupt void CLA1_5_ISR(void); // 11.5 - CLA1 Interrupt 5
|
||||
interrupt void CLA1_6_ISR(void); // 11.6 - CLA1 Interrupt 6
|
||||
interrupt void CLA1_7_ISR(void); // 11.7 - CLA1 Interrupt 7
|
||||
interrupt void CLA1_8_ISR(void); // 11.8 - CLA1 Interrupt 8
|
||||
interrupt void XINT3_ISR(void); // 12.1 - XINT3 Interrupt
|
||||
interrupt void XINT4_ISR(void); // 12.2 - XINT4 Interrupt
|
||||
interrupt void XINT5_ISR(void); // 12.3 - XINT5 Interrupt
|
||||
interrupt void VCU_ISR(void); // 12.6 - VCU Interrupt
|
||||
interrupt void FPU_OVERFLOW_ISR(void); // 12.7 - FPU Overflow Interrupt
|
||||
interrupt void FPU_UNDERFLOW_ISR(void); // 12.8 - FPU Underflow Interrupt
|
||||
interrupt void IPC0_ISR(void); // 1.13 - IPC Interrupt 0
|
||||
interrupt void IPC1_ISR(void); // 1.14 - IPC Interrupt 1
|
||||
interrupt void IPC2_ISR(void); // 1.15 - IPC Interrupt 2
|
||||
interrupt void IPC3_ISR(void); // 1.16 - IPC Interrupt 3
|
||||
interrupt void EPWM9_TZ_ISR(void); // 2.9 - ePWM9 Trip Zone Interrupt
|
||||
interrupt void EPWM10_TZ_ISR(void); // 2.10 - ePWM10 Trip Zone Interrupt
|
||||
interrupt void EPWM11_TZ_ISR(void); // 2.11 - ePWM11 Trip Zone Interrupt
|
||||
interrupt void EPWM12_TZ_ISR(void); // 2.12 - ePWM12 Trip Zone Interrupt
|
||||
interrupt void EPWM9_ISR(void); // 3.9 - ePWM9 Interrupt
|
||||
interrupt void EPWM10_ISR(void); // 3.10 - ePWM10 Interrupt
|
||||
interrupt void EPWM11_ISR(void); // 3.11 - ePWM11 Interrupt
|
||||
interrupt void EPWM12_ISR(void); // 3.12 - ePWM12 Interrupt
|
||||
interrupt void SD1_ISR(void); // 5.9 - SD1 Interrupt
|
||||
interrupt void SD2_ISR(void); // 5.10 - SD2 Interrupt
|
||||
interrupt void SPIC_RX_ISR(void); // 6.9 - SPIC Receive Interrupt
|
||||
interrupt void SPIC_TX_ISR(void); // 6.10 - SPIC Transmit Interrupt
|
||||
interrupt void UPPA_ISR(void); // 8.15 - uPPA Interrupt
|
||||
interrupt void USBA_ISR(void); // 9.15 - USBA Interrupt
|
||||
interrupt void ADCC_EVT_ISR(void); // 10.9 - ADCC Event Interrupt
|
||||
interrupt void ADCC2_ISR(void); // 10.10 - ADCC Interrupt 2
|
||||
interrupt void ADCC3_ISR(void); // 10.11 - ADCC Interrupt 3
|
||||
interrupt void ADCC4_ISR(void); // 10.12 - ADCC Interrupt 4
|
||||
interrupt void ADCD_EVT_ISR(void); // 10.13 - ADCD Event Interrupt
|
||||
interrupt void ADCD2_ISR(void); // 10.14 - ADCD Interrupt 2
|
||||
interrupt void ADCD3_ISR(void); // 10.15 - ADCD Interrupt 3
|
||||
interrupt void ADCD4_ISR(void); // 10.16 - ADCD Interrupt 4
|
||||
interrupt void EMIF_ERROR_ISR(void); // 12.9 - EMIF Error Interrupt
|
||||
interrupt void RAM_CORRECTABLE_ERROR_ISR(void); // 12.10 - RAM Correctable
|
||||
// Error Interrupt
|
||||
interrupt void FLASH_CORRECTABLE_ERROR_ISR(void); // 12.11 - Flash Correctable
|
||||
// Error Interrupt
|
||||
interrupt void RAM_ACCESS_VIOLATION_ISR(void); // 12.12 - RAM Access
|
||||
// Violation Interrupt
|
||||
interrupt void SYS_PLL_SLIP_ISR(void); // 12.13 - System PLL Slip
|
||||
// Interrupt
|
||||
interrupt void AUX_PLL_SLIP_ISR(void); // 12.14 - Auxiliary PLL
|
||||
// Slip Interrupt
|
||||
interrupt void CLA_OVERFLOW_ISR(void); // 12.15 - CLA Overflow
|
||||
// Interrupt
|
||||
interrupt void CLA_UNDERFLOW_ISR(void); // 12.16 - CLA Underflow
|
||||
// Interrupt
|
||||
|
||||
//
|
||||
// Catch-all for PIE Reserved Locations for testing purposes:
|
||||
//
|
||||
interrupt void PIE_RESERVED_ISR(void); // Reserved ISR
|
||||
interrupt void EMPTY_ISR(void); // Only does a return
|
||||
interrupt void NOTUSED_ISR(void); // Unused ISR
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // end of F2837xD_PIEVECT_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,70 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_sci_io.h
|
||||
//
|
||||
// TITLE: Prototypes for SCI redirection to STDIO
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_SCI_IO_H
|
||||
#define F2837xD_SCI_IO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
extern int SCI_open(const char * path, unsigned flags, int llv_fd);
|
||||
extern int SCI_close(int dev_fd);
|
||||
extern int SCI_read(int dev_fd, char * buf, unsigned count);
|
||||
extern int SCI_write(int dev_fd, char * buf, unsigned count);
|
||||
extern off_t SCI_lseek(int dev_fd, off_t offset, int origin);
|
||||
extern int SCI_unlink(const char * path);
|
||||
extern int SCI_rename(const char * old_name, const char * new_name);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,530 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_sdfm_drivers.h
|
||||
//
|
||||
// TITLE: Defines and Macros for the SDFM driver Controller
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_SDFM_DRIVERS_H
|
||||
#define F2837xD_SDFM_DRIVERS_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
|
||||
//
|
||||
// This is used to select either SDFM module 1 & SDFM module 2
|
||||
//
|
||||
#define SDFM1 1 //Can be used to select SDFM module 1
|
||||
#define SDFM2 2 //Can be used to select SDFM module 2
|
||||
|
||||
//
|
||||
// Max OSR values of different modules
|
||||
//
|
||||
#define COMPARATOR_MAX_OSR 32 //Max OSR for comparator
|
||||
#define DATA_FILTER_MAX_OSR 256 //Max OSR for Data filter
|
||||
|
||||
//
|
||||
// Different Input Control modes
|
||||
// These values can be passed as argument to Sdfm_configureInputCtrl()
|
||||
//
|
||||
#define MODE_0 0 //Used to select Mode0 :
|
||||
//Modulator clock rate = Modulator data rate
|
||||
#define MODE_1 1 //Used to select MODE1 :
|
||||
//Modulator clock rate = (Modulator data rate / 2)
|
||||
#define MODE_2 2 //Used to select MODE2 :
|
||||
//Manchester encoded data
|
||||
//(Modulator clock is encoded into data)
|
||||
#define MODE_3 3 //Used to select MODE3 :
|
||||
//Modulator clock rate = (2 x Modulator data rate)
|
||||
|
||||
//
|
||||
// The following are values that can be passed to following functions
|
||||
//
|
||||
// (1) Sdfm_configureInputCtrl()
|
||||
// (2) Sdfm_configureComparator()
|
||||
// (3) Sdfm_configureData_filter()
|
||||
// (4) Sdfm_configureInterrupt()
|
||||
//
|
||||
#define FILTER1 0x01 //Used to select filter1 for comparator or Data filter
|
||||
#define FILTER2 0x02 //Used to select filter2 for comparator or Data filter
|
||||
#define FILTER3 0x04 //Used to select filter3 for comparator or Data filter
|
||||
#define FILTER4 0x08 //Used to select filter4 for comparator or Data filter
|
||||
|
||||
//
|
||||
// The following are values that can be passed to Sdfm_configureData_filter()
|
||||
//
|
||||
#define FILTER_DISABLE 0 //Used to disable filter
|
||||
#define FILTER_ENABLE 1 //Used to enable filter
|
||||
|
||||
//
|
||||
// The following are values that can be passed to following functions
|
||||
//
|
||||
// (1) Sdfm_configureComparator()
|
||||
// (2) Sdfm_configureData_filter()
|
||||
//
|
||||
#define SINCFAST 0x00 //Used to select Sincfast filter type for comparator
|
||||
//or Data filter
|
||||
#define SINC1 0x01 //Used to select Sinc1 filter type for comparator
|
||||
//or Data filter
|
||||
#define SINC2 0x02 //Used to select Sinc2 filter type for comparator
|
||||
//or Data filter
|
||||
#define SINC3 0x03 //Used to select Sinc3 filter type for comparator
|
||||
//or Data filter
|
||||
|
||||
//
|
||||
// Enable / Disable High-level threshold interrupt for Comparator filter output
|
||||
// These values can be passed as argument to Sdfm_configureInterrupt()
|
||||
//
|
||||
#define IEH_DISABLE 0 //Used to disable over value interrupt to CPU
|
||||
#define IEH_ENABLE 1 //Used to enable over value interrupt to CPU
|
||||
|
||||
//
|
||||
// Enable / Disable Low-level threshold interrupt for Comparator filter output
|
||||
// These values can be passed as argument to Sdfm_configureInterrupt()
|
||||
//
|
||||
#define IEL_DISABLE 0 //Used to disable under value interrupt to CPU
|
||||
#define IEL_ENABLE 1 //Used to enable under value interrupt to CPU
|
||||
|
||||
//
|
||||
//Enable / Disable modulator failure interrupt
|
||||
// These values can be passed as argument to Sdfm_configureInterrupt()
|
||||
//
|
||||
#define MFIE_DISABLE 0 //Used to disable modulator failure interrupt to CPU
|
||||
#define MFIE_ENABLE 1 //Used to enable modulator failure interrupt to CPU
|
||||
|
||||
//
|
||||
// Enable / Disable Acknowledge flag
|
||||
// These values can be passed as argument to Sdfm_configureInterrupt()
|
||||
//
|
||||
#define AE_DISABLE 0 //Used to disable new filter data acknowledge
|
||||
//interrupt to CPU
|
||||
#define AE_ENABLE 1 //Used to enable new filter data acknowledge
|
||||
//interrupt to CPU
|
||||
|
||||
//
|
||||
// Sinc Filter Reset enable / disable for External Reset from PWM Compare
|
||||
// output
|
||||
// This following value can be passed to Sdfm_configureExternalreset()
|
||||
//
|
||||
#define FILTER_1_EXT_RESET_DISABLE 0
|
||||
#define FILTER_1_EXT_RESET_ENABLE 1
|
||||
#define FILTER_2_EXT_RESET_DISABLE 0
|
||||
#define FILTER_2_EXT_RESET_ENABLE 1
|
||||
#define FILTER_3_EXT_RESET_DISABLE 0
|
||||
#define FILTER_3_EXT_RESET_ENABLE 1
|
||||
#define FILTER_4_EXT_RESET_DISABLE 0
|
||||
#define FILTER_4_EXT_RESET_ENABLE 1
|
||||
|
||||
//
|
||||
// Filter output data can be represented in 16 bit (or) 32 bit format
|
||||
// This value can be passed to Sdfm_configureData_filter()
|
||||
//
|
||||
#define DATA_16_BIT 0 //Data stored in 16b 2's complement
|
||||
#define DATA_32_BIT 1 //Data stored in 32b 2's complement
|
||||
|
||||
//
|
||||
// Macro to read the SDFM1 filter data in 16 bit format
|
||||
//
|
||||
#define SDFM1_READ_FILTER1_DATA_16BIT (*(volatile int16 *)((Uint16)0x5E17))
|
||||
#define SDFM1_READ_FILTER2_DATA_16BIT (*(volatile int16 *)((Uint16)0x5E27))
|
||||
#define SDFM1_READ_FILTER3_DATA_16BIT (*(volatile int16 *)((Uint16)0x5E37))
|
||||
#define SDFM1_READ_FILTER4_DATA_16BIT (*(volatile int16 *)((Uint16)0x5E47))
|
||||
|
||||
//
|
||||
// Macro to read the SDFM1 filter data in 32 bit format
|
||||
//
|
||||
#define SDFM1_READ_FILTER1_DATA_32BIT (*(volatile int32 *)((Uint16)0x5E16))
|
||||
#define SDFM1_READ_FILTER2_DATA_32BIT (*(volatile int32 *)((Uint16)0x5E26))
|
||||
#define SDFM1_READ_FILTER3_DATA_32BIT (*(volatile int32 *)((Uint16)0x5E36))
|
||||
#define SDFM1_READ_FILTER4_DATA_32BIT (*(volatile int32 *)((Uint16)0x5E46))
|
||||
|
||||
//
|
||||
// Macro to read the SDFM2 filter data in 16 bit format
|
||||
//
|
||||
#define SDFM2_READ_FILTER1_DATA_16BIT (*(volatile int16 *)((Uint16)0x5E97))
|
||||
#define SDFM2_READ_FILTER2_DATA_16BIT (*(volatile int16 *)((Uint16)0x5EA7))
|
||||
#define SDFM2_READ_FILTER3_DATA_16BIT (*(volatile int16 *)((Uint16)0x5EB7))
|
||||
#define SDFM2_READ_FILTER4_DATA_16BIT (*(volatile int16 *)((Uint16)0x5EC7))
|
||||
|
||||
//
|
||||
// Macro to read the SDFM2 filter data in 32 bit format
|
||||
//
|
||||
#define SDFM2_READ_FILTER1_DATA_32BIT (*(volatile int32 *)((uint16_t)0x5E96))
|
||||
#define SDFM2_READ_FILTER2_DATA_32BIT (*(volatile int32 *)((uint16_t)0x5EA6))
|
||||
#define SDFM2_READ_FILTER3_DATA_32BIT (*(volatile int32 *)((uint16_t)0x5EB6))
|
||||
#define SDFM2_READ_FILTER4_DATA_32BIT (*(volatile int32 *)((uint16_t)0x5EC6))
|
||||
|
||||
//
|
||||
// The following are defines for different OSR values
|
||||
//
|
||||
#define OSR_1 0
|
||||
#define OSR_2 1
|
||||
#define OSR_3 2
|
||||
#define OSR_4 3
|
||||
#define OSR_5 4
|
||||
#define OSR_6 5
|
||||
#define OSR_7 6
|
||||
#define OSR_8 7
|
||||
#define OSR_9 8
|
||||
#define OSR_10 9
|
||||
#define OSR_11 10
|
||||
#define OSR_12 11
|
||||
#define OSR_13 12
|
||||
#define OSR_14 13
|
||||
#define OSR_15 14
|
||||
#define OSR_16 15
|
||||
#define OSR_17 16
|
||||
#define OSR_18 17
|
||||
#define OSR_19 18
|
||||
#define OSR_20 19
|
||||
#define OSR_21 20
|
||||
#define OSR_22 21
|
||||
#define OSR_23 22
|
||||
#define OSR_24 23
|
||||
#define OSR_25 24
|
||||
#define OSR_26 25
|
||||
#define OSR_27 26
|
||||
#define OSR_28 27
|
||||
#define OSR_29 28
|
||||
#define OSR_30 29
|
||||
#define OSR_31 30
|
||||
#define OSR_32 31
|
||||
#define OSR_33 32
|
||||
#define OSR_34 33
|
||||
#define OSR_35 34
|
||||
#define OSR_36 35
|
||||
#define OSR_37 36
|
||||
#define OSR_38 37
|
||||
#define OSR_39 38
|
||||
#define OSR_40 39
|
||||
#define OSR_41 40
|
||||
#define OSR_42 41
|
||||
#define OSR_43 42
|
||||
#define OSR_44 43
|
||||
#define OSR_45 44
|
||||
#define OSR_46 45
|
||||
#define OSR_47 46
|
||||
#define OSR_48 47
|
||||
#define OSR_49 48
|
||||
#define OSR_50 49
|
||||
#define OSR_51 50
|
||||
#define OSR_52 51
|
||||
#define OSR_53 52
|
||||
#define OSR_54 53
|
||||
#define OSR_55 54
|
||||
#define OSR_56 55
|
||||
#define OSR_57 56
|
||||
#define OSR_58 57
|
||||
#define OSR_59 58
|
||||
#define OSR_60 59
|
||||
#define OSR_61 60
|
||||
#define OSR_62 61
|
||||
#define OSR_63 62
|
||||
#define OSR_64 63
|
||||
#define OSR_65 64
|
||||
#define OSR_66 65
|
||||
#define OSR_67 66
|
||||
#define OSR_68 67
|
||||
#define OSR_69 68
|
||||
#define OSR_70 69
|
||||
#define OSR_71 70
|
||||
#define OSR_72 71
|
||||
#define OSR_73 72
|
||||
#define OSR_74 73
|
||||
#define OSR_75 74
|
||||
#define OSR_76 75
|
||||
#define OSR_77 76
|
||||
#define OSR_78 77
|
||||
#define OSR_79 78
|
||||
#define OSR_80 79
|
||||
#define OSR_81 80
|
||||
#define OSR_82 81
|
||||
#define OSR_83 82
|
||||
#define OSR_84 83
|
||||
#define OSR_85 84
|
||||
#define OSR_86 85
|
||||
#define OSR_87 86
|
||||
#define OSR_88 87
|
||||
#define OSR_89 88
|
||||
#define OSR_90 89
|
||||
#define OSR_91 90
|
||||
#define OSR_92 91
|
||||
#define OSR_93 92
|
||||
#define OSR_94 93
|
||||
#define OSR_95 94
|
||||
#define OSR_96 95
|
||||
#define OSR_97 96
|
||||
#define OSR_98 97
|
||||
#define OSR_99 98
|
||||
#define OSR_100 99
|
||||
#define OSR_101 100
|
||||
#define OSR_102 101
|
||||
#define OSR_103 102
|
||||
#define OSR_104 103
|
||||
#define OSR_105 104
|
||||
#define OSR_106 105
|
||||
#define OSR_107 106
|
||||
#define OSR_108 107
|
||||
#define OSR_109 108
|
||||
#define OSR_110 109
|
||||
#define OSR_111 110
|
||||
#define OSR_112 111
|
||||
#define OSR_113 112
|
||||
#define OSR_114 113
|
||||
#define OSR_115 114
|
||||
#define OSR_116 115
|
||||
#define OSR_117 116
|
||||
#define OSR_118 117
|
||||
#define OSR_119 118
|
||||
#define OSR_120 119
|
||||
#define OSR_121 120
|
||||
#define OSR_122 121
|
||||
#define OSR_123 122
|
||||
#define OSR_124 123
|
||||
#define OSR_125 124
|
||||
#define OSR_126 125
|
||||
#define OSR_127 126
|
||||
#define OSR_128 127
|
||||
#define OSR_129 128
|
||||
#define OSR_130 129
|
||||
#define OSR_131 130
|
||||
#define OSR_132 131
|
||||
#define OSR_133 132
|
||||
#define OSR_134 133
|
||||
#define OSR_135 134
|
||||
#define OSR_136 135
|
||||
#define OSR_137 136
|
||||
#define OSR_138 137
|
||||
#define OSR_139 138
|
||||
#define OSR_140 139
|
||||
#define OSR_141 140
|
||||
#define OSR_142 141
|
||||
#define OSR_143 142
|
||||
#define OSR_144 143
|
||||
#define OSR_145 144
|
||||
#define OSR_146 145
|
||||
#define OSR_147 146
|
||||
#define OSR_148 147
|
||||
#define OSR_149 148
|
||||
#define OSR_150 149
|
||||
#define OSR_151 150
|
||||
#define OSR_152 151
|
||||
#define OSR_153 152
|
||||
#define OSR_154 153
|
||||
#define OSR_155 154
|
||||
#define OSR_156 155
|
||||
#define OSR_157 156
|
||||
#define OSR_158 157
|
||||
#define OSR_159 158
|
||||
#define OSR_160 159
|
||||
#define OSR_161 160
|
||||
#define OSR_162 161
|
||||
#define OSR_163 162
|
||||
#define OSR_164 163
|
||||
#define OSR_165 164
|
||||
#define OSR_166 165
|
||||
#define OSR_167 166
|
||||
#define OSR_168 167
|
||||
#define OSR_169 168
|
||||
#define OSR_170 169
|
||||
#define OSR_171 170
|
||||
#define OSR_172 171
|
||||
#define OSR_173 172
|
||||
#define OSR_174 173
|
||||
#define OSR_175 174
|
||||
#define OSR_176 175
|
||||
#define OSR_177 176
|
||||
#define OSR_178 177
|
||||
#define OSR_179 178
|
||||
#define OSR_180 179
|
||||
#define OSR_181 180
|
||||
#define OSR_182 181
|
||||
#define OSR_183 182
|
||||
#define OSR_184 183
|
||||
#define OSR_185 184
|
||||
#define OSR_186 185
|
||||
#define OSR_187 186
|
||||
#define OSR_188 187
|
||||
#define OSR_189 188
|
||||
#define OSR_190 189
|
||||
#define OSR_191 190
|
||||
#define OSR_192 191
|
||||
#define OSR_193 192
|
||||
#define OSR_194 193
|
||||
#define OSR_195 194
|
||||
#define OSR_196 195
|
||||
#define OSR_197 196
|
||||
#define OSR_198 197
|
||||
#define OSR_199 198
|
||||
#define OSR_200 199
|
||||
#define OSR_201 200
|
||||
#define OSR_202 201
|
||||
#define OSR_203 202
|
||||
#define OSR_204 203
|
||||
#define OSR_205 204
|
||||
#define OSR_206 205
|
||||
#define OSR_207 206
|
||||
#define OSR_208 207
|
||||
#define OSR_209 208
|
||||
#define OSR_210 209
|
||||
#define OSR_211 210
|
||||
#define OSR_212 211
|
||||
#define OSR_213 212
|
||||
#define OSR_214 213
|
||||
#define OSR_215 214
|
||||
#define OSR_216 215
|
||||
#define OSR_217 216
|
||||
#define OSR_218 217
|
||||
#define OSR_219 218
|
||||
#define OSR_220 219
|
||||
#define OSR_221 220
|
||||
#define OSR_222 221
|
||||
#define OSR_223 222
|
||||
#define OSR_224 223
|
||||
#define OSR_225 224
|
||||
#define OSR_226 225
|
||||
#define OSR_227 226
|
||||
#define OSR_228 227
|
||||
#define OSR_229 228
|
||||
#define OSR_230 229
|
||||
#define OSR_231 230
|
||||
#define OSR_232 231
|
||||
#define OSR_233 232
|
||||
#define OSR_234 233
|
||||
#define OSR_235 234
|
||||
#define OSR_236 235
|
||||
#define OSR_237 236
|
||||
#define OSR_238 237
|
||||
#define OSR_239 238
|
||||
#define OSR_240 239
|
||||
#define OSR_241 240
|
||||
#define OSR_242 241
|
||||
#define OSR_243 242
|
||||
#define OSR_244 243
|
||||
#define OSR_245 244
|
||||
#define OSR_246 245
|
||||
#define OSR_247 246
|
||||
#define OSR_248 247
|
||||
#define OSR_249 248
|
||||
#define OSR_250 249
|
||||
#define OSR_251 250
|
||||
#define OSR_252 251
|
||||
#define OSR_253 252
|
||||
#define OSR_254 253
|
||||
#define OSR_255 254
|
||||
#define OSR_256 255
|
||||
|
||||
//
|
||||
// The following are defines for different OSR values
|
||||
//
|
||||
#define SHIFT_0_BITS 0
|
||||
#define SHIFT_1_BITS 1
|
||||
#define SHIFT_2_BITS 2
|
||||
#define SHIFT_3_BITS 3
|
||||
#define SHIFT_4_BITS 4
|
||||
#define SHIFT_5_BITS 5
|
||||
#define SHIFT_6_BITS 6
|
||||
#define SHIFT_7_BITS 7
|
||||
#define SHIFT_8_BITS 8
|
||||
#define SHIFT_9_BITS 9
|
||||
#define SHIFT_10_BITS 10
|
||||
#define SHIFT_11_BITS 11
|
||||
#define SHIFT_12_BITS 12
|
||||
#define SHIFT_13_BITS 13
|
||||
#define SHIFT_14_BITS 14
|
||||
#define SHIFT_15_BITS 15
|
||||
#define SHIFT_16_BITS 16
|
||||
#define SHIFT_17_BITS 17
|
||||
#define SHIFT_18_BITS 18
|
||||
#define SHIFT_19_BITS 19
|
||||
#define SHIFT_20_BITS 20
|
||||
#define SHIFT_21_BITS 21
|
||||
#define SHIFT_22_BITS 22
|
||||
#define SHIFT_23_BITS 23
|
||||
#define SHIFT_24_BITS 24
|
||||
#define SHIFT_25_BITS 25
|
||||
#define SHIFT_26_BITS 26
|
||||
#define SHIFT_27_BITS 27
|
||||
#define SHIFT_28_BITS 28
|
||||
#define SHIFT_29_BITS 29
|
||||
#define SHIFT_30_BITS 30
|
||||
#define SHIFT_31_BITS 31
|
||||
|
||||
//
|
||||
// Function prototypes
|
||||
//
|
||||
extern void Sdfm_configureInputCtrl(Uint16 SDFM_number,
|
||||
Uint16 Filter_number, Uint16 mode);
|
||||
extern void Sdfm_configureComparator(Uint16 SDFM_number,
|
||||
Uint16 Filter_number, Uint16 Filter_type,
|
||||
Uint16 OSR, Uint16 HLT, Uint16 LLT);
|
||||
extern void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber,
|
||||
Uint16 Filter_switch, Uint16 filterType,
|
||||
Uint16 OSR, Uint16 DR_switch,
|
||||
Uint16 shift_bits);
|
||||
extern void Sdfm_enableMFE(Uint16 SDFM_number);
|
||||
extern void Sdfm_disableMFE(Uint16 SDFM_number);
|
||||
extern void Sdfm_configureInterrupt(Uint16 SDFM_number, Uint16 Filter_number,
|
||||
Uint16 IEH_Switch, Uint16 IEL_Switch,
|
||||
Uint16 MFIE_Switch, Uint16 AE_Switch);
|
||||
extern void Sdfm_enableMIE(Uint16 SDFM_number);
|
||||
extern void Sdfm_disableMIE(Uint16 SDFM_number);
|
||||
extern void Sdfm_configureExternalreset(Uint16 SDFM_number,
|
||||
Uint16 filter1_Config_ext_reset,
|
||||
Uint16 filter2_Config_ext_reset,
|
||||
Uint16 filter3_Config_ext_reset,
|
||||
Uint16 filter4_Config_ext_reset);
|
||||
extern Uint32 Sdfm_readFlagRegister(Uint16 SDFM_number);
|
||||
extern void Sdfm_clearFlagRegister(Uint16 sdfmNumber,
|
||||
Uint32 sdfmReadFlagRegister);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of F2837xD_SDFM_DRIVERS_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,82 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_sdfm_strut.h
|
||||
//
|
||||
// TITLE: contains structures used for the SDFM driver.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F2837xD_SDFM_STRUCT_H
|
||||
#define F2837xD_SDFM_STRUCT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MAX_CPUTIMER 4
|
||||
#define MAX_ECAP 7
|
||||
#define MAX_EPWM 13
|
||||
#define MAX_EQEP 4
|
||||
#define MAX_I2C 2
|
||||
#define MAX_MCBSP 2
|
||||
#define MAX_SCI 2
|
||||
#define MAX_SPI 4
|
||||
#define MAX_ADC 5
|
||||
#define MAX_SDFM 3
|
||||
#define MAX_TRIPSEL 15
|
||||
|
||||
extern volatile Uint16 *TRIP_SEL[MAX_TRIPSEL];
|
||||
extern volatile struct ADC_REGS *ADC[MAX_ADC];
|
||||
extern volatile struct CPUTIMER_REGS *CPUTIMER[MAX_CPUTIMER];
|
||||
extern volatile struct ECAP_REGS *ECAP[MAX_ECAP];
|
||||
extern volatile struct EPWM_REGS *EPWM[MAX_EPWM];
|
||||
extern volatile struct EQEP_REGS *EQEP[MAX_EQEP];
|
||||
extern volatile struct I2C_REGS *I2C[MAX_I2C];
|
||||
extern volatile struct McBSP_REGS *MCBSP[MAX_MCBSP];
|
||||
extern volatile struct SCI_REGS *SCI[MAX_SCI];
|
||||
extern volatile struct SPI_REGS *SPI[MAX_SPI];
|
||||
extern volatile struct SDFM_REGS *SDFM[MAX_SDFM];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* extern "C" */
|
||||
|
||||
#endif // - end of F2837xD_SDFM_STRUCT_H
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,58 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F28x_Project.h
|
||||
//
|
||||
// TITLE: F28x Project Headerfile and Examples Include File
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#ifndef F28X_PROJECT_H
|
||||
#define F28X_PROJECT_H
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_Cla_typedefs.h" // F2837xD CLA Type definitions
|
||||
#include "F2837xD_device.h" // F2837xD Headerfile Include File
|
||||
#include "F2837xD_Examples.h" // F2837xD Examples Include File
|
||||
|
||||
|
||||
#endif // end of F28X_PROJECT_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,394 +0,0 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: device.h
|
||||
//
|
||||
// TITLE: Device setup for examples.
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "driverlib.h"
|
||||
|
||||
#if (!defined(CPU1) && !defined(CPU2))
|
||||
#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \
|
||||
the offsets in your header files will be inaccurate."
|
||||
#endif
|
||||
|
||||
#if (defined(CPU1) && defined(CPU2))
|
||||
#error "You have defined both CPU1 and CPU2 in your project properties. Only \
|
||||
a single CPU should be defined."
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for pin numbers and other GPIO configuration
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
// LEDs
|
||||
//
|
||||
#ifdef _LAUNCHXL_F28379D
|
||||
#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD10
|
||||
#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD9
|
||||
#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD10
|
||||
#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD9
|
||||
#else
|
||||
#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2
|
||||
#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3
|
||||
#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2
|
||||
#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// SCI for USB-to-UART adapter on FTDI chip
|
||||
//
|
||||
#ifdef _LAUNCHXL_F28379D
|
||||
#define DEVICE_GPIO_PIN_SCIRXDA 43U // GPIO number for SCI RX
|
||||
#define DEVICE_GPIO_PIN_SCITXDA 42U // GPIO number for SCI TX
|
||||
#define DEVICE_GPIO_CFG_SCIRXDA GPIO_43_SCIRXDA // "pinConfig" for SCI RX
|
||||
#define DEVICE_GPIO_CFG_SCITXDA GPIO_42_SCITXDA // "pinConfig" for SCI TX
|
||||
#else
|
||||
#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX
|
||||
#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX
|
||||
#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX
|
||||
#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX
|
||||
#endif
|
||||
|
||||
//
|
||||
// GPIO assignment for CAN-A and CAN-B
|
||||
//
|
||||
#ifdef _LAUNCHXL_F28379D
|
||||
#define DEVICE_GPIO_CFG_CANRXA GPIO_36_CANRXA // "pinConfig" for CANA RX
|
||||
#define DEVICE_GPIO_CFG_CANTXA GPIO_37_CANTXA // "pinConfig" for CANA TX
|
||||
#define DEVICE_GPIO_CFG_CANRXB GPIO_17_CANRXB // "pinConfig" for CANB RX
|
||||
#define DEVICE_GPIO_CFG_CANTXB GPIO_12_CANTXB // "pinConfig" for CANB TX
|
||||
#else
|
||||
#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX
|
||||
#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX
|
||||
#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX
|
||||
#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX
|
||||
|
||||
//I2CA GPIO pins
|
||||
#define DEVICE_GPIO_PIN_SDAA 104
|
||||
#define DEVICE_GPIO_PIN_SCLA 105
|
||||
|
||||
#define DEVICE_GPIO_CFG_SDAA GPIO_104_SDAA
|
||||
#define DEVICE_GPIO_CFG_SCLA GPIO_105_SCLA
|
||||
|
||||
|
||||
//I2CB GPIO pins
|
||||
#define DEVICE_GPIO_PIN_SDAB 40
|
||||
#define DEVICE_GPIO_PIN_SCLB 41
|
||||
|
||||
#define DEVICE_GPIO_CFG_SDAB GPIO_40_SDAB
|
||||
#define DEVICE_GPIO_CFG_SCLB GPIO_41_SCLB
|
||||
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines related to clock configuration
|
||||
//
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Launchpad Configuration
|
||||
//
|
||||
#ifdef _LAUNCHXL_F28379D
|
||||
|
||||
//
|
||||
// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock().
|
||||
//
|
||||
#define DEVICE_OSCSRC_FREQ 10000000U
|
||||
|
||||
//
|
||||
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
|
||||
// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
|
||||
//
|
||||
#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \
|
||||
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
|
||||
SYSCTL_PLL_ENABLE)
|
||||
|
||||
//
|
||||
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
|
||||
// code below if a different clock configuration is used!
|
||||
//
|
||||
#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2)
|
||||
|
||||
//
|
||||
// ControlCARD Configuration
|
||||
//
|
||||
#else
|
||||
|
||||
//
|
||||
// 20MHz XTAL on controlCARD. For use with SysCtl_getClock().
|
||||
//
|
||||
#define DEVICE_OSCSRC_FREQ 20000000U
|
||||
|
||||
//
|
||||
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
|
||||
// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
|
||||
//
|
||||
#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \
|
||||
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
|
||||
SYSCTL_PLL_ENABLE)
|
||||
|
||||
//
|
||||
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
|
||||
// code below if a different clock configuration is used!
|
||||
//
|
||||
#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2)
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
|
||||
// low speed peripheral clock divider of 4. Update the code below if a
|
||||
// different LSPCLK divider is used!
|
||||
//
|
||||
#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro
|
||||
// will convert the desired delay in microseconds to the count value expected
|
||||
// by the function. \b x is the number of microseconds to delay.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \
|
||||
(long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L)
|
||||
|
||||
//
|
||||
// The macros that can be used as parameter to the function Device_bootCPU2
|
||||
//
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000AU
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000BU
|
||||
|
||||
//
|
||||
// Other macros that are needed for the Device_bootCPU2 function
|
||||
//
|
||||
#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013U
|
||||
#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000CU
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000U
|
||||
#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001U
|
||||
#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002U
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003U
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004U
|
||||
#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005U
|
||||
|
||||
//
|
||||
// Macros used as return value by the Device_bootCPU2 function
|
||||
//
|
||||
#define STATUS_FAIL 0x0001
|
||||
#define STATUS_PASS 0x0000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines, Globals, and Header Includes related to Flash Support
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef _FLASH
|
||||
#include <stddef.h>
|
||||
|
||||
extern uint16_t RamfuncsLoadStart;
|
||||
extern uint16_t RamfuncsLoadEnd;
|
||||
extern uint16_t RamfuncsLoadSize;
|
||||
extern uint16_t RamfuncsRunStart;
|
||||
extern uint16_t RamfuncsRunEnd;
|
||||
extern uint16_t RamfuncsRunSize;
|
||||
|
||||
#define DEVICE_FLASH_WAITSTATES 3
|
||||
|
||||
#endif
|
||||
|
||||
extern uint32_t Example_PassCount;
|
||||
extern uint32_t Example_Fail;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup device_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! @brief Function to initialize the device. Primarily initializes system control to a
|
||||
//! known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
|
||||
//! and enabling the clocks to the peripherals.
|
||||
//!
|
||||
//! \param None.
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_init(void);
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//!
|
||||
//! @brief Function to turn on all peripherals, enabling reads and writes to the
|
||||
//! peripherals' registers.
|
||||
//!
|
||||
//! Note that to reduce power, unused peripherals should be disabled.
|
||||
//!
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_enableAllPeripherals(void);
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//!
|
||||
//! @brief Function to disable pin locks on GPIOs.
|
||||
//!
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_initGPIO(void);
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//! @brief Function to enable pullups for the unbonded GPIOs on the 176PTP package:
|
||||
//! GPIOs Grp Bits
|
||||
//! 95-132 C 31
|
||||
//! D 31:0
|
||||
//! E 4:0
|
||||
//! 134-168 E 31:6
|
||||
//! F 8:0
|
||||
//!
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_enableUnbondedGPIOPullupsFor176Pin(void);
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//! @brief Function to enable pullups for the unbonded GPIOs on the 100PZ package:
|
||||
//! GPIOs Grp Bits
|
||||
//! 0-1 A 1:0
|
||||
//! 5-9 A 9:5
|
||||
//! 22-40 A 31:22
|
||||
//! B 8:0
|
||||
//! 44-57 B 25:12
|
||||
//! 67-68 C 4:3
|
||||
//! 74-77 C 13:10
|
||||
//! 79-83 C 19:15
|
||||
//! 93-168 C 31:29
|
||||
//! D 31:0
|
||||
//! E 31:0
|
||||
//! F 8:0
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_enableUnbondedGPIOPullupsFor100Pin(void);
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//! @brief Function to enable pullups for the unbonded GPIOs on the
|
||||
//! 176PTP package.
|
||||
//!
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_enableUnbondedGPIOPullups(void);
|
||||
#ifdef CPU1
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//! @brief Function to implement Analog trim of TMX devices
|
||||
//!
|
||||
//! @param None
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void Device_configureTMXAnalogTrim(void);
|
||||
//*****************************************************************************
|
||||
//! @brief Executes a CPU02 control system bootloader.
|
||||
//!
|
||||
//! \param bootMode specifies which CPU02 control system boot mode to execute.
|
||||
//!
|
||||
//! This function will allow the CPU01 master system to boot the CPU02 control
|
||||
//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI,
|
||||
//! SCI, I2C, or parallel I/O. This function blocks and waits until the
|
||||
//! control system boot ROM is configured and ready to receive CPU01 to CPU02
|
||||
//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and
|
||||
//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the
|
||||
//! command to execute the selected bootloader.
|
||||
//!
|
||||
//! The \e bootMode parameter accepts one of the following values:
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH
|
||||
//!
|
||||
//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is
|
||||
//! invalid and command was not sent.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern uint16_t Device_bootCPU2(uint32_t ulBootMode);
|
||||
#endif
|
||||
//*****************************************************************************
|
||||
//!
|
||||
//! @brief Error handling function to be called when an ASSERT is violated
|
||||
//!
|
||||
//! @param *filename File name in which the error has occurred
|
||||
//! @param line Line number within the file
|
||||
//! @return None
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void __error__(const char *filename, uint32_t line);
|
||||
extern void Example_setResultPass(void);
|
||||
extern void Example_setResultFail(void);
|
||||
extern void Example_done(void);
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,87 +0,0 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: driverlib.h
|
||||
//
|
||||
// TITLE: C28x Driverlib Header File
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
#ifndef DRIVERLIB_H
|
||||
#define DRIVERLIB_H
|
||||
|
||||
#include "inc/hw_memmap.h"
|
||||
|
||||
#include "adc.h"
|
||||
#include "asysctl.h"
|
||||
#include "can.h"
|
||||
#include "cla.h"
|
||||
#include "clb.h"
|
||||
#include "cmpss.h"
|
||||
#include "cpu.h"
|
||||
#include "cputimer.h"
|
||||
#include "dac.h"
|
||||
#include "dcsm.h"
|
||||
#include "debug.h"
|
||||
#include "dma.h"
|
||||
#include "ecap.h"
|
||||
#include "emif.h"
|
||||
#include "epwm.h"
|
||||
#include "eqep.h"
|
||||
#include "flash.h"
|
||||
#include "gpio.h"
|
||||
#include "hrpwm.h"
|
||||
#include "i2c.h"
|
||||
#include "interrupt.h"
|
||||
#include "ipc.h"
|
||||
#include "mcbsp.h"
|
||||
#include "memcfg.h"
|
||||
#include "pin_map.h"
|
||||
#include "pin_map_legacy.h"
|
||||
#include "sci.h"
|
||||
#include "sdfm.h"
|
||||
#include "spi.h"
|
||||
#include "sysctl.h"
|
||||
#include "upp.h"
|
||||
#include "version.h"
|
||||
#include "xbar.h"
|
||||
|
||||
#include "driver_inclusive_terminology_mapping.h"
|
||||
|
||||
#endif // end of DRIVERLIB_H definition
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
-20399
File diff suppressed because it is too large.
Load diff
@@ -1,298 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Adc.c
|
||||
//
|
||||
// TITLE: F2837xD Adc Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// AdcSetMode - Set the resolution and signalmode for a given ADC. This will
|
||||
// ensure that the correct trim is loaded.
|
||||
//
|
||||
// NOTE!!! There is no EALLOW/EDIS in this function! You need to make sure you
|
||||
// perform the EALLOW before calling this function or else the ADC registers
|
||||
// will not be configured.
|
||||
//
|
||||
void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode)
|
||||
{
|
||||
Uint16 adcOffsetTrimOTPIndex; //index into OTP table of ADC offset trims
|
||||
Uint16 adcOffsetTrim; //temporary ADC offset trim
|
||||
|
||||
//
|
||||
//re-populate INL trim
|
||||
//
|
||||
CalAdcINL(adc);
|
||||
|
||||
if(0xFFFF != *((Uint16*)GetAdcOffsetTrimOTP))
|
||||
{
|
||||
//
|
||||
//offset trim function is programmed into OTP, so call it
|
||||
//
|
||||
|
||||
//
|
||||
//calculate the index into OTP table of offset trims and call
|
||||
//function to return the correct offset trim
|
||||
//
|
||||
#ifndef _DUAL_HEADERS
|
||||
if(ADC_RESOLUTION_12BIT == resolution)
|
||||
#else
|
||||
if(ADC_BITRESOLUTION_12BIT == resolution)
|
||||
#endif
|
||||
{
|
||||
adcOffsetTrimOTPIndex = 4*adc + 1*signalmode;
|
||||
}
|
||||
else
|
||||
{
|
||||
adcOffsetTrimOTPIndex = 4*adc + 1*signalmode + 2;
|
||||
}
|
||||
|
||||
adcOffsetTrim = (*GetAdcOffsetTrimOTP)(adcOffsetTrimOTPIndex);
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
//offset trim function is not populated, so set offset trim to 0
|
||||
//
|
||||
adcOffsetTrim = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// Apply the resolution and signalmode to the specified ADC.
|
||||
// Also apply the offset trim and, if needed, linearity trim correction.
|
||||
//
|
||||
switch(adc)
|
||||
{
|
||||
case ADC_ADCA:
|
||||
{
|
||||
AdcaRegs.ADCCTL2.bit.SIGNALMODE = signalmode;
|
||||
if(adcOffsetTrim > 0x0)
|
||||
{
|
||||
AdcaRegs.ADCOFFTRIM.all = adcOffsetTrim;
|
||||
}
|
||||
#ifndef _DUAL_HEADERS
|
||||
if(ADC_RESOLUTION_12BIT == resolution)
|
||||
#else
|
||||
if(ADC_BITRESOLUTION_12BIT == resolution)
|
||||
#endif
|
||||
{
|
||||
AdcaRegs.ADCCTL2.bit.RESOLUTION = 0;
|
||||
|
||||
//
|
||||
//12-bit linearity trim workaround
|
||||
//
|
||||
AdcaRegs.ADCINLTRIM1 &= 0xFFFF0000;
|
||||
AdcaRegs.ADCINLTRIM2 &= 0xFFFF0000;
|
||||
AdcaRegs.ADCINLTRIM4 &= 0xFFFF0000;
|
||||
AdcaRegs.ADCINLTRIM5 &= 0xFFFF0000;
|
||||
}
|
||||
else
|
||||
{
|
||||
AdcaRegs.ADCCTL2.bit.RESOLUTION = 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case ADC_ADCB:
|
||||
{
|
||||
AdcbRegs.ADCCTL2.bit.SIGNALMODE = signalmode;
|
||||
if(adcOffsetTrim > 0x0)
|
||||
{
|
||||
AdcbRegs.ADCOFFTRIM.all = adcOffsetTrim;
|
||||
}
|
||||
#ifndef _DUAL_HEADERS
|
||||
if(ADC_RESOLUTION_12BIT == resolution)
|
||||
#else
|
||||
if(ADC_BITRESOLUTION_12BIT == resolution)
|
||||
#endif
|
||||
{
|
||||
AdcbRegs.ADCCTL2.bit.RESOLUTION = 0;
|
||||
|
||||
//
|
||||
//12-bit linearity trim workaround
|
||||
//
|
||||
AdcbRegs.ADCINLTRIM1 &= 0xFFFF0000;
|
||||
AdcbRegs.ADCINLTRIM2 &= 0xFFFF0000;
|
||||
AdcbRegs.ADCINLTRIM4 &= 0xFFFF0000;
|
||||
AdcbRegs.ADCINLTRIM5 &= 0xFFFF0000;
|
||||
}
|
||||
else
|
||||
{
|
||||
AdcbRegs.ADCCTL2.bit.RESOLUTION = 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case ADC_ADCC:
|
||||
{
|
||||
AdccRegs.ADCCTL2.bit.SIGNALMODE = signalmode;
|
||||
if(adcOffsetTrim > 0x0)
|
||||
{
|
||||
AdccRegs.ADCOFFTRIM.all = adcOffsetTrim;
|
||||
}
|
||||
#ifndef _DUAL_HEADERS
|
||||
if(ADC_RESOLUTION_12BIT == resolution)
|
||||
#else
|
||||
if(ADC_BITRESOLUTION_12BIT == resolution)
|
||||
#endif
|
||||
{
|
||||
AdccRegs.ADCCTL2.bit.RESOLUTION = 0;
|
||||
//
|
||||
//12-bit linearity trim workaround
|
||||
//
|
||||
AdccRegs.ADCINLTRIM1 &= 0xFFFF0000;
|
||||
AdccRegs.ADCINLTRIM2 &= 0xFFFF0000;
|
||||
AdccRegs.ADCINLTRIM4 &= 0xFFFF0000;
|
||||
AdccRegs.ADCINLTRIM5 &= 0xFFFF0000;
|
||||
}
|
||||
else
|
||||
{
|
||||
AdccRegs.ADCCTL2.bit.RESOLUTION = 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case ADC_ADCD:
|
||||
{
|
||||
AdcdRegs.ADCCTL2.bit.SIGNALMODE = signalmode;
|
||||
if(adcOffsetTrim > 0x0)
|
||||
{
|
||||
AdcdRegs.ADCOFFTRIM.all = adcOffsetTrim;
|
||||
}
|
||||
#ifndef _DUAL_HEADERS
|
||||
if(ADC_RESOLUTION_12BIT == resolution)
|
||||
#else
|
||||
if(ADC_BITRESOLUTION_12BIT == resolution)
|
||||
#endif
|
||||
{
|
||||
AdcdRegs.ADCCTL2.bit.RESOLUTION = 0;
|
||||
|
||||
//
|
||||
//12-bit linearity trim workaround
|
||||
//
|
||||
AdcdRegs.ADCINLTRIM1 &= 0xFFFF0000;
|
||||
AdcdRegs.ADCINLTRIM2 &= 0xFFFF0000;
|
||||
AdcdRegs.ADCINLTRIM4 &= 0xFFFF0000;
|
||||
AdcdRegs.ADCINLTRIM5 &= 0xFFFF0000;
|
||||
}
|
||||
else
|
||||
{
|
||||
AdcdRegs.ADCCTL2.bit.RESOLUTION = 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// CalAdcINL - Loads INL trim values from OTP into the trim registers of the
|
||||
// specified ADC. Use only as part of AdcSetMode function, since
|
||||
// linearity trim correction is needed for some modes.
|
||||
//
|
||||
void CalAdcINL(Uint16 adc)
|
||||
{
|
||||
switch(adc)
|
||||
{
|
||||
case ADC_ADCA:
|
||||
if(0xFFFF != *((Uint16*)CalAdcaINL))
|
||||
{
|
||||
//
|
||||
//trim function is programmed into OTP, so call it
|
||||
//
|
||||
(*CalAdcaINL)();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
//do nothing, no INL trim function populated
|
||||
//
|
||||
}
|
||||
break;
|
||||
case ADC_ADCB:
|
||||
if(0xFFFF != *((Uint16*)CalAdcbINL))
|
||||
{
|
||||
//
|
||||
//trim function is programmed into OTP, so call it
|
||||
//
|
||||
(*CalAdcbINL)();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
//do nothing, no INL trim function populated
|
||||
//
|
||||
}
|
||||
break;
|
||||
case ADC_ADCC:
|
||||
if(0xFFFF != *((Uint16*)CalAdccINL))
|
||||
{
|
||||
//
|
||||
//trim function is programmed into OTP, so call it
|
||||
//
|
||||
(*CalAdccINL)();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
//do nothing, no INL trim function populated
|
||||
//
|
||||
}
|
||||
break;
|
||||
case ADC_ADCD:
|
||||
if(0xFFFF != *((Uint16*)CalAdcdINL))
|
||||
{
|
||||
//
|
||||
//trim function is programmed into OTP, so call it
|
||||
//
|
||||
(*CalAdcdINL)();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
//do nothing, no INL trim function populated
|
||||
//
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,112 +0,0 @@
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// FILE: F2837xD_CodeStartBranch.asm
|
||||
;//
|
||||
;// TITLE: Branch for redirecting code execution after boot.
|
||||
;//
|
||||
;// For these examples, code_start is the first code that is executed after
|
||||
;// exiting the boot ROM code.
|
||||
;//
|
||||
;// The codestart section in the linker cmd file is used to physically place
|
||||
;// this code at the correct memory location. This section should be placed
|
||||
;// at the location the BOOT ROM will re-direct the code to. For example,
|
||||
;// for boot to FLASH this code will be located at 0x3f7ff6.
|
||||
;//
|
||||
;// In addition, the example F2837xD projects are setup such that the codegen
|
||||
;// entry point is also set to the code_start label. This is done by linker
|
||||
;// option -e in the project build options. When the debugger loads the code,
|
||||
;// it will automatically set the PC to the "entry point" address indicated by
|
||||
;// the -e linker option. In this case the debugger is simply assigning the PC,
|
||||
;// it is not the same as a full reset of the device.
|
||||
;//
|
||||
;// The compiler may warn that the entry point for the project is other then
|
||||
;// _c_init00. _c_init00 is the C environment setup and is run before
|
||||
;// main() is entered. The code_start code will re-direct the execution
|
||||
;// to _c_init00 and thus there is no worry and this warning can be ignored.
|
||||
;//
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// $Release Date: $
|
||||
;// $Copyright:
|
||||
;// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
;//
|
||||
;// Redistribution and use in source and binary forms, with or without
|
||||
;// modification, are permitted provided that the following conditions
|
||||
;// are met:
|
||||
;//
|
||||
;// Redistributions of source code must retain the above copyright
|
||||
;// notice, this list of conditions and the following disclaimer.
|
||||
;//
|
||||
;// Redistributions in binary form must reproduce the above copyright
|
||||
;// notice, this list of conditions and the following disclaimer in the
|
||||
;// documentation and/or other materials provided with the
|
||||
;// distribution.
|
||||
;//
|
||||
;// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
;// its contributors may be used to endorse or promote products derived
|
||||
;// from this software without specific prior written permission.
|
||||
;//
|
||||
;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;// $
|
||||
;//###########################################################################
|
||||
|
||||
***********************************************************************
|
||||
|
||||
WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0
|
||||
|
||||
.ref _c_int00
|
||||
.global code_start
|
||||
|
||||
***********************************************************************
|
||||
* Function: codestart section
|
||||
*
|
||||
* Description: Branch to code starting point
|
||||
***********************************************************************
|
||||
|
||||
.sect "codestart"
|
||||
.retain
|
||||
|
||||
code_start:
|
||||
.if WD_DISABLE == 1
|
||||
LB wd_disable ;Branch to watchdog disable code
|
||||
.else
|
||||
LB _c_int00 ;Branch to start of boot._asm in RTS library
|
||||
.endif
|
||||
|
||||
;end codestart section
|
||||
|
||||
***********************************************************************
|
||||
* Function: wd_disable
|
||||
*
|
||||
* Description: Disables the watchdog timer
|
||||
***********************************************************************
|
||||
.if WD_DISABLE == 1
|
||||
|
||||
.text
|
||||
wd_disable:
|
||||
SETC OBJMODE ;Set OBJMODE for 28x object code
|
||||
EALLOW ;Enable EALLOW protected register access
|
||||
MOVZ DP, #7029h>>6 ;Set data page for WDCR register
|
||||
MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
|
||||
EDIS ;Disable EALLOW protected register access
|
||||
LB _c_int00 ;Branch to start of boot._asm in RTS library
|
||||
|
||||
.endif
|
||||
|
||||
;end wd_disable
|
||||
|
||||
.end
|
||||
|
||||
;//
|
||||
;// End of file.
|
||||
;//
|
||||
@@ -1,181 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_CpuTimers.c
|
||||
//
|
||||
// TITLE: CPU 32-bit Timers Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
struct CPUTIMER_VARS CpuTimer0;
|
||||
struct CPUTIMER_VARS CpuTimer1;
|
||||
struct CPUTIMER_VARS CpuTimer2;
|
||||
|
||||
//
|
||||
// InitCpuTimers - This function initializes all three CPU timers to a known
|
||||
// state.
|
||||
//
|
||||
void InitCpuTimers(void)
|
||||
{
|
||||
//
|
||||
// CPU Timer 0
|
||||
// Initialize address pointers to respective timer registers:
|
||||
//
|
||||
CpuTimer0.RegsAddr = &CpuTimer0Regs;
|
||||
|
||||
//
|
||||
// Initialize timer period to maximum:
|
||||
//
|
||||
CpuTimer0Regs.PRD.all = 0xFFFFFFFF;
|
||||
|
||||
//
|
||||
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||
//
|
||||
CpuTimer0Regs.TPR.all = 0;
|
||||
CpuTimer0Regs.TPRH.all = 0;
|
||||
|
||||
//
|
||||
// Make sure timer is stopped:
|
||||
//
|
||||
CpuTimer0Regs.TCR.bit.TSS = 1;
|
||||
|
||||
//
|
||||
// Reload all counter register with period value:
|
||||
//
|
||||
CpuTimer0Regs.TCR.bit.TRB = 1;
|
||||
|
||||
//
|
||||
// Reset interrupt counters:
|
||||
//
|
||||
CpuTimer0.InterruptCount = 0;
|
||||
|
||||
//
|
||||
// Initialize address pointers to respective timer registers:
|
||||
//
|
||||
CpuTimer1.RegsAddr = &CpuTimer1Regs;
|
||||
CpuTimer2.RegsAddr = &CpuTimer2Regs;
|
||||
|
||||
//
|
||||
// Initialize timer period to maximum:
|
||||
//
|
||||
CpuTimer1Regs.PRD.all = 0xFFFFFFFF;
|
||||
CpuTimer2Regs.PRD.all = 0xFFFFFFFF;
|
||||
|
||||
//
|
||||
// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||
//
|
||||
CpuTimer1Regs.TPR.all = 0;
|
||||
CpuTimer1Regs.TPRH.all = 0;
|
||||
CpuTimer2Regs.TPR.all = 0;
|
||||
CpuTimer2Regs.TPRH.all = 0;
|
||||
|
||||
//
|
||||
// Make sure timers are stopped:
|
||||
//
|
||||
CpuTimer1Regs.TCR.bit.TSS = 1;
|
||||
CpuTimer2Regs.TCR.bit.TSS = 1;
|
||||
|
||||
//
|
||||
// Reload all counter register with period value:
|
||||
//
|
||||
CpuTimer1Regs.TCR.bit.TRB = 1;
|
||||
CpuTimer2Regs.TCR.bit.TRB = 1;
|
||||
|
||||
//
|
||||
// Reset interrupt counters:
|
||||
//
|
||||
CpuTimer1.InterruptCount = 0;
|
||||
CpuTimer2.InterruptCount = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// ConfigCpuTimer - This function initializes the selected timer to the period
|
||||
// specified by the "Freq" and "Period" parameters. The "Freq"
|
||||
// is entered as "MHz" and the period in "uSeconds". The timer
|
||||
// is held in the stopped state after configuration.
|
||||
//
|
||||
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
|
||||
{
|
||||
Uint32 temp;
|
||||
|
||||
//
|
||||
// Initialize timer period:
|
||||
//
|
||||
Timer->CPUFreqInMHz = Freq;
|
||||
Timer->PeriodInUSec = Period;
|
||||
temp = (Uint32) (Freq * Period);
|
||||
|
||||
//
|
||||
// Counter decrements PRD+1 times each period
|
||||
//
|
||||
Timer->RegsAddr->PRD.all = temp - 1;
|
||||
|
||||
//
|
||||
// Set pre-scale counter to divide by 1 (SYSCLKOUT):
|
||||
//
|
||||
Timer->RegsAddr->TPR.all = 0;
|
||||
Timer->RegsAddr->TPRH.all = 0;
|
||||
|
||||
//
|
||||
// Initialize timer control register:
|
||||
//
|
||||
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart
|
||||
// Timer
|
||||
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
|
||||
Timer->RegsAddr->TCR.bit.SOFT = 0;
|
||||
Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled
|
||||
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer
|
||||
// Interrupt
|
||||
|
||||
//
|
||||
// Reset interrupt counter:
|
||||
//
|
||||
Timer->InterruptCount = 0;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,60 +0,0 @@
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// FILE: F2837xD_DBGIER.asm
|
||||
;//
|
||||
;// TITLE: Set the DBGIER register
|
||||
;//
|
||||
;// DESCRIPTION:
|
||||
;//
|
||||
;// Function to set the DBGIER register (for realtime emulation).
|
||||
;// Function Prototype: void SetDBGIER(Uint16)
|
||||
;// Usage: SetDBGIER(value);
|
||||
;// Input Parameters: Uint16 value = value to put in DBGIER register.
|
||||
;// Return Value: none
|
||||
;//
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// $Release Date: $
|
||||
;// $Copyright:
|
||||
;// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
;//
|
||||
;// Redistribution and use in source and binary forms, with or without
|
||||
;// modification, are permitted provided that the following conditions
|
||||
;// are met:
|
||||
;//
|
||||
;// Redistributions of source code must retain the above copyright
|
||||
;// notice, this list of conditions and the following disclaimer.
|
||||
;//
|
||||
;// Redistributions in binary form must reproduce the above copyright
|
||||
;// notice, this list of conditions and the following disclaimer in the
|
||||
;// documentation and/or other materials provided with the
|
||||
;// distribution.
|
||||
;//
|
||||
;// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
;// its contributors may be used to endorse or promote products derived
|
||||
;// from this software without specific prior written permission.
|
||||
;//
|
||||
;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;// $
|
||||
;//###########################################################################
|
||||
.global _SetDBGIER
|
||||
.text
|
||||
|
||||
_SetDBGIER:
|
||||
MOV *SP++,AL
|
||||
POP DBGIER
|
||||
LRETR
|
||||
|
||||
;//
|
||||
;// End of file
|
||||
;//
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -1,147 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_ECap.c
|
||||
//
|
||||
// TITLE: F2837xD eCAP Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// InitECap - This function initializes the eCAP(s) to a known state.
|
||||
//
|
||||
void InitECap(void)
|
||||
{
|
||||
// Initialize eCAP1/2/3/4/5/6
|
||||
|
||||
//tbd...
|
||||
}
|
||||
|
||||
//
|
||||
// InitECapGpio - This function initializes GPIO pins to function as ECAP pins
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3
|
||||
// different peripheral functional pins. By default all pins
|
||||
// come up as GPIO inputs after reset.
|
||||
// Caution:
|
||||
// For each eCAP peripheral
|
||||
// Only one GPIO pin should be enabled for ECAP operation.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
void InitECapGpio()
|
||||
{
|
||||
}
|
||||
|
||||
//
|
||||
// InitECap1Gpio - Initialize ECAP1 GPIOs
|
||||
//
|
||||
void InitECap1Gpio(Uint16 pin)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT7SELECT = pin; // Set eCAP1 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitECap2Gpio - Initialize ECAP2 GPIOs
|
||||
//
|
||||
void InitECap2Gpio(Uint16 pin)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT8SELECT = pin; // Set eCAP2 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitECap3Gpio - Initialize ECAP3 GPIOs
|
||||
//
|
||||
void InitECap3Gpio(Uint16 pin)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT9SELECT = pin; // Set eCAP3 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitECap4Gpio - Initialize ECAP4 GPIOs
|
||||
//
|
||||
void InitECap4Gpio(Uint16 pin)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT10SELECT = pin; // Set eCAP4 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitECap5Gpio - Initialize ECAP5 GPIOs
|
||||
//
|
||||
void InitECap5Gpio(Uint16 pin)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT11SELECT = pin; // Set eCAP5 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitECap6Gpio - Initialize ECAP6 GPIOs
|
||||
//
|
||||
void InitECap6Gpio(Uint16 pin)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT12SELECT = pin; // Set eCAP6 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitAPwm1Gpio - Initialize EPWM1 GPIOs
|
||||
//
|
||||
void InitAPwm1Gpio()
|
||||
{
|
||||
EALLOW;
|
||||
OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX0 = 3; // Select ECAP1.OUT on Mux0
|
||||
OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX0 = 1; // Enable MUX0 for ECAP1.OUT
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Select OUTPUTXBAR3 on GPIO5
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,436 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_EPwm.c
|
||||
//
|
||||
// TITLE: F2837xD EPwm Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// InitEPwmGpio - Initialize all EPWM modules' GPIOs
|
||||
//
|
||||
void InitEPwmGpio(void)
|
||||
{
|
||||
InitEPwm1Gpio();
|
||||
InitEPwm2Gpio();
|
||||
InitEPwm3Gpio();
|
||||
InitEPwm4Gpio();
|
||||
InitEPwm5Gpio();
|
||||
InitEPwm6Gpio();
|
||||
InitEPwm7Gpio();
|
||||
InitEPwm8Gpio();
|
||||
InitEPwm9Gpio();
|
||||
InitEPwm10Gpio();
|
||||
InitEPwm11Gpio();
|
||||
InitEPwm12Gpio();
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm1Gpio - Initialize EPWM1 GPIOs
|
||||
//
|
||||
void InitEPwm1Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO145 = 1; // Disable pull-up on GPIO145 (EPWM1A)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO146 = 1; // Disable pull-up on GPIO146 (EPWM1B)
|
||||
|
||||
//
|
||||
// Configure EPWM-1 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM1 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO145 = 1; // Configure GPIO145 as EPWM1A
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO146 = 1; // Configure GPIO0146 as EPWM1B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm2Gpio - Initialize EPWM2 GPIOs
|
||||
//
|
||||
void InitEPwm2Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO147 = 1; // Disable pull-up on GPIO147 (EPWM2A)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO148 = 1; // Disable pull-up on GPIO148 (EPWM2B)
|
||||
|
||||
//
|
||||
// Configure EPwm-2 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM2 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO147 = 1; // Configure GPIO147 as EPWM2A
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO148 = 1; // Configure GPIO148 as EPWM2B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm3Gpio - Initialize EPWM3 GPIOs
|
||||
//
|
||||
void InitEPwm3Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO149 = 1; // Disable pull-up on GPIO149 (EPWM3A)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO150 = 1; // Disable pull-up on GPIO150 (EPWM3B)
|
||||
|
||||
//
|
||||
// Configure EPwm-3 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM3 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO149 = 1; // Configure GPIO149 as EPWM3A
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO150 = 1; // Configure GPIO150 as EPWM3B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm4Gpio - Initialize EPWM4 GPIOs
|
||||
//
|
||||
void InitEPwm4Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EPWM4A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EPWM4B)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO151 = 1; // Disable pull-up on GPIO151 (EPWM4A)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO152 = 1; // Disable pull-up on GPIO152 (EPWM4B)
|
||||
|
||||
//
|
||||
// Configure EPWM-4 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM4 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO151 = 1; // Configure GPIO151 as EPWM4A
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO152 = 1; // Configure GPIO152 as EPWM4B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm5Gpio - Initialize EPWM5 GPIOs
|
||||
//
|
||||
void InitEPwm5Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EPWM5A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EPWM5B)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO153 = 1; // Disable pull-up on GPIO153 (EPWM5A)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO154 = 1; // Disable pull-up on GPIO154 (EPWM5B)
|
||||
|
||||
//
|
||||
// Configure EPWM-5 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM5 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO153 = 1; // Configure GPIO153 as EPWM5A
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO154 = 1; // Configure GPIO0154 as EPWM5B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm6Gpio - Initialize EPWM6 GPIOs
|
||||
//
|
||||
void InitEPwm6Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EPWM6A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EPWM6B)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO155 = 1; // Disable pull-up on GPIO155 (EPWM6A)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO156 = 1; // Disable pull-up on GPIO156 (EPWM6B)
|
||||
|
||||
//
|
||||
// Configure EPWM-6 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM6 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO155 = 1; // Configure GPIO155 as EPWM6A
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO156 = 1; // Configure GPIO156 as EPWM6B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm7Gpio - Initialize EPWM7 GPIOs
|
||||
//
|
||||
void InitEPwm7Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EPWM7A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EPWM7B)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO157 = 1; // Disable pull-up on GPIO157 (EPWM7A)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO158 = 1; // Disable pull-up on GPIO158 (EPWM7B)
|
||||
|
||||
//
|
||||
// Configure EPWM-6 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM6 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EPWM7A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EPWM7B
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO157 = 1; // Configure GPIO157 as EPWM7A
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO158 = 1; // Configure GPIO158 as EPWM7B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm8Gpio - Initialize EPWM8 GPIOs
|
||||
//
|
||||
void InitEPwm8Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (EPWM8A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (EPWM8B)
|
||||
// GpioCtrlRegs.GPEPUD.bit.GPIO159 = 1; // Disable pull-up on GPIO159 (EPWM8A)
|
||||
// GpioCtrlRegs.GPFPUD.bit.GPIO160 = 1; // Disable pull-up on GPIO160 (EPWM8B)
|
||||
|
||||
//
|
||||
// Configure EPWM-6 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM6 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as EPWM8A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as EPWM8B
|
||||
// GpioCtrlRegs.GPEMUX2.bit.GPIO159 = 1; // Configure GPIO159 as EPWM8A
|
||||
// GpioCtrlRegs.GPFMUX1.bit.GPIO160 = 1; // Configure GPIO160 as EPWM8B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm9Gpio - Initialize EPWM9 GPIOs
|
||||
//
|
||||
void InitEPwm9Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPFPUD.bit.GPIO161 = 1; // Disable pull-up on GPIO161 (EPWM9A)
|
||||
GpioCtrlRegs.GPFPUD.bit.GPIO162 = 1; // Disable pull-up on GPIO162 (EPWM9B)
|
||||
|
||||
//
|
||||
// Configure EPWM-6 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM6 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPFMUX1.bit.GPIO161 = 1; // Configure GPIO161 as EPWM9A
|
||||
GpioCtrlRegs.GPFMUX1.bit.GPIO162 = 1; // Configure GPIO162 as EPWM9B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm10Gpio - Initialize EPWM10 GPIOs
|
||||
//
|
||||
void InitEPwm10Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPFPUD.bit.GPIO163 = 1; // Disable pull-up on GPIO163 (EPWM10A)
|
||||
GpioCtrlRegs.GPFPUD.bit.GPIO164 = 1; // Disable pull-up on GPIO164 (EPWM10B)
|
||||
|
||||
//
|
||||
// Configure EPWM-6 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM6 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPFMUX1.bit.GPIO163 = 1; // Configure GPIO163 as EPWM10A
|
||||
GpioCtrlRegs.GPFMUX1.bit.GPIO164 = 1; // Configure GPIO164 as EPWM10B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm11Gpio - Initialize EPWM11 GPIOs
|
||||
//
|
||||
void InitEPwm11Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPFPUD.bit.GPIO165 = 1; // Disable pull-up on GPIO165 (EPWM11A)
|
||||
GpioCtrlRegs.GPFPUD.bit.GPIO166 = 1; // Disable pull-up on GPIO166 (EPWM11B)
|
||||
|
||||
//
|
||||
// Configure EPWM-6 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM6 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPFMUX1.bit.GPIO165 = 1; // Configure GPIO165 as EPWM11A
|
||||
GpioCtrlRegs.GPFMUX1.bit.GPIO166 = 1; // Configure GPIO166 as EPWM11B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm12Gpio - Initialize EPWM12 GPIOs
|
||||
//
|
||||
void InitEPwm12Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPFPUD.bit.GPIO167 = 1; // Disable pull-up on GPIO167 (EPWM12A)
|
||||
GpioCtrlRegs.GPFPUD.bit.GPIO168 = 1; // Disable pull-up on GPIO168 (EPWM12B)
|
||||
|
||||
//
|
||||
// Configure EPWM-6 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM6 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPFMUX1.bit.GPIO167 = 1; // Configure GPIO167 as EPWM12A
|
||||
GpioCtrlRegs.GPFMUX1.bit.GPIO168 = 1; // Configure GPIO168 as EPWM12B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
@@ -1,389 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_EQep.c
|
||||
//
|
||||
// TITLE: F2837xD eQEP Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// InitEQep - This function initializes the eQEP(s) to a known state.
|
||||
//
|
||||
void InitEQep(void)
|
||||
{
|
||||
// Initialize eQEP1
|
||||
|
||||
//tbd...
|
||||
}
|
||||
|
||||
//
|
||||
// InitEQepGpio - This function initializes GPIO pins to function as eQEP pins
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3
|
||||
// different peripheral functional pins. By default all pins
|
||||
// come up as GPIO inputs after reset.
|
||||
// Caution:
|
||||
// For each eQEP peripheral
|
||||
// Only one GPIO pin should be enabled for EQEPxA operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxB operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxS operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxI operation.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
void InitEQepGpio()
|
||||
{
|
||||
InitEQep1Gpio();
|
||||
InitEQep2Gpio();
|
||||
InitEQep3Gpio();
|
||||
}
|
||||
|
||||
//
|
||||
// InitEQep1Gpio - Initialize EQEP-1 GPIOs
|
||||
// Caution:
|
||||
// For each eQEP peripheral
|
||||
// Only one GPIO pin should be enabled for EQEPxA operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxB operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxS operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxI operation.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
void InitEQep1Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EQEP1A)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EQEP1B)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EQEP1S)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EQEP1I)
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (EQEP1A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (EQEP1B)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; // Disable pull-up on GPIO22 (EQEP1S)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; // Disable pull-up on GPIO23 (EQEP1I)
|
||||
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO50 = 1; // Disable pull-up on GPIO50 (EQEP1A)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO51 = 1; // Disable pull-up on GPIO51 (EQEP1B)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO52 = 1; // Disable pull-up on GPIO52 (EQEP1S)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO53 = 1; // Disable pull-up on GPIO53 (EQEP1I)
|
||||
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO96 = 1; // Disable pull-up on GPIO96 (EQEP1A)
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO97 = 1; // Disable pull-up on GPIO97 (EQEP1B)
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO98 = 1; // Disable pull-up on GPIO98 (EQEP1S)
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO99 = 1; // Disable pull-up on GPIO99 (EQEP1I)
|
||||
|
||||
//
|
||||
// Synchronize inputs to SYSCLK
|
||||
// Synchronization can be enabled or disabled by the user.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 0; // Sync GPIO10 to SYSCLK (EQEP1A)
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Sync GPIO11 to SYSCLK (EQEP1B)
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Sync GPIO12 to SYSCLK (EQEP1S)
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Sync GPIO13 to SYSCLK (EQEP1I)
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync GPIO20 to SYSCLK (EQEP1A)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync GPIO21 to SYSCLK (EQEP1B)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync GPIO22 to SYSCLK (EQEP1S)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync GPIO23 to SYSCLK (EQEP1I)
|
||||
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync GPIO50 to SYSCLK (EQEP1A)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync GPIO51 to SYSCLK (EQEP1B)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync GPIO52 to SYSCLK (EQEP1S)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync GPIO53 to SYSCLK (EQEP1I)
|
||||
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO96 = 0; // Sync GPIO96 to SYSCLK (EQEP1A)
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO97 = 0; // Sync GPIO97 to SYSCLK (EQEP1B)
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO98 = 0; // Sync GPIO98 to SYSCLK (EQEP1S)
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO99 = 0; // Sync GPIO99 to SYSCLK (EQEP1I)
|
||||
|
||||
//
|
||||
// Configure EQEP-1 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EQEP1 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
|
||||
// GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A
|
||||
// GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B
|
||||
// GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S
|
||||
// GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I
|
||||
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I
|
||||
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEQep2Gpio - Initialize EQEP-2 GPIOs
|
||||
//
|
||||
void InitEQep2Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // Disable pull-up on GPIO24 (EQEP2A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; // Disable pull-up on GPIO25 (EQEP2B)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO26 = 1; // Disable pull-up on GPIO26 (EQEP2S)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 1; // Disable pull-up on GPIO27 (EQEP2I)
|
||||
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO54 = 1; // Disable pull-up on GPIO54 (EQEP2A)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO55 = 1; // Disable pull-up on GPIO55 (EQEP2B)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO56 = 1; // Disable pull-up on GPIO56 (EQEP2S)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO57 = 1; // Disable pull-up on GPIO57 (EQEP2I)
|
||||
|
||||
// GpioCtrlRegs.GPCPUD.bit.GPIO78 = 1; // Disable pull-up on GPIO78 (EQEP2A)
|
||||
// GpioCtrlRegs.GPCPUD.bit.GPIO79 = 1; // Disable pull-up on GPIO79 (EQEP2B)
|
||||
// GpioCtrlRegs.GPCPUD.bit.GPIO80 = 1; // Disable pull-up on GPIO80 (EQEP2S)
|
||||
// GpioCtrlRegs.GPCPUD.bit.GPIO81 = 1; // Disable pull-up on GPIO81 (EQEP2I)
|
||||
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO100 = 1; // Disable pull-up on GPIO100 (EQEP2A)
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO101 = 1; // Disable pull-up on GPIO101 (EQEP2B)
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO102 = 1; // Disable pull-up on GPIO102 (EQEP2S)
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO103 = 1; // Disable pull-up on GPIO103 (EQEP2I)
|
||||
|
||||
//
|
||||
// Synchronize inputs to SYSCLK
|
||||
// Synchronization can be enabled or disabled by the user.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync GPIO24 to SYSCLK (EQEP2A)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync GPIO25 to SYSCLK (EQEP2B)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync GPIO26 to SYSCLK (EQEP2S)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync GPIO27 to SYSCLK (EQEP2I)
|
||||
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; // Sync GPIO54 to SYSCLK (EQEP2A)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 0; // Sync GPIO55 to SYSCLK (EQEP2B)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 0; // Sync GPIO56 to SYSCLK (EQEP2S)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 0; // Sync GPIO57 to SYSCLK (EQEP2I)
|
||||
|
||||
// GpioCtrlRegs.GPCQSEL1.bit.GPIO78 = 0; // Sync GPIO78 to SYSCLK (EQEP2A)
|
||||
// GpioCtrlRegs.GPCQSEL1.bit.GPIO79 = 0; // Sync GPIO79 to SYSCLK (EQEP2B)
|
||||
// GpioCtrlRegs.GPCQSEL2.bit.GPIO80 = 0; // Sync GPIO80 to SYSCLK (EQEP2S)
|
||||
// GpioCtrlRegs.GPCQSEL2.bit.GPIO81 = 0; // Sync GPIO81 to SYSCLK (EQEP2I)
|
||||
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 0; // Sync GPIO100 to SYSCLK (EQEP2A)
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO101 = 0; // Sync GPIO101 to SYSCLK (EQEP2B)
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 0; // Sync GPIO102 to SYSCLK (EQEP2S)
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO103 = 0; // Sync GPIO103 to SYSCLK (EQEP2I)
|
||||
|
||||
//
|
||||
// Configure EQEP-1 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EQEP2 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2S
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2I
|
||||
|
||||
// GpioCtrlRegs.GPBGMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A
|
||||
// GpioCtrlRegs.GPBGMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B
|
||||
// GpioCtrlRegs.GPBGMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S
|
||||
// GpioCtrlRegs.GPBGMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I
|
||||
|
||||
// GpioCtrlRegs.GPCGMUX1.bit.GPIO78 = 1; // Configure GPIO78 as EQEP2A
|
||||
// GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 2; // Configure GPIO78 as EQEP2A
|
||||
// GpioCtrlRegs.GPCGMUX1.bit.GPIO79 = 1; // Configure GPIO79 as EQEP2B
|
||||
// GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 2; // Configure GPIO79 as EQEP2B
|
||||
// GpioCtrlRegs.GPCGMUX2.bit.GPIO80 = 1; // Configure GPIO80 as EQEP2S
|
||||
// GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 2; // Configure GPIO80 as EQEP2S
|
||||
// GpioCtrlRegs.GPCGMUX2.bit.GPIO81 = 1; // Configure GPIO81 as EQEP2I
|
||||
// GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 2; // Configure GPIO81 as EQEP2I
|
||||
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEQep3Gpio - Initialize EQEP-3 GPIOs
|
||||
//
|
||||
void InitEQep3Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EQEP3A)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EQEP3B)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EQEP3S)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EQEP3I)
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up on GPIO28 (EQEP3A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1; // Disable pull-up on GPIO29 (EQEP3B)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 1; // Disable pull-up on GPIO30 (EQEP3S)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 1; // Disable pull-up on GPIO31 (EQEP3I)
|
||||
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO62 = 1; // Disable pull-up on GPIO62 (EQEP3A)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO63 = 1; // Disable pull-up on GPIO63 (EQEP3B)
|
||||
// GpioCtrlRegs.GPCPUD.bit.GPIO64 = 1; // Disable pull-up on GPIO64 (EQEP3S)
|
||||
// GpioCtrlRegs.GPCPUD.bit.GPIO65 = 1; // Disable pull-up on GPIO65 (EQEP3I)
|
||||
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO104 = 1; // Disable pull-up on GPIO104 (EQEP3A)
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO105 = 1; // Disable pull-up on GPIO105 (EQEP3B)
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO106 = 1; // Disable pull-up on GPIO106 (EQEP3S)
|
||||
// GpioCtrlRegs.GPDPUD.bit.GPIO107 = 1; // Disable pull-up on GPIO107 (EQEP3I)
|
||||
|
||||
//
|
||||
// Synchronize inputs to SYSCLK
|
||||
// Synchronization can be enabled or disabled by the user.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Sync GPIO6 to SYSCLK (EQEP3A)
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Sync GPIO7 to SYSCLK (EQEP3B)
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0; // Sync GPIO8 to SYSCLK (EQEP3S)
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Sync GPIO9 to SYSCLK (EQEP3I)
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 0; // Sync GPIO28 to SYSCLK (EQEP3A)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 0; // Sync GPIO29 to SYSCLK (EQEP3B)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 0; // Sync GPIO30 to SYSCLK (EQEP3S)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 0; // Sync GPIO31 to SYSCLK (EQEP3I)
|
||||
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 0; // Sync GPIO62 to SYSCLK (EQEP3A)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0; // Sync GPIO63 to SYSCLK (EQEP3B)
|
||||
// GpioCtrlRegs.GPCQSEL1.bit.GPIO64 = 0; // Sync GPIO64 to SYSCLK (EQEP3S)
|
||||
// GpioCtrlRegs.GPCQSEL1.bit.GPIO65 = 0; // Sync GPIO65 to SYSCLK (EQEP3I)
|
||||
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO104 = 0; // Sync GPIO104 to SYSCLK (EQEP3A)
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO105 = 0; // Sync GPIO105 to SYSCLK (EQEP3B)
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO106 = 0; // Sync GPIO106 to SYSCLK (EQEP3S)
|
||||
// GpioCtrlRegs.GPDQSEL1.bit.GPIO107 = 0; // Sync GPIO107 to SYSCLK (EQEP3I)
|
||||
|
||||
//
|
||||
// Configure EQEP-1 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EQEP3 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
|
||||
// GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A
|
||||
// GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B
|
||||
// GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S
|
||||
// GpioCtrlRegs.GPAGMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I
|
||||
|
||||
GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 1; // Configure GPIO28 as EQEP3A
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 2; // Configure GPIO28 as EQEP3A
|
||||
GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 1; // Configure GPIO29 as EQEP3B
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 2; // Configure GPIO29 as EQEP3B
|
||||
GpioCtrlRegs.GPAGMUX2.bit.GPIO30 = 1; // Configure GPIO30 as EQEP3S
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 2; // Configure GPIO30 as EQEP3S
|
||||
GpioCtrlRegs.GPAGMUX2.bit.GPIO31 = 1; // Configure GPIO31 as EQEP3I
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 2; // Configure GPIO31 as EQEP3I
|
||||
|
||||
// GpioCtrlRegs.GPBGMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A
|
||||
// GpioCtrlRegs.GPBGMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B
|
||||
// GpioCtrlRegs.GPCGMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S
|
||||
// GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S
|
||||
// GpioCtrlRegs.GPCGMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I
|
||||
// GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I
|
||||
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S
|
||||
// GpioCtrlRegs.GPDGMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I
|
||||
// GpioCtrlRegs.GPDMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,458 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Emif.c
|
||||
//
|
||||
// TITLE: F2837xD EMIF Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// Emif1Initialize - This function initializes the EMIF1 to a known state.
|
||||
//
|
||||
void Emif1Initialize(void)
|
||||
{
|
||||
EALLOW;
|
||||
//
|
||||
// Perform a Module soft reset on EMIF
|
||||
//
|
||||
#ifdef CPU1
|
||||
DevCfgRegs.SOFTPRES1.all = 0x1;
|
||||
__asm (" nop");
|
||||
DevCfgRegs.SOFTPRES1.all = 0x0;
|
||||
#endif
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// Emif2Initialize - This function initializes the EMIF2 to a known state.
|
||||
//
|
||||
void Emif2Initialize(void)
|
||||
{
|
||||
EALLOW;
|
||||
//
|
||||
// Perform a Module soft reset on EMIF
|
||||
//
|
||||
#ifdef CPU1
|
||||
DevCfgRegs.SOFTPRES1.all = 0x2;
|
||||
__asm (" nop");
|
||||
DevCfgRegs.SOFTPRES1.all = 0x0;
|
||||
#endif
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// ASync_wait_config - Async wait configuration function
|
||||
//
|
||||
void ASync_wait_config(Uint16 inst, Uint16 wait_count, Uint16 wait_polarity)
|
||||
{
|
||||
if (inst == 0)
|
||||
{
|
||||
//
|
||||
// 7:0 Maximum Extended Wait cycles.
|
||||
//
|
||||
Emif1Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count;
|
||||
|
||||
//
|
||||
// 28 Wait Polarity for pad_wait_i[0].
|
||||
//
|
||||
Emif1Regs.ASYNC_WCCR.bit.WP0 = wait_polarity;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// 7:0 Maximum Extended Wait cycles.
|
||||
//
|
||||
Emif2Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count;
|
||||
|
||||
//
|
||||
// 28 Wait Polarity for pad_wait_i[0].
|
||||
//
|
||||
Emif2Regs.ASYNC_WCCR.bit.WP0 = wait_polarity;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// ASync_cs2_config - Async CS2 Configuration
|
||||
//
|
||||
void ASync_cs2_config(Uint16 inst, Uint16 async_mem_data_width,
|
||||
Uint16 turn_around_time, Uint16 r_hold_time,
|
||||
Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold,
|
||||
Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait,
|
||||
Uint16 strobe_sel)
|
||||
{
|
||||
if (inst == 0)
|
||||
{
|
||||
//
|
||||
// 1:0 Asynchronous Memory Size.
|
||||
// 3:2 Turn Around cycles.
|
||||
// 6:4 Read Strobe Hold cycles.
|
||||
// 12:7 Read Strobe Duration cycles.
|
||||
// 16:13 Read Strobe Setup cycles.
|
||||
// 19:17 Write Strobe Hold cycles.
|
||||
// 25:20 Write Strobe Duration cycles.
|
||||
// 29:26 Write Strobe Setup cycles.
|
||||
// 30 Extend Wait mode.
|
||||
// 31 Select Strobe mode.
|
||||
//
|
||||
Emif1Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width;
|
||||
Emif1Regs.ASYNC_CS2_CR.bit.TA= turn_around_time;
|
||||
Emif1Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time;
|
||||
Emif1Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time;
|
||||
Emif1Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup;
|
||||
Emif1Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold;
|
||||
Emif1Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe;
|
||||
Emif1Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup;
|
||||
Emif1Regs.ASYNC_CS2_CR.bit.EW = extend_wait;
|
||||
Emif1Regs.ASYNC_CS2_CR.bit.SS = strobe_sel;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// 1:0 Asynchronous Memory Size.
|
||||
// 3:2 Turn Around cycles.
|
||||
// 6:4 Read Strobe Hold cycles.
|
||||
// 12:7 Read Strobe Duration cycles.
|
||||
// 16:13 Read Strobe Setup cycles.
|
||||
// 19:17 Write Strobe Hold cycles.
|
||||
// 25:20 Write Strobe Duration cycles.
|
||||
// 29:26 Write Strobe Setup cycles.
|
||||
// 30 Extend Wait mode.
|
||||
// 31 Select Strobe mode.
|
||||
//
|
||||
Emif2Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width;
|
||||
Emif2Regs.ASYNC_CS2_CR.bit.TA= turn_around_time;
|
||||
Emif2Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time;
|
||||
Emif2Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time;
|
||||
Emif2Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup;
|
||||
Emif2Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold;
|
||||
Emif2Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe;
|
||||
Emif2Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup;
|
||||
Emif2Regs.ASYNC_CS2_CR.bit.EW = extend_wait;
|
||||
Emif2Regs.ASYNC_CS2_CR.bit.SS = strobe_sel;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// ASync_cs3_config - Async CS3 Configuration
|
||||
//
|
||||
void ASync_cs3_config(Uint16 inst, Uint16 async_mem_data_width,
|
||||
Uint16 turn_around_time, Uint16 r_hold_time,
|
||||
Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold,
|
||||
Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait,
|
||||
Uint16 strobe_sel)
|
||||
{
|
||||
//
|
||||
// 1:0 Asynchronous Memory Size.
|
||||
// 3:2 Turn Around cycles.
|
||||
// 6:4 Read Strobe Hold cycles.
|
||||
// 12:7 Read Strobe Duration cycles.
|
||||
// 16:13 Read Strobe Setup cycles.
|
||||
// 19:17 Write Strobe Hold cycles.
|
||||
// 25:20 Write Strobe Duration cycles.
|
||||
// 29:26 Write Strobe Setup cycles.
|
||||
// 30 Extend Wait mode.
|
||||
// 31 Select Strobe mode.
|
||||
//
|
||||
Emif1Regs.ASYNC_CS3_CR.bit.ASIZE = async_mem_data_width;
|
||||
Emif1Regs.ASYNC_CS3_CR.bit.TA= turn_around_time;
|
||||
Emif1Regs.ASYNC_CS3_CR.bit.R_HOLD= r_hold_time;
|
||||
Emif1Regs.ASYNC_CS3_CR.bit.R_STROBE = r_strobe_time;
|
||||
Emif1Regs.ASYNC_CS3_CR.bit.R_SETUP = r_setup;
|
||||
Emif1Regs.ASYNC_CS3_CR.bit.W_HOLD = w_hold;
|
||||
Emif1Regs.ASYNC_CS3_CR.bit.W_STROBE = w_strobe;
|
||||
Emif1Regs.ASYNC_CS3_CR.bit.W_SETUP = w_setup;
|
||||
Emif1Regs.ASYNC_CS3_CR.bit.EW = extend_wait;
|
||||
Emif1Regs.ASYNC_CS3_CR.bit.SS = strobe_sel;
|
||||
}
|
||||
|
||||
//
|
||||
// ASync_cs4_config - Async CS4 Configuration
|
||||
//
|
||||
void ASync_cs4_config(Uint16 inst, Uint16 async_mem_data_width,
|
||||
Uint16 turn_around_time, Uint16 r_hold_time,
|
||||
Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold,
|
||||
Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait,
|
||||
Uint16 strobe_sel)
|
||||
{
|
||||
//
|
||||
// 1:0 Asynchronous Memory Size.
|
||||
// 3:2 Turn Around cycles.
|
||||
// 6:4 Read Strobe Hold cycles.
|
||||
// 12:7 Read Strobe Duration cycles.
|
||||
// 16:13 Read Strobe Setup cycles.
|
||||
// 19:17 Write Strobe Hold cycles.
|
||||
// 25:20 Write Strobe Duration cycles.
|
||||
// 29:26 Write Strobe Setup cycles.
|
||||
// 30 Extend Wait mode.
|
||||
// 31 Select Strobe mode.
|
||||
//
|
||||
Emif1Regs.ASYNC_CS4_CR.bit.ASIZE = async_mem_data_width;
|
||||
Emif1Regs.ASYNC_CS4_CR.bit.TA= turn_around_time;
|
||||
Emif1Regs.ASYNC_CS4_CR.bit.R_HOLD= r_hold_time;
|
||||
Emif1Regs.ASYNC_CS4_CR.bit.R_STROBE = r_strobe_time;
|
||||
Emif1Regs.ASYNC_CS4_CR.bit.R_SETUP = r_setup;
|
||||
Emif1Regs.ASYNC_CS4_CR.bit.W_HOLD = w_hold;
|
||||
Emif1Regs.ASYNC_CS4_CR.bit.W_STROBE = w_strobe;
|
||||
Emif1Regs.ASYNC_CS4_CR.bit.W_SETUP = w_setup;
|
||||
Emif1Regs.ASYNC_CS4_CR.bit.EW = extend_wait;
|
||||
Emif1Regs.ASYNC_CS4_CR.bit.SS = strobe_sel;
|
||||
}
|
||||
|
||||
#ifdef CPU1
|
||||
//
|
||||
// setup_emif1_pinmux_async_16bit - function for EMIF1 GPIO pin setup
|
||||
//
|
||||
void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel)
|
||||
{
|
||||
Uint16 i;
|
||||
|
||||
for (i=28; i<=52; i++)
|
||||
{
|
||||
if ((i != 42) && (i != 43))
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,2);
|
||||
}
|
||||
}
|
||||
for (i=63; i<=87; i++)
|
||||
{
|
||||
if (i != 84)
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,2);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_SetupPinMux(88,cpu_sel,3);
|
||||
GPIO_SetupPinMux(89,cpu_sel,3);
|
||||
GPIO_SetupPinMux(90,cpu_sel,3);
|
||||
GPIO_SetupPinMux(91,cpu_sel,3);
|
||||
GPIO_SetupPinMux(92,cpu_sel,3);
|
||||
GPIO_SetupPinMux(93,cpu_sel,3);
|
||||
GPIO_SetupPinMux(94,cpu_sel,2);
|
||||
|
||||
//
|
||||
//setup async mode and enable pull-ups for Data pins
|
||||
//
|
||||
for (i=69; i<=85; i++)
|
||||
{
|
||||
if (i != 84)
|
||||
{
|
||||
GPIO_SetupPinOptions(i,0,0x31); // GPIO_ASYNC||GPIO_PULLUP
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// setup_emif1_pinmux_async_32bit - Setup pinmux for 32bit async
|
||||
//
|
||||
void setup_emif1_pinmux_async_32bit(Uint16 cpu_sel)
|
||||
{
|
||||
Uint16 i;
|
||||
|
||||
for (i=28; i<=87; i++)
|
||||
{
|
||||
if ((i != 42) && (i != 43) && (i != 84))
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,2);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_SetupPinMux(88,cpu_sel,3);
|
||||
GPIO_SetupPinMux(89,cpu_sel,3);
|
||||
GPIO_SetupPinMux(90,cpu_sel,3);
|
||||
GPIO_SetupPinMux(91,cpu_sel,3);
|
||||
GPIO_SetupPinMux(92,cpu_sel,3);
|
||||
GPIO_SetupPinMux(93,cpu_sel,3);
|
||||
GPIO_SetupPinMux(94,cpu_sel,2);
|
||||
|
||||
//
|
||||
//setup async mode for Data pins
|
||||
//
|
||||
for (i=53; i<=85; i++)
|
||||
{
|
||||
if (i != 84)
|
||||
{
|
||||
GPIO_SetupPinOptions(i,0,0x31);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// setup_emif2_pinmux_async_16bit - function for EMIF1 GPIO pin setup
|
||||
//
|
||||
void setup_emif2_pinmux_async_16bit(Uint16 cpu_sel)
|
||||
{
|
||||
Uint16 i;
|
||||
|
||||
for (i=96; i<=121; i++)
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,3);
|
||||
}
|
||||
|
||||
for (i=53; i<=68; i++)
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,3);
|
||||
}
|
||||
|
||||
//
|
||||
//setup async mode for Data pins
|
||||
//
|
||||
for (i=53; i<=68; i++)
|
||||
{
|
||||
GPIO_SetupPinOptions(i,0,0x31);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// setup_emif1_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM
|
||||
//
|
||||
void setup_emif1_pinmux_sdram_16bit(Uint16 cpu_sel)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=29; i<=52; i++)
|
||||
{
|
||||
if ((i != 42) && (i != 43))
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,2);
|
||||
}
|
||||
}
|
||||
|
||||
for (i=69; i<=85; i++)
|
||||
{
|
||||
if (i != 84)
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,2);
|
||||
}
|
||||
}
|
||||
|
||||
for(i=86; i<=93; i++)
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,3);
|
||||
}
|
||||
|
||||
//
|
||||
//configure Data pins for Async mode
|
||||
//
|
||||
for (i = 69; i <= 85; i++)
|
||||
{
|
||||
if (i != 84)
|
||||
{
|
||||
GPIO_SetupPinOptions(i,0,0x31);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_SetupPinOptions(88,0,0x31);
|
||||
GPIO_SetupPinOptions(89,0,0x31);
|
||||
GPIO_SetupPinOptions(90,0,0x31);
|
||||
GPIO_SetupPinOptions(91,0,0x31);
|
||||
}
|
||||
|
||||
//
|
||||
// setup_emif2_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM
|
||||
//
|
||||
void setup_emif2_pinmux_sdram_16bit(Uint16 cpu_sel)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=53; i<=68; i++)
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,3);
|
||||
}
|
||||
for (i=96; i<=121; i++)
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,3);
|
||||
}
|
||||
|
||||
//
|
||||
//configure Data pins for Async mode
|
||||
//
|
||||
for (i = 53; i <= 68; i++)
|
||||
{
|
||||
GPIO_SetupPinOptions(i,0,0x31);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// setup_emif1_pinmux_sdram_32bit - Setup pinmux for 32bit SDRAM
|
||||
//
|
||||
void setup_emif1_pinmux_sdram_32bit(Uint16 cpu_sel)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=28; i<=85; i++)
|
||||
{
|
||||
if ((i != 42) && (i != 43) && (i != 84))
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,2);
|
||||
}
|
||||
}
|
||||
|
||||
for(i=86; i<=93; i++)
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,3);
|
||||
}
|
||||
|
||||
GPIO_SetupPinMux(94,cpu_sel,2);
|
||||
|
||||
//
|
||||
//configure Data pins for Async mode
|
||||
//
|
||||
for (i = 53; i <= 85; i++)
|
||||
{
|
||||
if (i != 84)
|
||||
{
|
||||
GPIO_SetupPinOptions(i,0,0x31);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_SetupPinOptions(88,0,0x31);
|
||||
GPIO_SetupPinOptions(89,0,0x31);
|
||||
GPIO_SetupPinOptions(90,0,0x31);
|
||||
GPIO_SetupPinOptions(91,0,0x31);
|
||||
}
|
||||
|
||||
#endif // CPU1
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,506 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Gpio.c
|
||||
//
|
||||
// TITLE: GPIO module support functions
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
//Low-level functions for GPIO configuration (CPU1 only)
|
||||
//
|
||||
|
||||
#ifdef CPU1
|
||||
//
|
||||
// InitGpio - Sets all pins to be muxed to GPIO in input mode.
|
||||
// Also resets CPU control to CPU1 and disables open
|
||||
// drain and polarity inversion and sets the qualification to
|
||||
// synchronous. Also unlocks all GPIOs. Only one CPU should call
|
||||
// this function.
|
||||
//
|
||||
void InitGpio()
|
||||
{
|
||||
volatile Uint32 *gpioBaseAddr;
|
||||
Uint16 regOffset;
|
||||
|
||||
//
|
||||
//Disable pin locks
|
||||
//
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPALOCK.all = 0x00000000;
|
||||
GpioCtrlRegs.GPBLOCK.all = 0x00000000;
|
||||
GpioCtrlRegs.GPCLOCK.all = 0x00000000;
|
||||
GpioCtrlRegs.GPDLOCK.all = 0x00000000;
|
||||
GpioCtrlRegs.GPELOCK.all = 0x00000000;
|
||||
GpioCtrlRegs.GPFLOCK.all = 0x00000000;
|
||||
|
||||
//
|
||||
// Fill all registers with zeros. Writing to each register separately
|
||||
// for six GPIO modules would make this function *very* long.
|
||||
// Fortunately, we'd be writing them all with zeros anyway, so this
|
||||
// saves a lot of space.
|
||||
//
|
||||
gpioBaseAddr = (Uint32 *)&GpioCtrlRegs;
|
||||
for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++)
|
||||
{
|
||||
//
|
||||
//Hack to avoid enabling pull-ups on all pins. GPyPUD is offset
|
||||
//0x0C in each register group of 0x40 words. Since this is a
|
||||
//32-bit pointer, the addresses must be divided by 2.
|
||||
//
|
||||
if (regOffset % (0x40/2) != (0x0C/2))
|
||||
{
|
||||
gpioBaseAddr[regOffset] = 0x00000000;
|
||||
}
|
||||
}
|
||||
|
||||
gpioBaseAddr = (Uint32 *)&GpioDataRegs;
|
||||
for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++)
|
||||
{
|
||||
gpioBaseAddr[regOffset] = 0x00000000;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The
|
||||
// appropriate parameters can be found in the GPIO Muxed
|
||||
// Pins table(4.4) in the datasheet. Use the GPIO index
|
||||
// row (0 to 15) to select a muxing option for the GPIO.
|
||||
//
|
||||
void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition)
|
||||
{
|
||||
volatile Uint32 *gpioBaseAddr;
|
||||
volatile Uint32 *mux, *gmux, *csel;
|
||||
Uint16 pin32, pin16, pin8;
|
||||
|
||||
pin32 = gpioNumber % 32;
|
||||
pin16 = gpioNumber % 16;
|
||||
pin8 = gpioNumber % 8;
|
||||
gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
|
||||
|
||||
//
|
||||
//Sanity check for valid cpu and peripheral values
|
||||
//
|
||||
if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF)
|
||||
return;
|
||||
|
||||
//
|
||||
//Create pointers to the appropriate registers. This is a workaround
|
||||
//for the way GPIO registers are defined. The standard definition
|
||||
//in the header file makes it very easy to do named accesses of one
|
||||
//register or bit, but hard to do arbitrary numerical accesses. It's
|
||||
//easier to have an array of GPIO modules with identical registers,
|
||||
//including arrays for multi-register groups like GPyCSEL1-4. But
|
||||
//the header file doesn't define anything we can turn into an array,
|
||||
//so manual pointer arithmetic is used instead.
|
||||
//
|
||||
mux = gpioBaseAddr + GPYMUX + pin32/16;
|
||||
gmux = gpioBaseAddr + GPYGMUX + pin32/16;
|
||||
csel = gpioBaseAddr + GPYCSEL + pin32/8;
|
||||
|
||||
//
|
||||
//Now for the actual function
|
||||
//
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
//To change the muxing, set the peripheral mux to 0/GPIO first to avoid
|
||||
//glitches, then change the group mux, then set the peripheral mux to
|
||||
//its target value. Finally, set the CPU select. This procedure is
|
||||
//described in the TRM. Unfortunately, since we don't know the pin in
|
||||
//advance we can't hardcode a bitfield reference, so there's some
|
||||
//tricky bit twiddling here.
|
||||
//
|
||||
*mux &= ~(0x3UL << (2*pin16));
|
||||
*gmux &= ~(0x3UL << (2*pin16));
|
||||
*gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16);
|
||||
*mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16);
|
||||
|
||||
*csel &= ~(0x3L << (4*pin8));
|
||||
*csel |= (Uint32)(cpu & 0x3L) << (4*pin8);
|
||||
|
||||
//
|
||||
//WARNING: This code does not touch the analog mode select registers,
|
||||
//which are needed to give the USB module control of its IOs.
|
||||
//
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_SetupPinOptions - Setup up the GPIO input/output options for the
|
||||
// specified pin.
|
||||
//
|
||||
//The flags are a 16-bit mask produced by ORing together options.
|
||||
//For input pins, the valid flags are:
|
||||
//GPIO_PULLUP Enable pull-up
|
||||
//GPIO_INVERT Enable input polarity inversion
|
||||
//GPIO_SYNC Synchronize the input latch to PLLSYSCLK
|
||||
// (default -- you don't need to specify this)
|
||||
//GPIO_QUAL3 Use 3-sample qualification
|
||||
//GPIO_QUAL6 Use 6-sample qualification
|
||||
//GPIO_ASYNC Do not use synchronization or qualification
|
||||
//(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed)
|
||||
//
|
||||
//For output pins, the valid flags are:
|
||||
//GPIO_OPENDRAIN Output in open drain mode
|
||||
//GPIO_PULLUP If open drain enabled, also enable the pull-up
|
||||
//and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above.
|
||||
//
|
||||
//With no flags, the default input state is synchronous with no
|
||||
//pull-up or polarity inversion. The default output state is
|
||||
//the standard digital output.
|
||||
//
|
||||
void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags)
|
||||
{
|
||||
volatile Uint32 *gpioBaseAddr;
|
||||
volatile Uint32 *dir, *pud, *inv, *odr, *qsel;
|
||||
Uint32 pin32, pin16, pinMask, qual;
|
||||
|
||||
pin32 = gpioNumber % 32;
|
||||
pin16 = gpioNumber % 16;
|
||||
pinMask = 1UL << pin32;
|
||||
gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
|
||||
|
||||
//
|
||||
//Create pointers to the appropriate registers. This is a workaround
|
||||
//for the way GPIO registers are defined. The standard definition
|
||||
//in the header file makes it very easy to do named accesses of one
|
||||
//register or bit, but hard to do arbitrary numerical accesses. It's
|
||||
//easier to have an array of GPIO modules with identical registers,
|
||||
//including arrays for multi-register groups like GPyQSEL1-2. But
|
||||
//the header file doesn't define anything we can turn into an array,
|
||||
//so manual pointer arithmetic is used instead.
|
||||
//
|
||||
dir = gpioBaseAddr + GPYDIR;
|
||||
pud = gpioBaseAddr + GPYPUD;
|
||||
inv = gpioBaseAddr + GPYINV;
|
||||
odr = gpioBaseAddr + GPYODR;
|
||||
qsel = gpioBaseAddr + GPYQSEL + pin32/16;
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
//Set the data direction
|
||||
//
|
||||
*dir &= ~pinMask;
|
||||
if (output == 1)
|
||||
{
|
||||
//
|
||||
//Output, with optional open drain mode and pull-up
|
||||
//
|
||||
*dir |= pinMask;
|
||||
|
||||
//
|
||||
//Enable open drain if necessary
|
||||
//
|
||||
if (flags & GPIO_OPENDRAIN)
|
||||
{
|
||||
*odr |= pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*odr &= ~pinMask;
|
||||
}
|
||||
|
||||
//
|
||||
//Enable pull-up if necessary. Open drain mode must be active.
|
||||
//
|
||||
if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP))
|
||||
{
|
||||
*pud &= ~pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pud |= pinMask;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
//Input, with optional pull-up, qualification, and polarity
|
||||
//inversion
|
||||
//
|
||||
*dir &= ~pinMask;
|
||||
|
||||
//
|
||||
//Enable pull-up if necessary
|
||||
//
|
||||
if (flags & GPIO_PULLUP)
|
||||
{
|
||||
*pud &= ~pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pud |= pinMask;
|
||||
}
|
||||
|
||||
//
|
||||
//Invert polarity if necessary
|
||||
//
|
||||
if (flags & GPIO_INVERT)
|
||||
{
|
||||
*inv |= pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*inv &= ~pinMask;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
//Extract the qualification parameter and load it into the register.
|
||||
//This is also needed for open drain outputs, so we might as well do it
|
||||
//all the time.
|
||||
//
|
||||
qual = (flags & GPIO_ASYNC) / GPIO_QUAL3;
|
||||
*qsel &= ~(0x3L << (2 * pin16));
|
||||
if (qual != 0x0)
|
||||
{
|
||||
*qsel |= qual << (2 * pin16);
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_SetupLock - Enable or disable the GPIO register bit lock for the
|
||||
// specified pin.
|
||||
// The valid flags are:
|
||||
// GPIO_UNLOCK - Unlock the pin setup register bits for
|
||||
// the specified pin
|
||||
// GPIO_LOCK - Lock the pin setup register bits for the
|
||||
// specified pin
|
||||
//
|
||||
void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags)
|
||||
{
|
||||
volatile Uint32 *gpioBaseAddr;
|
||||
volatile Uint32 *lock;
|
||||
Uint32 pin32, pinMask;
|
||||
|
||||
pin32 = gpioNumber % 32;
|
||||
pinMask = 1UL << pin32;
|
||||
gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
|
||||
|
||||
//
|
||||
//Create pointers to the appropriate registers. This is a workaround
|
||||
//for the way GPIO registers are defined. The standard definition
|
||||
//in the header file makes it very easy to do named accesses of one
|
||||
//register or bit, but hard to do arbitrary numerical accesses. It's
|
||||
//easier to have an array of GPIO modules with identical registers,
|
||||
//including arrays for multi-register groups like GPyQSEL1-2. But
|
||||
//the header file doesn't define anything we can turn into an array,
|
||||
//so manual pointer arithmetic is used instead.
|
||||
//
|
||||
lock = gpioBaseAddr + GPYLOCK;
|
||||
|
||||
EALLOW;
|
||||
if(flags)
|
||||
{
|
||||
//Lock the pin
|
||||
*lock |= pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
//Unlock the pin
|
||||
*lock &= ~pinMask;
|
||||
}
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
//External interrupt setup
|
||||
//
|
||||
void GPIO_SetupXINT1Gpio(Uint16 gpioNumber)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
void GPIO_SetupXINT2Gpio(Uint16 gpioNumber)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
void GPIO_SetupXINT3Gpio(Uint16 gpioNumber)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
void GPIO_SetupXINT4Gpio(Uint16 gpioNumber)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
void GPIO_SetupXINT5Gpio(Uint16 gpioNumber)
|
||||
{
|
||||
EALLOW;
|
||||
InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
//GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded
|
||||
// GPIOs on the 176PTP package:
|
||||
// GPIOs Grp Bits
|
||||
// 95-132 C 31
|
||||
// D 31:0
|
||||
// E 4:0
|
||||
// 134-168 E 31:6
|
||||
// F 8:0
|
||||
//
|
||||
void GPIO_EnableUnbondedIOPullupsFor176Pin()
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95
|
||||
GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127
|
||||
GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133
|
||||
GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_EnableUnbondedIOPullupsFor100Pin - Enable pullups for the unbonded
|
||||
// GPIOs on the 100PZ package:
|
||||
// GPIOs Grp Bits
|
||||
// 0-1 A 1:0
|
||||
// 5-9 A 9:5
|
||||
// 22-40 A 31:22
|
||||
// B 8:0
|
||||
// 44-57 B 25:12
|
||||
// 67-68 C 4:3
|
||||
// 74-77 C 13:10
|
||||
// 79-83 C 19:15
|
||||
// 93-168 C 31:29
|
||||
// D 31:0
|
||||
// E 31:0
|
||||
// F 8:0
|
||||
//
|
||||
void GPIO_EnableUnbondedIOPullupsFor100Pin()
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPAPUD.all = ~0xFFC003E3; //GPIOs 0-1, 5-9, 22-31
|
||||
GpioCtrlRegs.GPBPUD.all = ~0x03FFF1FF; //GPIOs 32-40, 44-57
|
||||
GpioCtrlRegs.GPCPUD.all = ~0xE10FBC18; //GPIOs 67-68, 74-77, 79-83, 93-95
|
||||
GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127
|
||||
GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFFF; //GPIOs 128-159
|
||||
GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function
|
||||
// this takes care of enabling IO pullups.
|
||||
//
|
||||
void GPIO_EnableUnbondedIOPullups()
|
||||
{
|
||||
//
|
||||
//bits 8-10 have pin count
|
||||
//
|
||||
unsigned char pin_count = ((DevCfgRegs.PARTIDL.all & 0x00000700) >> 8) ;
|
||||
|
||||
//
|
||||
//5 = 100 pin
|
||||
//6 = 176 pin
|
||||
//7 = 337 pin
|
||||
//
|
||||
if(pin_count == 5)
|
||||
{
|
||||
GPIO_EnableUnbondedIOPullupsFor100Pin();
|
||||
}
|
||||
else if (pin_count == 6)
|
||||
{
|
||||
GPIO_EnableUnbondedIOPullupsFor176Pin();
|
||||
}
|
||||
else
|
||||
{
|
||||
//do nothing - this is 337 pin package
|
||||
}
|
||||
}
|
||||
|
||||
#endif //CPU1
|
||||
|
||||
//
|
||||
// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that
|
||||
// this returns the actual state of the pin, not the state of
|
||||
// the output latch.
|
||||
//
|
||||
Uint16 GPIO_ReadPin(Uint16 gpioNumber)
|
||||
{
|
||||
volatile Uint32 *gpioDataReg;
|
||||
Uint16 pinVal;
|
||||
|
||||
gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET;
|
||||
pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1;
|
||||
|
||||
return pinVal;
|
||||
}
|
||||
|
||||
//
|
||||
// GPIO_WritePin - Set the GPyDAT register bit for the specified pin.
|
||||
//
|
||||
void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal)
|
||||
{
|
||||
volatile Uint32 *gpioDataReg;
|
||||
Uint32 pinMask;
|
||||
|
||||
gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET;
|
||||
pinMask = 1UL << (gpioNumber % 32);
|
||||
|
||||
if (outVal == 0)
|
||||
{
|
||||
gpioDataReg[GPYCLEAR] = pinMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
gpioDataReg[GPYSET] = pinMask;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,301 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_I2C.c
|
||||
//
|
||||
// TITLE: F2837xD I2C Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
//---------------------------------------------------------------------------
|
||||
// Example: I2cAGpioConfig(), I2cBGpioConfig()
|
||||
//---------------------------------------------------------------------------
|
||||
// These functions configures GPIO pins to function as I2C pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
|
||||
#ifdef CPU1
|
||||
//
|
||||
// I2cAGpioConfig - Configure I2CA GPIOs
|
||||
// 'I2caDataClkPin' should be assign with one of the
|
||||
// possible I2C_A SDA - SDL GPIO pin Use defined Macros from
|
||||
// "F2837xD_I2c_defines.h" for assignment
|
||||
//
|
||||
void I2cAGpioConfig(Uint16 I2caDataClkPin)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
switch(I2caDataClkPin)
|
||||
{
|
||||
case I2C_A_GPIO0_GPIO1:
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected I2C pins
|
||||
// Enable pull-up for GPIO0 (SDAA)
|
||||
// Enable pull-up for GPIO1 (SDLA)
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;
|
||||
|
||||
//
|
||||
// Set qualification for the selected I2C pins
|
||||
// Async/no qualification (I/ps sync to SYSCLKOUT by default)
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 3;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3;
|
||||
|
||||
//
|
||||
// Configure which of the possible GPIO pins will be I2C_A pins
|
||||
// using GPIO regs
|
||||
// Configure GPIO0 for SDAA operation
|
||||
// Configure GPIO0 for SDAA operation
|
||||
//
|
||||
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 1;
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 2;
|
||||
|
||||
//
|
||||
// Configure GPIO1 for SDLA operation
|
||||
// Configure GPIO1 for SDLA operation
|
||||
//
|
||||
GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 1;
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2;
|
||||
|
||||
break;
|
||||
|
||||
case I2C_A_GPIO32_GPIO33:
|
||||
//
|
||||
// Enable internal pull-up for the selected I2C pins
|
||||
//
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0;
|
||||
|
||||
//
|
||||
// Set qualification for the selected I2C pins
|
||||
//
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3;
|
||||
|
||||
//
|
||||
// Configure which of the possible GPIO pins will be I2C_A pins
|
||||
// using GPIO regs
|
||||
//
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1;
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1;
|
||||
|
||||
break;
|
||||
|
||||
case I2C_A_GPIO42_GPIO43:
|
||||
//
|
||||
// Enable internal pull-up for the selected I2C pins
|
||||
//
|
||||
|
||||
//
|
||||
// Set qualification for the selected I2C pins
|
||||
//
|
||||
|
||||
//
|
||||
// Configure which of the possible GPIO pins will be I2C_A pins
|
||||
// using GPIO regs
|
||||
//
|
||||
break;
|
||||
|
||||
case I2C_A_GPIO91_GPIO92:
|
||||
//
|
||||
// Enable internal pull-up for the selected I2C pins
|
||||
//
|
||||
GpioCtrlRegs.GPCPUD.bit.GPIO91 = 0;
|
||||
GpioCtrlRegs.GPCPUD.bit.GPIO92 = 0;
|
||||
|
||||
//
|
||||
// Set qualification for the selected I2C pins
|
||||
//
|
||||
GpioCtrlRegs.GPCQSEL2.bit.GPIO91 = 3;
|
||||
GpioCtrlRegs.GPCQSEL2.bit.GPIO92 = 3;
|
||||
|
||||
//
|
||||
// Configure which of the possible GPIO pins will be I2C_A pins
|
||||
// using GPIO regs
|
||||
//
|
||||
GpioCtrlRegs.GPCGMUX2.bit.GPIO91 = 1;
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO91 = 2;
|
||||
GpioCtrlRegs.GPCGMUX2.bit.GPIO92 = 1;
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO92 = 2;
|
||||
break;
|
||||
|
||||
case I2C_A_GPIO63104_GPIO105:
|
||||
//
|
||||
// Enable internal pull-up for the selected I2C pins
|
||||
//
|
||||
|
||||
//
|
||||
// Set qualification for the selected I2C pins
|
||||
//
|
||||
|
||||
//
|
||||
// Configure which of the possible GPIO pins will be I2C_A pins
|
||||
// using GPIO regs
|
||||
//
|
||||
break;
|
||||
|
||||
default:
|
||||
|
||||
break;
|
||||
|
||||
} // End of Switch
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// I2cBGpioConfig - Configure I2CB GPIOs
|
||||
// 'I2cbDataClkPin' should be assign with one of the possible
|
||||
// I2C_B SDA - SDL GPIO pin Use defined Macros from
|
||||
// "F2837xD_I2c_defines.h" for assignment
|
||||
//
|
||||
void I2cBGpioConfig(Uint16 I2cbDataClkPin)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
switch(I2cbDataClkPin)
|
||||
{
|
||||
case I2C_B_GPIO2_GPIO3:
|
||||
//
|
||||
// Enable internal pull-up for the selected I2C pins
|
||||
// Enable pull-up for GPIO2 (SDAB)
|
||||
// Enable pull-up for GPIO3 (SDLB)
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0;
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;
|
||||
|
||||
//
|
||||
// Set qualification for the selected I2C pins
|
||||
// Async/no qualification (I/ps sync to SYSCLKOUT by default)
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 3;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3;
|
||||
|
||||
//
|
||||
// Configure which of the possible GPIO pins will be I2C_B pins
|
||||
// using GPIO regs
|
||||
// Configure GPIO2 for SDAB operation
|
||||
// Configure GPIO3 for SDAB operation
|
||||
// Configure GPIO1 for SDLB operation
|
||||
// Configure GPIO1 for SDLB operation
|
||||
//
|
||||
GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 1;
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 2;
|
||||
|
||||
GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 1;
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2;
|
||||
|
||||
break;
|
||||
|
||||
case I2C_B_GPIO134_GPIO35:
|
||||
//
|
||||
// Enable internal pull-up for the selected I2C pins
|
||||
//
|
||||
|
||||
//
|
||||
// Set qualification for the selected I2C pins
|
||||
//
|
||||
|
||||
//
|
||||
// Configure which of the possible GPIO pins will be I2C_B pins
|
||||
// using GPIO regs
|
||||
//
|
||||
break;
|
||||
|
||||
case I2C_B_GPIO40_GPIO41:
|
||||
//
|
||||
// Enable internal pull-up for the selected I2C pins
|
||||
//
|
||||
|
||||
//
|
||||
// Set qualification for the selected I2C pins
|
||||
//
|
||||
|
||||
//
|
||||
// Configure which of the possible GPIO pins will be I2C_B pins
|
||||
// using GPIO regs
|
||||
//
|
||||
break;
|
||||
|
||||
case I2C_B_GPIO66_GPIO69:
|
||||
//
|
||||
// Enable internal pull-up for the selected I2C pins
|
||||
//
|
||||
GpioCtrlRegs.GPCPUD.bit.GPIO66 = 0; //SDAB
|
||||
GpioCtrlRegs.GPCPUD.bit.GPIO69 = 0; //SCLB
|
||||
|
||||
//
|
||||
// Set qualification for the selected I2C pins
|
||||
//
|
||||
GpioCtrlRegs.GPCQSEL1.bit.GPIO66 = 3;
|
||||
GpioCtrlRegs.GPCQSEL1.bit.GPIO69 = 3;
|
||||
|
||||
//
|
||||
// Configure which of the possible GPIO pins will be I2C_B pins
|
||||
// using GPIO regs
|
||||
//
|
||||
GpioCtrlRegs.GPCGMUX1.bit.GPIO66 = 1; //0x6
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 2;
|
||||
|
||||
GpioCtrlRegs.GPCGMUX1.bit.GPIO69 = 1; //0x6
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 2;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
|
||||
}
|
||||
EDIS;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,216 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Ipc.c
|
||||
//
|
||||
// TITLE: Inter-Processor Communication module support functions
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
#include <string.h>
|
||||
|
||||
//
|
||||
// InitIpc - Initialize all IPC registers and clear all flags
|
||||
//
|
||||
void InitIpc()
|
||||
{
|
||||
//
|
||||
//Clear sent flags. Received flags must not be cleared locally
|
||||
//to handle the case where the remote CPU starts executing first.
|
||||
//In this case, a remote flag could be sent correctly and be
|
||||
//incorrectly cleared by this function. Unfortunately, we're
|
||||
//still left with a startup synchronization problem if the
|
||||
//remote CPU has flags left over from a previous run. There's
|
||||
//probably a better way of handling this.
|
||||
//
|
||||
IpcRegs.IPCCLR.all = 0xFFFFFFFF;
|
||||
|
||||
//
|
||||
//Clear commands
|
||||
//
|
||||
IpcRegs.IPCSENDCOM = 0;
|
||||
IpcRegs.IPCSENDADDR = 0;
|
||||
IpcRegs.IPCSENDDATA = 0;
|
||||
IpcRegs.IPCLOCALREPLY = 0;
|
||||
|
||||
//
|
||||
//Clear boot status and pump semaphore
|
||||
//
|
||||
#if defined(CPU1)
|
||||
IpcRegs.IPCBOOTMODE = 0;
|
||||
#elif defined(CPU2)
|
||||
IpcRegs.IPCBOOTSTS = 0;
|
||||
#endif
|
||||
ReleaseFlashPump();
|
||||
}
|
||||
|
||||
//
|
||||
// ReadIpcTimer - Read the current IPC timer value. The low register must be
|
||||
// read first to latch a value in the high register.
|
||||
//
|
||||
unsigned long long ReadIpcTimer()
|
||||
{
|
||||
Uint32 low, high;
|
||||
|
||||
low = IpcRegs.IPCCOUNTERL;
|
||||
high = IpcRegs.IPCCOUNTERH;
|
||||
return ((unsigned long long)high << 32) | (unsigned long long)low;
|
||||
}
|
||||
|
||||
//
|
||||
// SendIpcData - Copy data into the IPC send message RAM for this CPU and set
|
||||
// a flag. If the specified 16-bit word length is greater than
|
||||
// the size of the message RAM, the data is truncated.
|
||||
//
|
||||
void SendIpcData(void *data, Uint16 word_length, Uint16 flag)
|
||||
{
|
||||
word_length = (word_length < MSG_RAM_SIZE) ? word_length : MSG_RAM_SIZE;
|
||||
|
||||
memcpy(SEND_MSG_RAM, data, word_length);
|
||||
|
||||
if (flag != NO_IPC_FLAG)
|
||||
{
|
||||
SendIpcFlag(flag);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// RecvIpcData - Copy data out of the IPC receive message RAM for this CPU. If
|
||||
// the specified 16-bit word length is greater than the size of
|
||||
// the message RAM, the data is truncated.
|
||||
//
|
||||
void RecvIpcData(void *recv_buf, Uint16 word_length)
|
||||
{
|
||||
word_length = (word_length < MSG_RAM_SIZE) ? word_length : MSG_RAM_SIZE;
|
||||
memcpy(recv_buf, RECV_MSG_RAM, word_length);
|
||||
}
|
||||
|
||||
//
|
||||
// FillIpcSendData - Fill the IPC send message RAM for this CPU with a constant
|
||||
// value
|
||||
//
|
||||
void FillIpcSendData(Uint16 fill_data)
|
||||
{
|
||||
memset(SEND_MSG_RAM, fill_data, MSG_RAM_SIZE);
|
||||
}
|
||||
|
||||
//
|
||||
// SendIpcCommand - Write the send command, address, and data registers with
|
||||
// the specified values, then set an IPC flag.
|
||||
//
|
||||
void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, Uint16 flag)
|
||||
{
|
||||
IpcRegs.IPCSENDCOM = command;
|
||||
IpcRegs.IPCSENDADDR = address;
|
||||
IpcRegs.IPCSENDDATA = data;
|
||||
|
||||
if (flag != NO_IPC_FLAG)
|
||||
{
|
||||
SendIpcFlag(flag);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// SendIpcFlag - Set an IPC flag bit for the other CPU. Flags 0-3 will generate
|
||||
// PIE interrupts.
|
||||
//
|
||||
void SendIpcFlag(Uint16 flag)
|
||||
{
|
||||
IpcRegs.IPCSET.all = 1UL << flag;
|
||||
}
|
||||
|
||||
//
|
||||
// AckIpcFlag - Acknowledge/clear a received IPC flag
|
||||
//
|
||||
void AckIpcFlag(Uint16 flag)
|
||||
{
|
||||
IpcRegs.IPCACK.all = 1UL << flag;
|
||||
}
|
||||
|
||||
//
|
||||
// CancelIpcFlag - Clear a sent IPC flag bit before the other CPU acknowledges
|
||||
// it. You will normally never use this function. To clear a
|
||||
// received flag, call AckIpcFlag() instead.
|
||||
//
|
||||
void CancelIpcFlag(Uint16 flag)
|
||||
{
|
||||
IpcRegs.IPCCLR.all = 1UL << flag;
|
||||
}
|
||||
|
||||
//
|
||||
// WaitForIpcFlag - Wait for any IPC flag in the specified mask to be set.
|
||||
// WARNING: If you use this function to wait for an IPC
|
||||
// interrupt, you must not clear the IPC flag in the interrupt
|
||||
// handler. Otherwise, this function will never return.
|
||||
//
|
||||
void WaitForIpcFlag(Uint16 flag)
|
||||
{
|
||||
//
|
||||
//WARNING: Don't use this function to wait for an IPC interrupt!
|
||||
//
|
||||
while ((IpcRegs.IPCSTS.all & (1UL << flag)) == 0x00000000) {;}
|
||||
}
|
||||
|
||||
//
|
||||
// WaitForIpcAck - Wait for any IPC flag in the specified mask to be
|
||||
// acknowledged.
|
||||
//
|
||||
void WaitForIpcAck(Uint16 flag)
|
||||
{
|
||||
while ((IpcRegs.IPCFLG.all & (1UL << flag)) != 0x00000000) {;}
|
||||
}
|
||||
|
||||
//
|
||||
// IpcSync - Synchronize the two CPUs. Neither CPU will return from this
|
||||
// function call before the other one enters it. Must be called with
|
||||
// the same flag number on both CPUs.
|
||||
//
|
||||
void IpcSync(Uint16 flag)
|
||||
{
|
||||
SendIpcFlag(flag);
|
||||
WaitForIpcFlag(flag);
|
||||
AckIpcFlag(flag);
|
||||
WaitForIpcAck(flag);
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -1,469 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Ipc_Driver_Util.c
|
||||
//
|
||||
// TITLE: F2837xD Inter-Processor Communication (IPC) API Driver Utility
|
||||
// Functions
|
||||
//
|
||||
// DESCRIPTION:
|
||||
// API functions for inter-processor communications between the
|
||||
// Local and Remote CPU system.
|
||||
// The driver functions in this file are available only as
|
||||
// sample functions for application development. Due to the generic
|
||||
// nature of these functions and the cycle overhead inherent to a
|
||||
// function call, the code is not intended to be used in cases where
|
||||
// maximum efficiency is required in a system.
|
||||
//
|
||||
// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2
|
||||
// cores use this code.
|
||||
// The active debug CPU will be referred to as Local CPU and the other
|
||||
// CPU will be referred to as Remote CPU.
|
||||
// When using this source code in CPU1, the term "local"
|
||||
// will mean CPU1 and the term "remote" CPU will be mean CPU2.
|
||||
// When using this source code in CPU2, the term "local"
|
||||
// will mean CPU2 and the term "remote" CPU will be mean CPU1.
|
||||
//
|
||||
// The abbreviations LtoR and RtoL within the function names mean
|
||||
// Local to Remote and Remote to Local respectively.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup ipc_util_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_GlobalPrototypes.h"
|
||||
#include "F2837xD_Gpio_defines.h"
|
||||
#include "F2837xD_Ipc_drivers.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Local CPU Acknowledges Remote to Local IPC Flag.
|
||||
//!
|
||||
//! \param ulFlags specifies the IPC flag mask for flags being acknowledged.
|
||||
//!
|
||||
//! This function will allow the Local CPU system to acknowledge/clear the IPC
|
||||
//! flag set by the Remote CPU system. The \e ulFlags parameter can be any of
|
||||
//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IPCRtoLFlagAcknowledge (uint32_t ulFlags)
|
||||
{
|
||||
IpcRegs.IPCACK.all = ulFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Determines whether the given Remote to Local IPC flags are busy or not.
|
||||
//!
|
||||
//! \param ulFlags specifies Remote to Local IPC Flag number masks to check the
|
||||
//! status of.
|
||||
//!
|
||||
//! Allows the caller to determine whether the designated IPC flags are
|
||||
//! pending. The \e ulFlags parameter can be any of the IPC flag
|
||||
//! values: \b IPC_FLAG0 - \b IPC_FLAG31.
|
||||
//!
|
||||
//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated
|
||||
//! IPC flags are free.
|
||||
//
|
||||
//*****************************************************************************
|
||||
Uint16
|
||||
IPCRtoLFlagBusy (uint32_t ulFlags)
|
||||
{
|
||||
Uint16 returnStatus;
|
||||
|
||||
if ((IpcRegs.IPCSTS.all & ulFlags) == 0)
|
||||
{
|
||||
returnStatus = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
returnStatus = 1;
|
||||
}
|
||||
|
||||
return returnStatus;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Determines whether the given IPC flags are busy or not.
|
||||
//!
|
||||
//! \param ulFlags specifies Local to Remote IPC Flag number masks to check the
|
||||
//! status of.
|
||||
//!
|
||||
//! Allows the caller to determine whether the designated IPC flags are
|
||||
//! available for further control to master system communication. If \b 0 is
|
||||
//! returned, then all designated tasks have completed and are available.
|
||||
//! The \e ulFlags parameter can be any of the IPC flag
|
||||
//! values: \b IPC_FLAG0 - \b IPC_FLAG31.
|
||||
//!
|
||||
//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated
|
||||
//! IPC flags are free.
|
||||
//
|
||||
//*****************************************************************************
|
||||
Uint16
|
||||
IPCLtoRFlagBusy (uint32_t ulFlags)
|
||||
{
|
||||
Uint16 returnStatus;
|
||||
|
||||
if ((IpcRegs.IPCFLG.all & ulFlags) == 0)
|
||||
{
|
||||
returnStatus = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
returnStatus = 1;
|
||||
}
|
||||
|
||||
return returnStatus;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Local CPU Sets Local to Remote IPC Flag
|
||||
//!
|
||||
//! \param ulFlags specifies the IPC flag mask for flags being set.
|
||||
//!
|
||||
//! This function will allow the Local CPU system to set the designated IPC
|
||||
//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any
|
||||
//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IPCLtoRFlagSet (uint32_t ulFlags)
|
||||
{
|
||||
IpcRegs.IPCSET.all = ulFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Local CPU Clears Local to Remote IPC Flag
|
||||
//!
|
||||
//! \param ulFlags specifies the IPC flag mask for flags being set.
|
||||
//!
|
||||
//! This function will allow the Local CPU system to set the designated IPC
|
||||
//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any
|
||||
//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IPCLtoRFlagClear (uint32_t ulFlags)
|
||||
{
|
||||
IpcRegs.IPCCLR.all = ulFlags;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Local Return CPU02 BOOT status
|
||||
//!
|
||||
//! This function returns the value at IPCBOOTSTS register.
|
||||
//!
|
||||
//! \return Boot status.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint32_t
|
||||
IPCGetBootStatus (void)
|
||||
{
|
||||
return(IpcRegs.IPCBOOTSTS);
|
||||
}
|
||||
|
||||
#if defined (CPU1)
|
||||
//*****************************************************************************
|
||||
//! Executes a CPU02 control system bootloader.
|
||||
//!
|
||||
//! \param ulBootMode specifies which CPU02 control system boot mode to execute.
|
||||
//!
|
||||
//! This function will allow the CPU01 master system to boot the CPU02 control
|
||||
//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI,
|
||||
//! SCI, I2C, or parallel I/O. Unlike other IPCLite driver functions, this
|
||||
//! function blocks and waits until the control system boot ROM is configured
|
||||
//! and ready to receive CPU01 to CPU02 IPC INT0 interrupts. It then blocks and
|
||||
//! waits until IPC INT0 and IPC FLAG31 are available in the CPU02 boot ROM
|
||||
//! prior to sending the command to execute the selected bootloader. The \e
|
||||
//! ulBootMode parameter accepts one of the following values: \b
|
||||
//! C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL, \b
|
||||
//! C1C2_BROM_BOOTMODE_BOOT_FROM_SCI, \b
|
||||
//! C1C2_BROM_BOOTMODE_BOOT_FROM_SPI, \b
|
||||
//! C1C2_BROM_BOOTMODE_BOOT_FROM_I2C, \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN,
|
||||
//! \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM, \b
|
||||
//! C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH.
|
||||
//!
|
||||
//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is
|
||||
//! invalid and command was not sent.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint16_t
|
||||
IPCBootCPU2(uint32_t ulBootMode)
|
||||
{
|
||||
uint32_t bootStatus;
|
||||
uint16_t pin;
|
||||
uint16_t returnStatus = STATUS_PASS;
|
||||
|
||||
//
|
||||
// If CPU2 has already booted, return a fail to let the application
|
||||
// know that something is out of the ordinary.
|
||||
//
|
||||
bootStatus = IPCGetBootStatus() & 0x0000000F;
|
||||
|
||||
if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK)
|
||||
{
|
||||
//
|
||||
// Check if MSB is set as well
|
||||
//
|
||||
bootStatus = ((uint32_t)(IPCGetBootStatus() & 0x80000000)) >> 31U;
|
||||
|
||||
if(bootStatus != 0)
|
||||
{
|
||||
returnStatus = STATUS_FAIL;
|
||||
|
||||
return returnStatus;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Wait until CPU02 control system boot ROM is ready to receive
|
||||
// CPU01 to CPU02 INT1 interrupts.
|
||||
//
|
||||
do
|
||||
{
|
||||
bootStatus = IPCGetBootStatus() & C2_BOOTROM_BOOTSTS_SYSTEM_READY;
|
||||
} while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY));
|
||||
|
||||
//
|
||||
// Loop until CPU02 control system IPC flags 1 and 32 are available
|
||||
//
|
||||
while ((IPCLtoRFlagBusy(IPC_FLAG0) == 1) ||
|
||||
(IPCLtoRFlagBusy(IPC_FLAG31) == 1))
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
if (ulBootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE)
|
||||
{
|
||||
returnStatus = STATUS_FAIL;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Based on boot mode, enable pull-ups on peripheral pins and
|
||||
// give GPIO pin control to CPU02 control system.
|
||||
//
|
||||
switch (ulBootMode)
|
||||
{
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI:
|
||||
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
//SCIA connected to CPU02
|
||||
//
|
||||
DevCfgRegs.CPUSEL5.bit.SCI_A = 1;
|
||||
|
||||
//
|
||||
//Allows CPU02 bootrom to take control of clock
|
||||
//configuration registers
|
||||
//
|
||||
ClkCfgRegs.CLKSEM.all = 0xA5A50000;
|
||||
|
||||
ClkCfgRegs.LOSPCP.all = 0x0002;
|
||||
EDIS;
|
||||
|
||||
GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(29,GPIO_MUX_CPU2,1);
|
||||
|
||||
GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(28,GPIO_MUX_CPU2,1);
|
||||
|
||||
break;
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI:
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
//SPI-A connected to CPU02
|
||||
//
|
||||
DevCfgRegs.CPUSEL6.bit.SPI_A = 1;
|
||||
|
||||
//
|
||||
//Allows CPU02 bootrom to take control of clock configuration
|
||||
// registers
|
||||
//
|
||||
ClkCfgRegs.CLKSEM.all = 0xA5A50000;
|
||||
EDIS;
|
||||
|
||||
GPIO_SetupPinOptions(16, GPIO_INPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(16,GPIO_MUX_CPU2,1);
|
||||
|
||||
GPIO_SetupPinOptions(17, GPIO_INPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(17,GPIO_MUX_CPU2,1);
|
||||
|
||||
GPIO_SetupPinOptions(18, GPIO_INPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(18,GPIO_MUX_CPU2,1);
|
||||
|
||||
GPIO_SetupPinOptions(19, GPIO_OUTPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(19,GPIO_MUX_CPU2,0);
|
||||
|
||||
break;
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C:
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
//I2CA connected to CPU02
|
||||
//
|
||||
DevCfgRegs.CPUSEL7.bit.I2C_A = 1;
|
||||
|
||||
//
|
||||
//Allows CPU2 bootrom to take control of clock
|
||||
//configuration registers
|
||||
//
|
||||
ClkCfgRegs.CLKSEM.all = 0xA5A50000;
|
||||
ClkCfgRegs.LOSPCP.all = 0x0002;
|
||||
EDIS;
|
||||
GPIO_SetupPinOptions(32, GPIO_INPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(32,GPIO_MUX_CPU2,1);
|
||||
|
||||
GPIO_SetupPinOptions(33, GPIO_INPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(33,GPIO_MUX_CPU2,1);
|
||||
|
||||
break;
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL:
|
||||
|
||||
for(pin=58;pin<=65;pin++)
|
||||
{
|
||||
GPIO_SetupPinOptions(pin, GPIO_INPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(pin,GPIO_MUX_CPU2,0);
|
||||
}
|
||||
|
||||
GPIO_SetupPinOptions(69, GPIO_OUTPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(69,GPIO_MUX_CPU2,0);
|
||||
|
||||
GPIO_SetupPinOptions(70, GPIO_INPUT, GPIO_ASYNC);
|
||||
GPIO_SetupPinMux(70,GPIO_MUX_CPU2,0);
|
||||
break;
|
||||
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN:
|
||||
//
|
||||
//Set up the GPIO mux to bring out CANATX on GPIO71
|
||||
//and CANARX on GPIO70
|
||||
//
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95
|
||||
|
||||
//
|
||||
//Give CPU2 control just in case
|
||||
//
|
||||
GpioCtrlRegs.GPCCSEL1.bit.GPIO71 = GPIO_MUX_CPU2;
|
||||
|
||||
//
|
||||
//Set the extended mux to 0x5
|
||||
//
|
||||
GpioCtrlRegs.GPCGMUX1.bit.GPIO71 = 0x1;
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 0x1;
|
||||
|
||||
//
|
||||
//Set qualification to async just in case
|
||||
//
|
||||
GpioCtrlRegs.GPCQSEL1.bit.GPIO71 = 0x3;
|
||||
|
||||
GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95
|
||||
|
||||
//
|
||||
//Give CPU2 control just in case
|
||||
//
|
||||
GpioCtrlRegs.GPCCSEL1.bit.GPIO70 = GPIO_MUX_CPU2;
|
||||
|
||||
//
|
||||
//Set the extended mux to bring out CANATX
|
||||
//
|
||||
GpioCtrlRegs.GPCGMUX1.bit.GPIO70 = 0x1;
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 0x1;
|
||||
|
||||
//
|
||||
//Set qualification to async just in case
|
||||
//
|
||||
GpioCtrlRegs.GPCQSEL1.bit.GPIO70 = 0x3;
|
||||
GpioCtrlRegs.GPCLOCK.all = 0xFFFFFFFF; //Lock GPIOs 64-95
|
||||
ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = 0x0;
|
||||
CpuSysRegs.PCLKCR10.bit.CAN_A = 1;
|
||||
EDIS;
|
||||
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
//CPU01 to CPU02 IPC Boot Mode Register
|
||||
//
|
||||
IpcRegs.IPCBOOTMODE = ulBootMode;
|
||||
|
||||
//
|
||||
// CPU01 To CPU02 IPC Command Register
|
||||
//
|
||||
IpcRegs.IPCSENDCOM = BROM_IPC_EXECUTE_BOOTMODE_CMD;
|
||||
|
||||
//
|
||||
// CPU01 to CPU02 IPC flag register
|
||||
//
|
||||
IpcRegs.IPCSET.all = 0x80000001;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
return returnStatus;
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
//*****************************************************************************
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//*****************************************************************************
|
||||
|
||||
|
||||
@@ -1,584 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_McBSP.c
|
||||
//
|
||||
// TITLE: F2837xD Device McBSP Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate
|
||||
// generator (SRG) cycles required for the Mcbsp initialization routine.
|
||||
// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock
|
||||
// generator (CLKG) cycles required for the Mcbsp initialization routine.
|
||||
//
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define CPU_SPD 200E6
|
||||
#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4)
|
||||
// for examples
|
||||
#define CLKGDV_VAL 1
|
||||
|
||||
// # of CPU cycles in 2 SRG cycles-init delay
|
||||
#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ)
|
||||
|
||||
// # of CPU cycles in 2 CLKG cycles-init delay
|
||||
#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL)))
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
void delay_loop(void); // Delay function used for SRG initialization
|
||||
void clkg_delay_loop(void); // Delay function used for CLKG initialization
|
||||
|
||||
//
|
||||
// InitMcbsp - This function initializes the McBSP to a known state.
|
||||
//
|
||||
void InitMcbspa(void)
|
||||
{
|
||||
//
|
||||
// Reset the McBSP
|
||||
// Disable all interrupts
|
||||
// Frame sync generator reset
|
||||
// Sample rate generator reset
|
||||
// Transmitter reset
|
||||
// Receiver reset
|
||||
//
|
||||
McbspaRegs.SPCR2.bit.FRST = 0;
|
||||
McbspaRegs.SPCR2.bit.GRST = 0;
|
||||
McbspaRegs.SPCR2.bit.XRST = 0;
|
||||
McbspaRegs.SPCR1.bit.RRST = 0;
|
||||
|
||||
//
|
||||
// Enable loop back mode
|
||||
// This does not require external hardware
|
||||
//
|
||||
McbspaRegs.SPCR2.all = 0x0000;
|
||||
McbspaRegs.SPCR1.all = 0x8000;
|
||||
|
||||
//
|
||||
// RX data delay is 1 bit
|
||||
// TX data delay is 1 bit
|
||||
//
|
||||
McbspaRegs.RCR2.bit.RDATDLY = 1;
|
||||
McbspaRegs.XCR2.bit.XDATDLY = 1;
|
||||
|
||||
//
|
||||
// No clock sync for CLKG
|
||||
// Frame-synchronization period
|
||||
//
|
||||
McbspaRegs.SRGR2.bit.GSYNC = 0;
|
||||
McbspaRegs.SRGR2.bit.FPER = 320;
|
||||
|
||||
//
|
||||
// Frame-synchronization pulses from
|
||||
// the sample rate generator
|
||||
//
|
||||
McbspaRegs.SRGR2.bit.FSGM = 1;
|
||||
|
||||
//
|
||||
// Sample rate generator input clock is LSPCLK
|
||||
//
|
||||
McbspaRegs.SRGR2.bit.CLKSM = 1;
|
||||
McbspaRegs.PCR.bit.SCLKME = 0;
|
||||
|
||||
//
|
||||
// Divide-down value for CLKG
|
||||
// Frame-synchronization pulse width
|
||||
//
|
||||
McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;
|
||||
clkg_delay_loop();
|
||||
McbspaRegs.SRGR1.bit.FWID = 1;
|
||||
|
||||
//
|
||||
// CLKX is driven by the sample rate generator
|
||||
// Transmit frame synchronization generated by internal
|
||||
// sample rate generator
|
||||
//
|
||||
McbspaRegs.PCR.bit.CLKXM = 1;
|
||||
McbspaRegs.PCR.bit.FSXM = 1;
|
||||
|
||||
//
|
||||
// Enable Sample rate generator and
|
||||
// wait at least 2 CLKG clock cycles
|
||||
//
|
||||
McbspaRegs.SPCR2.bit.GRST = 1;
|
||||
clkg_delay_loop();
|
||||
|
||||
//
|
||||
// Release from reset
|
||||
// RX, TX and frame sync generator
|
||||
//
|
||||
McbspaRegs.SPCR2.bit.XRST = 1;
|
||||
McbspaRegs.SPCR1.bit.RRST = 1;
|
||||
McbspaRegs.SPCR2.bit.FRST = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspaInt - Enable TX and RX interrupts
|
||||
//
|
||||
void InitMcbspaInt(void)
|
||||
{
|
||||
// Reset TX and RX
|
||||
// Enable interrupts for TX and RX
|
||||
// Release TX and RX
|
||||
McbspaRegs.SPCR2.bit.XRST = 0;
|
||||
McbspaRegs.SPCR1.bit.RRST = 0;
|
||||
McbspaRegs.MFFINT.bit.XINT = 1;
|
||||
McbspaRegs.MFFINT.bit.RINT = 1;
|
||||
McbspaRegs.SPCR2.bit.XRST = 1;
|
||||
McbspaRegs.SPCR1.bit.RRST = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspa8bit - McBSP uses an 8-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspa8bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1 = 0;
|
||||
McbspaRegs.XCR1.bit.XWDLEN1 = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspa12bit - McBSP uses an 12-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspa12bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1 = 1;
|
||||
McbspaRegs.XCR1.bit.XWDLEN1 = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspa16bit - McBSP uses an 16-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspa16bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1 = 2;
|
||||
McbspaRegs.XCR1.bit.XWDLEN1 = 2;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspa20bit - McBSP uses an 20-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspa20bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1 = 3;
|
||||
McbspaRegs.XCR1.bit.XWDLEN1 = 3;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspa24bit - McBSP uses an 24-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspa24bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1 = 4;
|
||||
McbspaRegs.XCR1.bit.XWDLEN1 = 4;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspa32bit - McBSP uses an 32-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspa32bit(void)
|
||||
{
|
||||
McbspaRegs.RCR1.bit.RWDLEN1 = 5;
|
||||
McbspaRegs.XCR1.bit.XWDLEN1 = 5;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspaGpio - Assign GPIO pins to the McBSP peripheral
|
||||
// (Note: This function must be called from CPU1.)
|
||||
//
|
||||
void InitMcbspaGpio(void)
|
||||
{
|
||||
#ifdef CPU1
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// This specifies which of the possible GPIO pins will be
|
||||
// McBSPA functional pins. Comment out unwanted connections.
|
||||
// Set qualification for selected input pins to asynchronous only
|
||||
// This will select asynchronous (no qualification) for the selected pins.
|
||||
//
|
||||
|
||||
//
|
||||
// MDXA
|
||||
// GPIO20
|
||||
// GPIO84
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2;
|
||||
//GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 3;
|
||||
//GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3;
|
||||
|
||||
//
|
||||
// MDRA
|
||||
// GPIO21 with asynchronous qualification
|
||||
// GPIO85 with asynchronous qualification
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3;
|
||||
//GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 3;
|
||||
//GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3;
|
||||
//GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3;
|
||||
|
||||
//
|
||||
// MCLKXA
|
||||
// GPIO22 with asynchronous qualification
|
||||
// GPIO86 with asynchronous qualification
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2;
|
||||
//GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3;
|
||||
//GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 3;
|
||||
//GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3;
|
||||
//GpioCtrlRegs.GPCQSEL2.bit.GPIO86 = 3;
|
||||
|
||||
//
|
||||
// MCLKRA
|
||||
// Select one of the following
|
||||
// GPIO7 with asynchronous qualification
|
||||
// GPIO58 with asynchronous qualification
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3;
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1;
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3;
|
||||
|
||||
//
|
||||
// MFSXA
|
||||
// GPIO23 with asynchronous qualification
|
||||
// GPIO87 with asynchronous qualification
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2;
|
||||
//GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3;
|
||||
//GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 3;
|
||||
//GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3;
|
||||
//GpioCtrlRegs.GPCQSEL2.bit.GPIO87 = 3;
|
||||
|
||||
//
|
||||
// MFSRA
|
||||
// Select one of the following
|
||||
// GPIO5 with asynchronous qualification
|
||||
// GPIO59 with asynchronous qualification
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3;
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1;
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3;
|
||||
|
||||
EDIS;
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspb - McBSPB initialization routine for examples
|
||||
//
|
||||
void InitMcbspb(void)
|
||||
{
|
||||
//
|
||||
// Reset the McBSP
|
||||
// Disable all interrupts
|
||||
// Frame sync generator reset
|
||||
// Sample rate generator reset
|
||||
// Transmitter reset
|
||||
// Receiver reset
|
||||
//
|
||||
McbspbRegs.SPCR2.bit.FRST = 0;
|
||||
McbspbRegs.SPCR2.bit.GRST = 0;
|
||||
McbspbRegs.SPCR2.bit.XRST = 0;
|
||||
McbspbRegs.SPCR1.bit.RRST = 0;
|
||||
|
||||
//
|
||||
// Enable loop back mode
|
||||
// This does not require external hardware
|
||||
//
|
||||
McbspbRegs.SPCR2.all = 0x0000;
|
||||
McbspbRegs.SPCR1.all = 0x8000;
|
||||
|
||||
//
|
||||
// RX data delay is 1 bit
|
||||
// TX data delay is 1 bit
|
||||
//
|
||||
McbspbRegs.RCR2.bit.RDATDLY = 1;
|
||||
McbspbRegs.XCR2.bit.XDATDLY = 1;
|
||||
|
||||
//
|
||||
// No clock sync for CLKG
|
||||
// Frame-synchronization period
|
||||
//
|
||||
McbspbRegs.SRGR2.bit.GSYNC = 0;
|
||||
McbspbRegs.SRGR2.bit.FPER = 320;
|
||||
|
||||
//
|
||||
// Frame-synchronization pulses from
|
||||
// the sample rate generator
|
||||
//
|
||||
McbspbRegs.SRGR2.bit.FSGM = 1;
|
||||
|
||||
//
|
||||
// Sample rate generator input clock is LSPCLK
|
||||
//
|
||||
McbspbRegs.SRGR2.bit.CLKSM = 1;
|
||||
McbspbRegs.PCR.bit.SCLKME = 0;
|
||||
|
||||
//
|
||||
// Divide-down value for CLKG
|
||||
// Frame-synchronization pulse width
|
||||
//
|
||||
McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;
|
||||
clkg_delay_loop();
|
||||
McbspbRegs.SRGR1.bit.FWID = 1;
|
||||
|
||||
//
|
||||
// CLKX is driven by the sample rate generator
|
||||
// Transmit frame synchronization generated by internal
|
||||
// sample rate generator
|
||||
//
|
||||
McbspbRegs.PCR.bit.CLKXM = 1;
|
||||
McbspbRegs.PCR.bit.FSXM = 1;
|
||||
|
||||
//
|
||||
// Enable Sample rate generator and
|
||||
// wait at least 2 CLKG clock cycles
|
||||
//
|
||||
McbspbRegs.SPCR2.bit.GRST = 1;
|
||||
clkg_delay_loop();
|
||||
|
||||
//
|
||||
// Release from reset
|
||||
// RX, TX and frame sync generator
|
||||
//
|
||||
McbspbRegs.SPCR2.bit.XRST = 1;
|
||||
McbspbRegs.SPCR1.bit.RRST = 1;
|
||||
McbspbRegs.SPCR2.bit.FRST = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspbInt - Enable TX and RX interrupts
|
||||
//
|
||||
void InitMcbspbInt(void)
|
||||
{
|
||||
//
|
||||
// Reset TX and RX
|
||||
// Enable interrupts for TX and RX
|
||||
// Release TX and RX
|
||||
//
|
||||
McbspbRegs.SPCR2.bit.XRST = 0;
|
||||
McbspbRegs.SPCR1.bit.RRST = 0;
|
||||
McbspbRegs.MFFINT.bit.XINT = 1;
|
||||
McbspbRegs.MFFINT.bit.RINT = 1;
|
||||
McbspbRegs.SPCR2.bit.XRST = 1;
|
||||
McbspbRegs.SPCR1.bit.RRST = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspb8bit - McBSPB uses an 8-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspb8bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1 = 0;
|
||||
McbspbRegs.XCR1.bit.XWDLEN1 = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// IniMcbspb12bit - McBSPB uses an 12-bit word for both TX and RX
|
||||
//
|
||||
void IniMcbspb12bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1 = 1;
|
||||
McbspbRegs.XCR1.bit.XWDLEN1 = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspb16bit - McBSPB uses an 16-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspb16bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1 = 2;
|
||||
McbspbRegs.XCR1.bit.XWDLEN1 = 2;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspb20bit - McBSPB uses an 20-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspb20bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1 = 3;
|
||||
McbspbRegs.XCR1.bit.XWDLEN1 = 3;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspb24bit - McBSPB uses an 24-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspb24bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1 = 4;
|
||||
McbspbRegs.XCR1.bit.XWDLEN1 = 4;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspb32bit - McBSPB uses an 32-bit word for both TX and RX
|
||||
//
|
||||
void InitMcbspb32bit(void)
|
||||
{
|
||||
McbspbRegs.RCR1.bit.RWDLEN1 = 5;
|
||||
McbspbRegs.XCR1.bit.XWDLEN1 = 5;
|
||||
}
|
||||
|
||||
//
|
||||
// InitMcbspbGpio - Assign GPIO pins to the McBSP peripheral
|
||||
// (Note: This function must be called from CPU1.)
|
||||
//
|
||||
void InitMcbspbGpio(void)
|
||||
{
|
||||
#ifdef CPU1
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// This specifies which of the possible GPIO pins will be
|
||||
// McBSPB functional pins. Comment out unwanted connections.
|
||||
// Set qualification for selected input pins to asynchronous only
|
||||
// This will select asynchronous (no qualification) for the selected pins.
|
||||
//
|
||||
|
||||
//
|
||||
// Select one of the following for MDXB
|
||||
// GPIO24
|
||||
// GPIO84
|
||||
//
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3;
|
||||
GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 1;
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2;
|
||||
|
||||
//
|
||||
// MDRB
|
||||
// GPIO13 with asynchronous qualification
|
||||
// GPIO25 with asynchronous qualification
|
||||
// GPIO85 with asynchronous qualification
|
||||
//
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3;
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3;
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3;
|
||||
//GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3;
|
||||
GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 1;
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 2;
|
||||
GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3;
|
||||
|
||||
//
|
||||
// MCLKXB
|
||||
// GPIO14 with asynchronous qualification
|
||||
// GPIO26 with asynchronous qualification
|
||||
// GPIO86 with asynchronous qualification
|
||||
//
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3;
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3;
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3;
|
||||
//GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3;
|
||||
GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 1;
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 2;
|
||||
GpioCtrlRegs.GPCQSEL2.bit.GPIO86= 3;
|
||||
|
||||
//
|
||||
// MCLKRB
|
||||
// Select one of the following
|
||||
// GPIO3 with asynchronous qualification
|
||||
// GPIO60 with asynchronous qualification
|
||||
//
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3;
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3;
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3;
|
||||
|
||||
//
|
||||
// MFSXB
|
||||
// GPIO15 with asynchronous qualification
|
||||
// GPIO27 with asynchronous qualification
|
||||
// GPIO87 with asynchronous qualification
|
||||
//
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3;
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3;
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3;
|
||||
//GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3;
|
||||
GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 1;
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 2;
|
||||
GpioCtrlRegs.GPCQSEL2.bit.GPIO87= 3;
|
||||
|
||||
//
|
||||
// MFSRB
|
||||
// Select one of the following
|
||||
// GPIO1 with asynchronous qualification
|
||||
// GPIO61 with asynchronous qualification
|
||||
//
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3;
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3;
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3;
|
||||
|
||||
EDIS;
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
//
|
||||
// delay_loop - Delay function (at least 2 SRG cycles)
|
||||
// Required in McBSP initialization
|
||||
//
|
||||
void delay_loop(void)
|
||||
{
|
||||
long i;
|
||||
for (i = 0; i < MCBSP_INIT_DELAY; i++) {}
|
||||
}
|
||||
|
||||
//
|
||||
// clkg_delay_loop - Delay function (at least 2 CLKG cycles)
|
||||
// Required in McBSP init
|
||||
//
|
||||
void clkg_delay_loop(void)
|
||||
{
|
||||
long i;
|
||||
for (i = 0; i < MCBSP_CLKG_DELAY; i++) {}
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,121 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_PieCtrl.c
|
||||
//
|
||||
// TITLE: F2837xD Device PIE Control Register Initialization Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h" // F2837xD Headerfile Include File
|
||||
#include "F2837xD_Examples.h" // F2837xD Examples Include File
|
||||
|
||||
//
|
||||
// InitPieCtrl - This function initializes the PIE control registers to a
|
||||
// known state.
|
||||
//
|
||||
void InitPieCtrl(void)
|
||||
{
|
||||
//
|
||||
// Disable Interrupts at the CPU level:
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Disable the PIE
|
||||
//
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
|
||||
|
||||
//
|
||||
// Clear all PIEIER registers:
|
||||
//
|
||||
PieCtrlRegs.PIEIER1.all = 0;
|
||||
PieCtrlRegs.PIEIER2.all = 0;
|
||||
PieCtrlRegs.PIEIER3.all = 0;
|
||||
PieCtrlRegs.PIEIER4.all = 0;
|
||||
PieCtrlRegs.PIEIER5.all = 0;
|
||||
PieCtrlRegs.PIEIER6.all = 0;
|
||||
PieCtrlRegs.PIEIER7.all = 0;
|
||||
PieCtrlRegs.PIEIER8.all = 0;
|
||||
PieCtrlRegs.PIEIER9.all = 0;
|
||||
PieCtrlRegs.PIEIER10.all = 0;
|
||||
PieCtrlRegs.PIEIER11.all = 0;
|
||||
PieCtrlRegs.PIEIER12.all = 0;
|
||||
|
||||
//
|
||||
// Clear all PIEIFR registers:
|
||||
//
|
||||
PieCtrlRegs.PIEIFR1.all = 0;
|
||||
PieCtrlRegs.PIEIFR2.all = 0;
|
||||
PieCtrlRegs.PIEIFR3.all = 0;
|
||||
PieCtrlRegs.PIEIFR4.all = 0;
|
||||
PieCtrlRegs.PIEIFR5.all = 0;
|
||||
PieCtrlRegs.PIEIFR6.all = 0;
|
||||
PieCtrlRegs.PIEIFR7.all = 0;
|
||||
PieCtrlRegs.PIEIFR8.all = 0;
|
||||
PieCtrlRegs.PIEIFR9.all = 0;
|
||||
PieCtrlRegs.PIEIFR10.all = 0;
|
||||
PieCtrlRegs.PIEIFR11.all = 0;
|
||||
PieCtrlRegs.PIEIFR12.all = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// EnableInterrupts - This function enables the PIE module and CPU __interrupts
|
||||
//
|
||||
void EnableInterrupts()
|
||||
{
|
||||
//
|
||||
// Enable the PIE
|
||||
//
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
//
|
||||
// Enables PIE to drive a pulse into the CPU
|
||||
//
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF;
|
||||
|
||||
//
|
||||
// Enable Interrupts at the CPU level
|
||||
//
|
||||
EINT;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,320 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_PieVect.c
|
||||
//
|
||||
// TITLE: F2837xD Device PIE Vector Initialization Functions
|
||||
//
|
||||
//###########################################################################
|
||||
// $
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
const struct PIE_VECT_TABLE PieVectTableInit = {
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
TIMER1_ISR, // CPU Timer 1 Interrupt
|
||||
TIMER2_ISR, // CPU Timer 2 Interrupt
|
||||
DATALOG_ISR, // Datalogging Interrupt
|
||||
RTOS_ISR, // RTOS Interrupt
|
||||
EMU_ISR, // Emulation Interrupt
|
||||
NMI_ISR, // Non-Maskable Interrupt
|
||||
ILLEGAL_ISR, // Illegal Operation Trap
|
||||
USER1_ISR, // User Defined Trap 1
|
||||
USER2_ISR, // User Defined Trap 2
|
||||
USER3_ISR, // User Defined Trap 3
|
||||
USER4_ISR, // User Defined Trap 4
|
||||
USER5_ISR, // User Defined Trap 5
|
||||
USER6_ISR, // User Defined Trap 6
|
||||
USER7_ISR, // User Defined Trap 7
|
||||
USER8_ISR, // User Defined Trap 8
|
||||
USER9_ISR, // User Defined Trap 9
|
||||
USER10_ISR, // User Defined Trap 10
|
||||
USER11_ISR, // User Defined Trap 11
|
||||
USER12_ISR, // User Defined Trap 12
|
||||
ADCA1_ISR, // 1.1 - ADCA Interrupt 1
|
||||
ADCB1_ISR, // 1.2 - ADCB Interrupt 1
|
||||
ADCC1_ISR, // 1.3 - ADCC Interrupt 1
|
||||
XINT1_ISR, // 1.4 - XINT1 Interrupt
|
||||
XINT2_ISR, // 1.5 - XINT2 Interrupt
|
||||
ADCD1_ISR, // 1.6 - ADCD Interrupt 1
|
||||
TIMER0_ISR, // 1.7 - Timer 0 Interrupt
|
||||
WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt
|
||||
EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt
|
||||
EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt
|
||||
EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt
|
||||
EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt
|
||||
EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt
|
||||
EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt
|
||||
EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt
|
||||
EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt
|
||||
EPWM1_ISR, // 3.1 - ePWM1 Interrupt
|
||||
EPWM2_ISR, // 3.2 - ePWM2 Interrupt
|
||||
EPWM3_ISR, // 3.3 - ePWM3 Interrupt
|
||||
EPWM4_ISR, // 3.4 - ePWM4 Interrupt
|
||||
EPWM5_ISR, // 3.5 - ePWM5 Interrupt
|
||||
EPWM6_ISR, // 3.6 - ePWM6 Interrupt
|
||||
EPWM7_ISR, // 3.7 - ePWM7 Interrupt
|
||||
EPWM8_ISR, // 3.8 - ePWM8 Interrupt
|
||||
ECAP1_ISR, // 4.1 - eCAP1 Interrupt
|
||||
ECAP2_ISR, // 4.2 - eCAP2 Interrupt
|
||||
ECAP3_ISR, // 4.3 - eCAP3 Interrupt
|
||||
ECAP4_ISR, // 4.4 - eCAP4 Interrupt
|
||||
ECAP5_ISR, // 4.5 - eCAP5 Interrupt
|
||||
ECAP6_ISR, // 4.6 - eCAP6 Interrupt
|
||||
PIE_RESERVED_ISR, // 4.7 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.8 - Reserved
|
||||
EQEP1_ISR, // 5.1 - eQEP1 Interrupt
|
||||
EQEP2_ISR, // 5.2 - eQEP2 Interrupt
|
||||
EQEP3_ISR, // 5.3 - eQEP3 Interrupt
|
||||
PIE_RESERVED_ISR, // 5.4 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.5 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.6 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.7 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.8 - Reserved
|
||||
SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt
|
||||
SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt
|
||||
SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt
|
||||
SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt
|
||||
MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt
|
||||
MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt
|
||||
MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt
|
||||
MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt
|
||||
DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt
|
||||
DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt
|
||||
DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt
|
||||
DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt
|
||||
DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt
|
||||
DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt
|
||||
PIE_RESERVED_ISR, // 7.7 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.8 - Reserved
|
||||
I2CA_ISR, // 8.1 - I2CA Interrupt 1
|
||||
I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2
|
||||
I2CB_ISR, // 8.3 - I2CB Interrupt 1
|
||||
I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2
|
||||
SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt
|
||||
SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt
|
||||
SCID_RX_ISR, // 8.7 - SCID Receive Interrupt
|
||||
SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt
|
||||
SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt
|
||||
SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt
|
||||
SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt
|
||||
SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt
|
||||
CANA0_ISR, // 9.5 - CANA Interrupt 0
|
||||
CANA1_ISR, // 9.6 - CANA Interrupt 1
|
||||
CANB0_ISR, // 9.7 - CANB Interrupt 0
|
||||
CANB1_ISR, // 9.8 - CANB Interrupt 1
|
||||
ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt
|
||||
ADCA2_ISR, // 10.2 - ADCA Interrupt 2
|
||||
ADCA3_ISR, // 10.3 - ADCA Interrupt 3
|
||||
ADCA4_ISR, // 10.4 - ADCA Interrupt 4
|
||||
ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt
|
||||
ADCB2_ISR, // 10.6 - ADCB Interrupt 2
|
||||
ADCB3_ISR, // 10.7 - ADCB Interrupt 3
|
||||
ADCB4_ISR, // 10.8 - ADCB Interrupt 4
|
||||
CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1
|
||||
CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2
|
||||
CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3
|
||||
CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4
|
||||
CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5
|
||||
CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6
|
||||
CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7
|
||||
CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8
|
||||
XINT3_ISR, // 12.1 - XINT3 Interrupt
|
||||
XINT4_ISR, // 12.2 - XINT4 Interrupt
|
||||
XINT5_ISR, // 12.3 - XINT5 Interrupt
|
||||
PIE_RESERVED_ISR, // 12.4 - Reserved
|
||||
PIE_RESERVED_ISR, // 12.5 - Reserved
|
||||
VCU_ISR, // 12.6 - VCU Interrupt
|
||||
FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt
|
||||
FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt
|
||||
PIE_RESERVED_ISR, // 1.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 1.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 1.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 1.12 - Reserved
|
||||
IPC0_ISR, // 1.13 - IPC Interrupt 0
|
||||
IPC1_ISR, // 1.14 - IPC Interrupt 1
|
||||
IPC2_ISR, // 1.15 - IPC Interrupt 2
|
||||
IPC3_ISR, // 1.16 - IPC Interrupt 3
|
||||
EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt
|
||||
EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt
|
||||
EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt
|
||||
EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt
|
||||
PIE_RESERVED_ISR, // 2.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 2.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 2.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 2.16 - Reserved
|
||||
EPWM9_ISR, // 3.9 - ePWM9 Interrupt
|
||||
EPWM10_ISR, // 3.10 - ePWM10 Interrupt
|
||||
EPWM11_ISR, // 3.11 - ePWM11 Interrupt
|
||||
EPWM12_ISR, // 3.12 - ePWM12 Interrupt
|
||||
PIE_RESERVED_ISR, // 3.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 3.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 3.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 3.16 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.16 - Reserved
|
||||
SD1_ISR, // 5.9 - SD1 Interrupt
|
||||
SD2_ISR, // 5.10 - SD2 Interrupt
|
||||
PIE_RESERVED_ISR, // 5.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.16 - Reserved
|
||||
SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt
|
||||
SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt
|
||||
PIE_RESERVED_ISR, // 6.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.16 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.16 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.14 - Reserved
|
||||
#ifdef CPU1
|
||||
UPPA_ISR, // 8.15 - uPPA Interrupt
|
||||
PIE_RESERVED_ISR, // 8.16 - Reserved
|
||||
#elif defined(CPU2)
|
||||
PIE_RESERVED_ISR, // 8.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.16 - Reserved
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 9.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.14 - Reserved
|
||||
#ifdef CPU1
|
||||
USBA_ISR, // 9.15 - USBA Interrupt
|
||||
#elif defined(CPU2)
|
||||
PIE_RESERVED_ISR, // 9.15 - Reserved
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 9.16 - Reserved
|
||||
ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt
|
||||
ADCC2_ISR, // 10.10 - ADCC Interrupt 2
|
||||
ADCC3_ISR, // 10.11 - ADCC Interrupt 3
|
||||
ADCC4_ISR, // 10.12 - ADCC Interrupt 4
|
||||
ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt
|
||||
ADCD2_ISR, // 10.14 - ADCD Interrupt 2
|
||||
ADCD3_ISR, // 10.15 - ADCD Interrupt 3
|
||||
ADCD4_ISR, // 10.16 - ADCD Interrupt 4
|
||||
PIE_RESERVED_ISR, // 11.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.16 - Reserved
|
||||
EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt
|
||||
RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt
|
||||
FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt
|
||||
RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt
|
||||
SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt
|
||||
AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt
|
||||
CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt
|
||||
CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt
|
||||
};
|
||||
|
||||
//
|
||||
// InitPieVectTable - This function initializes the PIE vector table to a
|
||||
// known state and must be executed after boot time.
|
||||
//
|
||||
void InitPieVectTable(void)
|
||||
{
|
||||
Uint16 i;
|
||||
Uint32 *Source = (void *) &PieVectTableInit;
|
||||
Uint32 *Dest = (void *) &PieVectTable;
|
||||
|
||||
//
|
||||
// Do not write over first 3 32-bit locations (these locations are
|
||||
// initialized by Boot ROM with boot variables)
|
||||
//
|
||||
Source = Source + 3;
|
||||
Dest = Dest + 3;
|
||||
|
||||
EALLOW;
|
||||
for(i = 0; i < 221; i++)
|
||||
{
|
||||
*Dest++ = *Source++;
|
||||
}
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Enable the PIE Vector Table
|
||||
//
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,974 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_SWPrioritizedPieVect.c
|
||||
//
|
||||
// TITLE: F2837xD Devices SW Prioritized PIE Vector Table Initialization.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
#include "F2837xD_SWPrioritizedIsrLevels.h"
|
||||
|
||||
const struct PIE_VECT_TABLE PieVectTableInit =
|
||||
{
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
PIE_RESERVED_ISR, // Reserved
|
||||
|
||||
//
|
||||
// Non-Peripheral Interrupts:
|
||||
//
|
||||
#if (INT13PL != 0)
|
||||
TIMER1_ISR, // CPU Timer 1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (INT14PL != 0)
|
||||
TIMER2_ISR, // CPU Timer 2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (INT15PL != 0)
|
||||
DATALOG_ISR, // Datalogging interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (INT16PL != 0)
|
||||
RTOS_ISR, // RTOS Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
EMU_ISR, // Emulation Interrupt
|
||||
NMI_ISR, // Non-Maskable Interrupt
|
||||
ILLEGAL_ISR, // Illegal Operation Trap
|
||||
USER1_ISR, // User Defined Trap 1
|
||||
USER2_ISR, // User Defined Trap 2
|
||||
USER3_ISR, // User Defined Trap 3
|
||||
USER4_ISR, // User Defined Trap 4
|
||||
USER5_ISR, // User Defined Trap 5
|
||||
USER6_ISR, // User Defined Trap 6
|
||||
USER7_ISR, // User Defined Trap 7
|
||||
USER8_ISR, // User Defined Trap 8
|
||||
USER9_ISR, // User Defined Trap 9
|
||||
USER10_ISR, // User Defined Trap 10
|
||||
USER11_ISR, // User Defined Trap 11
|
||||
USER12_ISR, // User Defined Trap 12
|
||||
|
||||
//
|
||||
// Group 1 PIE Vectors:
|
||||
//
|
||||
#if (G1_1PL != 0)
|
||||
ADCA1_ISR, // 1.1 - ADCA Interrupt 1
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G1_2PL != 0)
|
||||
ADCB1_ISR, // 1.2 - ADCB Interrupt 1
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G1_3PL != 0)
|
||||
ADCC1_ISR, // 1.3 - ADCC Interrupt 1
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G1_4PL != 0)
|
||||
XINT1_ISR, // 1.4 - XINT1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G1_5PL != 0)
|
||||
XINT2_ISR, // 1.5 - XINT2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G1_6PL != 0)
|
||||
ADCD1_ISR, // 1.6 - ADCD Interrupt 1
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G1_7PL != 0)
|
||||
TIMER0_ISR, // 1.7 - Timer 0 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G1_8PL != 0)
|
||||
WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
//
|
||||
// Group 2 PIE Vectors:
|
||||
//
|
||||
#if (G2_1PL != 0)
|
||||
EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_2PL != 0)
|
||||
EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_3PL != 0)
|
||||
EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_4PL != 0)
|
||||
EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_5PL != 0)
|
||||
EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_6PL != 0)
|
||||
EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_7PL != 0)
|
||||
EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_8PL != 0)
|
||||
EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
//
|
||||
// Group 3 PIE Vectors:
|
||||
//
|
||||
#if (G3_1PL != 0)
|
||||
EPWM1_ISR, // 3.1 - ePWM1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G3_2PL != 0)
|
||||
EPWM2_ISR, // 3.2 - ePWM2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G3_3PL != 0)
|
||||
EPWM3_ISR, // 3.3 - ePWM3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G3_4PL != 0)
|
||||
EPWM4_ISR, // 3.4 - ePWM4 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G3_5PL != 0)
|
||||
EPWM5_ISR, // 3.5 - ePWM5 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G3_6PL != 0)
|
||||
EPWM6_ISR, // 3.6 - ePWM6 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G3_7PL != 0)
|
||||
EPWM7_ISR, // 3.7 - ePWM7 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G3_8PL != 0)
|
||||
EPWM8_ISR, // 3.8 - ePWM8 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
//
|
||||
// Group 4 PIE Vectors:
|
||||
//
|
||||
#if (G4_1PL != 0)
|
||||
ECAP1_ISR, // 4.1 - eCAP1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G4_2PL != 0)
|
||||
ECAP2_ISR, // 4.2 - eCAP2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G4_3PL != 0)
|
||||
ECAP3_ISR, // 4.3 - eCAP3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G4_4PL != 0)
|
||||
ECAP4_ISR, // 4.4 - eCAP4 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G4_5PL != 0)
|
||||
ECAP5_ISR, // 4.5 - eCAP5 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G4_6PL != 0)
|
||||
ECAP6_ISR, // 4.6 - eCAP6 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
PIE_RESERVED_ISR, // 4.7 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.8 - Reserved
|
||||
|
||||
//
|
||||
// Group 5 PIE Vectors:
|
||||
//
|
||||
#if (G5_1PL != 0)
|
||||
EQEP1_ISR, // 5.1 - eQEP1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G5_2PL != 0)
|
||||
EQEP2_ISR, // 5.2 - eQEP2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G5_3PL != 0)
|
||||
EQEP3_ISR, // 5.3 - eQEP3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
PIE_RESERVED_ISR, // 5.4 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.5 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.6 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.7 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.8 - Reserved
|
||||
|
||||
//
|
||||
// Group 6 PIE Vectors:
|
||||
//
|
||||
#if (G6_1PL != 0)
|
||||
SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G6_2PL != 0)
|
||||
SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G6_3PL != 0)
|
||||
SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G6_4PL != 0)
|
||||
SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G6_5PL != 0)
|
||||
MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G6_6PL != 0)
|
||||
MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G6_7PL != 0)
|
||||
MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G6_8PL != 0)
|
||||
MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
//
|
||||
// Group 7 PIE Vectors:
|
||||
//
|
||||
#if (G7_1PL != 0)
|
||||
DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G7_2PL != 0)
|
||||
DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G7_3PL != 0)
|
||||
DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G7_4PL != 0)
|
||||
DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G7_5PL != 0)
|
||||
DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G7_6PL != 0)
|
||||
DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
PIE_RESERVED_ISR, // 7.7 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.8 - Reserved
|
||||
|
||||
//
|
||||
// Group 8 PIE Vectors:
|
||||
//
|
||||
#if (G8_1PL != 0)
|
||||
I2CA_ISR, // 8.1 - I2CA Interrupt 1
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G8_2PL != 0)
|
||||
I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G8_3PL != 0)
|
||||
I2CB_ISR, // 8.3 - I2CB Interrupt 1
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G8_4PL != 0)
|
||||
I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G8_5PL != 0)
|
||||
SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G8_6PL != 0)
|
||||
SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G8_7PL != 0)
|
||||
SCID_RX_ISR, // 8.7 - SCID Receive Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G8_8PL != 0)
|
||||
SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
//
|
||||
// Group 9 PIE Vectors:
|
||||
//
|
||||
#if (G9_1PL != 0)
|
||||
SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G9_2PL != 0)
|
||||
SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G9_3PL != 0)
|
||||
SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G9_4PL != 0)
|
||||
SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G9_5PL != 0)
|
||||
CANA0_ISR, // 9.5 - CANA Interrupt 0
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G9_6PL != 0)
|
||||
CANA1_ISR, // 9.6 - CANA Interrupt 1
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G9_7PL != 0)
|
||||
CANB0_ISR, // 9.7 - CANB Interrupt 0
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G9_8PL != 0)
|
||||
CANB1_ISR, // 9.8 - CANB Interrupt 1
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
//
|
||||
// Group 10 PIE Vectors
|
||||
//
|
||||
#if (G10_1PL != 0)
|
||||
ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_2PL != 0)
|
||||
ADCA2_ISR, // 10.2 - ADCA Interrupt 2
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_3PL != 0)
|
||||
ADCA3_ISR, // 10.3 - ADCA Interrupt 3
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_4PL != 0)
|
||||
ADCA4_ISR, // 10.4 - ADCA Interrupt 4
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_5PL != 0)
|
||||
ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_6PL != 0)
|
||||
ADCB2_ISR, // 10.6 - ADCB Interrupt 2
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_7PL != 0)
|
||||
ADCB3_ISR, // 10.7 - ADCB Interrupt 3
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_8PL != 0)
|
||||
ADCB4_ISR, // 10.8 - ADCB Interrupt 4
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
//
|
||||
// Group 11 PIE Vectors
|
||||
//
|
||||
#if (G11_1PL != 0)
|
||||
CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G11_2PL != 0)
|
||||
CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G11_3PL != 0)
|
||||
CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G11_4PL != 0)
|
||||
CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G11_5PL != 0)
|
||||
CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G11_6PL != 0)
|
||||
CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G11_7PL != 0)
|
||||
CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G11_8PL != 0)
|
||||
CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
//
|
||||
// Group 12 PIE Vectors
|
||||
//
|
||||
#if (G12_1PL != 0)
|
||||
XINT3_ISR, // 12.1 - XINT3 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_2PL != 0)
|
||||
XINT4_ISR, // 12.2 - XINT4 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_3PL != 0)
|
||||
XINT5_ISR, // 12.3 - XINT5 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 12.4 - Reserved
|
||||
PIE_RESERVED_ISR, // 12.5 - Reserved
|
||||
|
||||
#if (G12_6PL != 0)
|
||||
VCU_ISR, // 12.6 - VCU Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_7PL != 0)
|
||||
FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_8PL != 0)
|
||||
FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 1.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 1.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 1.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 1.12 - Reserved
|
||||
|
||||
#if (G1_13PL != 0)
|
||||
IPC0_ISR, // 1.13 - IPC Interrupt 0
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G1_14PL != 0)
|
||||
IPC1_ISR, // 1.14 - IPC Interrupt 1
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G1_15PL != 0)
|
||||
IPC2_ISR, // 1.15 - IPC Interrupt 2
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G1_16PL != 0)
|
||||
IPC3_ISR, // 1.16 - IPC Interrupt 3
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_9PL != 0)
|
||||
EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_10PL != 0)
|
||||
EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_11PL != 0)
|
||||
EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G2_12PL != 0)
|
||||
EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 2.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 2.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 2.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 2.16 - Reserved
|
||||
|
||||
#if (G3_9PL != 0)
|
||||
EPWM9_ISR, // 3.9 - ePWM9 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G3_10PL != 0)
|
||||
EPWM10_ISR, // 3.10 - ePWM10 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G3_11PL != 0)
|
||||
EPWM11_ISR, // 3.11 - ePWM11 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G3_12PL != 0)
|
||||
EPWM12_ISR, // 3.12 - ePWM12 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 3.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 3.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 3.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 3.16 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 4.16 - Reserved
|
||||
|
||||
#if (G5_9PL != 0)
|
||||
SD1_ISR, // 5.9 - SD1 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G5_10PL != 0)
|
||||
SD2_ISR, // 5.10 - SD2 Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 5.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 5.16 - Reserved
|
||||
|
||||
#if (G6_9PL != 0)
|
||||
SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G6_10PL != 0)
|
||||
SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 6.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 6.16 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 7.16 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.14 - Reserved
|
||||
#ifdef CPU1
|
||||
|
||||
#if (G8_15PL != 0)
|
||||
UPPA_ISR, // 8.15 - uPPA Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 8.16 - Reserved
|
||||
#elif defined(CPU2)
|
||||
PIE_RESERVED_ISR, // 8.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 8.16 - Reserved
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 9.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 9.14 - Reserved
|
||||
#ifdef CPU1
|
||||
|
||||
#if (G9_15PL != 0)
|
||||
USBA_ISR, // 9.15 - USBA Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
#elif defined(CPU2)
|
||||
PIE_RESERVED_ISR, // 9.15 - Reserved
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 9.16 - Reserved
|
||||
|
||||
#if (G10_9PL != 0)
|
||||
ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_10PL != 0)
|
||||
ADCC2_ISR, // 10.10 - ADCC Interrupt 2
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_11PL != 0)
|
||||
ADCC3_ISR, // 10.11 - ADCC Interrupt 3
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_12PL != 0)
|
||||
ADCC4_ISR, // 10.12 - ADCC Interrupt 4
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_13PL != 0)
|
||||
ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_14PL != 0)
|
||||
ADCD2_ISR, // 10.14 - ADCD Interrupt 2
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_15PL != 0)
|
||||
ADCD3_ISR, // 10.15 - ADCD Interrupt 3
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G10_16PL != 0)
|
||||
ADCD4_ISR, // 10.16 - ADCD Interrupt 4
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
PIE_RESERVED_ISR, // 11.9 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.10 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.11 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.12 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.13 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.14 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.15 - Reserved
|
||||
PIE_RESERVED_ISR, // 11.16 - Reserved
|
||||
|
||||
#if (G12_9PL != 0)
|
||||
EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_10PL != 0)
|
||||
RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_11PL != 0)
|
||||
FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_12PL != 0)
|
||||
RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_13PL != 0)
|
||||
SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_14PL != 0)
|
||||
AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_15PL != 0)
|
||||
CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
#if (G12_16PL != 0)
|
||||
CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt
|
||||
#else
|
||||
INT_NOTUSED_ISR,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
//
|
||||
// InitPieVectTable - This function initializes the PIE vector table to a known
|
||||
// state. This function must be executed after boot time.
|
||||
//
|
||||
void
|
||||
InitPieVectTable(void)
|
||||
{
|
||||
int16 i;
|
||||
Uint32 *Source = (void *) &PieVectTableInit;
|
||||
Uint32 *Dest = (void *) &PieVectTable;
|
||||
|
||||
//
|
||||
// Do not write over first 3 32-bit locations (these locations are
|
||||
// initialized by Boot ROM with boot variables)
|
||||
//
|
||||
Source = Source + 3;
|
||||
Dest = Dest + 3;
|
||||
|
||||
EALLOW;
|
||||
for(i=0; i < 221; i++)
|
||||
{
|
||||
*Dest++ = *Source++;
|
||||
}
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
@@ -1,48 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Sci.c
|
||||
//
|
||||
// TITLE: F2837xD SCI Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
#include "F2837xD_device.h" // F2837xD Headerfile Include File
|
||||
#include "F2837xD_Examples.h" // F2837xD Examples Include File
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,175 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Spi.c
|
||||
//
|
||||
// TITLE: F2837xD SPI Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// Calculate BRR: 7-bit baud rate register value
|
||||
// SPI CLK freq = 500 kHz
|
||||
// LSPCLK freq = CPU freq / 4 (by default)
|
||||
// BRR = (LSPCLK freq / SPI CLK freq) - 1
|
||||
//
|
||||
#if CPU_FRQ_200MHZ
|
||||
#define SPI_BRR ((200E6 / 4) / 500E3) - 1
|
||||
#endif
|
||||
|
||||
#if CPU_FRQ_150MHZ
|
||||
#define SPI_BRR ((150E6 / 4) / 500E3) - 1
|
||||
#endif
|
||||
|
||||
#if CPU_FRQ_120MHZ
|
||||
#define SPI_BRR ((120E6 / 4) / 500E3) - 1
|
||||
#endif
|
||||
|
||||
//
|
||||
// InitSPI - This function initializes the SPI to a known state
|
||||
//
|
||||
void InitSpi(void)
|
||||
{
|
||||
// Initialize SPI-A
|
||||
|
||||
// Set reset low before configuration changes
|
||||
// Clock polarity (0 == rising, 1 == falling)
|
||||
// 16-bit character
|
||||
// Enable loop-back
|
||||
SpiaRegs.SPICCR.bit.SPISWRESET = 0;
|
||||
SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
|
||||
SpiaRegs.SPICCR.bit.SPICHAR = (16-1);
|
||||
SpiaRegs.SPICCR.bit.SPILBK = 1;
|
||||
|
||||
// Enable master (0 == slave, 1 == master)
|
||||
// Enable transmission (Talk)
|
||||
// Clock phase (0 == normal, 1 == delayed)
|
||||
// SPI interrupts are disabled
|
||||
SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
|
||||
SpiaRegs.SPICTL.bit.TALK = 1;
|
||||
SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
|
||||
SpiaRegs.SPICTL.bit.SPIINTENA = 0;
|
||||
|
||||
// Set the baud rate
|
||||
SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR;
|
||||
|
||||
// Set FREE bit
|
||||
// Halting on a breakpoint will not halt the SPI
|
||||
SpiaRegs.SPIPRI.bit.FREE = 1;
|
||||
|
||||
// Release the SPI from reset
|
||||
SpiaRegs.SPICCR.bit.SPISWRESET = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// InitSpiGpio - This function initializes GPIO pins to function as SPI pins.
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3
|
||||
// different peripheral functional pins. By default all pins come
|
||||
// up as GPIO inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// For each SPI peripheral
|
||||
// Only one GPIO pin should be enabled for SPISOMO operation.
|
||||
// Only one GPIO pin should be enabled for SPISOMI operation.
|
||||
// Only one GPIO pin should be enabled for SPICLK operation.
|
||||
// Only one GPIO pin should be enabled for SPISTE operation.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
void InitSpiGpio()
|
||||
{
|
||||
InitSpiaGpio();
|
||||
}
|
||||
|
||||
//
|
||||
// InitSpiaGpio - Initialize SPIA GPIOs
|
||||
//
|
||||
void InitSpiaGpio()
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
//
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (SPISIMOA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (SPISOMIA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
//
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA)
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (SPISIMOA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA)
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (SPISOMIA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)
|
||||
|
||||
//
|
||||
//Configure SPI-A pins using GPIO regs
|
||||
//
|
||||
// This specifies which of the possible GPIO pins will be SPI functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // Configure GPIO5 as SPISIMOA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as SPISOMIA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,153 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_TempSensorConv.c
|
||||
//
|
||||
// TITLE: F2837xD Temperature Sensor Conversion Functions
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// Defines
|
||||
//
|
||||
#define FP_SCALE 32768 //Scale factor for Q15 fixed point numbers (2^15)
|
||||
#define FP_ROUND FP_SCALE/2 //Added to Q15 numbers before converting to
|
||||
//integer to round the number.
|
||||
#define KELVIN 273 // Amount to add to Q15 fixed point numbers
|
||||
// to shift from Celsius to Kelvin
|
||||
// (Converting guarantees number is
|
||||
// positive, which makes rounding more
|
||||
// efficient)
|
||||
#define KELVIN_OFF FP_SCALE*KELVIN
|
||||
#define getTempSlope() (*(int (*)(void))0x7036E)() //Slope of temperature sensor
|
||||
//(deg. C / ADC code).
|
||||
//Stored in fixed point Q15
|
||||
//format.
|
||||
#define getTempOffset() (*(int (*)(void))0x70372)() //ADC code corresponding to
|
||||
//temperature sensor output
|
||||
//at 0 deg. C
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
float32 tempSensor_tempSlope;
|
||||
float32 tempSensor_tempOffset;
|
||||
float32 tempSensor_scaleFactor;
|
||||
|
||||
//
|
||||
// InitTempSensor - Initialize the temperature sensor by powering up the
|
||||
// sensor, loading the calibration values from OTP to RAM,
|
||||
// and recording the intended VREFHI voltage.
|
||||
// Note: This function doesn't support VREFLO != 0.0V,
|
||||
// but this could be implemented if desired.
|
||||
//
|
||||
void InitTempSensor(float32 vrefhi_voltage)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
//power up the the temperature sensor
|
||||
//
|
||||
AnalogSubsysRegs.TSNSCTL.bit.ENABLE = 1;
|
||||
|
||||
//
|
||||
//delay to allow the sensor to power up
|
||||
//
|
||||
DELAY_US(1000);
|
||||
|
||||
EDIS;
|
||||
|
||||
//
|
||||
//need to remember VREFHI voltage so that sensor readings can be scaled
|
||||
//to match 2.5V values used for calibration data.
|
||||
//
|
||||
tempSensor_scaleFactor = vrefhi_voltage;
|
||||
|
||||
//
|
||||
//check the device revision
|
||||
//
|
||||
if(DevCfgRegs.REVID >= 3)
|
||||
{
|
||||
//
|
||||
//for production devices (Rev. C), pull the slope and offset from OTP
|
||||
//
|
||||
tempSensor_tempSlope = (int32)getTempSlope();
|
||||
tempSensor_tempOffset = getTempOffset();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
//for pre-production devices, use these static values for slope
|
||||
//and offset
|
||||
//
|
||||
tempSensor_tempSlope = 5196;
|
||||
tempSensor_tempOffset = 1788;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// GetTemperatureC - This function uses the reference data stored in OTP to
|
||||
// convert the raw temperature sensor reading into degrees C
|
||||
//
|
||||
int16 GetTemperatureC(int16 sensorSample)
|
||||
{
|
||||
sensorSample = (int16)((tempSensor_scaleFactor/2.5)*(sensorSample));
|
||||
|
||||
return (((sensorSample - tempSensor_tempOffset)*tempSensor_tempSlope +
|
||||
FP_ROUND + KELVIN_OFF)/FP_SCALE - KELVIN);
|
||||
}
|
||||
|
||||
//
|
||||
// GetTemperatureK - This function uses the reference data stored in OTP to
|
||||
// convert the raw temperature sensor reading into degrees K
|
||||
//
|
||||
int16 GetTemperatureK(int16 sensorSample)
|
||||
{
|
||||
sensorSample = (int16)((tempSensor_scaleFactor/2.5)*(sensorSample));
|
||||
|
||||
return (((sensorSample - tempSensor_tempOffset)*tempSensor_tempSlope +
|
||||
FP_ROUND + KELVIN_OFF)/FP_SCALE);
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,153 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_Upp.c
|
||||
//
|
||||
// TITLE: F2837xD Upp Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// InitUpp1Gpio - Initialize UPP1 GPIOs
|
||||
//
|
||||
void InitUpp1Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Disable internal pull-up for the selected output pins
|
||||
// for reduced power consumption
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (uPP_WAIT)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (uPP_START)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (uPP_ENA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (uPP_D7)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (uPP_D6)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (uPP_D5)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 1; // Disable pull-up on GPIO16 (uPP_D4)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 1; // Disable pull-up on GPIO17 (uPP_D3)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; // Disable pull-up on GPIO18 (uPP_D2)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 1; // Disable pull-up on GPIO19 (uPP_D1)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (uPP_D0)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (uPP_CLK)
|
||||
|
||||
//
|
||||
// Disable QUAL for selected pins (ASYNC Input)
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Disable pull-up on GPIO10 (uPP_WAIT)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Disable pull-up on GPIO11 (uPP_START)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Disable pull-up on GPIO12 (uPP_ENA)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Disable pull-up on GPIO13 (uPP_D7)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Disable pull-up on GPIO14 (uPP_D6)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Disable pull-up on GPIO15 (uPP_D5)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Disable pull-up on GPIO16 (uPP_D4)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Disable pull-up on GPIO17 (uPP_D3)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Disable pull-up on GPIO18 (uPP_D2)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Disable pull-up on GPIO19 (uPP_D1)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 3; // Disable pull-up on GPIO20 (uPP_D0)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Disable pull-up on GPIO21 (uPP_CLK)
|
||||
|
||||
//
|
||||
// Configure uPP-1 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPWM1 functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 3; // Configure GPIO10 as uPP_WAIT
|
||||
GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 3; // Configure GPIO11 as uPP_START
|
||||
GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 3; // Configure GPIO12 as uPP_ENA
|
||||
GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7
|
||||
GpioCtrlRegs.GPAGMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6
|
||||
GpioCtrlRegs.GPAGMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5
|
||||
GpioCtrlRegs.GPAGMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4
|
||||
GpioCtrlRegs.GPAGMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3
|
||||
GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2
|
||||
GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1
|
||||
GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0
|
||||
GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 3; // Configure GPIO21 as uPP_CLK
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 3; // Configure GPIO10 as uPP_WAIT
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as uPP_START
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // Configure GPIO12 as uPP_ENA
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 as uPP_CLK
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// SoftResetUpp - Trigger an internal uPP reset
|
||||
//
|
||||
void SoftResetUpp(void)
|
||||
{
|
||||
UppRegs.PERCTL.bit.SOFTRST = 1; // Issue uPP Internal Reset.
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
UppRegs.PERCTL.bit.SOFTRST = 0; // Release uPP Internal Reset.
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,131 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_can.c
|
||||
//
|
||||
// TITLE: F2837xD CAN Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_Examples.h"
|
||||
|
||||
//
|
||||
// InitCAN - Initializes the CAN-A controller after reset.
|
||||
//
|
||||
void InitCAN(void)
|
||||
{
|
||||
int16_t iMsg;
|
||||
|
||||
//
|
||||
// Place CAN controller in init state, regardless of previous state. This
|
||||
// will put controller in idle, and allow the message object RAM to be
|
||||
// programmed.
|
||||
//
|
||||
CanaRegs.CAN_CTL.bit.Init = 1;
|
||||
CanaRegs.CAN_CTL.bit.SWR = 1;
|
||||
|
||||
//
|
||||
// Wait for busy bit to clear
|
||||
//
|
||||
while(CanaRegs.CAN_IF1CMD.bit.Busy)
|
||||
{
|
||||
}
|
||||
|
||||
//
|
||||
// Clear the message value bit in the arbitration register. This indicates
|
||||
// the message is not valid and is a "safe" condition to leave the message
|
||||
// object. The same arb reg is used to program all the message objects.
|
||||
//
|
||||
CanaRegs.CAN_IF1CMD.bit.DIR = 1;
|
||||
CanaRegs.CAN_IF1CMD.bit.Arb = 1;
|
||||
CanaRegs.CAN_IF1CMD.bit.Control = 1;
|
||||
|
||||
CanaRegs.CAN_IF1ARB.all = 0;
|
||||
|
||||
CanaRegs.CAN_IF1MCTL.all = 0;
|
||||
|
||||
CanaRegs.CAN_IF2CMD.bit.DIR = 1;
|
||||
CanaRegs.CAN_IF2CMD.bit.Arb = 1;
|
||||
CanaRegs.CAN_IF2CMD.bit.Control = 1;
|
||||
|
||||
CanaRegs.CAN_IF2ARB.all = 0;
|
||||
|
||||
CanaRegs.CAN_IF2MCTL.all = 0;
|
||||
|
||||
//
|
||||
// Loop through to program all 32 message objects
|
||||
//
|
||||
for(iMsg = 1; iMsg <= 32; iMsg+=2)
|
||||
{
|
||||
//
|
||||
// Wait for busy bit to clear
|
||||
//
|
||||
while(CanaRegs.CAN_IF1CMD.bit.Busy)
|
||||
{
|
||||
}
|
||||
|
||||
//
|
||||
// Initiate programming the message object
|
||||
//
|
||||
CanaRegs.CAN_IF1CMD.bit.MSG_NUM = iMsg;
|
||||
|
||||
//
|
||||
// Wait for busy bit to clear
|
||||
//
|
||||
while(CanaRegs.CAN_IF2CMD.bit.Busy)
|
||||
{
|
||||
}
|
||||
|
||||
//
|
||||
// Initiate programming the message object
|
||||
//
|
||||
CanaRegs.CAN_IF2CMD.bit.MSG_NUM = iMsg + 1;
|
||||
}
|
||||
|
||||
//
|
||||
// Acknowledge any pending status interrupts.
|
||||
//
|
||||
volatile uint32_t discardRead = CanaRegs.CAN_ES.all;
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,185 +0,0 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// File: F2837xD_sci_io.c
|
||||
//
|
||||
// Description: Contains the various functions related to the serial
|
||||
// communications interface (SCI) object
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include <stdio.h>
|
||||
#include <file.h>
|
||||
#include "F28x_Project.h"
|
||||
#include "F2837xD_sci_io.h"
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
uint16_t deviceOpen = 0;
|
||||
|
||||
//
|
||||
// SCI_open - Initialize and setup SCI
|
||||
//
|
||||
int SCI_open(const char * path, unsigned flags, int llv_fd)
|
||||
{
|
||||
if(deviceOpen)
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
else
|
||||
{
|
||||
EALLOW;
|
||||
CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
|
||||
SciaRegs.SCIFFTX.all=0xE040;
|
||||
SciaRegs.SCIFFRX.all=0x2044;
|
||||
SciaRegs.SCIFFCT.all=0x0;
|
||||
SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
|
||||
// No parity,8 char bits,
|
||||
// async mode, idle-line protocol
|
||||
SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
|
||||
// Disable RX ERR, SLEEP, TXWAKE
|
||||
SciaRegs.SCICTL2.all =0x0003;
|
||||
SciaRegs.SCICTL2.bit.TXINTENA =1;
|
||||
SciaRegs.SCICTL2.bit.RXBKINTENA =1;
|
||||
|
||||
SciaRegs.SCIHBAUD.bit.BAUD =0x0000; // 9600 baud @LSPCLK = 10MHz
|
||||
//(40 MHz SYSCLK).
|
||||
SciaRegs.SCILBAUD.bit.BAUD =0x0081;
|
||||
|
||||
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
|
||||
EDIS;
|
||||
|
||||
deviceOpen = 1;
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// SCI_close - Set SCI to closed
|
||||
//
|
||||
int SCI_close(int dev_fd)
|
||||
{
|
||||
if((dev_fd != 1) || (!deviceOpen))
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
else
|
||||
{
|
||||
deviceOpen = 0;
|
||||
return (0);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// SCI_read - Read from the SCI RX buffer
|
||||
//
|
||||
int SCI_read(int dev_fd, char * buf, unsigned count)
|
||||
{
|
||||
uint16_t readCount = 0;
|
||||
uint16_t * bufPtr = (uint16_t *) buf;
|
||||
|
||||
if(count == 0)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
while((readCount < count) && SciaRegs.SCIRXST.bit.RXRDY)
|
||||
{
|
||||
*bufPtr = SciaRegs.SCIRXBUF.bit.SAR;
|
||||
readCount++;
|
||||
bufPtr++;
|
||||
}
|
||||
|
||||
return (readCount);
|
||||
}
|
||||
|
||||
//
|
||||
// SCI_write - Write to the SCI TX buffer
|
||||
//
|
||||
int SCI_write(int dev_fd, char * buf, unsigned count)
|
||||
{
|
||||
uint16_t writeCount = 0;
|
||||
uint16_t * bufPtr = (uint16_t *) buf;
|
||||
|
||||
if(count == 0)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
while(writeCount < count)
|
||||
{
|
||||
while(SciaRegs.SCICTL2.bit.TXRDY != 1)
|
||||
{
|
||||
}
|
||||
SciaRegs.SCITXBUF.bit.TXDT = *bufPtr;
|
||||
writeCount++;
|
||||
bufPtr++;
|
||||
}
|
||||
|
||||
return (writeCount);
|
||||
}
|
||||
|
||||
//
|
||||
// SCI_lseek - Do nothing
|
||||
//
|
||||
off_t SCI_lseek(int dev_fd, off_t offset, int origin)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
//
|
||||
// SCI_unlink - Do nothing
|
||||
//
|
||||
int SCI_unlink(const char * path)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
//
|
||||
// SCI_rename - Do nothing
|
||||
//
|
||||
int SCI_rename(const char * old_name, const char * new_name)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,554 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_sdfm_drivers.c
|
||||
//
|
||||
// TITLE: SDFM Driver functions
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F28x_Project.h"
|
||||
#include "F2837xD_struct.h"
|
||||
#include "F2837xD_sdfm_drivers.h"
|
||||
|
||||
//
|
||||
// Sdfm_configureInputCtrl - This function configures SDFM Input control unit.
|
||||
// sdfmNumber - This parameter should be used to
|
||||
// select SDFM1 (or) SDFM2
|
||||
// filterNumber - This parameter is used to select
|
||||
// which filter (FILTER1,FILTER2,
|
||||
// FILTER3,FILTER4) needs to be
|
||||
// configured.
|
||||
// mode - This parameter is used to select
|
||||
// one of the modes mentioned above
|
||||
//
|
||||
// Input control unit can be configured in four different modes:
|
||||
// MODE_0 : Modulator clock rate = Modulator data rate
|
||||
// MODE_1 : Modulator clock rate = (Modulator data rate / 2)
|
||||
// MODE_2 : Manchester encoded data (Modulator clock is encoded into data)
|
||||
// MODE_3 : Modulator clock rate = (2 x Modulator data rate)
|
||||
//
|
||||
void Sdfm_configureInputCtrl(Uint16 sdfmNumber, Uint16 filterNumber,
|
||||
Uint16 mode)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
switch (filterNumber)
|
||||
{
|
||||
case FILTER1:
|
||||
(*SDFM[sdfmNumber]).SDCTLPARM1.bit.MOD = mode;
|
||||
break;
|
||||
|
||||
case FILTER2:
|
||||
(*SDFM[sdfmNumber]).SDCTLPARM2.bit.MOD = mode;
|
||||
break;
|
||||
|
||||
case FILTER3:
|
||||
(*SDFM[sdfmNumber]).SDCTLPARM3.bit.MOD = mode;
|
||||
break;
|
||||
|
||||
case FILTER4:
|
||||
(*SDFM[sdfmNumber]).SDCTLPARM4.bit.MOD = mode;
|
||||
break;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// Sdfm_configureComparator - This function configures SDFM Comparator unit.
|
||||
// Comparator unit can be configured to monitor
|
||||
// input conditions with a fast settling time.
|
||||
// This module can be programmed to detect over and
|
||||
// under value conditions.
|
||||
//
|
||||
// sdfmNumber - This parameter should be used to
|
||||
// select SDFM1 (or) SDFM2
|
||||
// filterNumber - This parameter is used to select
|
||||
// which filter (FILTER1,FILTER2,
|
||||
// FILTER3,FILTER3)
|
||||
// filterType - This parameter is used to select
|
||||
// one of the filter type mentioned
|
||||
// above (SINC1,SINC2,SINC3,SINCFAST)
|
||||
// OSR - This parameter is used to
|
||||
// configure oversampling ratio for
|
||||
// comparator
|
||||
// HLT - This parameter is used to
|
||||
// configure to detect over value
|
||||
// condition
|
||||
// LLT - This parameter is used to
|
||||
// configure to detect under value
|
||||
// condition
|
||||
//
|
||||
void Sdfm_configureComparator(Uint16 sdfmNumber, Uint16 filterNumber,
|
||||
Uint16 filterType, Uint16 OSR, Uint16 HLT,
|
||||
Uint16 LLT)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
switch (filterNumber)
|
||||
{
|
||||
case FILTER1: //Filter 1
|
||||
|
||||
//
|
||||
//Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3
|
||||
//
|
||||
(*SDFM[sdfmNumber]).SDCPARM1.bit.CS1_CS0 = filterType;
|
||||
|
||||
//
|
||||
//Configure OSR value
|
||||
//
|
||||
if(OSR<=COMPARATOR_MAX_OSR)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = OSR;
|
||||
}
|
||||
else
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = COMPARATOR_MAX_OSR;
|
||||
}
|
||||
|
||||
(*SDFM[sdfmNumber]).SDCMPH1.bit.HLT = HLT;
|
||||
(*SDFM[sdfmNumber]).SDCMPL1.bit.LLT = LLT;
|
||||
break;
|
||||
|
||||
case FILTER2: //Filter 2
|
||||
//
|
||||
//Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3
|
||||
//
|
||||
(*SDFM[sdfmNumber]).SDCPARM2.bit.CS1_CS0 = filterType;
|
||||
|
||||
//
|
||||
//Configure OSR value
|
||||
//
|
||||
if(OSR<=COMPARATOR_MAX_OSR)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = OSR;
|
||||
}
|
||||
else
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = COMPARATOR_MAX_OSR;
|
||||
}
|
||||
|
||||
(*SDFM[sdfmNumber]).SDCMPH2.bit.HLT = HLT;
|
||||
(*SDFM[sdfmNumber]).SDCMPL2.bit.LLT = LLT;
|
||||
break;
|
||||
|
||||
case FILTER3: //Filter 3
|
||||
//
|
||||
//Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3
|
||||
//
|
||||
(*SDFM[sdfmNumber]).SDCPARM3.bit.CS1_CS0 = filterType;
|
||||
|
||||
//
|
||||
//Configure OSR value
|
||||
//
|
||||
if(OSR<=COMPARATOR_MAX_OSR)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = OSR;
|
||||
}
|
||||
else
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = COMPARATOR_MAX_OSR;
|
||||
}
|
||||
|
||||
(*SDFM[sdfmNumber]).SDCMPH3.bit.HLT = HLT;
|
||||
(*SDFM[sdfmNumber]).SDCMPL3.bit.LLT = LLT;
|
||||
break;
|
||||
|
||||
case FILTER4: //Filter 4
|
||||
//
|
||||
//Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3
|
||||
//
|
||||
(*SDFM[sdfmNumber]).SDCPARM4.bit.CS1_CS0 = filterType;
|
||||
|
||||
//
|
||||
//Configure Comparator OSR value
|
||||
//
|
||||
if(OSR<=COMPARATOR_MAX_OSR)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = OSR;
|
||||
}
|
||||
else
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = COMPARATOR_MAX_OSR;
|
||||
}
|
||||
|
||||
(*SDFM[sdfmNumber]).SDCMPH4.bit.HLT = HLT;
|
||||
(*SDFM[sdfmNumber]).SDCMPL4.bit.LLT = LLT;
|
||||
break;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// SDFM_configureData_filter - This function configures SDFM Data filter unit
|
||||
//
|
||||
// SDFM Data filter unit can be configured in any
|
||||
// of four different Sinc filter types:
|
||||
// sdfmNumber - This parameter should be used to
|
||||
// select SDFM1 (or) SDFM2
|
||||
// filterNumber - This parameter is used to select
|
||||
// which filter(FILTER1,FILTER2,
|
||||
// FILTER3,FILTER3) needs to be
|
||||
// configured
|
||||
// Filter_switch - This parameter is used to
|
||||
// enable/disable a filter
|
||||
// filterType - This parameter is used to select
|
||||
// one of the filter type mentioned
|
||||
// above (SINC1 / SINC2 / SINC3 /
|
||||
// SINCFAST)
|
||||
// OSR - This parameter is used to
|
||||
// configure oversampling ratio
|
||||
// for Data filter (Upto OSR_256)
|
||||
// DR_switch - This parameter selects whether
|
||||
// data is represented in 16 (or)
|
||||
// 32 bits
|
||||
// shift_bits - When user chooses 16 bit
|
||||
// representation, this variable
|
||||
// allows to right shift by
|
||||
// specific number of bits
|
||||
//
|
||||
void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber,
|
||||
Uint16 Filter_switch, Uint16 filterType,
|
||||
Uint16 OSR, Uint16 DR_switch, Uint16 shift_bits)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
switch(filterNumber)
|
||||
{
|
||||
|
||||
case FILTER1: //Filter 1
|
||||
(*SDFM[sdfmNumber]).SDDFPARM1.bit.FEN = Filter_switch;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM1.bit.SST = filterType;
|
||||
|
||||
//
|
||||
//Configure Sinc filter OSR value
|
||||
//
|
||||
if(OSR<=DATA_FILTER_MAX_OSR)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = OSR;
|
||||
}
|
||||
else
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = DATA_FILTER_MAX_OSR;
|
||||
}
|
||||
|
||||
//
|
||||
//Configure Data filter data representation
|
||||
//DR_switch - Data Representation (0/1 = 16/32b 2's complement)
|
||||
//
|
||||
(*SDFM[sdfmNumber]).SDDPARM1.bit.DR = DR_switch;
|
||||
if(DR_switch == 0)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDPARM1.bit.SH = shift_bits;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case FILTER2: //Filter 2
|
||||
(*SDFM[sdfmNumber]).SDDFPARM2.bit.FEN = Filter_switch;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM2.bit.SST = filterType;
|
||||
|
||||
//
|
||||
//Configure Sinc filter OSR value
|
||||
//
|
||||
if(OSR<=DATA_FILTER_MAX_OSR)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = OSR;
|
||||
}
|
||||
else
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = DATA_FILTER_MAX_OSR;
|
||||
}
|
||||
|
||||
//
|
||||
//Configure Data filter data representation
|
||||
// DR_switch - Data Representation (0/1 = 16/32b 2's complement)
|
||||
//
|
||||
(*SDFM[sdfmNumber]).SDDPARM2.bit.DR = DR_switch;
|
||||
if(DR_switch == 0)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDPARM2.bit.SH = shift_bits;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case FILTER3: //Filter 3
|
||||
(*SDFM[sdfmNumber]).SDDFPARM3.bit.FEN = Filter_switch;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM3.bit.SST = filterType;
|
||||
|
||||
//
|
||||
//Configure Sinc filter OSR value
|
||||
//
|
||||
if(OSR<=DATA_FILTER_MAX_OSR)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = OSR;
|
||||
}
|
||||
else
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = DATA_FILTER_MAX_OSR;
|
||||
}
|
||||
|
||||
//
|
||||
//Configure Data filter data representation
|
||||
// DR_switch - Data Representation (0/1 = 16/32b 2's complement)
|
||||
//
|
||||
(*SDFM[sdfmNumber]).SDDPARM3.bit.DR = DR_switch;
|
||||
if(DR_switch == 0)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDPARM3.bit.SH = shift_bits;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case FILTER4: //Filter 4
|
||||
(*SDFM[sdfmNumber]).SDDFPARM4.bit.FEN = Filter_switch;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM4.bit.SST = filterType;
|
||||
|
||||
//
|
||||
//Configure Sinc filter OSR value
|
||||
//
|
||||
if(OSR<=DATA_FILTER_MAX_OSR)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = OSR;
|
||||
}
|
||||
else
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = DATA_FILTER_MAX_OSR;
|
||||
}
|
||||
|
||||
//
|
||||
//Configure Data filter data representation
|
||||
// DR_switch - Data Representation (0/1 = 16/32b 2's complement)
|
||||
//
|
||||
(*SDFM[sdfmNumber]).SDDPARM4.bit.DR = DR_switch;
|
||||
if(DR_switch == 0)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDDPARM4.bit.SH = shift_bits;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// Sdfm_configureInterrupt - This function configures SDFM Interrupt unit.
|
||||
// SDFM Interrupt unit can be configured to
|
||||
// enable/disable different sources of SDFM
|
||||
// interrupts which should trigger CPU interrupt.
|
||||
//
|
||||
// sdfmNumber - This parameter should be used to
|
||||
// select SDFM1 (or) SDFM2
|
||||
// filterNumber - This parameter is used to select
|
||||
// which filter(FILTER1,FILTER2,
|
||||
// FILTER3,FILTER3) needs to be
|
||||
// configured
|
||||
// IEH_Switch - This parameter allows over value
|
||||
// condition to trigger CPU interrupt
|
||||
// IEL_Switch - This parameter allows under value
|
||||
// condition to trigger CPU interrupt
|
||||
// MFIE_Switch - This parameter allows modulator
|
||||
// failure to trigger CPU interrupt
|
||||
// AE_Switch - This parameter allows new filter
|
||||
// data acknowledge interrupt signal
|
||||
// to trigger CPU interrupt
|
||||
//
|
||||
void Sdfm_configureInterrupt(Uint16 sdfmNumber, Uint16 filterNumber,
|
||||
Uint16 IEH_Switch, Uint16 IEL_Switch,
|
||||
Uint16 MFIE_Switch, Uint16 AE_Switch)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
switch(filterNumber)
|
||||
{
|
||||
case FILTER1: //Filter 1
|
||||
(*SDFM[sdfmNumber]).SDCPARM1.bit.IEH = IEH_Switch;
|
||||
(*SDFM[sdfmNumber]).SDCPARM1.bit.IEL = IEL_Switch;
|
||||
(*SDFM[sdfmNumber]).SDCPARM1.bit.MFIE = MFIE_Switch;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM1.bit.AE = AE_Switch;
|
||||
break;
|
||||
|
||||
case FILTER2: //Filter 2
|
||||
(*SDFM[sdfmNumber]).SDCPARM2.bit.IEH = IEH_Switch;
|
||||
(*SDFM[sdfmNumber]).SDCPARM2.bit.IEL = IEL_Switch;
|
||||
(*SDFM[sdfmNumber]).SDCPARM2.bit.MFIE = MFIE_Switch;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM2.bit.AE = AE_Switch;
|
||||
break;
|
||||
|
||||
case FILTER3: //Filter 3
|
||||
(*SDFM[sdfmNumber]).SDCPARM3.bit.IEH = IEH_Switch;
|
||||
(*SDFM[sdfmNumber]).SDCPARM3.bit.IEL = IEL_Switch;
|
||||
(*SDFM[sdfmNumber]).SDCPARM3.bit.MFIE = MFIE_Switch;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM3.bit.AE = AE_Switch;
|
||||
break;
|
||||
|
||||
case FILTER4: //Filter 4
|
||||
(*SDFM[sdfmNumber]).SDCPARM4.bit.IEH = IEH_Switch;
|
||||
(*SDFM[sdfmNumber]).SDCPARM4.bit.IEL = IEL_Switch;
|
||||
(*SDFM[sdfmNumber]).SDCPARM4.bit.MFIE = MFIE_Switch;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM4.bit.AE = AE_Switch;
|
||||
break;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// SDFM_configExternalreset - This function configures SDFM module to
|
||||
// enable/disable external filter reset from PWM
|
||||
//
|
||||
// sdfmNumber - This parameter should
|
||||
// be used to select
|
||||
// SDFM1 (or) SDFM2
|
||||
// filter1_Config_ext_reset - This parameter is used
|
||||
// to enable/disable
|
||||
// external PWM reset for
|
||||
// filter1
|
||||
// filter2_Config_ext_reset - This parameter is used
|
||||
// to enable/disable
|
||||
// external PWM reset for
|
||||
// filter2
|
||||
// filter3_Config_ext_reset - This parameter is used
|
||||
// to enable / disable
|
||||
// external PWM reset for
|
||||
// filter3
|
||||
// filter4_Config_ext_reset - This parameter is used
|
||||
// to enable / disable
|
||||
// external PWM reset for
|
||||
// filter4
|
||||
//
|
||||
void Sdfm_configureExternalreset(Uint16 sdfmNumber,
|
||||
Uint16 filter1_Config_ext_reset,
|
||||
Uint16 filter2_Config_ext_reset,
|
||||
Uint16 filter3_Config_ext_reset,
|
||||
Uint16 filter4_Config_ext_reset)
|
||||
{
|
||||
EALLOW;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM1.bit.SDSYNCEN = filter1_Config_ext_reset;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM2.bit.SDSYNCEN = filter2_Config_ext_reset;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM3.bit.SDSYNCEN = filter3_Config_ext_reset;
|
||||
(*SDFM[sdfmNumber]).SDDFPARM4.bit.SDSYNCEN = filter4_Config_ext_reset;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// SDFM_enableMFE - This function enables Master filter bit of SDFM module
|
||||
//
|
||||
// sdfmNumber - This parameter should be used to select
|
||||
// SDFM1 (or) SDFM2
|
||||
//
|
||||
void Sdfm_enableMFE(Uint16 sdfmNumber)
|
||||
{
|
||||
EALLOW;
|
||||
(*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 1; //Master Filter bit is enabled
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// SDFM_disableMFE - This function disable Master filter bit of SDFM module
|
||||
//
|
||||
// sdfmNumber - This parameter should be used to select
|
||||
// SDFM1 (or) SDFM2
|
||||
//
|
||||
void SDFM_disableMFE(Uint16 sdfmNumber)
|
||||
{
|
||||
EALLOW;
|
||||
(*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 0; //Master Filter bit is disabled
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// SDFM_enableMIE - This function enable Master Interrupt bit of SDFM module
|
||||
//
|
||||
// sdfmNumber - This parameter should be used to select
|
||||
// SDFM1 (or) SDFM2
|
||||
//
|
||||
void Sdfm_enableMIE(Uint16 sdfmNumber)
|
||||
{
|
||||
EALLOW;
|
||||
//
|
||||
//Enable MIE (Master Interrupt Enable) bit
|
||||
//
|
||||
(*SDFM[sdfmNumber]).SDCTL.bit.MIE = 1;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// Sdfm_disableMIE - This function disable Master Interrupt bit of SDFM module
|
||||
//
|
||||
// sdfmNumber - This parameter should be used to select
|
||||
// SDFM1 (or) SDFM2
|
||||
//
|
||||
void Sdfm_disableMIE(Uint16 sdfmNumber)
|
||||
{
|
||||
|
||||
EALLOW;
|
||||
//
|
||||
//Disable MIE (Master Interrupt Enable) bit
|
||||
//
|
||||
(*SDFM[sdfmNumber]).SDCTL.bit.MIE = 0;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// Sdfm_readFlagRegister - This function helps user read SDFM flag
|
||||
// register (SDIFLG)
|
||||
//
|
||||
Uint32 Sdfm_readFlagRegister(Uint16 sdfmNumber)
|
||||
{
|
||||
return ((*SDFM[sdfmNumber]).SDIFLG.all);
|
||||
}
|
||||
|
||||
//
|
||||
// Sdfm_clearFlagRegister - This function helps is used to clear
|
||||
// SDIFLG register
|
||||
//
|
||||
void Sdfm_clearFlagRegister(Uint16 sdfmNumber,Uint32 sdfmReadFlagRegister)
|
||||
{
|
||||
(*SDFM[sdfmNumber]).SDIFLGCLR.all = sdfmReadFlagRegister;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,100 +0,0 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F2837xD_struct.c
|
||||
//
|
||||
// TITLE: F2837xD SDFM structure
|
||||
//
|
||||
//###########################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "F2837xD_device.h"
|
||||
#include "F2837xD_struct.h"
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
#if defined(CPU1)
|
||||
volatile struct ADC_REGS *ADC[MAX_ADC] =
|
||||
{ 0, &AdcaRegs, &AdcbRegs,
|
||||
&AdccRegs, &AdcdRegs };
|
||||
#endif
|
||||
|
||||
volatile struct ECAP_REGS *ECAP[MAX_ECAP] =
|
||||
{ 0, &ECap1Regs, &ECap2Regs, &ECap3Regs,
|
||||
&ECap4Regs, &ECap5Regs, &ECap6Regs };
|
||||
|
||||
volatile struct EPWM_REGS *EPWM[MAX_EPWM] =
|
||||
{ 0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs,
|
||||
&EPwm4Regs, &EPwm5Regs, &EPwm6Regs,
|
||||
&EPwm7Regs, &EPwm8Regs, &EPwm9Regs,
|
||||
&EPwm10Regs, &EPwm11Regs, &EPwm12Regs };
|
||||
|
||||
volatile struct EQEP_REGS *EQEP[MAX_EQEP] =
|
||||
{ 0, &EQep1Regs, &EQep2Regs, &EQep3Regs };
|
||||
|
||||
volatile struct I2C_REGS *I2C[MAX_I2C] =
|
||||
{ 0, &I2caRegs };
|
||||
|
||||
volatile struct McBSP_REGS *MCBSP[MAX_MCBSP] =
|
||||
{ 0, &McbspaRegs };
|
||||
|
||||
volatile struct SCI_REGS *SCI[MAX_SCI] =
|
||||
{ 0, &SciaRegs };
|
||||
|
||||
volatile struct SPI_REGS *SPI[MAX_SPI] =
|
||||
{ 0, &SpiaRegs, &SpibRegs, &SpicRegs };
|
||||
|
||||
volatile struct SDFM_REGS *SDFM[MAX_SDFM] =
|
||||
{ 0, &Sdfm1Regs, &Sdfm2Regs};
|
||||
|
||||
#if defined(CPU1)
|
||||
volatile Uint16 *TRIP_SEL[MAX_TRIPSEL] =
|
||||
{ 0, &InputXbarRegs.INPUT1SELECT, &InputXbarRegs.INPUT2SELECT,
|
||||
&InputXbarRegs.INPUT3SELECT, &InputXbarRegs.INPUT4SELECT,
|
||||
&InputXbarRegs.INPUT5SELECT, &InputXbarRegs.INPUT6SELECT,
|
||||
&InputXbarRegs.INPUT7SELECT, &InputXbarRegs.INPUT8SELECT,
|
||||
&InputXbarRegs.INPUT9SELECT, &InputXbarRegs.INPUT10SELECT,
|
||||
&InputXbarRegs.INPUT11SELECT, &InputXbarRegs.INPUT12SELECT,
|
||||
&InputXbarRegs.INPUT13SELECT, &InputXbarRegs.INPUT14SELECT
|
||||
};
|
||||
#endif
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@@ -1,109 +0,0 @@
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// FILE: F2837xD_usDelay.asm
|
||||
;//
|
||||
;// TITLE: Simple delay function
|
||||
;//
|
||||
;// DESCRIPTION:
|
||||
;// This is a simple delay function that can be used to insert a specified
|
||||
;// delay into code.
|
||||
;// This function is only accurate if executed from internal zero-waitstate
|
||||
;// SARAM. If it is executed from waitstate memory then the delay will be
|
||||
;// longer then specified.
|
||||
;// To use this function:
|
||||
;// 1 - update the CPU clock speed in the F2837xD_Examples.h
|
||||
;// file. For example:
|
||||
;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
|
||||
;// 2 - Call this function by using the DELAY_US(A) macro
|
||||
;// that is defined in the F2837xD_Device.h file. This macro
|
||||
;// will convert the number of microseconds specified
|
||||
;// into a loop count for use with this function.
|
||||
;// This count will be based on the CPU frequency you specify.
|
||||
;// 3 - For the most accurate delay
|
||||
;// - Execute this function in 0 waitstate RAM.
|
||||
;// - Disable interrupts before calling the function
|
||||
;// If you do not disable interrupts, then think of
|
||||
;// this as an "at least" delay function as the actual
|
||||
;// delay may be longer.
|
||||
;// The C assembly call from the DELAY_US(time) macro will
|
||||
;// look as follows:
|
||||
;// extern void Delay(long LoopCount);
|
||||
;// MOV AL,#LowLoopCount
|
||||
;// MOV AH,#HighLoopCount
|
||||
;// LCR _Delay
|
||||
;// Or as follows (if count is less then 16-bits):
|
||||
;// MOV ACC,#LoopCount
|
||||
;// LCR _Delay
|
||||
;//
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// $Release Date: $
|
||||
;// $Copyright:
|
||||
;// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
;//
|
||||
;// Redistribution and use in source and binary forms, with or without
|
||||
;// modification, are permitted provided that the following conditions
|
||||
;// are met:
|
||||
;//
|
||||
;// Redistributions of source code must retain the above copyright
|
||||
;// notice, this list of conditions and the following disclaimer.
|
||||
;//
|
||||
;// Redistributions in binary form must reproduce the above copyright
|
||||
;// notice, this list of conditions and the following disclaimer in the
|
||||
;// documentation and/or other materials provided with the
|
||||
;// distribution.
|
||||
;//
|
||||
;// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
;// its contributors may be used to endorse or promote products derived
|
||||
;// from this software without specific prior written permission.
|
||||
;//
|
||||
;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;// $
|
||||
;//###########################################################################
|
||||
|
||||
.if __TI_EABI__
|
||||
.asg F28x_usDelay, _F28x_usDelay
|
||||
.endif
|
||||
|
||||
.def _F28x_usDelay
|
||||
|
||||
.cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro
|
||||
%{
|
||||
%}
|
||||
|
||||
.if __TI_COMPILER_VERSION__
|
||||
.if __TI_COMPILER_VERSION__ >= 15009000
|
||||
.sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer
|
||||
.else
|
||||
.sect "ramfuncs" ;;Used with compilers older than v15.9.0
|
||||
.endif
|
||||
.endif
|
||||
|
||||
.global __F28x_usDelay
|
||||
_F28x_usDelay:
|
||||
SUB ACC,#1
|
||||
BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0
|
||||
LRETR
|
||||
|
||||
;There is a 9/10 cycle overhead and each loop
|
||||
;takes five cycles. The LoopCount is given by
|
||||
;the following formula:
|
||||
; DELAY_CPU_CYCLES = 9 + 5*LoopCount
|
||||
; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
|
||||
; The macro DELAY_US(A) performs this calculation for you
|
||||
;
|
||||
;
|
||||
|
||||
;//
|
||||
;// End of file
|
||||
;//
|
||||
@@ -1,706 +0,0 @@
|
||||
//#############################################################################
|
||||
//
|
||||
// FILE: device.c
|
||||
//
|
||||
// TITLE: Device setup for examples.
|
||||
//
|
||||
//#############################################################################
|
||||
//
|
||||
// $Release Date: $
|
||||
// $Copyright:
|
||||
// Copyright (C) 2013-2024 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// $
|
||||
//#############################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "device.h"
|
||||
#include "driverlib.h"
|
||||
#include "inc/hw_ipc.h"
|
||||
|
||||
#ifdef CMDTOOL
|
||||
#include "device_cmd.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
using std::memcpy;
|
||||
#endif
|
||||
|
||||
#define PASS 0
|
||||
#define FAIL 1
|
||||
|
||||
uint32_t Example_Result = FAIL;
|
||||
uint32_t Example_PassCount = 0;
|
||||
uint32_t Example_Fail = 0;
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to initialize the device. Primarily initializes system control to a
|
||||
// known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
|
||||
// and enabling the clocks to the peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_init(void)
|
||||
{
|
||||
//
|
||||
// Disable the watchdog
|
||||
//
|
||||
SysCtl_disableWatchdog();
|
||||
|
||||
#ifdef CMDTOOL
|
||||
CMD_init();
|
||||
#endif
|
||||
|
||||
#ifdef _FLASH
|
||||
#ifndef CMDTOOL
|
||||
//
|
||||
// Copy time critical code and flash setup code to RAM. This includes the
|
||||
// following functions: InitFlash();
|
||||
//
|
||||
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
|
||||
// are created by the linker. Refer to the device .cmd file.
|
||||
//
|
||||
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
|
||||
#endif
|
||||
|
||||
//
|
||||
// Call Flash Initialization to setup flash waitstates. This function must
|
||||
// reside in RAM.
|
||||
//
|
||||
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
|
||||
#endif
|
||||
#ifdef CPU1
|
||||
|
||||
//
|
||||
// Configure Analog Trim in case of untrimmed or TMX sample
|
||||
//
|
||||
if((SysCtl_getDeviceParametric(SYSCTL_DEVICE_QUAL) == 0x0U) &&
|
||||
(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) == 0x0U))
|
||||
{
|
||||
Device_configureTMXAnalogTrim();
|
||||
}
|
||||
|
||||
//
|
||||
// Set up PLL control and clock dividers
|
||||
//
|
||||
SysCtl_setClock(DEVICE_SETCLOCK_CFG);
|
||||
|
||||
//
|
||||
// Make sure the LSPCLK divider is set to the default (divide by 4)
|
||||
//
|
||||
SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4);
|
||||
|
||||
//
|
||||
// These asserts will check that the #defines for the clock rates in
|
||||
// device.h match the actual rates that have been configured. If they do
|
||||
// not match, check that the calculations of DEVICE_SYSCLK_FREQ and
|
||||
// DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
|
||||
// expected if these are not correct.
|
||||
//
|
||||
ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
|
||||
ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
|
||||
|
||||
#ifndef _FLASH
|
||||
//
|
||||
// Call Device_cal function when run using debugger
|
||||
// This function is called as part of the Boot code. The function is called
|
||||
// in the Device_init function since during debug time resets, the boot code
|
||||
// will not be executed and the gel script will reinitialize all the
|
||||
// registers and the calibrated values will be lost.
|
||||
// Sysctl_deviceCal is a wrapper function for Device_Cal
|
||||
//
|
||||
SysCtl_deviceCal();
|
||||
#endif
|
||||
|
||||
#endif
|
||||
//
|
||||
// Turn on all peripherals
|
||||
//
|
||||
Device_enableAllPeripherals();
|
||||
|
||||
//
|
||||
// Initialize result parameter as FAIL
|
||||
//
|
||||
Example_Result = FAIL;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to turn on all peripherals, enabling reads and writes to the
|
||||
// peripherals' registers.
|
||||
//
|
||||
// Note that to reduce power, unused peripherals should be disabled.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_enableAllPeripherals(void)
|
||||
{
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2);
|
||||
#ifdef CPU1
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM);
|
||||
#endif
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
|
||||
|
||||
#ifdef CPU1
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2);
|
||||
#endif
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB);
|
||||
|
||||
#ifdef CPU1
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA);
|
||||
#endif
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8);
|
||||
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to disable pin locks on GPIOs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_initGPIO(void)
|
||||
{
|
||||
//
|
||||
// Disable pin locks.
|
||||
//
|
||||
GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF);
|
||||
GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF);
|
||||
|
||||
//
|
||||
// Enable GPIO Pullups
|
||||
//
|
||||
Device_enableUnbondedGPIOPullups();
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to enable pullups for the unbonded GPIOs on the 176PTP package:
|
||||
// GPIOs Grp Bits
|
||||
// 95-132 C 31
|
||||
// D 31:0
|
||||
// E 4:0
|
||||
// 134-168 E 31:6
|
||||
// F 8:0
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
void Device_enableUnbondedGPIOPullupsFor176Pin(void)
|
||||
{
|
||||
EALLOW;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to enable pullups for the unbonded GPIOs on the 100PZ package:
|
||||
// GPIOs Grp Bits
|
||||
// 0-1 A 1:0
|
||||
// 5-9 A 9:5
|
||||
// 22-40 A 31:22
|
||||
// B 8:0
|
||||
// 44-57 B 25:12
|
||||
// 67-68 C 4:3
|
||||
// 74-77 C 13:10
|
||||
// 79-83 C 19:15
|
||||
// 93-168 C 31:29
|
||||
// D 31:0
|
||||
// E 31:0
|
||||
// F 8:0
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_enableUnbondedGPIOPullupsFor100Pin(void)
|
||||
{
|
||||
EALLOW;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU;
|
||||
HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to enable pullups for the unbonded GPIOs on the 100PZ or
|
||||
// 176PTP package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_enableUnbondedGPIOPullups(void)
|
||||
{
|
||||
//
|
||||
// bits 8-10 have pin count
|
||||
//
|
||||
uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) &
|
||||
(uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >>
|
||||
SYSCTL_PARTIDL_PIN_COUNT_S);
|
||||
|
||||
/*
|
||||
* 5 = 100 pin
|
||||
* 6 = 176 pin
|
||||
* 7 = 337 pin
|
||||
*/
|
||||
if(pinCount == 5)
|
||||
{
|
||||
Device_enableUnbondedGPIOPullupsFor100Pin();
|
||||
}
|
||||
else if(pinCount == 6)
|
||||
{
|
||||
Device_enableUnbondedGPIOPullupsFor176Pin();
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Do nothing - this is 337 pin package
|
||||
//
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CPU1
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Function to implement Analog trim of TMX devices
|
||||
//
|
||||
//*****************************************************************************
|
||||
void Device_configureTMXAnalogTrim(void)
|
||||
{
|
||||
//
|
||||
// Enable ADC clock
|
||||
//
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
|
||||
|
||||
//
|
||||
// Configure ADC reference trim for TMX devices
|
||||
//
|
||||
EALLOW;
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) = 0x7BDDU;
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMB) = 0x7BDDU;
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMC) = 0x7BDDU;
|
||||
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMD) = 0x7BDDU;
|
||||
|
||||
//
|
||||
// Configure ADC offset trim. The user should generate the trim values
|
||||
// by following the instructions in the "ADC Zero Offset Calibration"
|
||||
// section in device TRM. The below lines needs to be uncommented and
|
||||
// updated with the correct trim values.
|
||||
//
|
||||
// HWREGH(ADCA_BASE + ADC_O_OFFTRIM) = 0x0U;
|
||||
// HWREGH(ADCB_BASE + ADC_O_OFFTRIM) = 0x0U;
|
||||
// HWREGH(ADCC_BASE + ADC_O_OFFTRIM) = 0x0U;
|
||||
// HWREGH(ADCD_BASE + ADC_O_OFFTRIM) = 0x0U;
|
||||
|
||||
//
|
||||
// Configure internal oscillator trim. If the internal oscillator trim
|
||||
// contains all zeros, the user can adjust the lowest 10 bits of the
|
||||
// oscillator trim register between 1 (minimum) and 1023 (maximum)
|
||||
// while observing the system clock on the XCLOCKOUT pin. The below
|
||||
// lines needs to be uncommented and updated with the correct trim values.
|
||||
//
|
||||
// if(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) == 0x0U)
|
||||
// {
|
||||
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) = 0x0U;
|
||||
// }
|
||||
// if( HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U)
|
||||
// {
|
||||
// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U;
|
||||
// }
|
||||
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Disable ADC clock
|
||||
//
|
||||
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
|
||||
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCB);
|
||||
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
|
||||
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCD);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//! Executes a CPU02 control system bootloader.
|
||||
//!
|
||||
//! \param bootMode specifies which CPU02 control system boot mode to execute.
|
||||
//!
|
||||
//! This function will allow the CPU01 master system to boot the CPU02 control
|
||||
//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI,
|
||||
//! SCI, I2C, or parallel I/O. This function blocks and waits until the
|
||||
//! control system boot ROM is configured and ready to receive CPU01 to CPU02
|
||||
//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and
|
||||
//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the
|
||||
//! command to execute the selected bootloader.
|
||||
//!
|
||||
//! The \e bootMode parameter accepts one of the following values:
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM
|
||||
//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH
|
||||
//!
|
||||
//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is
|
||||
//! invalid and command was not sent.
|
||||
//
|
||||
//*****************************************************************************
|
||||
uint16_t
|
||||
Device_bootCPU2(uint32_t bootMode)
|
||||
{
|
||||
uint32_t bootStatus;
|
||||
uint16_t pin;
|
||||
uint16_t returnStatus = STATUS_PASS;
|
||||
|
||||
//
|
||||
// If CPU2 has already booted, return a fail to let the application
|
||||
// know that something is out of the ordinary.
|
||||
//
|
||||
bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & 0x0000000FU;
|
||||
|
||||
if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK)
|
||||
{
|
||||
//
|
||||
// Check if MSB is set as well
|
||||
//
|
||||
bootStatus = ((uint32_t)(HWREG(IPC_BASE + IPC_O_BOOTSTS) &
|
||||
0x80000000U)) >> 31U;
|
||||
|
||||
if(bootStatus != 0)
|
||||
{
|
||||
returnStatus = STATUS_FAIL;
|
||||
|
||||
return returnStatus;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Wait until CPU02 control system boot ROM is ready to receive
|
||||
// CPU01 to CPU02 INT1 interrupts.
|
||||
//
|
||||
do
|
||||
{
|
||||
bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) &
|
||||
C2_BOOTROM_BOOTSTS_SYSTEM_READY;
|
||||
} while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY));
|
||||
|
||||
//
|
||||
// Loop until CPU02 control system IPC flags 1 and 32 are available
|
||||
//
|
||||
while (((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC0) != 0U) ||
|
||||
((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC31) != 0U))
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
if (bootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE)
|
||||
{
|
||||
returnStatus = STATUS_FAIL;
|
||||
}
|
||||
else
|
||||
{
|
||||
//
|
||||
// Based on boot mode, enable pull-ups on peripheral pins and
|
||||
// give GPIO pin control to CPU02 control system.
|
||||
//
|
||||
switch (bootMode)
|
||||
{
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI:
|
||||
|
||||
//
|
||||
//SCIA connected to CPU02
|
||||
//
|
||||
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL5_SCI, 1,
|
||||
SYSCTL_CPUSEL_CPU2);
|
||||
|
||||
//
|
||||
//Allows CPU02 bootrom to take control of clock
|
||||
//configuration registers
|
||||
//
|
||||
EALLOW;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U;
|
||||
EDIS;
|
||||
|
||||
GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT);
|
||||
GPIO_setQualificationMode(29, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_29_SCITXDA);
|
||||
GPIO_setMasterCore(29, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(28, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(28, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_28_SCIRXDA);
|
||||
GPIO_setMasterCore(28, GPIO_CORE_CPU2);
|
||||
|
||||
break;
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI:
|
||||
|
||||
//
|
||||
//SPI-A connected to CPU02
|
||||
//
|
||||
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL6_SPI, 1,
|
||||
SYSCTL_CPUSEL_CPU2);
|
||||
|
||||
//
|
||||
//Allows CPU02 bootrom to take control of clock configuration
|
||||
// registers
|
||||
//
|
||||
EALLOW;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
|
||||
EDIS;
|
||||
|
||||
GPIO_setDirectionMode(16, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_16_SPISIMOA);
|
||||
GPIO_setMasterCore(16, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(17, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_17_SPISOMIA);
|
||||
GPIO_setMasterCore(17, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(18, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(18, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_18_SPICLKA);
|
||||
GPIO_setMasterCore(18, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(19, GPIO_DIR_MODE_OUT);
|
||||
GPIO_setQualificationMode(19, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_19_GPIO19);
|
||||
GPIO_setMasterCore(19, GPIO_CORE_CPU2);
|
||||
|
||||
break;
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C:
|
||||
|
||||
//
|
||||
//I2CA connected to CPU02
|
||||
//
|
||||
SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL7_I2C, 1,
|
||||
SYSCTL_CPUSEL_CPU2);
|
||||
|
||||
//
|
||||
//Allows CPU2 bootrom to take control of clock
|
||||
//configuration registers
|
||||
//
|
||||
EALLOW;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U;
|
||||
EDIS;
|
||||
|
||||
GPIO_setDirectionMode(32, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(32, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_32_SDAA);
|
||||
GPIO_setMasterCore(32, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(33, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(33, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_33_SCLA);
|
||||
GPIO_setMasterCore(33, GPIO_CORE_CPU2);
|
||||
|
||||
break;
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL:
|
||||
|
||||
for(pin=58;pin<=65;pin++)
|
||||
{
|
||||
GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
|
||||
GPIO_setMasterCore(pin, GPIO_CORE_CPU2);
|
||||
}
|
||||
|
||||
GPIO_setDirectionMode(69, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(69, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_69_GPIO69);
|
||||
GPIO_setMasterCore(69, GPIO_CORE_CPU2);
|
||||
|
||||
GPIO_setDirectionMode(70, GPIO_DIR_MODE_IN);
|
||||
GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC);
|
||||
GPIO_setPinConfig(GPIO_70_GPIO70);
|
||||
GPIO_setMasterCore(70, GPIO_CORE_CPU2);
|
||||
|
||||
break;
|
||||
|
||||
|
||||
case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN:
|
||||
//
|
||||
//Set up the GPIO mux to bring out CANATX on GPIO71
|
||||
//and CANARX on GPIO70
|
||||
//
|
||||
GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU);
|
||||
|
||||
GPIO_setMasterCore(71, GPIO_CORE_CPU2);
|
||||
GPIO_setPinConfig(GPIO_71_CANTXA);
|
||||
GPIO_setQualificationMode(71, GPIO_QUAL_ASYNC);
|
||||
|
||||
GPIO_setMasterCore(70, GPIO_CORE_CPU2);
|
||||
GPIO_setPinConfig(GPIO_70_CANRXA);
|
||||
GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC);
|
||||
|
||||
|
||||
GPIO_lockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU);
|
||||
|
||||
//
|
||||
// Set CANA Bit-Clock Source Select = SYSCLK and enable CAN
|
||||
//
|
||||
EALLOW;
|
||||
HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &=
|
||||
SYSCTL_CLKSRCCTL2_CANABCLKSEL_M;
|
||||
EDIS;
|
||||
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA);
|
||||
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
//CPU01 to CPU02 IPC Boot Mode Register
|
||||
//
|
||||
HWREG(IPC_BASE + IPC_O_BOOTMODE) = bootMode;
|
||||
|
||||
//
|
||||
// CPU01 To CPU02 IPC Command Register
|
||||
//
|
||||
HWREG(IPC_BASE + IPC_O_SENDCOM) = BROM_IPC_EXECUTE_BOOTMODE_CMD;
|
||||
|
||||
//
|
||||
// CPU01 to CPU02 IPC flag register
|
||||
//
|
||||
HWREG(IPC_BASE + IPC_O_SET) = 0x80000001U;
|
||||
|
||||
}
|
||||
return returnStatus;
|
||||
}
|
||||
#endif // #ifdef CPU1
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Error handling function to be called when an ASSERT is violated
|
||||
//
|
||||
//*****************************************************************************
|
||||
void __error__(const char *filename, uint32_t line)
|
||||
{
|
||||
//
|
||||
// An ASSERT condition was evaluated as false. You can use the filename and
|
||||
// line parameters to determine what went wrong.
|
||||
//
|
||||
ESTOP0;
|
||||
}
|
||||
|
||||
void Example_setResultPass(void)
|
||||
{
|
||||
Example_Result = PASS;
|
||||
}
|
||||
|
||||
void Example_setResultFail(void)
|
||||
{
|
||||
Example_Result = FAIL;
|
||||
}
|
||||
|
||||
void Example_done(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
@@ -1,22 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<configurations XML_version="1.2" id="configurations_0">
|
||||
<configuration XML_version="1.2" id="Texas Instruments XDS100v2 USB Debug Probe_0">
|
||||
<instance XML_version="1.2" desc="Texas Instruments XDS100v2 USB Debug Probe_0" href="connections/TIXDS100v2_Connection.xml" id="Texas Instruments XDS100v2 USB Debug Probe_0" xml="TIXDS100v2_Connection.xml" xmlpath="connections"/>
|
||||
<connection XML_version="1.2" id="Texas Instruments XDS100v2 USB Debug Probe_0">
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2icepick_c.xml" id="drivers" xml="tixds100v2icepick_c.xml" xmlpath="drivers"/>
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2c28x.xml" id="drivers" xml="tixds100v2c28x.xml" xmlpath="drivers"/>
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2cla1.xml" id="drivers" xml="tixds100v2cla1.xml" xmlpath="drivers"/>
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2cs_child.xml" id="drivers" xml="tixds100v2cs_child.xml" xmlpath="drivers"/>
|
||||
<platform XML_version="1.2" id="platform_0">
|
||||
<instance XML_version="1.2" desc="TMS320F28377D_0" href="devices/tms320f28377d.xml" id="TMS320F28377D_0" xml="tms320f28377d.xml" xmlpath="devices"/>
|
||||
<device HW_revision="1" XML_version="1.2" description="" id="TMS320F28377D_0" partnum="TMS320F28377D">
|
||||
<router HW_revision="1.0" XML_version="1.2" description="ICEPick_C router" id="IcePick_C_0" isa="ICEPICK_C">
|
||||
<subpath id="Subpath_1">
|
||||
<property Type="numericfield" Value="0x11" desc="Port Number_0" id="Port Number"/>
|
||||
</subpath>
|
||||
</router>
|
||||
</device>
|
||||
</platform>
|
||||
</connection>
|
||||
</configuration>
|
||||
</configurations>
|
||||
@@ -1,22 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<configurations XML_version="1.2" id="configurations_0">
|
||||
<configuration XML_version="1.2" id="Texas Instruments XDS100v2 USB Debug Probe_0">
|
||||
<instance XML_version="1.2" desc="Texas Instruments XDS100v2 USB Debug Probe_0" href="connections/TIXDS100v2_Connection.xml" id="Texas Instruments XDS100v2 USB Debug Probe_0" xml="TIXDS100v2_Connection.xml" xmlpath="connections"/>
|
||||
<connection XML_version="1.2" id="Texas Instruments XDS100v2 USB Debug Probe_0">
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2icepick_c.xml" id="drivers" xml="tixds100v2icepick_c.xml" xmlpath="drivers"/>
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2c28x.xml" id="drivers" xml="tixds100v2c28x.xml" xmlpath="drivers"/>
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2cla1.xml" id="drivers" xml="tixds100v2cla1.xml" xmlpath="drivers"/>
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2cs_child.xml" id="drivers" xml="tixds100v2cs_child.xml" xmlpath="drivers"/>
|
||||
<platform XML_version="1.2" id="platform_0">
|
||||
<instance XML_version="1.2" desc="TMS320F28379D_0" href="devices/f28379d.xml" id="TMS320F28379D_0" xml="f28379d.xml" xmlpath="devices"/>
|
||||
<device HW_revision="1" XML_version="1.2" description="" id="TMS320F28379D_0" partnum="TMS320F28379D">
|
||||
<router HW_revision="1.0" XML_version="1.2" description="ICEPick_C router" id="IcePick_C_0" isa="ICEPICK_C">
|
||||
<subpath id="Subpath_1">
|
||||
<property Type="numericfield" Value="0x11" desc="Port Number_0" id="Port Number"/>
|
||||
</subpath>
|
||||
</router>
|
||||
</device>
|
||||
</platform>
|
||||
</connection>
|
||||
</configuration>
|
||||
</configurations>
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,8 +0,0 @@
|
||||
<html>
|
||||
<body>
|
||||
<script type="text/javascript">
|
||||
window.location.href = "http://www.ti.com/product/TMS320F28379D"; //change this to the URL
|
||||
//you want to redirect to
|
||||
</script>
|
||||
</body>
|
||||
</html>
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,4 +0,0 @@
|
||||
# Sphinx build info version 1
|
||||
# This file hashes the configuration used when building these files. When it is not found, a full rebuild will be done.
|
||||
config: 4df5738a0adb2a1adbb6760c7be63e24
|
||||
tags: 645f666f9bcd5a90fca523b33c5a78b7
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 84 KiB |
Loaded 100 of 2470 files, more files were not shown because too many files have changed in this diff.
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Block a user